JP2024082342A - Field-effect transistor - Google Patents

Abstract

[Problem] To provide a field effect transistor capable of improving the maximum available power gain. [Solution] A field effect transistor 1 includes source electrodes S1a, S1b, a drain electrode D1, gate fingers 10a, 10b having one end to which a signal is input and the other end, and impedance elements 18a, 18b connected to the other ends of the gate fingers 10a, 10b. The impedance of the impedance elements 18a, 18b as viewed from the other ends of the gate fingers 10a, 10b is capacitive or inductive. [Selected Figure] Figure 3

Description

This disclosure relates to high frequency field effect transistors (FETs).

In recent years, the development of wireless communication systems and wireless power transmission systems has progressed. These systems require high-frequency amplification elements. For example, Patent Document 1 discloses a high-frequency MOSFET.

JP 2009-16686 A

In conventional field effect transistors, the larger the gate width, the lower the maximum available power gain (MAG). It is desirable to improve the MAG.

The present disclosure has been made in consideration of these problems, and one of its exemplary objectives is to provide a field effect transistor that can improve the maximum available power gain.

In order to solve the above problem, a field effect transistor according to one embodiment of the present disclosure includes a source electrode, a drain electrode, a gate finger having one end to which a signal is input and the other end, and an impedance element connected to the other end of the gate finger. The impedance of the impedance element as viewed from the other end of the gate finger is capacitive or inductive.

In addition, any combination of the above components, or mutual substitution of the components or expressions of this disclosure between methods, systems, etc., are also valid aspects of this disclosure.

The present disclosure provides a field effect transistor that can improve the maximum available power gain.

FIG. 1 is a plan view showing a configuration of a field effect transistor of a comparative example. FIG. 2 is a diagram showing the frequency dependence of MAG in the field effect transistor of FIG. 1 is a diagram showing a configuration of a field effect transistor according to an embodiment; FIG. 4 is a diagram showing a circuit model of the field effect transistor of FIG. 3 . FIG. 4 is a circuit diagram of the impedance element of FIG. 3 for a simulation. 1 is a diagram showing high-frequency characteristics of a field-effect transistor according to an embodiment and a field-effect transistor according to a comparative example; 11 is a diagram showing another example of high-frequency characteristics of the field-effect transistor of the embodiment and the field-effect transistor of the comparative example. FIG. 11 is a diagram showing measurement results of frequency dependence of MAG in the field effect transistor of the embodiment and the field effect transistor of the comparative example. FIG. FIG. 11 is a plan view showing another configuration example of the field effect transistor according to the embodiment. FIG. 11 is a plan view showing yet another configuration example of the field effect transistor according to the embodiment.

The inventors have studied field effect transistors for high frequencies in the microwave and millimeter wave bands and have obtained the following findings. FIG. 1 is a plan view showing the configuration of a field effect transistor 100 of a comparative example. The field effect transistor 100 includes a gate electrode G1, a source electrode S1a, a source electrode S1b, and a drain electrode D1.

The gate electrode G1 has gate finger 10a and gate finger 10b. Hereinafter, gate finger 10a and gate finger 10b are collectively referred to as "gate finger 10" as appropriate. One end of each of the two gate fingers 10 is connected to a connection portion 12. The connection portion 12 constitutes a signal input terminal for a high-frequency signal. The end of the gate finger 10 opposite the signal input terminal is open. The width of the gate finger 10 is defined as the gate finger width Wg. The field effect transistor 100 has a known configuration, and therefore further detailed description is omitted.

Figure 2 shows the frequency dependence of MAG in the field effect transistor 100 of Figure 1. In this example, the field effect transistor 100 is a HEMT (High Electron Mobility Transistor). Figure 2 shows the measured values of a GaN HEMT with a gate length of 0.25 μm, gate finger width Wg = 50 μm, 100 μm, or 200 μm, and the number of gate fingers is 2. The bias conditions are Vds = 28 V, Ids = 100 mA/mm.

As shown in FIG. 2, in the comparative field effect transistor 100, for example, in the high frequency band of approximately 10 GHz or more, the MAG decreases as the gate finger width Wg increases.

After much consideration and analysis, the inventors discovered that one of the main reasons for the phenomenon in which the MAG decreases as the gate finger width Wg increases is that the behavior of the gate finger 10 as a distributed constant line becomes more pronounced as the gate finger width Wg increases.

Based on these findings, the inventors conducted further research and discovered that by connecting an impedance element to the end of the gate finger 10 opposite the signal input end, i.e., to the tip of the gate finger 10, it is possible to effectively utilize the behavior of the gate finger 10 as a distributed constant line and improve the MAG in a specified frequency band. The embodiment was devised based on these considerations, and the specific configuration is described below.

Below, the embodiments for implementing the present disclosure will be described in detail with reference to the drawings. Note that in the description, the same elements are given the same reference numerals, and duplicate descriptions will be omitted as appropriate.

Figure 3 shows the configuration of a field effect transistor 1 according to an embodiment. Figure 3(a) is a plan view of the field effect transistor 1, and Figure 3(b) is a longitudinal cross-sectional view of the field effect transistor 1 taken along line A-A' in Figure 3(a). The field effect transistor 1 can be used, for example, as an amplifying element in a power amplifier or a low noise amplifier.

The field effect transistor 1 includes a gate electrode G1, a source electrode S1a, a source electrode S1b, a drain electrode D1, an impedance element 18a, and an impedance element 18b. Hereinafter, the source electrode S1a and the source electrode S1b are collectively referred to as the "source electrode S1" as appropriate. The impedance elements 18a and 18b are collectively referred to as the "impedance element 18" as appropriate. The configuration other than the impedance element 18 is shown as an example that is the same as the comparative example, but may have other field effect transistor configurations.

As shown in FIG. 3B, the gate electrode G1, the source electrode S1, and the drain electrode D1 are formed on the semiconductor substrate 30. The impedance element 18 is also formed on the semiconductor substrate 30. The semiconductor substrate 30 is not particularly limited, but may be, for example, a semiconductor substrate such as silicon, a compound semiconductor substrate, or a substrate including a compound semiconductor layer. The compound semiconductor is not particularly limited, but may be, for example, gallium arsenide (GaAs) or a nitride semiconductor such as gallium nitride (GaN). The field effect transistor 1 is not particularly limited, but may be, for example, a high electron mobility transistor using gallium nitride, i.e., a GaN HEMT.

The drain electrode D1 extends in a first direction d1 along the surface of the semiconductor substrate 30. One end of the drain electrode D1 is connected to the drain terminal 22.

The source electrode S1a and the source electrode S1b are arranged substantially parallel to each other on either side of the drain electrode D1 in the second direction d2 and extend in the first direction d1. The second direction d2 is perpendicular to the first direction d1 and runs along the surface of the semiconductor substrate 30. The source electrode S1a is arranged away from the drain electrode D1, and the source electrode S1b is arranged away from the drain electrode D1.

The source electrode S1a is connected to the via 20a. The via 20a is connected to the ground conductor 32 formed on the back surface of the semiconductor substrate 30. The source electrode S1b is connected to the via 20b. The via 20b is connected to the ground conductor 32. In other words, the source electrode S1 is grounded. Note that the source electrode S1 does not have to be grounded.

The gate electrode G1 has a gate finger 10a, a gate finger 10b, and a connection portion 12. The gate finger 10a is disposed between the source electrode S1a and the drain electrode D1 and extends in the first direction d1. The gate finger 10b is disposed between the source electrode S1b and the drain electrode D1 and extends in the first direction d1.

One end of gate finger 10a and one end of gate finger 10b are connected at connection 12. Connection 12 is one end of gate electrode G1, to which a high-frequency input signal is input. The number of gate fingers is "2" in the example of FIG. 3, but it may be "1" or "3" or more.

Impedance element 18a is connected to the other end of gate finger 10a. Impedance element 18b is connected to the other end of gate finger 10b. The number of impedance elements 18 is the same as the number of gate fingers. The impedance elements 18 are connected to the other ends of the gate fingers 10 with which they correspond one-to-one. Multiple impedance elements 18 may have the same configuration and the same impedance.

The impedance seen from the other end of the gate finger 10 to the impedance element 18 is capacitive or inductive in the frequency band of the input signal. Also, the impedance seen from the other end of the gate finger 10 to the impedance element 18 is an open impedance in DC, i.e., is substantially infinite.

The impedance element 18a has a transmission line 14a and a capacitance element 16a. The transmission line 14a has one end connected to the other end of the gate finger 10a, and the other end.

The capacitance element 16a is, for example, a MIM (Metal-Insulator-Metal) capacitance, and is connected between the other end of the transmission line 14a and the source electrode S1a. For example, the upper electrode of the capacitance element 16a is connected to the other end of the transmission line 14a, and the lower electrode of the capacitance element 16a is connected to the source electrode S1a. Since the source electrode S1a is connected to the ground conductor 32 through the via 20a, it can also be said that the capacitance element 16a is connected between the other end of the transmission line 14a and the ground. The capacitance element 16a may be connected to a grounded electrode other than the source electrode S1a.

Impedance element 18b has transmission line 14b and capacitance element 16b. Transmission line 14b has one end connected to the other end of gate finger 10b, and the other end. Capacitance element 16b is, for example, an MIM capacitance, and is connected between the other end of transmission line 14b and source electrode S1b. Hereinafter, transmission line 14a and transmission line 14b will be collectively referred to as "transmission line 14" as appropriate. Capacitance element 16a and capacitance element 16b will be collectively referred to as "capacitance element 16" as appropriate.

The width and length of the transmission line 14 and the capacitance of the capacitive element 16 can be appropriately determined by experiment or simulation so that MAG is the desired value in the frequency band of the input signal. If the transmission line 14 and the capacitive element 16 are connected by a via, the inductance of the via may be included in the length of the transmission line 14.

In addition, the transmission line 14 may not be provided, and the capacitance element 16 may be directly connected between the other end of the gate finger 10 and the source electrode S1 or ground. For example, the upper electrode of the capacitance element 16 may be directly connected to the other end of the gate finger 10. In other words, the impedance element 18 may be the capacitance element 16.

When the capacitance element 16 is connected between the other end of the gate finger 10 and the source electrode S1 or ground via a transmission line 14 or directly, a capacitance element 16 having an elongated shape in a planar view may be used, and the elongated upper electrode of the capacitance element 16 may also function as the transmission line 14.

Also, the capacitance element 16 may not be provided, and the impedance element 18 may be an open stub formed by the transmission line 14.

The impedance of impedance element 18 is not particularly limited, but for example, the absolute value of the impedance in the frequency band of the input signal may be 0 Ω or more and 10 kΩ or less.

Figure 4 shows a circuit model of the field effect transistor 1 in Figure 3. Figure 4(a) shows a detailed circuit model, and Figure 4(b) shows a circuit model that conceptually expresses the circuit model in Figure 4(a). As shown in Figures 4(a) and 4(b), the field effect transistor operates as a voltage-controlled current source.

In FIG. 4(a), the peripheral portion of the gate finger 10 is modeled as a distributed constant line. The gate finger 10 is represented by a distributed constant line in which a resistance component Rdx and an inductance component Ldx that exist within a small section dx in the direction of the gate finger width Wg are distributed. The resistance R represents the resistance value per unit length of the gate finger 10. The inductance L represents the inductance per unit length of the gate finger 10.

A capacitance component Cdx and a conductance component Gin·dx are connected in series between each position of the gate finger 10 and the grounded source. The capacitance C represents the gate-source capacitance per unit length. The conductance Gin represents the conductance per unit length that exists in series with the capacitance C between the gate and source.

In FIG. 4(a), in order to clarify the drawing, only a portion of the resistance component Rdx, the inductance component Ldx, the capacitance component Cdx, and the conductance component Gin·dx are shown.

The input voltage to the gate, i.e., the input voltage to one end of the gate finger 10, is Vi. The gate voltage in a small section within the gate finger 10 due to the input voltage Vi is Vg(x). The gate voltage Vg(x) in the small section is the voltage applied to the capacitance component Cdx.

First, a comparative example will be described. In the comparative example, the other end of the gate finger 10 is open, so the impedance element 18 in FIG. 4(a) does not exist. Therefore, the input voltage Vi of the high frequency signal input to the gate is totally reflected at the other end of the gate finger 10, which is the open end, and a standing wave is generated within the gate finger 10, and the gate voltage Vg(x) in the small section within the gate finger 10 has a distribution in the direction of the gate finger width Wg, i.e., the x direction.

The output current id is calculated by multiplying the gate voltage Vg(x) in the small section by the mutual conductance per unit length gmo, and integrating the current in the small section over the gate finger width Wg. The effective mutual conductance gm _eff is calculated by id/Vi.

From the above, the effective mutual conductance gm _eff of the comparative example is expressed by the following formula (1).

Here, the propagation constants γ, Zs, and Gp are expressed by the following equation (2).

As described above, the effective mutual conductance gm _eff depends on the integral value of the gate voltage Vg(x) in a small section in the gate finger 10. Therefore, in the embodiment, the other end of the gate finger 10 is not opened, but is terminated by an impedance element 18 having a predetermined impedance _ZL , thereby causing a change in the distribution of the gate voltage Vg(x) in the small section in the gate finger 10. As a result, the effective mutual conductance gm _eff , which depends on the integral value of the gate voltage Vg(x) in the small section, can be increased in a predetermined frequency band more than the comparative example.

In other words, by connecting an appropriate impedance _ZL by utilizing the fact that the distribution of the gate voltage Vg(x) in a small section in the gate finger 10 changes depending on the impedance _ZL , it is possible to increase the effective mutual conductance gm _eff in a predetermined frequency band compared to the comparative example. As a result, it is possible to improve the MAG in a predetermined frequency band compared to the comparative example.

In the embodiment, the effective mutual conductance gm _eff is expressed by the following equation (3).

4A, the reflection coefficient of the impedance element 18 viewed from the other end of the gate finger 10 is denoted as _ΓL . The impedance of the impedance element 18 viewed from the other end of the gate finger 10 is denoted as _ZL . The characteristic impedance of the gate finger 10 as a transmission line is denoted as Z0. The reflection coefficient _ΓL and characteristic impedance Z0 based on Z0 are expressed by the following equation (4).

In the embodiment, as shown in formula (3), the effective mutual conductance gm _eff changes depending on the impedance _ZL . Therefore, as described above, by setting an appropriate impedance _ZL , the effective mutual conductance gm _eff can be made larger than the effective mutual conductance gm _eff of the comparative example shown in formula (1).

Next, the results of a simulation of the field effect transistor 1 will be described. FIG. 5 is a circuit diagram of the impedance element 18 of FIG. 3 for the simulation. FIG. 6 shows the high-frequency characteristics of the field effect transistor 1 of the embodiment and the field effect transistor 100 of the comparative example. FIG. 7 shows another example of the high-frequency characteristics of the field effect transistor 1 of the embodiment and the field effect transistor 100 of the comparative example.

The characteristics shown in Figures 6 and 7 differ in the length La of the transmission line 14 shown in Figure 5. In Figure 6, the length La of the transmission line 14 is 0 μm. In other words, the impedance element 18 is composed of a capacitance element 16. In Figure 7, the width Wa of the transmission line 14 is 9 μm and the length La is 120 μm. In Figures 6 and 7, the capacitance of the capacitance element 16 is 0.2 pF.

In Figures 6 and 7, the characteristics of the embodiment are shown by solid lines, and the characteristics of the comparative example are shown by dashed lines. Figures 6 and 7 show the simulation results of a GaN HEMT with a gate length of 0.15 μm, a gate finger width Wg = 150 μm, and two gate fingers. The bias conditions are Vds = 28 V, Ids = 50 mA/mm.

Figure 6(a) shows the simulation results of the frequency dependence of the MAG, and Figure 6(b) shows the simulation results of the frequency dependence of the effective mutual conductance. As shown in Figure 6(a), the MAG is improved over the comparative example in the frequency range from about 56 GHz to about 160 GHz. In the frequency range from about 70 GHz to about 110 GHz, the MAG is improved by about 10 dB over the comparative example. The maximum oscillation frequency fmax, which is the frequency at which MAG = 0, is also improved over the comparative example.

6, the frequency at which the magnitude relationship of MAG is reversed between the comparative example and the embodiment and the frequency at which the magnitude relationship of effective mutual conductance gm _eff is reversed between the comparative example and the embodiment are approximately the same, at about 56 GHz. This shows that an increase in effective mutual conductance gm _eff contributes to an improvement in MAG.

Figure 7(a) shows the simulation results of the frequency dependence of the MAG, and Figure 7(b) shows the simulation results of the frequency dependence of the effective transconductance. As shown in Figure 7(a), the MAG is an improvement over the comparative example in the frequency range from about 48 GHz to about 90 GHz. In the frequency range from about 60 GHz to about 70 GHz, the MAG is about 10 dB better than the comparative example. The maximum oscillation frequency fmax is also improved over the comparative example.

As shown by the dashed lines in FIG. 7, the frequency at which the magnitude relationship of MAG is reversed between the comparative example and the embodiment and the frequency at which the magnitude relationship of effective mutual conductance gm _eff is reversed between the comparative example and the embodiment are approximately the same, at about 48 GHz.

Although not shown, other conditions are the same as in Figures 6 and 7, and the MAG is improved compared to the comparative example even when the length La of the transmission line 14 is 40 μm and 80 μm. By adjusting the length La of the transmission line 14, the frequency range in which the MAG is improved can be adjusted. As the length La of the transmission line 14 becomes longer than zero, the frequency at which the magnitude relationship of the MAG is reversed between the comparative example and the embodiment becomes lower.

Although not shown, even when the transmission line 14 is an open stub, simulation results are obtained in which the MAG is improved over the comparative example in a frequency range according to the length of the transmission line 14. The simulation results of Figures 6 and 7 using the capacitance element 16 show a greater improvement in MAG than the simulation results using the open stub. This is thought to be because connecting the capacitance element 16 to the open gate finger 10 of the comparative example can increase the phase rotation of the reflection coefficient compared to connecting an open stub, and can greatly change the distribution of the gate voltage Vg(x) in a small section within the gate finger 10.

Although not shown, the simulation results in which the gate finger width Wg is changed to 50 μm under the conditions of Figures 6 and 7 also show that the MAG is improved compared to the comparative example, but the amount of improvement is less than in the examples of Figures 6 and 7. In this case, when compared with the same length of transmission line 14, the frequency band in which the MAG is improved compared to the comparative example shifts to the higher frequency side than in the examples of Figures 6 and 7. This is thought to be because when the gate finger width Wg is shortened, the behavior of the distributed constant line in the gate finger 10 becomes smaller. In other words, it is thought to be because the distribution of the gate voltage Vg(x) in a small section in the gate finger 10 becomes closer to uniform within the gate finger 10.

Figure 8 shows the measurement results of the frequency dependence of MAG in the field effect transistor 1 of the embodiment and the field effect transistor 100 of the comparative example. Figure 8 shows the measurement results of a GaN HEMT with a gate length of 0.25 μm, a gate finger width Wg = 200 μm, and two gate fingers. The bias conditions are Vds = 28 V, Ids = 100 mA/mm. In other words, the measurement results of the comparative example shown in Figure 8 are the measurement results for Wg = 200 μm shown in Figure 2.

In the field effect transistor 1, the width Wa of the transmission line 14 is 5 μm, the length La of the transmission line 14 is 70 μm, and the capacitance of the capacitive element 16 is 0.2 pF.

As shown in Figure 8, measurements show that at frequencies above 33 GHz, MAG is an improvement over the comparative example. It has been demonstrated that MAG can provide an improvement of up to 10 dB or more.

Furthermore, the measurement results show that fmax is also improved compared to the comparative example. It has been demonstrated that fmax is approximately 41 GHz in the comparative example, whereas in the embodiment, it exceeds the upper measurement limit of 65 GHz.

Although not shown in FIG. 8, when compared with the measurement results for Wg = 50 μm shown in FIG. 2, the measurement results for the MAG in the embodiment with Wg = 200 μm are improved over the comparative example at frequencies of about 40 GHz or higher. In other words, even if the gate finger width Wg of the field effect transistor 1 is larger than that of the comparative example, the MAG can be made larger than that of the comparative example.

When the field effect transistor 1 is used as an amplifying element such as a power amplifier, the total Wg needs to be large. In this case, in the configuration of the comparative example, it is common to ensure the total Wg while suppressing the decrease in MAG by shortening the gate finger width Wg and increasing the number of gate fingers. However, the increase in the number of gate fingers can cause the MAG to decrease.

On the other hand, in the embodiment, since the decrease in MAG can be suppressed even if the gate finger width Wg is increased, the number of gate fingers can be reduced compared to the case where the configuration of the comparative example is used under the same total Wg conditions. Therefore, the decrease in MAG caused by the increase in the number of gate fingers can be suppressed.

As described above, according to the embodiment, compared to the comparative example in which the other end of the gate finger 10 is open, the impedance element 18 can shift the phase of the reflection coefficient at the other end of the gate finger 10, thereby making it possible to differ the voltage distribution within the gate finger 10. This makes it possible to increase the effective mutual conductance gm _eff in a predetermined frequency band compared to the comparative example, and therefore to increase the MAG in the predetermined frequency band.

By using a transmission line 14 and a capacitance element 16 connected in series as the impedance element 18, the MAG can be effectively increased. If the length of the transmission line 14 is set to zero, the area of the impedance element 18 can be reduced. By using an open stub as the impedance element 18, the impedance element 18 can be realized with a simple configuration without using the capacitance element 16.

In addition, the impedance of the impedance element 18 when viewed from the other end of the gate finger 10 is an open impedance for direct current, so it is possible to prevent direct current from flowing through the impedance element 18. This makes it possible to suppress an increase in power consumption.

In addition, by having the absolute impedance value of impedance element 18 be greater than or equal to 0 Ω and less than or equal to 10 kΩ in the frequency band of the input signal, the MAG can be increased more effectively.

The inventors believe that it is extremely difficult to improve the MAG by, for example, about 10 dB by improving semiconductor process technology, such as by shortening the gate length. Improving the semiconductor process technology also requires a great deal of cost and time. In contrast, in the embodiment, by utilizing existing semiconductor process technology, the MAG can be improved by, for example, about 10 dB simply by adding an impedance element 18 to an existing field effect transistor, thereby suppressing increases in costs and eliminating the need for a long development period.

Next, another configuration example of the field effect transistor 1 will be described. FIG. 9 is a plan view showing another configuration example of the field effect transistor 1 of the embodiment. FIG. 9 shows a configuration example of a coplanar line having a ground conductor 34 on the surface of a semiconductor substrate. The source electrode S1a and the lower electrode of the capacitance element 16a are each connected to the ground conductor 34 adjacent to the source electrode S1a and extending in the first direction d1. The source electrode S1b and the lower electrode of the capacitance element 16b are each connected to the ground conductor 34 adjacent to the source electrode S1b and extending in the first direction d1. The other configurations are the same as those in FIG. 3. Even with this configuration, the above-mentioned effects can be obtained. In addition, since the ground conductor 34 extends in the first direction d1, the lower electrode of the capacitance element 16 can be connected to the ground conductor 34 at a position away from the source electrode S1 in the first direction d1. This improves the degree of freedom in layout.

Figure 10 is a plan view showing yet another configuration example of the field effect transistor 1 of the embodiment. The configuration example of Figure 10 differs from Figure 9 in that one end of the capacitance element 16a is connected to the other end of the gate finger 10a without passing through the transmission line 14, and one end of the capacitance element 16b is connected to the other end of the gate finger 10b without passing through the transmission line 14.

Therefore, the capacitance element 16a is disposed adjacent to the other end of the gate finger 10a and the end of the source electrode S1a on the capacitance element 16a side. The lower electrode of the capacitance element 16a is connected to the source electrode S1a and the ground conductor 34.

Similarly, the capacitance element 16b is disposed adjacent to the other end of the gate finger 10b and the end of the source electrode S1b on the capacitance element 16b side. The lower electrode of the capacitance element 16b is connected to the source electrode S1b and the ground conductor 34.

The above-mentioned effects can be obtained with the configuration shown in FIG. 10. In addition, since the transmission line 14 is not provided, it is possible to make the field effect transistor 1 smaller than with the configuration shown in FIG. 9.

The present disclosure has been described above based on the embodiments. It will be understood by those skilled in the art that the present disclosure is not limited to the above embodiments, that various design changes are possible, that various modifications are possible, and that such modifications are also within the scope of the present disclosure.

An overview of one aspect of the present disclosure is as follows: A field effect transistor of one aspect of the present disclosure includes a gate finger having a source electrode, a drain electrode, one end to which a signal is input, and the other end, and an impedance element connected to the other end of the gate finger, and the impedance of the impedance element as viewed from the other end of the gate finger is capacitive or inductive.

This aspect allows the maximum available power gain to be improved.

The impedance element may include a transmission line having one end connected to the other end of the gate finger and the other end, and a capacitive element connected between the other end of the transmission line and ground or the source electrode. In this case, the maximum available power gain can be effectively increased in a predetermined frequency band.

The impedance element may be a capacitive element connected between the other end of the gate finger and ground or the source electrode. In this case, the area of the impedance element can be reduced.

The impedance element may be an open stub. In this case, the impedance element can be realized with a simple configuration.

The impedance of the impedance element as viewed from the other end of the gate finger may be an open impedance in direct current. In this case, it is possible to suppress the flow of direct current through the impedance element.

1...field effect transistor, 10, 10a, 10b...gate fingers, 14, 14a, 14b...transmission line, 16, 16a, 16b...capacitive element, 18, 18a, 18b...impedance element, D1...drain electrode, G1...gate electrode, S1, S1a, S1b...source electrode.

Claims (5)

A source electrode;
A drain electrode;
a gate finger having one end to which a signal is input and the other end;
an impedance element connected to the other end of the gate finger;
The impedance of the impedance element viewed from the other end of the gate finger is capacitive or inductive.
1. A field effect transistor comprising: The impedance element is
a transmission line having one end connected to the other end of the gate finger, and the other end;
a capacitance element connected between the other end of the transmission line and a ground or the source electrode;
2. The field effect transistor of claim 1, comprising: the impedance element is a capacitive element connected between the other end of the gate finger and ground or the source electrode;
2. The field effect transistor according to claim 1 . The impedance element is an open stub.
2. The field effect transistor according to claim 1 . The impedance of the impedance element as viewed from the other end of the gate finger is an open circuit impedance in DC.
5. A field effect transistor according to claim 1, wherein the first and second electrodes are electrically connected to each other.

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