JP2024070699A - Optical detection device and electronic apparatus - Google Patents

Abstract

To provide technology for achieving high image quality.SOLUTION: A light detection device includes: a semiconductor layer having a first surface portion and a second surface portion positioned on opposite sides to each other; a separation region extending in a thickness direction of the semiconductor layer; a plurality of photoelectric conversion regions demarcated by the separation region; a photoelectric conversion unit that is provided in respective photoelectric conversion regions among the plurality of photoelectric conversion regions, and that photoelectrically converts light which has entered from the second surface portion side of the semiconductor layer; and a light-shielding body and a multilayer wiring layer provided at the first surface portion side of the semiconductor layer. The separation region includes a light reflector that is provided in a dug part of the semiconductor layer across the first surface portion side and the second surface portion side of the semiconductor layer, and that has a lower refractive index than that of the semiconductor layer. The light-shielding body is provided across the separation region and the multilayer wiring layer, and has a higher extinction coefficient than that of the semiconductor layer.SELECTED DRAWING: Figure 6

Description

This technology (the technology disclosed herein) relates to a photodetector and electronic device, and in particular to a technology that is effective when applied to a photodetector having a photoelectric conversion region separated by an isolation region in a semiconductor layer and an electronic device equipped with the same.

In light detection devices such as solid-state imaging devices and distance measuring devices, the photoelectric conversion region of a semiconductor layer is divided by a separation region. Patent Document 1 discloses a technology in which a front-side light shielding portion and a back-side light shielding portion are provided in the separation region that divides the photoelectric conversion region.

JP 2021-193718 A

The photodetector device includes a multilayer wiring layer and pixel transistors on the side opposite to the light incident surface of the semiconductor layer. As a result, incident light that enters from the light incident surface of the semiconductor layer and passes through a specified photoelectric conversion region may be reflected by the wiring of the multilayer wiring layer or the gate electrode of the pixel transistor, and may enter an adjacent photoelectric conversion region different from the specified photoelectric conversion region as unwanted light. The incidence of this unwanted light induces color mixing and leads to a deterioration in image quality, leaving room for improvement.

In addition, when a metal light shield is provided in the separation region as in Patent Document 1, the metal in the light shield absorbs light, which reduces sensitivity and causes degradation of image quality, leaving room for improvement.

The purpose of this technology is to provide technology that can achieve high image quality.

(1) A photodetector according to an aspect of the present disclosure,
a semiconductor layer having a first surface and a second surface opposite each other;
A plurality of photoelectric conversion regions provided in the semiconductor layer and partitioned by isolation regions;
a photoelectric conversion unit provided in each of the plurality of photoelectric conversion regions and configured to photoelectrically convert light incident from the second surface side of the semiconductor layer;
a light shield and a multilayer wiring layer provided on the first surface side of the semiconductor layer;
Equipped with
the separation region includes a light reflector that is provided in a recessed portion of the semiconductor layer across the first surface side and the second surface side of the semiconductor layer and has a refractive index lower than that of the semiconductor layer;
The light shield is provided across the isolation region and the semiconductor layer, and has an extinction coefficient higher than that of the semiconductor layer.

(2) An electronic device according to another aspect of the present technology includes the above-mentioned light detection device, an optical system that forms an image light from a subject on the light detection device, and a signal processing circuit that processes a signal output from the light detection device.

1 is a planar layout diagram illustrating a schematic configuration example of a solid-state imaging device according to a first embodiment of the present technology. 1 is a block diagram showing a configuration example of a solid-state imaging device according to a first embodiment of the present technology. 1 is an equivalent circuit diagram showing a configuration example of a pixel of a solid-state imaging device according to a first embodiment of the present technology. 2 is a plan view illustrating a schematic planar pattern of an isolation region in a pixel array portion of the solid-state imaging device according to the first embodiment of the present technology. FIG. 5 is a longitudinal sectional view showing a schematic longitudinal sectional structure taken along line a4-a4 in FIG. 4. FIG. 6 is a vertical cross-sectional view showing a part of FIG. 5 . A vertical cross-sectional view showing a schematic diagram of oblique light in an isolation region and reflected light reflected on the multilayer wiring layer side (the first surface side of the semiconductor layer) of a photoelectric conversion region in a solid-state imaging device according to a first embodiment of the present technology. FIG. 7 is a diagram for explaining the reflection of oblique light 71 on the side opposite to the multilayer wiring layer side (light incident surface side of the semiconductor layer) of the isolation region. FIG. 7 is a diagram for explaining the reflection of oblique light on the multilayer wiring layer side of the isolation region (the first surface side of the semiconductor layer) and the absorption of reflected light on the multilayer wiring layer side of the photoelectric conversion region (semiconductor layer). FIG. 7 is a diagram for explaining the embedding depth (embedding height) of the light shielding body 30 embedded in the isolation region 50. In FIG. FIG. 2 is a plan view showing a diagonal direction of a photoelectric conversion region in a plan view. FIG. 1 is a plan view illustrating a first modified example of the first embodiment of the present technology. FIG. 11 is a longitudinal sectional view illustrating a modified example 2 of the first embodiment of the present technology. FIG. 11 is a longitudinal sectional view illustrating a third modified example of the first embodiment of the present technology. FIG. 13 is a longitudinal sectional view illustrating a fourth modified example of the first embodiment of the present technology. 13 is a plan view illustrating a schematic planar pattern of an isolation region in a pixel array portion of a solid-state imaging device according to a second embodiment of the present technology. FIG. 13 is a longitudinal sectional view showing a schematic longitudinal sectional structure taken along line a12-a12 in FIG. 12. 13 is a plan view illustrating a schematic planar pattern of an isolation region in a pixel array portion of a solid-state imaging device according to a third embodiment of the present technology. FIG. 15 is a longitudinal sectional view showing a schematic longitudinal sectional structure taken along line a14-a14 in FIG. 14. 13 is a plan view illustrating a schematic planar pattern of an isolation region in a pixel array portion of a solid-state imaging device according to a fourth embodiment of the present technology. FIG. 17 is a longitudinal sectional view showing a schematic longitudinal sectional structure taken along line a16-a16 in FIG. 16. 13 is a plan view illustrating a schematic planar pattern of an isolation region in a pixel array portion of a solid-state imaging device according to a fifth embodiment of the present technology. FIG. 18. FIG. 20 is a longitudinal sectional view showing a schematic longitudinal sectional structure taken along line a18-a18 in FIG. 13 is a longitudinal sectional view illustrating a schematic longitudinal sectional structure of a solid-state imaging device according to a sixth embodiment of the present technology. FIG. FIG. 23 is a diagram showing a configuration example of an electronic device according to a seventh embodiment of the present technology.

Hereinafter, embodiments of the present technology will be described in detail with reference to the drawings.
In the drawings referred to in the following description, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each layer, etc., differ from the actual ones. Therefore, the specific thickness and dimensions should be determined by taking into consideration the following description.

Of course, there are parts in which the dimensional relationships and ratios differ between the drawings. Furthermore, the effects described in this specification are merely examples and are not limiting, and other effects may also exist.

The following embodiments are merely examples of devices and methods for embodying the technical ideas of the present technology, and are not intended to limit the configuration to those described below. In other words, the technical ideas of the present technology can be modified in various ways within the technical scope described in the claims.

In addition, the definitions of up and down and other directions in the following explanation are merely for the convenience of explanation and do not limit the technical ideas of the present technology. For example, if an object is rotated 90 degrees and observed, up and down are converted into left and right and read, and of course, if it is rotated 180 degrees and observed, up and down are read inverted.

In the following embodiment, in the three mutually orthogonal directions (X direction, Y direction, Z direction) in space, the first and second directions that are mutually orthogonal in the two-dimensional plane of the semiconductor layer 20 described later are respectively defined as the X direction and the Y direction, and the third direction that is orthogonal to each of the first and second directions is respectively defined as the Z direction along the thickness direction of the semiconductor layer 20.

First Embodiment
In the first embodiment, an example in which the present technology is applied to a solid-state imaging device that is a back-illuminated complementary metal oxide semiconductor (CMOS) image sensor as a photodetector will be described.

<Overall configuration of solid-state imaging device>
First, the overall configuration of the solid-state imaging device 1A will be described.

As shown in FIG. 1, the solid-state imaging device 1A according to the first embodiment of the present technology is mainly composed of a semiconductor chip 2 that has a rectangular two-dimensional planar shape when viewed in a plane. That is, the solid-state imaging device 1A is mounted on the semiconductor chip 2, and the semiconductor chip 2 can be considered as the solid-state imaging device 1A. As shown in FIG. 21, this solid-state imaging device 1A (101) captures image light (incident light 106) from a subject via an optical lens 102, converts the amount of incident light 106 focused on the imaging surface into an electrical signal on a pixel-by-pixel basis, and outputs the signal as a pixel signal.

As shown in FIG. 1, the semiconductor chip 2 on which the solid-state imaging device 1A is mounted has a square pixel array section 2A provided in the center in a two-dimensional plane including mutually orthogonal X and Y directions, and a peripheral section 2B provided outside the pixel array section 2A so as to surround the pixel array section 2A. In the manufacturing process, the semiconductor chip 2 is formed by dicing a semiconductor wafer including a semiconductor layer 20 described below into chip formation regions. Therefore, the configuration of the solid-state imaging device 1A described below is generally the same in the wafer state before the semiconductor wafer is diced. In other words, the present technology can be applied in the state of a semiconductor chip and in the state of a semiconductor wafer.

The pixel array section 2A is a light receiving surface that receives light collected by, for example, an optical lens (optical system) 102 shown in FIG. 21. In the pixel array section 2A, a plurality of sensor pixels 3 are arranged in a matrix on a two-dimensional plane including the X direction and the Y direction. In other words, the sensor pixels 3 are repeatedly arranged in each of the X direction and the Y direction that are mutually orthogonal within the two-dimensional plane.

As shown in FIG. 1, a plurality of bonding pads 14 are arranged in the peripheral portion 2B. Each of the plurality of bonding pads 14 is arranged, for example, along each of the four sides of the semiconductor chip 2 in a two-dimensional plane. Each of the plurality of bonding pads 14 functions as an input/output terminal that electrically connects the semiconductor chip 2 to an external device.

<Logic circuit>
The semiconductor chip 2 includes a logic circuit 13 shown in Fig. 2. As shown in Fig. 2, the logic circuit 13 includes a vertical drive circuit 4, a column signal processing circuit 5, a horizontal drive circuit 6, an output circuit 7, and a control circuit 8. The logic circuit 13 is configured of a CMOS (Complementary MOS) circuit having, as field effect transistors, for example, an n-channel conductivity type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) and a p-channel conductivity type MOSFET.

The vertical drive circuit 4 is composed of, for example, a shift register. The vertical drive circuit 4 sequentially selects the desired pixel drive lines 10, supplies pulses to the selected pixel drive lines 10 for driving the sensor pixels 3, and drives each sensor pixel 3 row by row. That is, the vertical drive circuit 4 sequentially selects and scans each sensor pixel 3 in the pixel array section 2A in the vertical direction row by row, and supplies pixel signals from the sensor pixels 3 based on signal charges generated by the photoelectric conversion section (photoelectric conversion element) of each sensor pixel 3 according to the amount of light received to the column signal processing circuit 5 through the vertical signal line 11.

The column signal processing circuit 5 is arranged, for example, for each column of sensor pixels 3, and performs signal processing such as noise removal for each pixel column on signals output from one row of sensor pixels 3. For example, the column signal processing circuit 5 performs signal processing such as CDS (Correlated Double Sampling) and AD (Analog-Digital) conversion to remove pixel-specific fixed pattern noise.

The horizontal drive circuit 6 is composed of, for example, a shift register. The horizontal drive circuit 6 sequentially outputs horizontal scanning pulses to the column signal processing circuits 5, thereby selecting each of the column signal processing circuits 5 in turn, and causing each of the column signal processing circuits 5 to output a pixel signal that has been subjected to signal processing to the horizontal signal line 12.

The output circuit 7 processes and outputs pixel signals sequentially supplied from each of the column signal processing circuits 5 through the horizontal signal line 12. For example, the signal processing may include buffering, black level adjustment, column variation correction, various types of digital signal processing, etc.

The control circuit 8 generates clock signals and control signals that serve as a reference for the operation of the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc., based on the vertical synchronization signal, horizontal synchronization signal, and master clock signal. The control circuit 8 then outputs the generated clock signals and control signals to the vertical drive circuit 4, column signal processing circuit 5, horizontal drive circuit 6, etc.

<Circuit configuration of sensor pixel>
3, each of the sensor pixels 3 includes a photoelectric conversion region 21 and a pixel circuit (readout circuit) 15. The photoelectric conversion region 21 includes a photoelectric conversion unit 24, a transfer transistor TR as a pixel transistor, and a floating diffusion region FD as a charge holding unit. The pixel circuit 15 is electrically connected to the floating diffusion region FD of the photoelectric conversion region 21.

In the first embodiment, as an example, one pixel circuit 15 is assigned to one sensor pixel 3, but the present invention is not limited to this first embodiment. For example, one pixel circuit 15 may be shared by multiple sensor pixels 3. Specifically, one pixel circuit 15 may be shared by one sensor pixel group (photoelectric conversion group) in which four sensor pixels 3 are arranged in a 2×2 arrangement, two in each of the X and Y directions, as one unit. In addition, one pixel circuit 15 may be shared by one sensor pixel group (photoelectric conversion group) in which two sensor pixels 3 are arranged as one unit. In addition, one pixel circuit 15 may be shared by one sensor pixel group (photoelectric conversion group) in which four or more sensor pixels 3 are arranged as one unit.

Here, in this first embodiment, the transfer transistor TR corresponds to a specific example of a "pixel transistor provided on the first surface side of the semiconductor layer" in the present technology, and the floating diffusion region FD corresponds to a specific example of a "charge holding portion" in the present technology.

The photoelectric conversion unit 24 shown in FIG. 3 is composed of, for example, a pn junction type photodiode (PD) and generates a signal charge according to the amount of light received. The cathode side of the photoelectric conversion unit 24 is electrically connected to the source region of the transfer transistor TR, and the anode side is electrically connected to a reference potential line (for example, ground).

The transfer transistor TR shown in FIG. 3 transfers the signal charge photoelectrically converted by the photoelectric conversion unit 24 to the floating diffusion region FD. The source region of the transfer transistor RT is electrically connected to the cathode side of the photoelectric conversion unit 24, and the drain region of the transfer transistor TR is electrically connected to the floating diffusion region FD. The gate electrode of the transfer transistor TR is electrically connected to the transfer transistor drive line of the pixel drive line 10 (see FIG. 2).

The floating diffusion region FD shown in FIG. 3 temporarily holds (accumulates) the signal charge transferred from the photoelectric conversion unit 24 via the transfer transistor TR.

The photoelectric conversion region 21, which includes the photoelectric conversion unit 24, the transfer transistor TR, and the floating diffusion region FD, is mounted for each sensor pixel 3 on the semiconductor layer 20 shown in FIG. 5.

The pixel circuit 15 shown in FIG. 3 reads out the signal charge held in the floating diffusion region FD and outputs a pixel signal based on the read-out signal charge. The pixel circuit 15 includes, but is not limited to, an amplification transistor AMP, a selection transistor SEL, and a reset transistor RST as pixel transistors. Each of these pixel transistors (AMP, SEL, RST) and the above-mentioned transfer transistor TR is configured as a field effect transistor, for example, a MOSFET having a gate insulating film made of a silicon oxide (SiO ₂ ) film, a gate electrode, and a pair of main electrode regions functioning as a source region and a drain region. In addition, these transistors may be MISFETs (Metal Insulator Semiconductor FETs) whose gate insulating film is made of a silicon nitride (Si ₃ N ₄ ) film or a laminated film such as a silicon nitride film and a silicon oxide film.

Here, in this first embodiment, each of the amplification transistor AMP, the selection transistor SEL, and the reset transistor RST corresponds to a specific example of the "pixel transistor" of the present technology.

As shown in FIG. 3, the source region of the amplification transistor AMP is electrically connected to the drain region of the selection transistor SEL, and the drain region is electrically connected to the power supply line Vdd and the drain region of the reset transistor RST. The gate electrode of the amplification transistor AMP is electrically connected to the floating diffusion region FD and the source region of the reset transistor RST.

As shown in FIG. 3, the source of the selection transistor SEL is electrically connected to the vertical signal line 11 (VSL), and the drain region is electrically connected to the source region of the amplification transistor AMP. The gate electrode of the selection transistor SEL is electrically connected to the selection transistor drive line of the pixel drive line 10 shown in FIG. 2.

As shown in FIG. 3, the source region of the reset transistor RST is electrically connected to the floating diffusion region FD and the gate electrode of the amplification transistor AMP, and the drain region is electrically connected to the power supply line Vdd and the drain region of the amplification transistor AMP. The gate electrode of the reset transistor RST is electrically connected to the reset transistor drive line of the pixel drive line 10 shown in FIG. 2.

When the transfer transistor TRG shown in FIG. 3 is turned on, the transfer transistor TR transfers the signal charge generated in the photoelectric conversion unit 24 to the floating diffusion region FD.

When the reset transistor RST shown in FIG. 3 is turned on, it resets the potential (signal charge) of the floating diffusion region FD to the potential of the power supply line Vdd. The selection transistor SEL controls the output timing of the pixel signal from the pixel circuit 15.

The amplification transistor AMP shown in FIG. 3 generates a pixel signal whose voltage corresponds to the level of the signal charge held in the floating diffusion region FD. The amplification transistor AMP constitutes a source-follower type amplifier, and outputs a pixel signal whose voltage corresponds to the level of the signal charge generated by the photoelectric conversion unit 24. When the selection transistor SEL is turned on, the amplification transistor AMP amplifies the potential of the floating diffusion region FD and outputs a voltage corresponding to the potential to the column signal processing circuit 5 via the vertical signal line 11 (VSL).

Now, referring to FIG. 3, during operation of the solid-state imaging device 1A according to the first embodiment, the signal charge generated in the photoelectric conversion unit 24 of the sensor pixel 3 is held (accumulated) in the floating diffusion region FD via the transfer transistor TR of the sensor pixel 3. The signal charge held in the floating diffusion region FD is read out by the pixel circuit 15 and applied to the gate electrode of the amplification transistor AMP of the pixel circuit 15. A horizontal line selection control signal is provided to the gate electrode of the selection transistor SEL of the pixel circuit 15 from the vertical shift register. Then, by setting the selection control signal to a high (H) level, the selection transistor SEL becomes conductive, and a current corresponding to the potential of the floating diffusion region FD amplified by the amplification transistor AMP flows in the vertical signal line 11. Also, by setting the reset control signal applied to the gate electrode of the reset transistor RST of the pixel circuit 15 to a high (H) level, the reset transistor RST becomes conductive, and the signal charge accumulated in the floating diffusion region FD is reset.

<Other pixel circuits>
The selection transistor SEL may be omitted if necessary. In the case where the selection transistor SEL is omitted, the source region of the amplification transistor AMP is electrically connected to the vertical signal line 11 (VSL).

A switching transistor may be provided between the reset transistor RST and the gate electrode of the floating diffusion region FD and the amplifier transistor AMP. The switching transistor controls charge retention by the floating diffusion region FD and adjusts the voltage multiplication factor according to the potential amplified by the amplifier transistor AMP.

The switching transistor is also used to switch the conversion efficiency. In general, the pixel signal is small when shooting in a dark place. Based on Q=CV, if the FD capacitance C (floating diffusion capacitance C) of the charge holding section (floating diffusion region FD) is large when performing charge-voltage conversion, the voltage V when converted to voltage by the amplification transistor AMP will be small. On the other hand, in a bright place, the pixel signal is large, so if the FD capacitance C of the charge holding section is not large, the charge holding section cannot receive the charge of the photoelectric conversion section 24 (photodiode PD). Furthermore, the FD capacitance C of the charge holding section needs to be large so that the voltage V when converted to voltage by the amplification transistor AMP does not become too large (in other words, to become small). In light of this, when the switching transistor is turned on, the gate capacitance of the switching transistor increases, so the overall FD capacitance C becomes large. On the other hand, when the switching transistor is turned off, the overall FD capacitance C becomes small. In this way, by switching the switching transistor on/off, the FD capacitance C can be made variable and the conversion efficiency can be switched.

<<Specific configuration of solid-state imaging device>>
Next, a specific configuration of the semiconductor chip 2 (solid-state imaging device 1A) will be described with reference to FIGS.
FIG. 4 is a plan view illustrating a schematic planar pattern of an isolation region in a pixel array portion of the solid-state imaging device according to the first embodiment of the present technology.
FIG. 5 is a vertical cross-sectional view that typically shows a vertical cross-sectional structure taken along line a4-a4 in FIG.
FIG. 6 is a vertical cross-sectional view showing a part of FIG.
4 is a plan view seen from the opposite side to the paper surface of FIG.
5 and 6 omit illustration of layers above an interlayer insulating film 44 of a multi-layer wiring layer 40, which will be described later.

<Semiconductor chip>
As shown in Figures 4, 5 and 6, the semiconductor chip 2 comprises a semiconductor layer 20 having a first surface portion S1 and a second surface portion S2 located opposite each other in the thickness direction (Z direction), an isolation region 50 provided in the semiconductor layer 20, and a plurality of photoelectric conversion regions 21 provided in the semiconductor layer 20 and partitioned by the isolation region 50.

The semiconductor chip 2 further includes a photoelectric conversion section 24 that is provided in each of the multiple photoelectric conversion regions 21 and photoelectrically converts light incident (penetrating) from the second surface S2 side of the semiconductor layer 20, and a light shield 30 and a multilayer wiring layer 40 that are provided on the first surface S1 side of the semiconductor layer 20.

The semiconductor chip 2 further includes an insulating film 54 provided on the second surface S2 side of the semiconductor layer 20, and a light-shielding film 61, a color filter 62, and a microlens (on-chip lens) 63 provided in this order from the insulating film 54 side on the side opposite the semiconductor layer 20 side of the insulating film 54.

<Semiconductor Layer>
4 and 5, the semiconductor layer 20 includes an isolation region 50 extending in the thickness direction (Z direction) of the semiconductor layer 20, and a plurality of photoelectric conversion regions 21 partitioned by the isolation region 50. Each of the plurality of photoelectric conversion regions 21 is provided for each sensor pixel 3, and is adjacent to one another via the isolation region 50 in a plan view. That is, the solid-state imaging device 1A of the first embodiment includes a plurality of photoelectric conversion regions 21 provided in the semiconductor layer 20 adjacent to one another via the isolation region 50 extending in the thickness direction (Z direction) of the semiconductor layer 20.

As the semiconductor layer 20, a Si substrate, a SiGe substrate, an InGaAs substrate, or the like can be used. In this first embodiment, a p-type semiconductor substrate made of single crystal silicon, for example, is used as the semiconductor layer 20.

Here, the first surface S1 of the semiconductor layer 20 is sometimes called the element formation surface or main surface, and the second surface S2 is sometimes called the light incident surface or back surface. The solid-state imaging device 1A of this first embodiment is a back-illuminated type in which light incident from the second surface (light incident surface, back surface) S2 of the semiconductor layer 20 is photoelectrically converted by a photoelectric conversion unit 24 provided in the photoelectric conversion region 21 of the semiconductor layer 20.

In addition, a planar view refers to a view from a direction along the thickness direction (Z direction) of the semiconductor layer 20. In addition, a cross-sectional view refers to a view of a vertical section along the thickness direction (Z direction) of the semiconductor layer 20 from a direction (X direction or Y direction) perpendicular to the thickness direction (Z direction) of the semiconductor layer 20. In addition, the photoelectric conversion region 21 can also be called a photoelectric conversion cell.

<Photoelectric conversion region>
5 and 6, each of the multiple photoelectric conversion regions (photoelectric conversion cells) 21 includes a p-type well region 22 provided in the semiconductor layer 20, an n-type semiconductor region 23 provided in the p-type well region 22, a photoelectric conversion section 24, and a diffraction scattering section 52. Also, as shown in Fig. 4, each photoelectric conversion region 21 further includes the above-mentioned pixel transistors (AMP, SEL, RST, TR) and a floating diffusion region FD.

<p-type well region and n-type semiconductor region>
5 and 6, the p-type well region 22 is provided widely across the first surface portion S1 side and the second surface portion S2 side of the semiconductor layer 20. The p-type well region 22 is composed of, for example, a p-type semiconductor region.

The n-type semiconductor region 23 is provided in the p-type well region 22 across the first surface S1 side and the second surface S2 side of the semiconductor layer 20, while being spaced apart from each of the first surface S1 and the second surface S2 of the semiconductor layer 20 and the isolation region 50. That is, the upper surface of the n-type semiconductor region 23 on the first surface S1 side of the semiconductor layer 20, the lower surface of the second surface S2 side of the semiconductor layer 20, and the side surface of the isolation region 50 side are each surrounded by the p-type well region 22. In other words, the p-type well region 22 is provided between the first surface S1 of the semiconductor layer 20 and the upper surface of the n-type semiconductor region 23, and between the second surface S2 of the semiconductor layer 20 and the lower surface of the n-type semiconductor region 23, overlapping with the n-type semiconductor region 23. In addition, a p-type well region 22 is provided between the isolation region 50 and the n-type semiconductor region 23, and extends along the thickness direction (Z direction) of the semiconductor layer 20.

<Pixel Transistor and Floating Diffusion Region>
Although not shown in detail, the transfer transistor TR shown in Figure 4 includes a gate electrode 26t provided on the first surface portion S1 side of the semiconductor layer 20 via a gate insulating film, a photoelectric conversion portion 24 that mainly functions as a source region, and a main electrode region 25a that is provided in the surface portion (upper portion) on the first surface portion S1 side of the semiconductor layer 20 and mainly functions as a drain region.

The reset transistor RST shown in FIG. 4 includes, although not shown in detail, a gate electrode 26r provided on the first surface portion S1 side of the semiconductor layer 20 via a gate insulating film, a main electrode region 25a that mainly functions as a source region, and a main electrode region 25b that is provided in the surface layer portion (upper portion) of the first surface portion S1 side of the semiconductor layer 20 and mainly functions as a drain region. That is, the reset transistor RST and the transfer transistor TR share their respective main electrode regions 25a and are connected in series.

The amplification transistor AMP shown in FIG. 4 includes, although not shown in detail, a gate electrode 26a provided on the first surface S1 side of the semiconductor layer 20 via a gate insulating film, a main electrode region 25c provided in the surface layer (upper portion) on the first surface S1 side of the semiconductor layer 20 and functioning mainly as a source region, and a main electrode region 25b functioning mainly as a drain region. That is, the amplification transistor AMP and the reset transistor RST share the main electrode region 25b and are connected in series.

The selection transistor SEL shown in FIG. 4 includes, although not shown in detail, a gate electrode 26s provided on the first surface S1 side of the semiconductor layer 20 via a gate insulating film, a main electrode region 25d provided on the surface layer (upper portion) of the first surface S1 side of the semiconductor layer 20 and functioning mainly as a source region, and a main electrode region 25c functioning mainly as a drain region. That is, the selection transistor SEL and the amplification transistor AMP share the main electrode region 25c and are connected in series.

In the pixel transistors TR, RST, AMP, and SEL, the gate insulating film is composed of, for example, a silicon oxide film. The gate electrodes 26t, 26r, 26a, and 26s are composed of, for example, a polycrystalline silicon film into which an impurity that reduces the resistance value is introduced. The main electrode regions 25a, 25b, 25c, and 25d are composed of, for example, an n-type semiconductor region provided in the p-type semiconductor region 22 of the photoelectric conversion region 21.

Although not shown in detail, the pixel transistors TR, AMP, SEL, and RST are provided for each photoelectric conversion region 21 on the surface layer on the first surface portion S1 side of the semiconductor layer 20, and each gate electrode (26t, 26r, 26a, 26s) is provided on the first surface portion S1 side of the semiconductor layer 20.

The floating diffusion region FD shown in FIG. 4 is not shown in detail, but is provided in the surface layer (upper part) on the first surface portion S1 side of the semiconductor layer 20. As shown in FIG. 4, the floating diffusion region FD is shared with the main electrode region 25a. In other words, the floating diffusion region FD is composed of an n-type semiconductor region provided in the p-type semiconductor region 22 of the photoelectric conversion region 21.

Note that each of the pixel transistors TR, AMP, SEL, and RST is disposed at a position different from the position of the line a4-a4 in FIG. 4 in a plan view, but in FIG. 5 and FIG. 6, the gate electrode 26t of the transfer transistor TR is illustrated as an example of the pixel transistors TR, AMP, SEL, and RST.

<Separation Region>
4, the separation region 50 individually separates each of the multiple photoelectric conversion regions 21. The separation region 50 includes a first portion 50x extending in the X direction in a plan view and a second portion 50y extending in the Y direction. The first portion 50x and the second portion 50y are perpendicular to each other.

As shown in FIG. 4, the first portions 50x are repeatedly arranged in the Y direction at a predetermined interval. The second portions 50y are repeatedly arranged in the X direction at a predetermined interval. That is, the separation region 50 has a lattice-like planar pattern in plan view. Each of the multiple photoelectric conversion regions 21 is partitioned at both ends in the X direction by two adjacent second portions 50y of the separation region 50, and at both ends in the Y direction by two adjacent first portions 50x of the separation region 50.

As shown in Figures 5 and 6, the separation region 50 extends in the thickness direction (Z direction) of the semiconductor layer 20 in a vertical cross-sectional view, and electrically and optically separates adjacent photoelectric conversion regions 21. The separation region 50 extends across the first surface portion S1 side and the second surface portion S2 side of the semiconductor layer 20 in a vertical cross-sectional view. In this first embodiment, the separation region 50 reaches, for example, both the first surface portion S1 and the second surface portion S2 of the semiconductor layer 20, although this is not limited thereto.

As shown in FIG. 6, the separation region 50 includes a recessed portion 51 that extends in the depth direction (Z direction) of the semiconductor layer 20, and an insulating film 54a that is provided in the recessed portion 51 across the second surface portion S2 side and the first surface portion S1 side of the semiconductor layer 20 and serves as a light reflector having a lower refractive index than the semiconductor layer 20.

Air can also be used as a dielectric material having a lower refractive index than the semiconductor layer 20. In this case, the separation region 50 includes a cavity filled with air.

Here, the recessed portion 51 of the first embodiment corresponds to a specific example of a "recessed portion of a semiconductor layer" in the present technology, and the insulating film 54a of the first embodiment corresponds to a specific example of a "dielectric" in the present technology.

The insulating film 54a is provided in the recessed portion 51 of the semiconductor layer 20, from the second surface portion S2 side to the first surface portion S1 side of the semiconductor layer 20. The insulating film 54a in the recessed portion 51 is integrated with the insulating film 54 provided on the second surface portion S2 side of the semiconductor layer 20.

For example, silicon oxide films can be used as the insulating films 54 and 54a. Silicon oxide films have a lower refractive index than semiconductor materials such as Si, SiGe, and InGaAs. The insulating film 54a in the recessed portion 51, which will be described in detail later, mainly functions as a light reflector that reflects oblique light 71 irradiated from the predetermined photoelectric conversion region 21 side to the interface portion If (see FIG. 7) between the photoelectric conversion region 21 and the separation region 50 and returns it to the predetermined photoelectric conversion region 21. The insulating film 54a on the first surface portion S1 side of the semiconductor layer 20 covers the entire second surface portion S2 side of the semiconductor layer 20 in the pixel array portion 2A so that the second surface portion S2 (light incident surface) side of the semiconductor layer 20 is a flat surface without irregularities.

<Multi-layer wiring>
6, the multilayer wiring layer (wiring layer stack) 40 is provided on the first surface S1 side opposite to the light incident surface side (second surface S2 side) of the semiconductor layer 20. The multilayer wiring layer 40 has a stacked structure including, but not limited to, an interlayer insulating film 41, a first wiring layer M1, an interlayer insulating film 44, a second wiring layer M2, an interlayer insulating film 46, a third wiring layer M3, an interlayer insulating film 48, and the like, which are stacked in order from the first surface S1 side of the semiconductor layer 20.

The interlayer insulating film 41 is provided on the first surface portion S1 side of the semiconductor layer 20 so as to cover the gate electrodes of the pixel transistors (AMP, SEL, RST, TR). In FIG. 6, only the gate electrode 26t of the transfer transistor TR is shown.

A first-layer wiring layer M1 is provided on the interlayer insulating film 41, and this first-layer wiring layer M1 is covered by the upper interlayer insulating film 44. A second-layer wiring layer M2 is provided on the interlayer insulating film 44, and this second-layer wiring layer M2 is covered by the upper interlayer insulating film 46. A third-layer wiring layer M3 is provided on the interlayer insulating film 46, and this third-layer wiring layer M3 is covered by the upper interlayer insulating film 48.

Various wirings are formed in each of the first to third wiring layers M1 to M3. Figures 5 and 6 respectively show wiring 43 formed in the first wiring layer M1, wiring 45 formed in the second wiring layer M2, and wiring 47 formed in the third wiring layer M3.

Each of the first to third wiring layers M1 to M3 is made of a metal film such as copper (Cu) or an alloy mainly made of Cu. Each of the interlayer insulating films 41 to 48 is made of a single layer film of any one of a silicon oxide film, a silicon nitride (Si ₃ N ₄ ) film, and a silicon carbonitride (SiCN) film, or a laminated film of any two or more of these films.

<Diffraction scattering part>
6, the diffraction scattering section 52 has a configuration in which periodic irregularities are provided on the interface on the light incident surface side (second surface portion S2 side) of the semiconductor layer 20. The diffraction scattering section 52 is provided so as to overlap the photoelectric conversion section 24 for each photoelectric conversion region 21 in a plan view. The irregularities of the diffraction scattering section 52 are covered with an insulating film 54 provided on the first surface portion S1 side of the semiconductor layer 20.

The unevenness of the diffraction scattering section 52 acts as a diffraction grating, and high-order components are diffracted in an oblique direction, making it possible to lengthen the optical path length within the photoelectric conversion section 24, thereby improving the sensitivity of near-infrared light components in particular. Specifically, the diffraction scattering section 52 can be a quadrangular pyramid formed by wet etching the Si(111) surface using alkaline ionized water (AKW). In addition, the diffraction scattering section 52 may be formed by dry etching. Furthermore, by making the shape such that the cross-sectional area changes in the depth direction, reflection is suppressed and the sensitivity is slightly improved.

<Light-shielding film>
5 and 6, the light-shielding film 61 is provided on the side opposite to the semiconductor layer 20 side of the insulating film 54. The light-shielding film 61 has a lattice-like planar pattern in plan view that opens the light-receiving surface side of each of the multiple photoelectric conversion regions 21 so that light incident (penetrating) into a specific photoelectric conversion region 21 does not leak into an adjacent photoelectric conversion region 21. The light-shielding film 61 is configured with the same lattice-like planar pattern as the separation region 50, and is disposed at a position overlapping the separation region 50 in plan view. For example, a tungsten (W) film having light-shielding properties is used as the light-shielding film 61.

<Color filters and microlenses>
5 and 6, the color filters 62 are provided for each photoelectric conversion region 21 (sensor pixel 3) on the side (light incident surface side) opposite to the semiconductor layer 20 side of the light shielding film 61. The color filters 62 separate the incident light from the light incident surface side of the semiconductor chip 2 into colors. The color filters 62 include a first color filter of red (R), a second color filter of green (G), and a third color filter of blue (B). In this first embodiment, for example, the color filters 62 of three colors, R, G, and B, are provided.

The microlens 63 is provided for each photoelectric conversion region 21 (sensor pixel 3) on the side opposite to the light-shielding film 61 side (light incident side) of the color filter 62. The microlens 63 focuses the irradiated light and allows the focused light to efficiently enter the photoelectric conversion region 21.

<Light shield>
6, the light shield 30 is provided on the first surface S1 side of the semiconductor layer 20. The light shield 30 is provided across the isolation region 50 and the multi-layer wiring layer 40 in the thickness direction (Z direction) of the semiconductor layer 20, and is made of a metal film having a higher extinction coefficient than the semiconductor layer 20. For example, a tungsten (W) film having light shielding properties is used as the light shield 30. The tungsten film has a higher refractive index than semiconductor materials such as Si, SiGe, and InGaAs.

6, the light shield 30 has a buried portion (first portion) 31a located in the isolation region 50 in the thickness direction (Z direction) of the semiconductor layer 20 and surrounded by the insulating film 54a of the isolation region 50, and a protruding portion (second portion) 30b protruding from the buried portion 31a into the wiring layer 40 and surrounded by the interlayer insulating film 41 of the multilayer wiring layer 40. The buried portion 31a of the light shield 30 is adjacent to the photoelectric conversion region 21 of the semiconductor layer 20 via the insulating film 54a of the isolation region 50 in the direction perpendicular to the thickness direction (Z direction) of the semiconductor layer 20.

The light shield 30 has a lattice-like planar pattern in plan view that opens the light receiving surface side of each of the multiple photoelectric conversion regions 21, as shown in FIG. 4, so that light that is incident from the light incident surface side (second surface S2 side) of the semiconductor layer 20 and transmitted through a specific photoelectric conversion region 21 is not reflected by the wiring of the multilayer wiring layer 40 or the gate electrode of the pixel transistor and does not enter an adjacent photoelectric conversion region 21 different from the specific photoelectric conversion region 21 as unwanted light. The light shield 30 has a lattice-like planar pattern similar to the separation region 50 of the lattice-like planar pattern, and overlaps with the separation region 50 in plan view.

Specifically, as shown in FIG. 4, the light shielding body 30 includes a first portion 3x extending in the X direction in a plan view and a second portion 30y extending in the Y direction. The first portion 30x and the second portion 30y are perpendicular to each other. The first portion 30x is repeatedly arranged in the Y direction with the same arrangement pitch as the first portion 50x of the separation region 50, and the second portion 30y is repeatedly arranged in the X direction with the same arrangement pitch as the second portion 50y of the separation region 50. The first portion 30x of the light shielding body 30 overlaps with the first portion 50x of the separation region 50 in a plan view, and the second portion 30y of the light shielding body 30 overlaps with the second portion 50y of the separation region 50 in a plan view.

The light shielding body 30 corresponding to multiple photoelectric conversion regions 21 has a lattice-like planar pattern, while the light shielding body 30 corresponding to one photoelectric conversion region 21 has an annular planar pattern that surrounds the periphery of one photoelectric conversion region 21. In addition, the light shielding body 30 of this first embodiment continuously surrounds the periphery of one photoelectric conversion region 21 in an annular (ring-like) shape in a planar view.

<Reflection of oblique light and blocking of reflected light>
Next, the reflection of oblique light 71 at the separation region 50 and the blocking of the reflected light at the light blocking body 30 will be described with reference to FIG. 7 and FIGS. 8A to 8D.
FIG. 7 is a vertical cross-sectional view that typically illustrates oblique light 71 in the photoelectric conversion region 21 and light reflected on the multilayer wiring layer 40 side of the photoelectric conversion region 21 (semiconductor layer 20).
FIG. 8A is a diagram for explaining the reflection of oblique light 71 on the side of isolation region 50 opposite to multilayer wiring layer 40 side (light incident surface side of semiconductor layer 20) in FIG.
8B is a diagram for explaining the reflection of oblique light 71 on the multilayer wiring layer 40 side (the first surface S1 side of the semiconductor layer 20) of the isolation region 50 in FIG. 7, and the absorption of the reflected light on the multilayer wiring layer 40 side of the semiconductor layer 20.
FIG. 8C is a diagram for explaining the embedding depth (embedding height) of the light shielding body 30 embedded in the isolation region 50 in FIG.
FIG. 8D is a plan view showing the diagonal direction of the photoelectric conversion region in a plan view.
It should be noted that FIG. 7 is upside down compared to FIG.

<Reflection of oblique light in separation area>
First, the reflection of the oblique light 71 at the separation region 50 will be described.

7, incident light 70 passes through the microlens 63, the color filter 62, the insulating film 54, the diffractive scattering portion 52, etc., and enters the photoelectric conversion region 21 from the second surface portion S2 side (light incident surface side) of the semiconductor layer 20. At this time, in the photoelectric conversion region 21, oblique light 71 is generated from the incident light 70 due to collection by the microlens 63 and scattering by the diffractive scattering portion 52.
As shown in Figure 8A, oblique light 71 generated in the photoelectric conversion region 21 is irradiated (hits) on the interface If between the photoelectric conversion region 21 and the insulating film 54a of the isolation region 50 on the light incident surface side of the semiconductor layer 20 (the side opposite to the multilayer wiring layer 40 side of the semiconductor layer 20).

Here, as shown in FIG.
The refractive index of the photoelectric conversion region 21 (semiconductor layer 20) is n2,
The refractive index of the insulating film (dielectric) 54a of the isolation region 50 is n1,
The angle formed at the interface If between a virtual line La perpendicular to the thickness direction (Z direction) of the photoelectric conversion region 21 (semiconductor layer 20) and oblique light 71 irradiated to the interface If is defined as θ,
When n2>n1,
If the oblique light 71 satisfies Sinθ>n1/n2, then
Oblique light 71 irradiated onto the interface If between the photoelectric conversion region 21 and the insulating film 54 of the separation region 50 is totally reflected toward the photoelectric conversion region 21 and returns to the photoelectric conversion region 21 .

The generated oblique light 71 is irradiated (hits) on the interface If between the photoelectric conversion region 21 and the insulating film 54a of the isolation region 50 on the multilayer wiring layer 40 side of the photoelectric conversion region 21 (the multilayer wiring layer 40 side of the semiconductor layer 20) as shown in FIG. 8B. If "Sinθ>n1/n2" when "n2>n1", the oblique light 71 irradiated on this interface If is also totally reflected toward the photoelectric conversion region 21 and returns to the photoelectric conversion region 21.

In this first embodiment, the photoelectric conversion region 21 is silicon, the insulating film 54 of the separation region 50 is silicon oxide, and the refractive index of silicon oxide is lower than that of silicon, so in this case, "n2>n1", and for light with a wavelength of 940 nm, when "θ>19.5°", "Sinθ>n1/n2" is satisfied. Therefore, by using an insulating film 54a with a refractive index (n1) lower than the refractive index (n2) of the semiconductor layer 20 as the light reflector contained in the separation region 50, the oblique light 71 irradiated to the interface If between the photoelectric conversion region 21 and the insulating film 54 of the separation region 50 is totally reflected from the second surface S2 side (light incident surface side) of the semiconductor layer 20 to the first surface S1 side (multilayer wiring layer 40 side) toward the photoelectric conversion region 21 when "θ>19.5°" is satisfied, and returns to the photoelectric conversion region 21, so that a decrease in sensitivity can be suppressed.

In addition, since the refractive index of air is lower than that of silicon, when the refractive index n1 is air, "Sinθ>n2/n1" is satisfied when "θ>13.8°" for light with a wavelength of 940 nm. Therefore, even when air is used as the light reflector contained in the separation region 50, the oblique light 71 irradiated to the interface If between the photoelectric conversion region 21 and the insulating film 54a of the separation region 50 is totally reflected from the second surface S2 side (light incident surface side) of the semiconductor layer 20 to the first surface S1 side (multilayer wiring layer 40 side) toward the photoelectric conversion region 21 when "θ>13.8°" is satisfied, and returns to the photoelectric conversion region 21, so that a decrease in sensitivity can be suppressed.

As an example, for light with a wavelength of 940 nm, silicon has a refractive index (n2) of, for example, about 3.62, silicon oxide has a refractive index (n1) of, for example, about 1.45, and air has a refractive index (n1) of, for example, about 1.00.
As another example, for light with a wavelength of 550 nm, silicon has a refractive index (n2) of, for example, about 4.08, silicon oxide has a refractive index (n1) of, for example, about 1.46, and air has a refractive index (n1) of, for example, about 1.00.

For any wavelength of light, n2>n1 is satisfied.

<Shielding reflected light>
Next, a description will be given of the blocking of reflected light by the light blocking body 30. Here, a gate reflected light 72 reflected by the gate electrode 26t of the transfer transistor TR will be described as an example of the reflected light reflected on the multilayer wiring layer 40 side of the semiconductor layer 20.

7, oblique light 71 generated in the photoelectric conversion region 21 is reflected by the gate electrode 26t of the transfer transistor TR provided on the first surface S1 side of the semiconductor layer 20. Then, gate-reflected light 72 reflected by the gate electrode 26t is transmitted again through a predetermined photoelectric conversion region 21 and is irradiated onto the interface If.
Now, referring to FIG. 8B,
The refractive index of the photoelectric conversion region 21 (semiconductor layer 20) is n2, and the extinction coefficient is k2.
The refractive index of the insulating film (dielectric) 54a of the isolation region 50 is n1, and the extinction coefficient is k1.
The extinction coefficient of the light blocking body 30 is k3,
The angle formed at the interface If between a virtual line Lb perpendicular to the thickness direction (Z direction) of the semiconductor layer 20 and the gate reflected light 72 irradiated to the interface If is defined as θ1,
When n1>n2, k3>k1, and k3>k2,
The gate reflected light 72 of Sin θ1<n2/n1 is transmitted through the insulating film 54a of the isolation region 50 and is irradiated (impinges) on the buried portion 30a of the light shield 30. The gate reflected light 72 irradiated on the buried portion 30a is absorbed (shielded) by this buried portion 30a.

That is, oblique light 71 generated in the photoelectric conversion region 21 is reflected by the gate electrode 26t of the transfer transistor TR, and the gate reflected light 72 reflected by this gate electrode 26t passes through the specified photoelectric conversion region 21 again, and then passes through the insulating film 54a of the separation region 50 to be irradiated onto the buried portion 30a of the light shield 30, where it is absorbed (blocked) by this buried portion 30a.

Therefore, the buried portion 30a of the light shield 30 can suppress the phenomenon in which the gate reflected light 72 reflected by the gate electrode 26t enters (penetrates) as unwanted light into an adjacent photoelectric conversion region 21 (21a) different from the specified photoelectric conversion region 21. This can suppress color mixing.

It is preferable to use a material with a high extinction coefficient k for the wavelength of light used as the light shield 30. In this first embodiment, for example, a tungsten (W) film with a high extinction coefficient k for visible light and near-infrared light is used as the light shield 30.

In addition, since the refractive index of air is lower than that of silicon, even when air is used as the light reflector contained in the separation region 50, the phenomenon in which the gate reflected light 72 reflected by the gate electrode 26t is incident as unwanted light on an adjacent photoelectric conversion region 21 (21a) different from the specified photoelectric conversion region 21 can be suppressed by the buried portion 30a of the light shield 30. This makes it possible to suppress color mixing.

<Depth of buried part of light shielding body>
Next, the depth _X1 of the embedded portion 30a of the light blocking body 30 will be described with reference to FIGS. 8C and 8D. FIG.
The depth _X1 of the embedded portion 30a of the light shield 30 is the depth from the first surface S1 of the semiconductor layer 20 toward the semiconductor layer 20. The height _X2 of the protruding portion 30b of the light shield 30 is the height from the first surface S1 of the semiconductor layer 20 toward the multilayer wiring layer 40.
As shown in FIG.
The depth of the embedded portion 30a of the light shielding body 30 is _X1 .
The length from the light shield 30 to the starting point _P1 of the gate reflected light 72 is defined as _Y1 .
When the angle formed by a virtual line Lc perpendicular to the thickness direction (Z direction) of the photoelectric conversion region 21 (semiconductor layer 20) and the gate reflected light 72 irradiated to the interface If is _θ0 ,
The depth _X1 of the embedded portion 30a of the light blocking body 30 is determined by " _X1 > _Y1 ×tan _θ0 ".
Then, referring to FIG. 8D , the maximum value of _Y1 is the length in a diagonal direction Dg connecting two corners 21c located on opposite sides of the photoelectric conversion region 21 in a plan view, and therefore the depth _X1 of the embedded portion 30a of the light shielding body 30 satisfies the following conditions 1 and 2.
Condition 1: Depth of _X1 > _Y1 ×tan 19.5° or more (when n1 is silicon oxide)
Condition 2: Depth of _X1 > _Y1 ×tan 13.8° or more (when n1 is air)

Therefore, in the case where the insulating film 54a having a refractive index (n1) lower than the refractive index (n2) of the semiconductor layer 20 is used as the dielectric contained in the isolation region 50, by setting the depth _X1 of the embedded portion 30a of the light shield 30 as condition 1, the gate reflected light 72 which is reflected by the gate electrode 26t and transmitted again through the predetermined photoelectric conversion region 21 and further transmitted through the insulating film 54a in the isolation region 50 can be absorbed and blocked by the embedded portion 30a of the light shield 30.

Furthermore, in the case where air having a refractive index (n1) lower than the refractive index (n2) of the semiconductor layer 20 is used as the light reflector contained in the separation region 50, by setting the depth _X1 of the embedded portion 30a of the light shield 30 to satisfy the above-mentioned condition 2, the gate reflected light 72 which is reflected by the gate electrode 26t, transmitted again through the predetermined photoelectric conversion region 21, and further transmitted through the insulating film 54a in the separation region 50 can be absorbed and blocked by the embedded portion 30a of the light shield 30.

This makes it possible to suppress the phenomenon in which gate reflected light 72 reflected by the gate electrode 26t located on the multilayer wiring layer 40 side of a specified photoelectric conversion region 21 in a plan view is incident as unwanted light on an adjacent photoelectric conversion region 21 (21a) different from the specified photoelectric conversion region 21 by the embedded portion 30a of the light shield 30, thereby suppressing color mixing.

Incidentally, the reflected light of the oblique light 71 reflected on the multilayer wiring layer 40 side of the photoelectric conversion region 21 (semiconductor layer 20) also includes wiring reflected light reflected by the wiring of the multilayer wiring layer 40. By setting the depth _X1 of the embedded portion 30a of the light shield 30 to the above-mentioned condition 1 and condition 2, the phenomenon in which the wiring reflected light reflected by the wiring located on the multilayer wiring layer 40 side of a predetermined photoelectric conversion region 21 in a plan view is incident as unnecessary light on an adjacent photoelectric conversion region 21 (21a) different from the predetermined photoelectric conversion region 21 can be suppressed by the embedded portion 30a of the light shield 30, and color mixing can be suppressed.

Moreover, the light shield 30 of the first embodiment has a protruding portion 40b protruding from the buried portion 30a toward the multilayer wiring layer 40. Therefore, the protruding portion 30b of the light shield 30 can also block the wiring reflected light that is reflected by the wiring of the multilayer wiring layer 40 that overlaps with the predetermined photoelectric conversion region 21 in a plan view, passes through the multilayer wiring layer 40 again, and enters an adjacent photoelectric conversion region 21 (21a) different from the predetermined photoelectric conversion region 21. This makes it possible to further suppress color mixing. The effect of suppressing color mixing caused by wiring reflected light is proportional to the height _X2 of the protruding portion 30b of the light shield 30.

<<Main Effects of the First Embodiment>>
As described above, the solid-state imaging device 1A according to the first embodiment includes the isolation region 50 and the light shielding body 30.
The separation region 50 is provided in the recessed portion 51 of the semiconductor layer 20 across the first face portion S1 side and the second face portion S2 side of the semiconductor layer 20, and includes an insulating film 54a having a refractive index (n1) lower than the refractive index (n2) of the semiconductor layer 20. As a result, the oblique light 71 irradiated to the interface portion If between the photoelectric conversion region 21 and the insulating film 54 of the separation region 50 is totally reflected toward the photoelectric conversion region 21 across the second face portion S2 side (light incident surface side) of the semiconductor layer 20 to the first face portion S1 side (multilayer wiring layer 40 side), thereby suppressing a decrease in sensitivity.

The light shield 30 is provided across the isolation region 50 and the multi-layer wiring layer 40, and has an extinction coefficient (k3) higher than the extinction coefficient (k2) of the semiconductor layer 20. As a result, the embedded portion 30a of the light shield 30 can suppress the phenomenon in which the gate reflected light 72 reflected by the gate electrode 26t overlapping the specified photoelectric conversion region 21 in a planar view as reflected light reflected on the multi-layer wiring layer 40 side of the specified photoelectric conversion region 21 enters (penetrates) as unwanted light into an adjacent photoelectric conversion region 21 (21a) different from the specified photoelectric conversion region 21, thereby suppressing color mixing.

In addition, the phenomenon in which wiring reflected light reflected by the wiring of the multilayer wiring layer 40 that overlaps the specified photoelectric conversion region 21 in a planar view as reflected light is incident as unwanted light on an adjacent photoelectric conversion region 21 (21a) different from the specified photoelectric conversion region 21 can be suppressed by the embedded portion 30a and protruding portion 30b of the light shielding body 30, thereby suppressing color mixing.

Therefore, the solid-state imaging device 1A according to the first embodiment can suppress the decrease in sensitivity that causes deterioration in image quality, and can suppress color mixing that causes deterioration in image quality. Therefore, the solid-state imaging device 1A according to the first embodiment can achieve high image quality.

The light shield 30 according to the first embodiment surrounds the photoelectric conversion region 21 in a continuous ring shape in a plan view. This allows the light shield 30 to absorb gate reflected light 72 reflected by the gate electrode 26t of the transfer transistor TR and wiring reflected light reflected by the wiring of the multilayer wiring layer 40 over the entire circumference of the photoelectric conversion region 21, thereby further enhancing the effect of suppressing color mixing.

In recent years, there has been a demand in the market for high-resolution image sensors, and the development of image sensors with miniaturized sensor pixels 3 is underway. In order to miniaturize the sensor pixels 3, it is necessary to miniaturize the photoelectric conversion region 21 of the semiconductor layer 20. However, as the photoelectric conversion region 21 is miniaturized, the quantum efficiency QE decreases, so it is important to reflect more oblique light toward the photoelectric conversion region 21 at the interface If to increase the photoelectric conversion efficiency. Therefore, this technology is also effective in realizing high-resolution image sensors.

In the above-described first embodiment, the gate reflected light 72 reflected by the gate electrode 26t of the transfer transistor TR has been described as an example of the gate reflected light of the oblique light 71 reflected on the multilayer wiring layer 40 side of the photoelectric conversion region 21, but is not limited to this gate reflected light 72. For example, in addition to the gate reflected light 72 reflected by the gate electrode 26t of the transfer transistor TR, the gate reflected light may be the gate reflected light reflected by each of the gate electrodes (26r, 26a, 26s) of the reset transistor RST, the amplification transistor AMP, and the selection transistor SEL included in the pixel circuit 15. These gate reflected lights can also be blocked by the embedded portion 30a of the light shield 30.

<Modification of the First Embodiment>
<Modifications of the Planar Shape of the Light Shielding Body>
In the above-described first embodiment, the planar shape of the light shielding body 30 corresponding to one photoelectric conversion region 21 is described as a planar shape that continuously surrounds the periphery of the photoelectric conversion region 21 in a ring shape, but the planar shape of the light shielding body 30 is not limited to the above-described first embodiment.

(Variation 1)
For example, as shown in FIG. 9A, the light shields 30 corresponding to one photoelectric conversion region 21 may have a planar shape that is dotted in an annular shape surrounding the periphery of the photoelectric conversion region 21 in a plan view.

(Variation 2)
9B , the light shield 30 corresponding to one photoelectric conversion region 21 may have a planar shape surrounding part of the periphery of the pixel transistors (TR, RST, AMP, SEL). In this case, when a plurality of pixel transistors are grouped, the light shield 30 has a planar shape surrounding part of the periphery of the group.

<Modification of the protruding portion of the light blocking body>
In addition, in the above-described first embodiment, the height _X2 of the protruding portion 30b of the light shield 30 (the height protruding upward from the first surface portion S1 of the semiconductor layer 20) is set to a height at which the protruding portion 30b does not reach the first wiring layer M1. However, the height _X2 of the protruding portion 30b of the light shield 30 is not limited to the above-described first embodiment.

(Variation 3)
10, the height _X2 of the protruding portion 30b of the light shield 30 may be set to a height at which the protruding portion 30b is joined to the wiring 43 formed in the first wiring layer M1. In this case, color mixing caused by wiring reflected light reflected by the wiring in the first wiring layer M1 can be more effectively suppressed.

11, the height _X2 of the protruding portion 30b of the light shield 30 may be set to a height at which the protruding portion 30b is joined to the wiring 45 of the second wiring layer M2. In this case, color mixing caused by wiring reflected light reflected by the wiring 43 of the first wiring layer M1 and wiring reflected light reflected by the wiring 45 of the second wiring layer M2 can be suppressed more effectively than in the first embodiment.

In other words, by setting the height _X2 of the protruding portion 30b of the light shield 30 to the height at which the protruding portion 30b joins with the wiring of the nth wiring layer (n is a natural number), it is possible to suppress color mixing caused by wiring reflected light reflected by the wiring of the nth wiring layer, and when the nth layer is a natural number of 2 or more, it is possible to suppress color mixing caused by reflected light reflected by the wiring of a wiring layer lower than the nth layer. Therefore, it is possible to suppress color mixing more effectively than in the first embodiment.

Second Embodiment
A solid-state imaging device 1B according to the second embodiment of the present technology has a configuration basically similar to that of the solid-state imaging device 1A according to the above-described first embodiment, but differs in the following configuration.

That is, as shown in Figures 12 and 13, the solid-state imaging device 1B according to the second embodiment further includes wiring 43b in a circular planar pattern that continuously surrounds the periphery of the photoelectric conversion region 21 for each photoelectric conversion region 21. This wiring 43b is formed, for example, in the first wiring layer M1 of the multi-layer wiring layer 40, and the protruding portion 30b of the light shield 30 is continuously joined along the circular planar pattern of the wiring 43b. That is, the light shield 30 and the wiring 43b overlap each other in a planar view, surrounding the entire periphery of the photoelectric conversion region 21, and are electrically and mechanically joined to each other.

The solid-state imaging device 1B according to the second embodiment provides the same effects as the solid-state imaging device 1A according to the first embodiment described above.

The wiring 43b of the annular planar pattern is not limited to the first wiring layer M1 of the multilayer wiring layer 40, and may be formed in a second or higher wiring layer. However, when the wiring 43b of the annular planar pattern is formed in a second or higher wiring layer, the routing of the wiring connected to the pixel transistors (TR, RST, AMP, SEL) is restricted compared to when the wiring 43b of the annular planar pattern is formed in the first wiring layer M1, so that the wiring 43b of the annular planar pattern is preferably formed in the first wiring layer M1.
Furthermore, the wiring 43b of the annular planar pattern may surround only a portion of the photoelectric conversion region 21 rather than the entire periphery thereof in plan view.

In this second embodiment, color mixing can be more effectively suppressed and high resolution can be achieved.

Third Embodiment
A solid-state imaging device 1C according to the third embodiment of the present technology has a configuration basically similar to that of the solid-state imaging device 1B according to the above-described second embodiment, but the configuration of the multilayer wiring layer 40 is different.

That is, as shown in Figures 14 and 15, the multilayer wiring layer 40 of the solid-state imaging device 1C according to the third embodiment includes a light reflection plate 43c that partially covers the photoelectric conversion region 21 in a planar view. The light reflection plate 43c is provided inside the wiring 43b that is formed in a frame shape for one photoelectric conversion region 21, overlapping the photoelectric conversion region 21 in a planar view. The light reflection plate 43c is formed, for example, in the first wiring layer M1 of the multilayer wiring layer 40. The light reflection plate 43c is formed to be wider than the width of the wiring 43 connected to the pixel transistors (TR, RST, AMP, SEL) and the width of the frame-shaped wiring 43b.

It is preferable to use a material with a high reflectance for the wavelength of light used as the light reflection plate 43c. In this third embodiment, for example, an aluminum (Al) film with a high reflectance coefficient for visible light and near-infrared light is used as the light reflection plate 43c.

By providing such a light reflecting plate 43c, the oblique light 71 that passes through a specified photoelectric conversion region 21 and enters the multilayer wiring layer 40 can be reflected by the light reflecting plate 43c and returned to the specified photoelectric conversion region 21, thereby improving sensitivity.

In addition, the oblique light 71 is reflected by the light reflecting plate 43c, and the light reflected by this light reflecting plate 43c is blocked by the embedded portion 30a and the protruding portion 30b of the light shielding body 30 from entering an adjacent photoelectric conversion region 21 different from the specified photoelectric conversion region 21 as unwanted light, so that the sensitivity can be improved and color mixing can be suppressed.

The light reflecting plate 43c is preferably made of a material having a high reflectance with respect to the wavelength of light to be used. In the third embodiment, the light reflecting plate 43c is made of, for example, aluminum (Al) or silver (Ag), which has a high reflectance coefficient with respect to visible light and near infrared light.
In the third embodiment, it is possible to suppress color mixing and increase the quantum efficiency QE while achieving high resolution.

Fourth Embodiment
A solid-state imaging device 1D according to the fourth embodiment of the present technology has a configuration basically similar to that of the solid-state imaging device 1A according to the above-described first embodiment, but the configuration of the multilayer wiring layer 40 is different.

That is, as shown in Fig. 16 and Fig. 17, the multi-layer wiring layer 40 of the solid-state imaging device 1D according to the fourth embodiment includes a light reflection plate 43d that covers a plurality of photoelectric conversion regions 21 in a plan view. The light reflection plate 43d is provided across the photoelectric conversion regions 21 adjacent to each other in a plan view, and covers the photoelectric conversion regions 21 and the separation region 50. The light reflection plate 43d covers almost the entire photoelectric conversion region 21 for one photoelectric conversion region 21. The light reflection plate 43d is formed, for example, in the first wiring layer M1 of the multi-layer wiring layer 40. The light reflection plate 43d includes a through hole 43d ₁ through which a contact electrode 49 that electrically connects the wiring 45 of an upper wiring layer, for example, the second wiring layer M2, and the pixel transistors (TR, RST, AMP, SEL) penetrates. The light reflection plate 43d covers, for example, the entire pixel array section 2A.

As with the light reflecting plate 43c described above, it is preferable to use a material with a high refractive index for the wavelength of light used as the light reflecting plate 43d. In this fourth embodiment, for example, an aluminum (Al) or silver (Ag) film with a high reflection coefficient for visible light and near-infrared light is used as the light reflecting plate 43d.

By providing such a light reflecting plate 43d, the oblique light 71 that passes through a specified photoelectric conversion region 21 and enters the multilayer wiring layer 40 can be reflected by the light reflecting plate 43d and returned to the specified photoelectric conversion region 21, thereby improving sensitivity.

In addition, the oblique light 71 is reflected by the light reflecting plate 43d, and the light reflected by this light reflecting plate 43d is blocked by the embedded portion 30a and the protruding portion 30b of the light shielding body 30 from entering an adjacent photoelectric conversion region 21 different from the specified photoelectric conversion region 21 as unwanted light, so that the sensitivity can be improved and color mixing can be suppressed.

Fifth Embodiment
A solid-state imaging device 1E according to the fifth embodiment of the present technology has a configuration basically similar to that of the solid-state imaging device 1A according to the above-described first embodiment, but the configuration of the multilayer wiring layer 40 is different.

That is, as shown in Figures 18 and 19, the multilayer wiring layer 40 of the solid-state imaging device 1E according to the fifth embodiment includes a first wiring 43e provided in the first wiring layer M1, counting from the semiconductor layer 20 side, so as to overlap the photoelectric conversion region in a planar view, and a second wiring 45e provided in the second wiring layer M2, which is above the first wiring layer M1, so as to overlap the photoelectric conversion region 21 in a planar view and to intersect with the first wiring M1.

The first wiring 43e extends in the Y direction of the X direction and the Y direction that intersect each other in a two-dimensional plane that intersects with the thickness direction (Z direction) of the semiconductor layer 20, and is repeatedly arranged at a predetermined interval in the X direction. The second wiring 45e extends in the X direction and is repeatedly arranged at a predetermined interval in the Y direction. The arrangement pitch of each of the first wiring 43e and the second wiring 45e is preferably 1/4 or less of the wavelength to be used.

By providing such first wiring 43e and second wiring 45e, the oblique light 71 that passes through the specified photoelectric conversion region 21 and enters the multilayer wiring layer 40 can be reflected by the first wiring 43e and second wiring 45e and returned to the specified photoelectric conversion region 21, thereby improving sensitivity.

In addition, the oblique light 71 is reflected by the first wiring 43e and the second wiring 45e, and the light reflected by the first wiring 43e and the second wiring 45e is blocked by the embedded portion 30a and the protruding portion 30b of the light shielding body 30 from entering an adjacent photoelectric conversion region 21 different from the specified photoelectric conversion region 21 as unwanted light, so that the sensitivity can be improved and color mixing can be suppressed.

The first wiring 43e and the second wiring 45e are not limited to the first wiring layer M1 and the second wiring layer M2. That is, the multi-layer wiring layer 40 may include a first wiring 43e provided in an n-th wiring layer (n is a natural number) counting from the semiconductor layer 20 side so as to overlap the photoelectric conversion region 21 in a planar view, and a second wiring 45e provided in a wiring layer above the n-th wiring layer so as to overlap the photoelectric conversion region 21 in a planar view and intersect with the first wiring 43e. The first wiring 43e may extend in the Y direction (or X direction) of the X direction and Y direction intersecting each other in a two-dimensional plane intersecting the thickness direction (Z direction) of the semiconductor layer 20, and may be repeatedly arranged at a predetermined interval in the X direction (or Y direction), and the second wiring 45e may extend in the X direction (or Y direction) and may be repeatedly arranged at a predetermined interval in the Y direction (or X direction). In this case as well, it is preferable that the arrangement pitch of each of the first wirings 43e and the second wirings 45e is equal to or smaller than ¼ of the wavelength to be used.
In the fifth embodiment, it is possible to suppress color mixing, increase the quantum efficiency QE while realizing high resolution, and further to utilize each wiring layer as a signal line.

Sixth Embodiment
A solid-state imaging device 1F according to the sixth embodiment of the present technology has a configuration basically similar to that of the solid-state imaging device 1A according to the above-described first embodiment, but the configuration of the isolation region 50 is different.

That is, as shown in FIG. 20, the separation region 50 of the solid-state imaging device 1F according to the sixth embodiment includes a fixed charge film 53 provided along the inner wall (side wall and bottom wall) of a recessed portion 51 extending in the depth direction (Z direction) of the semiconductor layer 20, and an insulating film 54a provided in the recessed portion 51 via the fixed charge film 53 and serving as a light reflector having a refractive index lower than that of the semiconductor layer 20.

The fixed charge film 53 is provided across the second surface S2 of the semiconductor layer 20 and the recessed portion 51 of the semiconductor layer 20. The fixed charge film 53 includes, for example, a dielectric film that generates negative fixed charges. As this dielectric film, for example, hafnium oxide (HfO ₂ ) having a high dielectric constant can be used. This fixed charge film 53 induces holes (h ⁺ ) at the interface between the semiconductor layer 20 and the isolation region 50, and pinning at this interface can be ensured, so that the generation of dark current can be suppressed. As this dielectric film, zirconium oxide (ZrO ₂ ), tantalum oxide (Ta ₂ O ₅ ), etc. can also be used.

Since the thickness of the fixed charge film 53 is extremely thin compared to the thickness of the insulating film 54a, the fixed charge film 53 and the insulating film 54a can be regarded as a light reflector. Therefore, the present technology can be applied to a solid-state imaging device 1F including an isolation region 50 including the fixed charge film 53 and the insulating film 54a as a light reflector.
In the sixth embodiment, it is possible to suppress color mixing, increase the quantum efficiency QE while realizing high resolution, and further suppress noise components in the dark.

Seventh Embodiment
<Applications to electronic devices>
The present technology (technology related to the present disclosure) can be applied to various electronic devices, such as imaging devices such as digital still cameras and digital video cameras, mobile phones with imaging functions, or other devices with imaging functions.

Figure 21 is a diagram showing the schematic configuration of an electronic device (e.g., a camera) according to a seventh embodiment of the present technology.

As shown in FIG. 21, electronic device 100 includes solid-state imaging device 101, optical lens 102, shutter device 103, drive circuit 104, and signal processing circuit 105. This electronic device 100 illustrates an embodiment in which solid-state imaging devices 1 to 1F according to the first to sixth embodiments of the present technology are used as solid-state imaging device 101 in an electronic device (e.g., a camera).

The optical lens 102 focuses image light (incident light 106) from the subject on the imaging surface of the solid-state imaging device 101. This causes signal charges to accumulate in the solid-state imaging device 101 for a certain period of time. The shutter device 103 controls the light irradiation period and light blocking period for the solid-state imaging device 101. The drive circuit 104 supplies a drive signal that controls the transfer operation of the solid-state imaging device 101 and the shutter operation of the shutter device 103. The drive signal (timing signal) supplied from the drive circuit 104 transfers signals from the solid-state imaging device 101. The signal processing circuit 105 performs various signal processing on signals (pixel signals (image signals)) output from the solid-state imaging device 101. The video signals that have undergone signal processing are stored in a storage medium such as a memory, or output to a monitor.

This configuration allows the solid-state imaging device 201 to achieve high image quality, so the electronic device 100 of the seventh embodiment can also achieve high image quality.

The electronic device 100 to which the solid-state imaging device of the above-described embodiment can be applied is not limited to a camera, but can also be applied to other electronic devices. For example, the solid-state imaging device may be applied to an imaging device such as a camera module for mobile devices such as mobile phones and tablet terminals.

In addition to the solid-state imaging device as the image sensor described above, this technology can be applied to all light detection devices, including distance measuring sensors called ToF (Time of Flight) sensors that measure distance. A distance measuring sensor is a sensor that emits irradiation light toward an object, detects the reflected light that is reflected back from the surface of the object, and calculates the distance to the object based on the flight time from when the irradiation light is emitted to when the reflected light is received. The structure of the element isolation region described above can be adopted as the structure of the element isolation region of this distance measuring sensor.

The present technology may be configured as follows.
(1)
a semiconductor layer having a first surface and a second surface opposite each other;
an isolation region extending in a thickness direction of the semiconductor layer;
A plurality of photoelectric conversion regions partitioned by the separation regions;
a photoelectric conversion unit provided in each of the plurality of photoelectric conversion regions and configured to photoelectrically convert light incident from the second surface side of the semiconductor layer;
a light shield and a multilayer wiring layer provided on the first surface side of the semiconductor layer;
Equipped with
the separation region includes a light reflector that is provided in a carved portion of the semiconductor layer across the first surface side and the second surface side of the semiconductor layer and has a refractive index lower than that of the semiconductor layer;
The light-detecting device, wherein the light-shielding body is provided across the isolation region and the multilayer wiring layer, and has an extinction coefficient higher than that of the semiconductor layer.
(2)
The light detection device according to (1) above, wherein the light shield is joined to wiring in an n-th wiring layer (n is a natural number) counted from the semiconductor layer side of the multilayer wiring layer.
(3)
The light detection device according to (1) above, wherein the light shield is joined to a wiring in a first wiring layer counted from the semiconductor layer side of the multilayer wiring layer.
(4)
The light detection device according to any one of (1) to (3), wherein the light shielding body is adjacent to the semiconductor layer in the separation region via the light reflecting body.
(5)
The light detection device according to any one of (1) to (4), wherein the light shielding body surrounds the photoelectric conversion region in a planar view.
(6)
The light detection device according to (5) above, wherein the light blocking body is continuous or scattered in a ring shape in a plan view.
(7)
the photoelectric conversion region further includes a field effect transistor having a gate electrode provided on the first surface side of the semiconductor layer,
The photodetector according to any one of (1) to (4), wherein the light shield surrounds a part of the periphery of the pixel transistor in a plan view.
(8)
the light shield is joined to an n-th layer (n is a natural number) of wiring counted from the semiconductor layer side of the multilayer wiring layer,
The photodetector according to any one of (1) to (7) above, wherein the light shield and the wiring overlap each other in a planar view and surround the entire or part of the periphery of the photoelectric conversion region.
(9)
The photodetector according to any one of (1) to (8) above, wherein the multilayer wiring layer includes a light reflecting plate that partially covers the photoelectric conversion region in a plan view.
(10)
The photodetector according to any one of (1) to (8) above, wherein the multilayer wiring layer includes a light reflecting plate that covers a plurality of the photoelectric conversion regions in a planar view.
(11)
The multilayer wiring layer includes a first wiring provided in an n-th wiring layer (n is a natural number) counted from the semiconductor layer side so as to overlap the photoelectric conversion region in a plan view;
a second wiring provided in a wiring layer above the n-th wiring layer, the second wiring overlapping the photoelectric conversion region in a plan view and intersecting the first wiring;
the first wiring extends in the X direction out of an X direction and a Y direction intersecting each other in a two-dimensional plane intersecting a thickness direction of the semiconductor layer, and is repeatedly arranged at predetermined intervals in the Y direction;
The photodetector according to any one of (1) to (8) above, wherein the second wiring extends in the Y direction and is repeatedly arranged at predetermined intervals in the X direction.
(12)
The optical detection device according to any one of (1) to (11) above, wherein the optical reflector is a silicon oxide film or air.
(13)
an interface portion between the photoelectric conversion region and the separation region is denoted by If;
The angle formed at the interface between a virtual line perpendicular to the thickness direction of the photoelectric conversion region and the reflected light irradiated to the interface is defined as _θ0 ;
a depth from the first surface portion of the semiconductor layer toward the second surface portion of the semiconductor layer in a buried portion located in the isolation region of the light shield is defined as _X1 ;
When a diagonal length connecting two corners located on opposite sides of the photoelectric conversion region in a plan view is defined as _Y1 ,
When the light reflector is an oxide film, the depth _X1 of the embedded portion is
X ₁ > Y ₁ × tan 19.5° or more;
An optical detection device according to any one of (1) to (12) above.
(14)
an interface portion between the photoelectric conversion region and the separation region is denoted by If;
The angle formed at the interface between a virtual line perpendicular to the thickness direction of the photoelectric conversion region and the reflected light irradiated to the interface is defined as _θ0 ;
a depth from the first surface portion of the semiconductor layer toward the second surface portion of the semiconductor layer in a buried portion located in the isolation region of the light shield is defined as _X1 ;
When a diagonal length connecting two corners located on opposite sides of the photoelectric conversion region in a plan view is defined as _Y1 ,
When the light reflector is air, the depth _X1 of the embedded portion is
_X1 > _Y1 ×tan 13.8° or more;
An optical detection device according to any one of (1) to (12) above.
(15)
The photodetector according to any one of (1) to (14) above,
an optical lens that forms an image of image light from a subject on an imaging surface of the light detection device;
a signal processing circuit for processing a signal output from the photodetector;
An electronic device comprising:

The scope of the present technology is not limited to the exemplary embodiments shown and described, but includes all embodiments that achieve the same effect as the intended purpose of the present technology. Furthermore, the scope of the present technology is not limited to the combination of the features of the invention defined by the claims, but may be defined by any desired combination of specific features among all the respective features disclosed.

1A, 1B, 1C, 1D, 1E, 1F Solid-state imaging device 2 Semiconductor chip 2A Pixel array section 2B Peripheral section 3 Sensor pixel 4 Vertical drive circuit 5 Column signal processing circuit 6 Horizontal drive circuit 7 Output circuit 8 Control circuit 10 Pixel drive line 11 Vertical signal line 13 Logic circuit 14 Bonding pad 15 Pixel circuit (readout circuit)
20 Semiconductor layer 21 Photoelectric conversion region 22 P-type well region 23 N-type well region 24 Photoelectric conversion section 30 Light shielding body 31 Metal film 32 Cavity 40 Multilayer wiring layer 41 Interlayer insulating film M1 First wiring layer 43, 43b Wiring 43c, 43d Light reflecting plate 43d ₁ Through hole 43e First wiring 44 Interlayer insulating film M2 Second wiring layer 45 Wiring 45e Second wiring 46 Interlayer insulating film M3 Third wiring layer 47 Wiring 48 Interlayer insulating film 49 Contact electrode 50 Isolation region 51 Engraved portion 52 Diffraction scattering portion 53 Fixed charge film 61 Light shielding film 62 Color filter 63 Microlens AMP Amplification transistor RST Reset transistor SEL Selection transistor S1 First surface S2 Second surface TR Transfer transistor

Claims (15)

a semiconductor layer having a first surface and a second surface opposite each other;
an isolation region extending in a thickness direction of the semiconductor layer;
A plurality of photoelectric conversion regions partitioned by the separation regions;
a photoelectric conversion unit provided in each of the plurality of photoelectric conversion regions and configured to photoelectrically convert light incident from the second surface side of the semiconductor layer;
a light shield and a multilayer wiring layer provided on the first surface side of the semiconductor layer;
Equipped with
the separation region includes a light reflector that is provided in a carved portion of the semiconductor layer across the first surface side and the second surface side of the semiconductor layer and has a refractive index lower than that of the semiconductor layer;
The light-detecting device, wherein the light-shielding body is provided across the isolation region and the multilayer wiring layer, and has an extinction coefficient higher than that of the semiconductor layer. The photodetector according to claim 1, wherein the light shield is joined to the wiring of the nth wiring layer (n is a natural number) counted from the semiconductor layer side of the multilayer wiring layer. The photodetector according to claim 1, wherein the light shield is joined to the wiring of the first wiring layer counted from the semiconductor layer side of the multilayer wiring layer. The photodetector according to claim 1, wherein the light shielding body is adjacent to the semiconductor layer in the separation region via the light reflector. The light detection device according to claim 1, wherein the light shield surrounds the photoelectric conversion region in a plan view. The light detection device according to claim 5, wherein the light blocking body is continuous or scattered in a ring shape in a plan view. the photoelectric conversion region further includes a field effect transistor having a gate electrode provided on the first surface side of the semiconductor layer,
The light detection device according to claim 1 , wherein the light shielding body surrounds a part of a periphery of the pixel transistor in a plan view. the light shield is joined to an n-th layer (n is a natural number) of wiring counted from the semiconductor layer side of the multilayer wiring layer,
The photodetector according to claim 1 , wherein the light shield and the wiring overlap each other in a plan view and surround a whole or a part of the periphery of the photoelectric conversion region. The photodetector according to claim 1, wherein the multilayer wiring layer includes a light reflecting plate that partially covers the photoelectric conversion region in a plan view. The photodetector according to claim 1, wherein the multilayer wiring layer includes a light reflecting plate that covers a plurality of the photoelectric conversion regions in a plan view. The multilayer wiring layer includes a first wiring provided in an n-th wiring layer (n is a natural number) counted from the semiconductor layer side so as to overlap the photoelectric conversion region in a plan view;
a second wiring provided in a wiring layer above the n-th wiring layer, the second wiring overlapping the photoelectric conversion region in a plan view and intersecting the first wiring;
the first wiring extends in the X direction out of an X direction and a Y direction intersecting each other in a two-dimensional plane intersecting a thickness direction of the semiconductor layer, and is repeatedly arranged at predetermined intervals in the Y direction;
The photodetector according to claim 1 , wherein the second wirings extend in the Y direction and are repeatedly arranged at predetermined intervals in the X direction. The optical detection device according to claim 1, wherein the optical reflector is a silicon oxide film or air. an interface portion between the photoelectric conversion region and the separation region is denoted by If;
The angle formed at the interface between a virtual line perpendicular to the thickness direction of the photoelectric conversion region and the reflected light irradiated to the interface is defined as _θ0 ;
a depth from the first surface portion of the semiconductor layer toward the second surface portion of the semiconductor layer in a buried portion located in the isolation region of the light shield is defined as _X1 ;
When a diagonal length connecting two corners located on opposite sides of the photoelectric conversion region in a plan view is defined as _Y1 ,
When the light reflector is an oxide film, the depth _X1 of the embedded portion is
X ₁ > Y ₁ × tan 19.5° or more;
2. The optical detection device according to claim 1. an interface portion between the photoelectric conversion region and the separation region is denoted by If;
The angle formed at the interface between a virtual line perpendicular to the thickness direction of the photoelectric conversion region and the reflected light irradiated to the interface is defined as _θ0 ;
a depth from the first surface portion of the semiconductor layer toward the second surface portion of the semiconductor layer in a buried portion located in the isolation region of the light shield is defined as _X1 ;
When a diagonal length connecting two corners located on opposite sides of the photoelectric conversion region in a plan view is defined as _Y1 ,
When the light reflector is air, the depth _X1 of the embedded portion is
_X1 > _Y1 ×tan 13.8° or more;
2. The optical detection device according to claim 1. A photodetector;
an optical lens that forms an image of image light from a subject on an imaging surface of the light detection device;
a signal processing circuit for processing a signal output from the photodetector;
Equipped with
The light detection device includes:
a semiconductor layer having a first surface and a second surface opposite each other;
an isolation region extending in a thickness direction of the semiconductor layer;
A plurality of photoelectric conversion regions partitioned by the separation regions;
a photoelectric conversion unit provided in each of the plurality of photoelectric conversion regions and configured to photoelectrically convert light incident from the second surface side of the semiconductor layer;
a light shield and a multilayer wiring layer provided on the first surface side of the semiconductor layer;
Equipped with
the separation region includes a light reflector that is provided in a carved portion of the semiconductor layer across the first surface side and the second surface side of the semiconductor layer and has a refractive index lower than that of the semiconductor layer;
the light shield is provided across the isolation region and the multilayer wiring layer, and has a refractive index higher than that of the semiconductor layer.

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