JP2011165951A - Solid-state imaging element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging element suitable to effectively use incident light without making the structure complicated. <P>SOLUTION: The solid-state imaging element includes a pixel group arrayed on the same substrate and microlenses (65) provided to respective pixels (20) constituting the pixel group. The pixels (20) each have at least two light reception portions (41, 42) arrayed, and a microlens (65) of each pixel (20) has a main lens surface (65M) having positive refracting power to the incident light and a sub-lens surface (65S) having lower refracting power to the incident light than the positive refracting power. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device.

  2. Description of the Related Art Conventionally, for the purpose of expanding a dynamic range, a solid-state imaging device in which a high sensitivity light receiving portion and a low sensitivity light receiving portion are provided for each pixel has been proposed (see Patent Document 1 and the like).

  In particular, the solid-state imaging device described in Patent Document 1 is provided with an on-chip microlens on the pixel in order to increase the utilization efficiency of light incident on the pixel, and further, the light condensed by the on-chip microlens. An inner lens is provided between the on-chip microlens and the high-sensitivity light-receiving unit (see FIG. 1 of Patent Document 2).

Japanese Patent No. 4236168

  However, since the solid-state imaging device is usually manufactured by a semiconductor process, the manufacturing cost increases remarkably when the structure becomes complicated.

  Therefore, an object of the present invention is to provide a solid-state imaging device having a configuration suitable for effectively using incident light without complicating the structure.

  A solid-state imaging device exemplifying the present invention includes a pixel group arranged on the same substrate, and a microlens provided in each pixel constituting the pixel group, and each pixel includes at least two A light receiving portion is arranged, and the micro lens of each pixel has a main lens surface having a positive refractive power with respect to incident light and a refractive power weaker than the refractive power with respect to incident light. A sub lens surface is formed.

  According to the present invention, a solid-state imaging device having a configuration suitable for effectively using incident light is realized without complicating the structure.

The circuit diagram which shows schematic structure of a solid-state image sensor. FIG. 4 is a circuit diagram of each of a plurality of pixels 20. FIG. 3 is a schematic plan view when the pixel 20 arranged in the center of the imaging region 31 is viewed from the light incident side. FIG. 4 is a schematic cross-sectional view obtained by cutting the pixel 20 along the line A-A ′ of FIG. 3. FIG. 4 is a schematic cross-sectional view obtained by cutting the pixel 20 along line B-B ′ in FIG. 3 (when the connection / separation transistor 55 is off). FIG. 4 is a schematic cross-sectional view obtained by cutting the pixel 20 along line B-B ′ in FIG. 3 (when the connection / separation transistor 55 is on). The figure explaining the function of the pixel 20 (about the main lens 65M). The figure explaining the function of the pixel 20 (about the sub lens 65S). The figure explaining the function of the pixel 20 in which the crosstalk prevention measure was taken (about the main lens 65M). The figure explaining the function of the pixel 20 in which the crosstalk prevention measure was given (about the sub lens 65S). FIG. 4 is a diagram for explaining the structure of a pixel 20 arranged in the periphery of an imaging region 31. The figure explaining the function of the pixel 20 of the peripheral part (about the main lens 65M). The figure explaining the function of the pixel 20 of a peripheral part (about the sub lens 65S). The figure explaining the function of the pixel 20 when the refractive power of the sub lens surface 65S is made zero (about the main lens 65M). The figure explaining the function of the pixel 20 when the refractive power of the sub lens surface 65S is made into zero (about the sub lens 65S). The figure explaining the function of the pixel 20 of a peripheral part (when the refractive power of the sub lens 65S is zero).

[Embodiment]
Hereinafter, a solid-state imaging device will be described as an embodiment of the present invention.

  First, the overall configuration of the solid-state image sensor will be described.

  FIG. 1 is an overall circuit diagram of the solid-state imaging device. As shown in FIG. 1, the solid-state imaging device 3 includes an imaging region 31 in which a plurality of pixels 20 are arranged in a matrix, and a peripheral circuit for outputting a signal from each of the plurality of pixels 20. In FIG. 1, the number of pixels 20 arranged in the imaging region 31 is 4 × 4 = 16, but the actual number is much larger than that.

  Peripheral circuits of the solid-state imaging device 3 include a vertical scanning circuit 21, a horizontal scanning circuit 22, a driving signal line 23 connected to the vertical scanning circuit 21, a driving signal line 24 connected to the horizontal scanning circuit 22, A vertical signal line 25 that receives signals from a plurality of pixels 20, a constant current source 26 and a correlated double sampling circuit (CDS circuit) 27 connected to the vertical signal line 25, and a horizontal signal that receives signals output from the CDS circuit 27. A signal line 28 and an output amplifier 29 are provided.

  When the vertical scanning circuit 21 outputs a drive signal, each of the plurality of pixels 20 is driven by receiving the drive signal via the drive signal line 23 and outputs a signal generated by the pixel 20 to the vertical signal line 25. . Since a plurality of types of drive signals are output from the vertical scanning circuit 21, the same number of drive signal lines 23 as the number of types of drive signals are prepared.

  The signal output from each of the plurality of pixels 20 is subjected to noise removal by the CDS circuit 27. The signal after noise removal is output to the outside through the horizontal signal line 28 and the output amplifier 29 in accordance with the drive signal from the horizontal scanning circuit 22.

  FIG. 2 is a circuit diagram of each of the plurality of pixels 20. As shown in FIG. 2, the pixel 20 has two embedded photodiodes 41 and 42, a first charge storage portion 43 that accumulates charges transferred from the embedded photodiode 41, and charges transferred from the embedded photodiode 42. Charge accumulated from the second charge storage unit 44, the first transfer transistor 45 for transferring charge from the embedded photodiode 41 to the first charge storage unit 43, and the charge from the embedded photodiode 42 to the second charge storage unit 44 Transfer transistor 46, floating diffusion region (FD) 47, third transfer transistor 48 that transfers charges from first charge storage unit 43 to FD 47, and second charge storage unit 44 to FD 47. A fourth transfer transistor 49 for transferring charges to the output transistor, and an amplification transistor for outputting a signal corresponding to the charge amount of the FD The register 50, the FD reset transistor 51 that discharges the charge of the FD 47, the selection transistor 52 that outputs the signal of the amplification transistor 50 to the outside of the pixel 20, and the charge from the embedded photodiode 41 (unnecessary generated by the embedded photodiode 41 A first PD reset transistor 53 that discharges charges) and a second PD reset transistor 54 that discharges charges (unnecessary charges generated by the embedded photodiode 42) from the embedded photodiode 42 are provided. The pixel 20 also includes a connection / separation transistor 55 that performs electrical connection and separation between the two embedded photodiodes 41 and 42.

  First transfer transistor 45, second transfer transistor 46, third transfer transistor 48, fourth transfer transistor 49, amplification transistor 50, FD reset transistor 51, selection transistor 52, first PD transistor 53, second PD reset transistor 54. Each of the connection / separation transistor 55 is formed of a MOS transistor.

  Here, the characteristics of these transistors (excluding the amplification transistor 50) are assumed to be on (N-channel MOS transistor) that turns on when the gate electrode is high and off when the gate electrode is low.

  The gate electrode of the connection / separation transistor 55 is common among the plurality of pixels 20 on the same line, and the drive signal φPDB is supplied from the vertical scanning circuit 21 of FIG.

  If φPDB is high, the connection / separation transistor 55 is turned on, and the two embedded photodiodes 41 and 42 of the pixel 20 are electrically connected. As a result, the entire two embedded photodiodes 41 and 42 function as one photoelectric conversion unit.

  On the other hand, if φPDB is low, the connection / separation transistor 55 is turned off, and the two embedded photodiodes 41 and 42 of the pixel 20 are electrically separated. As a result, each of the two embedded photodiodes 41 and 42 functions as an individual photoelectric conversion unit.

  The charge generated by the embedded photodiode 41 is accumulated in the first charge storage unit 43 before being transferred to the FD 47, and the charge generated by the embedded photodiode 42 is transferred to the FD 47 before being transferred to the FD 47. 2 is stored in the charge storage unit 44.

  The first transfer transistor 45 transfers charge from the embedded photodiode 41 to the first charge storage unit 43, and the second transfer transistor 46 transfers charge from the embedded photodiode 42 to the second charge storage unit 44. To do.

  The gate electrode of the first transfer transistor 45 and the gate electrode of the second transfer transistor 46 are common, and the gate electrodes are also common among the plurality of pixels 20 on the same line. A common drive signal φTGA is supplied to these gate electrodes from the vertical scanning circuit 21 of FIG. The first transfer transistor 45 and the second transfer transistor 46 are simultaneously turned on at a predetermined timing in accordance with the drive signal φTGA, and the charges of the two embedded photodiodes 41 and 42 are charged at the same timing. Forward to.

  On the other hand, separate drive signals are supplied to the gate electrode of the third transfer transistor 48 and the gate electrode of the fourth transfer transistor 49. That is, the drive signal φTGB is supplied to the gate electrode of the third transfer transistor 48 from the vertical scanning circuit 21 of FIG. Another drive signal φTGC is supplied to the electrodes from the vertical scanning circuit 21 in FIG. 1 via another signal line of the drive signal line 23. Note that the gate electrode of the third transfer transistor 48 is common among the plurality of pixels 20 on the same line, and the gate electrode of the fourth transfer transistor 49 is common among the plurality of pixels 20 on the same line. is there.

  The third transfer transistor 48 and the fourth transfer transistor 49 are individually turned on at a predetermined timing in accordance with the drive signal φTGB and the drive signal φTGC, and the first charge storage unit 43 and the second charge storage unit 44 The charge is transferred to the FD 47 at an individual timing or at the same timing.

  The gate electrode of the selection transistor 52 is common among the plurality of pixels 20 on the same line, and the drive signal φS is supplied from the vertical scanning circuit 21 of FIG. The gate electrode of the FD reset transistor 51 is common among the plurality of pixels 20 on the same line, and the drive signal φFDR is supplied from the vertical scanning circuit 21 via the drive signal line 23.

  Further, the gate electrode of the first PD reset transistor 53 and the gate electrode of the second PD reset transistor 54 are common, and further, these gate electrodes are common among the plurality of pixels 20 on the same line. is there. A common drive signal φPDR is supplied to the gate electrodes from the vertical scanning circuit 21 via the drive signal line 23.

  In FIG. 2, one terminal of the embedded photodiode 41, one terminal of the embedded photodiode 42, one terminal of the charge storage unit 43, one terminal of the charge storage unit 44, and one of the FDs 47. Although the terminal is grounded for convenience, the terminal is actually set to the same potential as a P-type well 61 described later.

  Next, as a representative of the plurality of pixels 20, the structure of one pixel 20 arranged in the center of the imaging region 31 will be described in detail.

  FIG. 3 is a schematic plan view when the pixel 20 arranged in the center of the imaging region 31 is viewed from the light incident side. However, in FIG. 3, only representative elements are shown, and illustration of drive signal lines and the like is omitted.

  As shown in FIG. 3, an embedded photodiode 41 is formed at the center of the pixel 20, and the embedded photodiode 42 is placed on one side (the lower side in the drawing) of the embedded photodiode 41 with a certain gap. Is formed.

  On the other side (right side of the figure) of the embedded photodiode 41, a first charge storage portion 43 is formed with a certain gap, and on the same side (right side of the figure) of the embedded photodiode 42, Second charge storage portions 44 are formed at regular intervals.

  Among these, the opening of one embedded photodiode 41 is wider than the opening of the other embedded photodiode 42. The embedded photodiode 41 is used as a high sensitivity light receiving unit that detects incident light intensity with respect to the pixel 20 with high sensitivity, and the other embedded photodiode 42 has low sensitivity light receiving with which the incident light intensity with respect to the pixel 20 is detected with low sensitivity. Used as part. Hereinafter, the embedded photodiode 41 is referred to as “high sensitivity embedded photodiode 41”, and the embedded photodiode 42 is referred to as “low sensitivity embedded photodiode 42”.

  An on-chip microlens 65 is provided on the light incident side of the pixel 20, and the center of the on-chip microlens 65 is located at the center of the highly sensitive embedded photodiode 41.

  4 is a schematic cross-sectional view obtained by cutting the pixel 20 along the line AA ′ in FIG. 3, and FIG. 5 is a schematic cross-sectional view obtained by cutting the pixel 20 along the line BB ′ in FIG. 3. is there. In FIGS. 4 and 5, the drive signal lines are not shown.

  As shown in FIGS. 4 and 5, the pixel 20 is formed on an N-type silicon substrate 61. A P-type well 62 is provided in the silicon substrate 61. As shown in FIG. 5, an N-type charge storage layer 63 is formed in each of two different regions of the P-type well 62, and the charge storage of these N-type charge storage layers 63 is performed. A P-type depletion preventing layer 64 is added to the surface of the layer 63. Among these, one charge storage layer 63 constitutes a high sensitivity embedded photodiode 41, and the other charge storage layer 63 constitutes a low sensitivity embedded photodiode 42.

  As shown in FIG. 5, a gate electrode 67 is formed on the gap between the high sensitivity embedded photodiode 41 and the low sensitivity embedded photodiode 42 via a thin silicon oxide film 66. This gate electrode 67 constitutes the gate of a MOS transistor (connection / separation transistor 55) having the charge storage layer 63 of the high sensitivity embedded photodiode 41 and the charge storage layer 63 of the low sensitivity embedded photodiode 42 as source / drain.

  If the drive signal φPDB supplied to the gate electrode 67 is low, since the inversion layer cannot be formed in the channel region of the connection / separation transistor 55, the connection / separation transistor 55 is turned off. On the other hand, if the drive signal φPDB supplied to the gate electrode 67 is high, the inversion layer 69 is formed in the channel region of the connection / separation transistor 55, so that the connection / separation transistor 55 is turned on.

  Note that since the gate electrode 67 is made of a material having translucency with respect to the visible wavelength region, such as an ITO film, the light incident on the image 20 is not blocked by the gate electrode 67 and embedded with high sensitivity. The gap between the photodiodes 41 and 42 is also reached.

  Therefore, if the connection / separation transistor 55 is off, the inversion layer 69 does not appear in the gap between the high sensitivity embedded photodiodes 41 and 42 as shown in FIG. If the coupling / separation transistor 55 is turned on, an inversion layer 69 appears in the gap between the high sensitivity embedded photodiodes 41 and 42 as shown in FIG. Functions as one photoelectric conversion unit.

  When the connection / separation transistor 55 is turned off, the signals of the high sensitivity embedded photodiodes 41 and 42 are individually read out. When the connection / separation transistor 55 is turned on, the high sensitivity embedded photodiode 41, The 42 signals are read together (added).

  In addition, as shown in FIG. 4, a gate electrode 71 is formed on the gap between the high sensitivity embedded photodiode 41 and the first charge storage portion 43 with a thin silicon oxide film 66 interposed therebetween. Although not shown in FIG. 4, similarly, a gate electrode 71 is formed on the gap between the low-sensitivity embedded photodiode 42 and the second charge storage portion 44 via a thin silicon oxide film 66. Yes.

  The gate electrode 71 constitutes the gate of a MOS transistor (first transfer transistor 45) having the charge storage layer 63 of the high sensitivity embedded photodiode 41 and the first charge storage unit 43 as a source or drain. Although not appearing in FIG. 4, similarly, the gate electrode 71 is a MOS transistor having the charge storage layer 63 and the second charge storage portion 44 of the low-sensitivity embedded photodiode 42 as sources or drains (FIG. 2). Constitutes the gate of the second transfer transistor 46).

  Thus, since the gate of the first transfer transistor 45 and the gate of the second transfer transistor 46 are the common gate electrode 71, the first transfer transistor 45 and the second transfer transistor 46 are connected to the gate electrode 71. They are simultaneously turned on and off in accordance with the supplied drive signal φTGA. Therefore, the timing at which the charge of the high sensitivity embedded photodiode 41 is stored in the charge storage unit 43 coincides with the timing at which the charge of the low sensitivity embedded photodiode 42 is stored in the charge storage unit 44.

  As shown in FIG. 4, the gate electrode 71 of the first transfer transistor 45 is disposed so as to cover the upper portion of the N-type layer 73 of the first charge storage unit 43. This constitutes a MOS capacitor. Although not shown in FIG. 4, similarly, the gate electrode 71 of the second transfer transistor 46 is disposed so as to cover the upper portion of the N-type layer of the second charge storage unit 44. This constitutes a MOS capacitor.

  Further, as shown in FIG. 4, a gate electrode 78 is formed on the gap between the first charge storage portion 43 and the N-type diffusion layer 75 of the FD 47 via a thin silicon oxide film 66. The gate electrode 78 constitutes the gate of a MOS transistor (third transfer transistor 48) having the N-type layer 73 of the first charge storage unit 43 and the N-type diffusion region 75 of the FD 47 as source / drain. Although not shown in FIG. 4, similarly, another gate electrode is interposed on the gap between the second charge storage portion 44 and the N-type diffusion layer 75 of the FD 47 via a thin silicon oxide film 66. Is formed. This another gate electrode constitutes the gate of a MOS transistor (fourth transfer transistor 49 in FIG. 2) having the N-type layer of the second charge storage portion 44 and the N-type diffusion layer 75 of the FD 47 as the source or drain. .

  Thus, since the gates of the third transfer transistor 48 and the fourth transfer transistor 49 are separate gate electrodes, the third transfer transistor 48 and the fourth transfer transistor 49 are individually connected to these gate electrodes. The drive signals φTGB and φTGC are individually turned on and off according to the supplied drive signals φTGB and φTGC. Therefore, the timing at which the charge in the first charge storage unit 43 is transferred to the FD 47 and the timing at which the charge in the second charge storage unit 44 is transferred to the FD 47 can be individually set.

  Further, as shown in FIG. 4, an N-type layer 87 is formed on the side of the high-sensitivity embedded photodiode 41, and a thin silicon oxide is formed on the gap between the high-sensitivity embedded photodiode 41 and the N-type layer 87. A gate electrode 88 is formed via the film 66. The gate electrode 88 constitutes the gate of a MOS transistor (first PD reset transistor 53) having the charge storage layer 63 and the N-type layer 87 of the high sensitivity embedded photodiode 41 as sources / drains. Although not shown in FIG. 4, similarly, an N-type layer is formed on the side of the low-sensitivity embedded photodiode 42, and above the gap between the low-sensitivity embedded photodiode 42 and the N-type layer. Another gate electrode is formed through a thin silicon oxide film 66. This gate electrode constitutes the gate of the MOS transistor (second PD reset transistor 54 in FIG. 2) that sources / drains the charge storage layer 63 and the N-type layer of the low-sensitivity embedded photodiode 42.

  In addition, the gate electrode 88 of the first PD reset transistor 53 and the gate electrode of the second PD reset transistor 54 are connected to each other by wiring, and a common drive signal φPDR is supplied. Note that both gate electrodes may be shared in advance instead of being connected by wiring.

  The first PD reset transistor 53 has a function of discharging unnecessary charges generated by the high sensitivity embedded photodiode 41, and the second PD reset transistor 54 has an unnecessary function generated by the low sensitivity embedded photodiode 42. There is a function to discharge electric charge.

  Further, as shown in FIGS. 4 to 6, a thick silicon oxide film 70 is formed around the high-sensitivity embedded photodiodes 41 and 42 and the N-type layers, and the elements are separated from each other. .

  Further, a flattening film 79 is formed on the upper part (light incident side) of each element as shown in FIGS. 4 to 6, and a color filter layer 80 is formed on the surface of the flattening film 79. A planarizing film 81 is formed on the surface of the color filter layer 80, and an on-chip microlens 65 having a diameter of approximately the same size as the width of the pixel 20 is formed on the surface of the planarizing film 81.

  The on-chip microlens 65 is a spherical plano-convex lens (positive lens having a positive refractive power) that is convex with respect to the light incident side, and a concave portion is formed in the vicinity of the apex of the plano-convex lens. The wall surface of the recess is spherical. That is, the peripheral portion of the surface of the on-chip microlens 65 is a main lens surface 65M having a positive refractive power, and the central portion of the surface of the on-chip microlens 65 is a sub lens having a negative refractive power. It is a lens surface 65S.

  The on-chip microlens 65 having such a surface shape can be formed by a semiconductor process similar to a conventional on-chip microlens that does not have a concave portion (that is, the sub-lens surface 65S). In this semiconductor process, for example, a photoresist is formed on a silicon nitride film serving as a base of the on-chip microlens 65, the photoresist is exposed with an illuminance distribution corresponding to the surface shape of the on-chip microlens 65, and developed. This is a semiconductor process in which the silicon nitride film is etched using the photoresist remaining after development as an etching mask. Any known technique can be applied to the exposure and etching techniques.

  7 and 8 are diagrams for explaining the function of the pixel 20.

  First, as shown in FIG. 7, the center of curvature CM of the main lens surface 65M is located in the vicinity of the opening center of the high-sensitivity embedded photodiode 41 (that is, in the vicinity of the center of the pixel 20). Therefore, all of the imaging light beam incident on the main lens surface 65M when using the solid-state imaging device 3 enters the high-sensitivity embedded photodiode 41.

  Note that the “imaging beam” here refers to an imaging beam of a standard photographic lens applied to the solid-state imaging device 3, and an imaging beam incident on the central pixel 20 in the imaging region 31. Is an imaging light beam whose principal ray is parallel to the substrate normal.

  Further, as shown in FIG. 8, the center of curvature CS of the sub lens surface 65S is located on the substrate normal passing through the center of the aperture of the high sensitivity embedded photodiode 41 and above the sub lens surface 65S (light incident side). . Therefore, the imaging light beam incident on the sub-lens surface 65S when using the solid-state imaging device 3 is directed toward the opening of the highly sensitive embedded photodiode 41 and its periphery while diverging.

  Here, the radius of curvature of the sub-lens surface 65S is set to an optimum value so that the imaging light beam diverged from the sub-lens surface 65S can cover all the openings of the two embedded photodiodes without excess or deficiency. . Therefore, the light beam incident on the high-sensitivity embedded photodiode 41 in the imaging light beam is set as the light beam La, the light beam incident on the low-sensitivity embedded photodiode 42 is set as the light beam Lb, and the remaining light beam is set as Lc. The light beam Lc is a wasteful light beam that is not photoelectrically converted, but if the size of the radius of curvature of the sub-lens surface 65S is set to an optimum value, the light amount of the wasteful light beam should be minimized.

  Further, in the above on-chip microlens 65, the ratio of the area of the sub lens surface 65S viewed from the light incident side to the area of the main lens surface 65M viewed from the same side is set to a predetermined ratio. Yes. Therefore, the imaging light beam incident on the on-chip microlens 65 is distributed to the two embedded photodiodes at a predetermined ratio.

  The area ratio of the sub lens surface 65S to the area of the main lens surface 65M and the incident light amount ratio of the low sensitivity embedded photodiode 42 to the incident light amount of the high sensitivity embedded photodiode 41 are not necessarily equal, but the area ratio is Increasing it should increase the incident light ratio.

  Accordingly, the on-chip microlens 65 is a single lens, but maintains the utilization efficiency of the imaging light beam incident on the pixel 20 at a certain level or more, and the high-sensitivity embedded photodiode 41 and the low-sensitivity embedded photodiode 42. Therefore, the imaging light flux can be distributed at an appropriate ratio.

  In the pixel 20 described above, the divergence that has passed through the sub-lens surface 65S is set by setting the refractive index of the planarizing film 81, which is the formation destination of the on-chip microlens 65, higher than the refractive index of the on-chip microlens 65. Leakage (crosstalk) of light flux into adjacent pixels may be prevented. FIG. 9 and FIG. 10 are diagrams showing an example when the preventive measure is taken.

  In addition, other methods for suppressing crosstalk can be employed for the pixel 20 described above. For example, a groove (air gap) may be formed in the boundary portion between adjacent pixels in the planarizing film 81.

  Next, the structure of the pixels 20 arranged in the periphery of the imaging region 31 will be described.

  FIG. 11 is a diagram illustrating the structure of the pixels 20 arranged in the peripheral part of the imaging region 31. The structure of the pixel 20 arranged in the peripheral part of the imaging region 31 is basically the same as the structure of the pixel 20 arranged in the central part of the imaging region 31, but in order to reduce the shading of the solid-state imaging device 3. In addition, in the pixel 20 arranged in the peripheral portion, the formation position of the on-chip microlens 65 is different from that of the pixel 20 arranged in the central portion. Further, in the pixel 20 arranged in the peripheral portion, the formation position of the sub lens surface 65S on the on-chip microlens 65 is different from that of the pixel 20 arranged in the central portion.

  Specifically, the on-chip microlens 65 of the pixel 20 arranged in the periphery of the imaging region 31 is shifted toward the center of the imaging region 31, and the amount of deviation of the on-chip microlens 65 in each pixel 20 is The larger the pixel 20 is from the center of the imaging region 31, the larger the pixel 20 is.

  Further, the sub-lens 65S of the on-chip microlens 65 arranged in the periphery of the imaging region 31 is shifted toward the center of the imaging region 31, and the amount of deviation of the sub-lens 65S in each on-chip microlens 65 is as follows. The larger the on-chip micro lens 65 is, the larger the distance from the center of the imaging region 31 is.

  Hereinafter, one pixel 20 arranged in the peripheral part of the imaging region 31 will be described as a representative.

  FIGS. 12 and 13 are diagrams (schematic cross-sectional views obtained by cutting along the line B-B ′ in FIG. 11) for explaining the function of the pixel 20 located on the lower side of FIG. 11. In FIGS. 12 and 13, the left direction in the figure may be regarded as the center direction of the imaging region 31.

  In the pixel 20, the principal ray of the imaging light beam incident on the on-chip microlens 65 is inclined from the upper left to the lower right.

  In order to cope with such an inclination, as shown in FIG. 12, the center line L of the on-chip microlens 65 is shifted to the left side from the center line LP of the high-sensitivity embedded photodiode 41. "Line" refers to the substrate normal passing through the center.)

  Further, as shown in FIG. 12, the center line LS of the sub-lens 65 </ b> S is shifted further to the left than the center line L of the on-chip microlens 65 so as to correspond to the inclination of the imaging light beam.

  Therefore, when the tilted imaging light beam enters the main lens 65M, it is condensed toward the right side of the center line L of the on-chip microlens 65 as shown in FIG. The light is reliably incident on the sensitivity-embedded photodiode 41.

  Further, as shown in FIG. 13, the sub lens surface 65S formed on the left side of the center line L receives the tilted imaging light beam in a posture (or a posture close to the front), so that the imaging light beam is received. Light can be efficiently guided (in addition, when the center line LS of the sub lens 65S coincides with the center line L of the on-chip micro lens 65, the tilted imaging light beam is received in an oblique posture. Therefore, there is a possibility that the imaged light beam cannot be guided efficiently.)

  According to the above configuration, the light incident efficiency with respect to the high-sensitivity embedded photodiode 41 and the light incident efficiency with respect to the low-sensitivity embedded photodiode 42 of the pixel 20 disposed in the peripheral portion of the imaging region 31 can be maintained high. .

Therefore, the solid-state imaging device 3 can suppress both shading relating to the high sensitivity embedded photodiode 41 and shading relating to the low sensitivity embedded photodiode 42.
[Supplement]
In the pixel 20 described above, in order to give a difference in sensitivity between the two embedded photodiodes, a difference is provided in both the opening size and the incident light amount ratio of the two embedded photodiodes. A difference may be provided.

  In the pixel 20 described above, the refractive power of the sub lens surface 65S is set to be negative, but the refractive power of the sub lens surface 65S may be set to a positive value that is weaker than the refractive power of the main lens 65M. In this case, the sub lens surface 65S is a convex surface having a gentle curve.

  Alternatively, the refractive power of the sub lens surface 65S may be set to zero. In this case, the sub lens surface 65S is a flat surface. 14 and 15 are examples in the case where the refractive power of the sub lens surface 65S is zero. In this case, the structure of the on-chip microlens 65 is the simplest.

  Also in this case, it is desirable to shift the formation position of the sub lens surface 65S on the on-chip microlens 65 toward the center of the imaging region 31 in the pixels 20 located in the peripheral part of the imaging region 31. In that case, the sub-lens surface 65S is arranged so that the pixel 20 positioned in the peripheral portion of the imaging region 31 can receive the tilted imaging light beam in a posture (or a posture close to the front) as shown in FIG. It is necessary to tilt.

  Further, in the pixel 20 described above, a part of the light beam Lc (see FIGS. 8, 10, 13, and 15) of the imaging light beam diverged from the sub-lens surface 65 </ b> S is a useless light beam. If there is a degree of freedom in the layout within the pixel 20, useless light rays may be reduced or prevented by extending the high sensitivity embedded photodiode 41 to the incident position of the light rays Lc (in this case, however) The center of the high-sensitivity embedded photodiode 41 deviates from the center of the pixel 20).

  Further, in the pixel 20 described above, a part of the light beam Lc (see FIGS. 8, 10, 13, and 15) of the imaging light beam diverged from the sub-lens surface 65 </ b> S is a useless light beam. By shifting the formation position of the sub-lens surface 65S directly above the low-sensitivity embedded photodiode 42, useless light rays may be reduced or prevented.

  Further, in the pixel 20 described above, a part of the light beam Lc (see FIGS. 8, 10, 13, and 15) of the imaging light beam diverged from the sub-lens surface 65 </ b> S is a useless light beam. When the layout in the pixel 20 has a degree of freedom, one or a plurality of other embedded photodiodes (low sensitivity embedded photodiodes) may be formed at the incident position of the light beam Lc, and the light beam Lc may be effectively used. .

  Moreover, although the solid-state imaging device 3 described above is a solid-state imaging device having only one microlens layer, the present invention can also be applied to a solid-state imaging device having two layers of microlenses. For example, in a solid-state imaging device having an outer lens and an inner lens, the above-described sub lens surface may be provided on the inner lens side.

  The solid-state imaging device 3 described above is a MOS type solid-state imaging device, but the present invention can also be applied to other types of solid-state imaging devices such as a CCD type.

65: On-chip micro lens, 65M: Main lens surface, 65S: Sub lens surface, 41: High sensitivity embedded photodiode, 42: Low sensitivity embedded photodiode

Claims (9)

A group of pixels arranged on the same substrate;
A microlens provided in each pixel constituting the pixel group,
In each of the pixels, two light receiving portions are arranged,
The micro lens of each pixel is formed with a main lens surface having a positive refractive power with respect to incident light and a sub lens surface having a refractive power weaker than the refractive power with respect to incident light. A solid-state image sensor characterized by comprising: The solid-state imaging device according to claim 1,
The main lens surface of each pixel guides incident light to only one of the two light receiving portions of the pixel,
The sub-lens surface of each of the pixels guides incident light to at least the other of the two light receiving portions of the pixel. The solid-state imaging device according to claim 2,
The main lens surface of each pixel is located at the periphery of the microlens of the pixel,
The sub-lens surface of each pixel is located in the center of the microlens of the pixel. The solid-state imaging device according to claim 3,
The main lens surface of each pixel guides incident light to only one of the two light receiving portions of the pixel,
The sub-lens surface of each pixel guides incident light to both of the two light receiving portions of the pixel. The solid-state imaging device according to claim 4,
The refractive power of the main lens surface of each pixel is positive,
The solid-state imaging device, wherein the refractive power of the sub-lens surface of each pixel is positive that is weaker than the refractive power of the main lens surface of the pixel. The solid-state imaging device according to claim 4,
The refractive power of the main lens surface of each pixel is positive,
The refractive power of the sub lens surface of each pixel is zero. The solid-state imaging device according to claim 5,
The refractive power of the main lens surface of each pixel is positive,
The solid-state imaging device, wherein the refractive power of the sub lens surface of each pixel is negative. In the solid-state image sensor according to any one of claims 1 to 7,
The solid-state image sensor, wherein the formation position of the microlens is shifted to the center side as the pixel is farther from the center of the imaging surface of the solid-state image sensor. In the solid-state imaging device according to any one of claims 1 to 8,
The solid-state image sensor, wherein the sub-lens surface forming position of the microlens is shifted to the center side as the pixel is farther from the center of the imaging surface of the solid-state image sensor.

Images