JP2024059045A - Manufacturing method of GSR element - Google Patents

Abstract

[Problem] To provide a manufacturing method of a GSR element using a highly visible alignment mark in the integration process of a magnetic field detection element and an application specific integrated circuit (ASIC). [Solution] The method employs a two-layer resin coating method in which resin coatings with different functions are formed in two separate steps on an ASIC substrate (20), and includes simultaneously forming a groove forming portion (22) that forms a groove (221) for arranging and fixing a magnetic wire (223) and an alignment mark forming portion (23) on the resin coating, and forming a second layer resin coating (225) on the flat surface obtained by polishing away unevenness originating from the ASIC substrate that remains on the first layer resin coating. [Selected Figure] Figure 2

Description

The present invention relates to a method for manufacturing a GSR element using highly visible alignment marks in the process of integrating a magnetic field detection element with an application specific integrated circuit (hereinafter referred to as ASIC).

High-sensitivity magnetic sensors include Hall sensors, GMR sensors, TMR sensors, high-frequency carrier sensors, FG sensors, MI sensors, GSR sensors, etc. Of these sensors, Hall sensors, GMR sensors, TMR sensors, and carrier sensors have been made smaller and thinner by integrating the element with an ASIC, but improving detection sensitivity remains an issue.
On the other hand, FG sensors, MI sensors, and GSR sensors have high sensitivity, but the element and ASIC are arranged separately and joined by wire bonding, making it difficult to reduce the thickness of the sensors.

In order to solve this problem, the present inventors have worked on developing technology for forming a GSR element on the surface of an ASIC, and as a result have achieved a smaller, thinner sensor (Patent Document 1).
Patent Document 1 discloses a thin, highly sensitive magnetic sensor in which an insulating resist is applied to the ASIC surface, a groove is formed therein in which a magnetic wire is disposed, and a GSR element consisting of a magnetic wire, a detection coil surrounding the magnetic wire, and electrodes is integrally formed on the ASIC surface. However, the technology for its manufacturing method has not been disclosed. Furthermore, although the manufacturing technology has been improved up to the present, it has not been disclosed.

On the other hand, to increase the sensitivity of the sensor, it is necessary to form a fine pitch coil and increase the number of turns in the coil. However, the finer the coil pitch, the more precisely it is required to align the position of the ASIC board and the position of the mask. To achieve this precision, highly visible alignment marks can be formed at the same time as the grooves are formed, which is expected to improve alignment precision.

Generally, alignment marks are formed on a _SiO2 film formed on a flat portion, so that high visibility can be easily obtained. Methods for forming alignment marks are disclosed in Patent Documents 2, 3, and 4, but none of them form alignment marks on a photosensitive resin.

JP 2019-191016 A JP 2006-229132 A JP 2009-004793 A Patent No. 2016776 Patent No. 5747294 Patent No. 6438616 Patent No. 3693119 Patent No. 4529783 Patent No. 4835805

2018 IEICE The Development of a High Sensitive Micro Size Magnetic Sensor Named as GSR Sensor Exited by GHz Pulse Current p.325 2020 JMMN The development of micro-coil-on-ASIC type GSR sensor driven by GHz Pulse current p.5

When integrating a GSR element onto an ASIC substrate, it is necessary to form a coil that wraps around the magnetic wire near the wire, and the groove shape for arranging the magnetic wire must be an inverted trapezoid. If a groove is created in an insulating film such as SiO2 using RIE (Reactive Ion Etching), the shape becomes rectangular, making it difficult to form the lower coil along the groove.

The formation of this inverted trapezoidal groove can be achieved by masking and exposing the groove to a positive resist resin film, developing it, and then applying a curing heat treatment. In other words, a positive resist resin film is essential to forming an inverted trapezoidal groove. Also, in this process, alignment marks are formed at the same time as the grooves to improve alignment accuracy. Therefore, the alignment marks are formed on the resin film, not on SiO2 as in the past.

However, the surface of an ASIC board usually has 2-3 μm irregularities (Figure 1) caused by the integrated circuit wiring, and even if a resin film is applied to the thickness required for groove formation (approximately 5-15 μm), the irregularities are transferred and remain on the surface, making it difficult to obtain the flat resin film required for alignment mark formation.

On the other hand, to increase the sensitivity of the sensor, it is necessary to reduce the coil pitch to 5 μm or less and increase the number of coil turns. However, the finer the coil pitch, the more precisely it is required to align the position of the ASIC board and the position of the multiple masks. To achieve this precision, an auto-alignment mechanism is necessary. The auto-alignment mechanism depends on the degree of contrast of the alignment mark image. As mentioned above, if there are irregularities on the surface of the ASIC board, the signal is disturbed and the contrast of the mark image is distorted. Therefore, if the mark is misrecognized and an attempt is made to form a fine coil with a coil pitch of 5 μm or less, the connection positions of the two will be misaligned when forming the upper coil after forming the lower coil, resulting in a problem of poor connection between the coils.

The present invention solves these problems by providing a manufacturing method for directly connecting a magnetic field detection element to an application specific integrated circuit (hereinafter referred to as ASIC), in which grooves for arranging magnetic wires and alignment marks with excellent contrast are simultaneously formed on a resin coating on an ASIC substrate with unevenness of several microns, and multiple GSR elements with detection coils formed with a fine coil pitch of 5 μm or less are integrally formed on the ASIC substrate.

Instead of the conventional method of applying a resin coating once, the inventors devised a two-layer resin coating method in which resin coatings with different functions are applied in two separate steps, and discovered that grooves and alignment marks can be formed simultaneously on the resin coating.

Here, the cross-sectional view of the GSR element fabricated on the ASIC substrate according to the present invention and the alignment mark used in the fabrication will be explained with reference to Figure 3. Each is illustrated one by one so that the relationship between the two can be understood, and the invention will be explained in detail below.
4A and 4B are plan and cross-sectional views of a groove forming portion and an alignment mark forming portion in a certain step of the manufacturing process.
As for the manufacture of the element alone, the present inventors have disclosed it in Japanese Patent No. 5747294 (Patent Documents 5 and 6) and presented it at an international academic conference (Non-Patent Documents 1 and 2), and Aichi Steel Corporation has disclosed Patent Documents 7, 8, and 9, etc., and it is a well-known technique.

First, the GSR element fabricated on the ASIC substrate and the alignment used in the fabrication will be described with reference to FIG.
The ASIC substrate 20 has an unevenness 201 of about 2 to 3 μm on its surface due to the integrated circuit wiring. Therefore, an alignment mark forming section 23 is required in addition to a normal groove forming section 22.

In the groove forming section (element forming section) 22, a first seat 211 is formed on the ASIC 20. An inverted trapezoidal groove 221 is formed in a second seat 212 constituting an element on its flat surface. A lower coil 222 is formed on the surface of the groove 221, and a magnetic wire 223 with an insulating glass coating is arranged on the upper part of the lower coil 222. The magnetic wire is fixed with resin and embedded in the groove 221.
An upper coil 224 is formed on the magnetic wire 223 via resin, and is connected to the lower coil 222 at both ends and wound around the magnetic wire 223 .
Wire electrodes are formed on both ends of the magnetic wire 223 and both ends of the surrounding coil.

In the alignment mark forming section 23, a first base 211 is formed on the ASIC 20. On the flat surface of the first base 211, a second base 212 constituting the alignment mark is formed, which has an alignment mark recess, which is a long, steep, pseudo-inverted trapezoid groove 231, and a metal film is formed on the surface of the recess. In addition, a reflective film made of a metal film is formed on the flat surface.

Use of these alignment marks enables accurate and precise alignment, and an auto-alignment mechanism enables formation of the lower coil and the upper coil with a coil pitch of 5 μm or less.
For example, when the coil pitch is 3 μm, if the coil width is 2.0 μm, the coil spacing is 1.0. Taking into account adjacent coils, accuracy of 0.5 μm or less is required.

Next, a groove forming portion and an alignment mark forming portion in a certain step of the manufacturing process will be described with reference to FIG.
1A is a plan view, and FIG. 1B is a cross-sectional view taken along line A1-A2 of the plan view of FIG.
A groove forming portion 32 and an alignment mark forming portion 33 are formed on an ASIC substrate 30. In the groove forming portion 32, a second pedestal consisting of an inverted trapezoid groove and a flat surface is formed on a first pedestal 311 having a flat upper surface.

The alignment mark section has an alignment mark recess, which is a long, inverted trapezoidal groove 331, formed on a first base 311 with a flat upper surface, and a second base 312 consisting of a flat surface.

The two-layer resin coating method of the present invention will now be described.
The first step is to form a first layer by applying a first resin film (negative resist) on the ASIC substrate having irregularities, place a flattened hard resin first pedestal under the inverted trapezoid groove and alignment mark, and remove the irregularities that occur in the first resin film. The irregularities on the other parts of the ASIC surface, where the first pedestal is not placed, are left as they are used as electrode wiring.

The second step is to apply a second resin film (positive resist) thicker than the depth of the groove onto the first pedestal to form a second layer, which becomes the second pedestal, and then simultaneously form an inverted trapezoid groove and a recess for an alignment mark in this second pedestal (the second resin film of the second layer), and then deposit a metal film on top of that.

Next, in each step, the first resin coating layer in the first step is preferably a polyimide-based negative resist because it is preferable to ensure that the top of the base is flat and that the edges of the base have a steep shape. However, a positive resist can also be used.
In addition, the second resin coating film, which is the second layer in the second step, is applied onto the planarized first pedestal, and it is necessary to use a positive resist in order to form an inverted trapezoidal groove after a curing heat treatment.

There was a concern about the adhesion between the heat-cured first resin of the first layer of the first base and the second resin coating of the second layer, but this was resolved by confirming that they were firmly integrated even though the resin types were different. In addition, the alignment mark portion is formed at the same time as the groove portion, so it has an inverted trapezoid shape like the groove portion. Therefore, by using this inverted trapezoid second base itself as a mask and digging into the first base by RIE, the steepness of the alignment mark recess is increased. Furthermore, by using a metal film as a reflective film, it is possible to improve the visibility of the alignment mark. By adopting a two-layer resin coating in this way, it is possible to remove unevenness that cannot be achieved with a one-layer structure.

In the first step, a first resin film is applied onto the uneven surface of the ASIC substrate to form first pedestals in the groove formation area and the alignment mark formation area, but unevenness occurs. Since the unevenness remains on the surface of the first pedestal even after the curing heat treatment, it is necessary to flatten the upper surface of the hardened first pedestal by CMP (Chemical-Mechanical Polishing).
This CMP may damage the electrodes of the ASIC, so it is preferable to apply a resist to the entire surface of the ASIC before CMP to protect the ASIC surface other than the pedestal, and then remove the resist with a resist remover after CMP to achieve flattening.

When a resin film is applied, the groove and alignment mark recess are exposed to light using a mask, developed, and then cured with heat, the groove changes from a rectangular shape to an inverted trapezoid, and the alignment mark recess also changes from a rectangular shape to an inverted trapezoid. This is the effect of using a positive resist resin film instead of a SiO2 film. Because the first base has already been flattened, the groove surface and alignment mark portion itself are smooth.

Here, the shape of the alignment mark recess also becomes an inverted trapezoid, so in order to make the edges of the alignment mark steeper, the area other than the alignment mark is protected with resist, and the alignment mark is etched by RIE using the inverted trapezoid second pedestal itself as a mask to engrave the first pedestal. At this time, since the second pedestal is also a resin coating, the etching selectivity of the RIE is roughly the same. Therefore, the amount of engraving is preferably 0.5 to 1.5 μm. Below 0.5 μm, the effect of steepening is small and no improvement in visibility is observed. Above 1.5 μm, the film loss of the second pedestal is large, affecting visibility.

In this state, however, the unevenness on the ASIC board is visible through the first resin and the second resin, making it impossible to ensure the high visibility contrast required for alignment.
Therefore, by forming a metal film on the alignment mark to enhance the reflection function, the visibility of the alignment mark can be improved. If the first pedestal is not flattened, the unevenness of the ASIC substrate cannot be eliminated even if the metal film is formed, and sufficient visibility of the alignment mark cannot be ensured. In other words, flattening the pedestal and forming a metal film to enhance the reflection function are essential. On the other hand, since the metal film needs to be formed to form the lower coil in the inverted trapezoid groove, it is desirable that the metal film of the alignment mark portion that enhances the reflection function and that of the lower coil are the same metal film. In addition, before forming the metal film, a negative resist-based resin film is applied to the groove portion, exposed to light, and developed to leave the resin film only in the groove portion, and an R-shape is formed at the bottom of the groove by a curing heat treatment, thereby preventing disconnection of the metal film.

The two-layer resin coating method makes it possible to simultaneously form grooves and alignment marks, and to form highly visible alignment marks on the resin coating.
The thickness of the first resin film forming the first pedestal of the first layer is preferably three times or more the irregularities (usually about 2 μm to 3 μm) of the ASIC surface in order to perform CMP.
The film thickness of the second resin in the second layer must be thicker than the minimum groove depth in order to enable groove formation (groove depth of about 5 μm to 10 μm).

The present invention makes it possible to simultaneously form an inverted trapezoidal groove for placing magnetic wires and a highly visible alignment mark on a resin coating without damaging the ASIC substrate, and by using this alignment mark, it becomes possible to integrally form a GSR element with a fine coil pitch of 5 μm or less, or even around 3 μm, on the ASIC substrate.

FIG. 2 is a diagram showing the uneven state of the surface of an ASIC substrate; 1 is a conceptual diagram of a GSR element and alignment marks fabricated on an ASIC substrate by a two-layer resin coating method. 1A and 1B are a plan view and a cross-sectional view showing an inverted trapezoidal groove and an alignment mark on an ASIC substrate. 1A and 1B are first and second flow diagrams showing cross-sectional views of a groove forming portion and an alignment mark for fabricating a GSR element. 11A and 11B are third and fourth flow charts showing cross-sectional views of a groove forming portion and an alignment mark for fabricating a GSR element. 5 and 6 are flow charts showing cross-sectional views of a groove forming portion and an alignment mark for fabricating a GSR element. 7A and 7B are flow charts showing cross-sectional views of a groove forming portion and an alignment mark for fabricating a GSR element. FIG. 1A shows alignment marks on the surface of an ASIC substrate before a metal film is formed, and marks and uneven signals on the A1-A2 line. FIG. 1B is a diagram showing the signal of the alignment mark on the C1-C2 line on the surface of the ASIC substrate after the metal film has been formed. 1 is a SEM photograph showing a 3.0 μm coil pitch produced according to the present invention and a SEM photograph showing a 5.5 μm coil pitch of a comparative example. 13 is a diagram showing the uneven state of the surface of the first pedestal after the CMP is performed. FIG.

The method for producing a GSR element of the present invention comprises the steps of:
A method for manufacturing a GSR element, which comprises a detection coil having a coil pitch of 5 μm or less, which is made up of a magnetic wire, a lower coil and an upper coil surrounding the magnetic wire, and electrode wiring, and is directly fabricated on a substrate of an application specific integrated circuit (hereinafter referred to as ASIC), comprising:
(1) applying a negative resist-based first resin coating onto the ASIC substrate to form a groove forming portion and an alignment mark forming portion first base made of a flat and hard resin;
(2) A second resin coating of a positive resist system having a thickness greater than the depth of the groove is applied onto the first pedestal to form a second pedestal, and a rectangular recess for forming an inverted trapezoid groove (hereinafter referred to as a groove) for arranging the magnetic wire is simultaneously formed in the groove forming portion of the second pedestal, and a recess for forming an alignment mark recess is simultaneously formed in the alignment mark forming portion, and the second pedestal is cured by a curing heat treatment to harden the second pedestal and form the inverted trapezoid groove and the alignment mark recess;
(3) applying a negative resist resin film to the groove portion, exposing and developing the resin film so that the resin film remains only in the groove portion, and forming an R-shape in the bottom of the groove by a curing heat treatment; and forming a metal film on the groove forming portion formed by the groove and on an alignment mark forming portion formed by an alignment mark recess;
(4) Using an alignment mark having high visibility, which is composed of the alignment mark recess on which the metal film of the alignment mark forming portion is formed and a reflective film formed on the flat surface of the alignment mark forming portion, a metal coating of the groove forming portion on which the metal film is formed is formed along the surface of the groove, forming the lower coil and an upper coil connection portion on the flat surface of the groove forming portion (hereinafter, the lower coil and the upper coil connection portion are referred to as the lower coil);
(5) disposing the magnetic wire on the lower coil in the groove, embedding the wire in the groove with resin and fixing the magnetic wire;
(6) forming the upper coil and the electrodes on the upper part of the resin using the alignment marks by an auto-alignment mechanism;
(7) The assembly of elements each consisting of the magnetic wire, the detection coil, and the electrodes is separated into individual pieces.

In addition, in the step (2) described in claim 1,
(2') A second resin coating of a positive resist system having a thickness greater than the depth of the groove is applied onto the first pedestal to form a second pedestal, and a rectangular recess for forming an inverted trapezoidal groove (hereinafter referred to as the groove) for positioning the magnetic wire is simultaneously formed in the groove forming portion of the second pedestal, and a long and narrow recess for forming a recess for an alignment mark is simultaneously formed in the alignment mark forming portion, and the groove and the recess for the alignment mark are formed while being hardened by a curing heat treatment, and further the recess for the alignment mark is formed by digging down to the first pedestal by RIE processing.

(5') The magnetic wire is placed on top of the lower coil in the groove with a tension of 30 to 100 kg/mm2, the magnetic wire is embedded in the groove with resin, and tension heat treatment is performed at a temperature of 250 to 350°C to fix the magnetic wire and improve the GSR characteristics.

The thickness of the negative resist-based first resin coating is at least three times the irregularities on the ASIC substrate.

Hereinafter, the best mode for carrying out the invention will be described in detail for each step with reference to FIGS.
In the first paragraph, the present invention relates to a method for directly fabricating a GSR element consisting of a magnetic wire, a detection coil, and electrodes on an ASIC board. Note that a magnetic detection element consisting of a magnetic wire, a detection coil, and electrodes and having a coil pitch of 5 μm or less is included in the technical concept of the present invention.

<Step (1)>
This will be explained with reference to Figures 4(a) to 4(h).
Reference numeral 4a indicates that unevenness 401a exists on the surface of the ASIC board 40a.
Hereinafter, the ASIC substrate will be denoted as 40x (x: b to h), the concaves and convexes as 401x (x: a to h), the groove formation portion as 4Gx (x: b to h), and the alignment mark formation portion as 4Ax (x: b to h).

In the step 4b, a negative resist-based first resin coating 41b is applied onto an ASIC substrate 40b, and then exposed and developed using a mask material by photolithography to form a first pedestal consisting of a groove forming section 4Gb for forming a groove for forming a GSR element and an alignment mark forming section 4Ab for forming an alignment mark. As a result, the first resin coating is disposed only on the portion that will become the first pedestal.
The irregularities 401b on the ASIC substrate 40b remain, by being transferred, on the first base made up of the groove forming portion 4Gb and the alignment mark forming portion 4Ab to which the first resin coating 41b is applied.

At this stage, the first resin film is subjected to a heat treatment for curing, and the first resin film is hardened. Even at this stage, the irregularities 401c on the ASIC 40c are transferred and remain on the surface of the first resin film 51c that will become the first pedestal.
The temperature for the curing heat treatment is 250 to 350° C. If the temperature is less than 250° C., the curing is insufficient, and there is a concern that the shape may change in a later process, whereas if the temperature exceeds 350° C., there is a concern that problems may occur in the ASIC circuit.

4d flattens the unevenness 401d remaining on the first resin coating 41d of the first base consisting of the groove forming portion 4Gc and the alignment mark forming portion 4Ac to which the unevenness 401c has been transferred and hardened, by CMP, to form a flat first base 1A consisting of the groove forming portion 4Gd and the alignment mark forming portion 4Ad.

In addition, in forming the first pedestal 1A, a resist may be applied to the entire surface of the ASIC substrate 40c, the resist on the first pedestal may be removed, the surface of the ASIC substrate other than the first pedestal may be protected, CMP may be performed to flatten the first pedestal, and the resist that was protecting the surface of the ASIC substrate other than the first pedestal may be peeled off.

The thickness of the first resin coating 41b that forms the first pedestal 1A is preferably at least three times the irregularities 401b on the surface of the ASIC substrate 40b on which the first pedestal is placed. If it is less than three times, the first pedestal itself will become thin before the irregularities 401c of the first pedestal are flattened by the CMP in this process.

FIG. 8 shows the irregularities on the surface of the first base 1A that has been planarized by CMP.
The 2 μm irregularities on the surface of the ASIC substrate shown in FIG. 1 were transferred and remained even after the first resin coating was applied and subjected to a curing heat treatment, but as shown in FIG. 8, it can be seen that the irregularities have been flattened to less than 0.02 μm by CMP of the first base.
The next step (2) is carried out using the first base A1 flattened to 0.02 μm or less.

<Step (2)>
In order to form the grooves and alignment marks, a second resin coating 42e thicker than the groove depth is applied to the first pedestal 1A. Since the first pedestal 1A is flattened, the second pedestal 1B, which forms the grooves and alignment marks, is not affected by the unevenness 401e of the ASIC substrate 40e. In other words, the second pedestal 1B has a flat surface.

The thickness of the second resin coating 42e is 7 μm to 17 μm, depending on the diameter of the magnetic wire to be placed in the groove. After that, exposure and development are performed using a mask material in which a pattern of grooves and multiple alignment marks is arranged. At this time, the shape of the groove is a rectangular recess (rectangular parallelepiped shape). The alignment marks are recesses.

4f is a curing heat treatment to harden the second resin coating 42e. The curing heat treatment temperature is 250°C to 350°C. If it is less than 250°C, the hardening will be insufficient, and there is a concern that the shape will change in subsequent processes. If it exceeds 350°C, there is a concern that malfunctions will occur in the ASIC circuit.

After the heat treatment, the shape of the groove changes from a rectangular parallelepiped to an inverted trapezoid 4Gf due to stress generated during the curing heat treatment. The upper surface of the second pedestal 1B remains flat, and the groove depth is 5 μm to 15 μm.
Similarly, the alignment mark recess also has an inverted trapezoid shape 44Af.

4g is preferably performed by first protecting the area other than the alignment mark forming area 4Ag with resist, and then performing oxygen RIE using the second base 1B of the alignment mark area as a mask to excavate an alignment mark recess in the first base 1A, thereby making the shape of the alignment mark recess 44Ag steeper.

<Step (3)>
4h is formed by applying a negative resist resin coating to the grooves, exposing and developing the resin coating to leave it only in the grooves, and then forming an R-shape 43h at the bottom of the grooves by a curing heat treatment, and then forming a metal film over the entire surface of the ASIC substrate 40h. This metal film (45G, 45A) is used as a reflective film (44Ah, 45A) in the alignment mark area, forming multiple alignment marks with high visibility. The thickness of the metal film is 0.2 μm to 1 μm.

FIG. 5 shows the alignment mark forming portion 44Ag before the metal film is formed, a plane of the alignment mark of the mask, and a waveform (signal) along the line B1-B2.
1A shows a plan view of an alignment mark forming portion 44Ag consisting of an alignment mark recess 44Ag which is formed by applying a first resin coating 41b applied to the surface of an ASIC substrate 40a and then subjecting it to a curing heat treatment 41b, planarizing it by CMP, applying a second resin coating 42e onto the flat surface 1A, and subjecting it to a curing heat treatment, as well as the alignment mark of the mask.
(b) shows the waveform (signal) on line B1-B2 of (a).

FIG. 6 shows the alignment mark forming portion 44Ah after the metal film is formed, a plane of the alignment mark of the mask, and a waveform (signal) along the line C1-C2.
1A shows an alignment mark 44Ah formed by depositing a metal film in an alignment mark forming portion 44Ag consisting of an alignment mark recess 44Ag, a plane of a reflective film 45A, and the alignment mark of the mask.
(b) shows the waveform (signal) at line C1-C2 of (a).

Before the metal film is formed, a flat and hard first base 1A is formed with a first resin coating in the area where the groove and alignment mark are to be located, but as shown in Figure 5(a), the contrast required for alignment is not secured.
It was presumed that this was because the wiring on the ASIC board 40g was visible through the resin coatings (first resin coating and second resin coating), and further, a metal film was formed over the entire surface of the ASIC board 40h.

This metal film also functions as a reflective film 45A for the alignment mark. As shown in FIG. 6(b), this alignment mark has high signal strength for both the alignment mark and the wafer mark, and there is no signal caused by steps, so it can be seen that it can be recognized without problems by the auto-alignment mechanism.

<Step (4)>
Using the highly visible alignment marks and metal film formed in the above process, the lower coil is formed along the inverted trapezoidal groove through resist coating, exposure, development, and etching processes.
Here, the lower coil includes the coil formed on the bottom and side surfaces of the inverted trapezoidal groove, as well as the coil formed on the flat surface of the groove forming portion, which simultaneously forms a connection with the upper coil.

<Step (5)>
A magnetic wire covered with insulating glass is placed on the lower coil formed in the groove, and is then embedded and fixed in place with resin.
When fixing the magnetic wire, it is preferable to apply a tension of 30 to 100 kg/mm2 to the magnetic wire and fix the embedding resin by curing at a temperature of 250 to 350° C. This improves the magnetic properties.
In addition, when using a magnetic wire that is not covered with insulating glass, it is preferable to apply an insulating resist to the surface of the lower coil before placing the magnetic wire, which makes it possible to prevent a short circuit between the lower coil and the metallic magnetic wire.

<Step (6)>
Using a highly visible alignment mark created by an auto-alignment mechanism on top of the resin that secures the magnetic wire, a 1-2 μm thick metal film is evaporated (or plated), resist is applied, exposed, developed, and etched to form an upper coil, producing the GSR element.
It is also preferable to form the electrodes and the wiring between the electrodes and the coil/magnetic wire at the same time. Prior to forming the wiring, the insulating glass coating on both ends of the magnetic wire is removed by CF4-RIE.

When forming the upper coil, the alignment accuracy between the alignment mark and the multiple masks is set to 1 μm or less, preferably 0.5 μm or less. At this time, the alignment mark has a first base 1A and a reflective film (metal film), so the signal strength is sufficient, and the lower coil and upper coil can be joined by auto-alignment without any problems.

FIG. 7 shows an SEM photograph of a 3.0 μm narrow pitch coil produced according to the present invention, together with a 5.5 μm pitch coil as a comparative example.
It is seen that a coil with a pitch of 3.0 μm can be formed without any misalignment between the upper coil and the lower coil.

The two-layer resin coating method is used to simultaneously form grooves and alignment marks in the resin coating on the ASIC substrate, and the manufacturing flow for a GSR element consisting of a narrow-pitch coil using highly visible alignment marks is described below with reference to Figures 4(a) to (h).

Step A) On the surface of the ASIC substrate 40a, there are irregularities 401a of several μm caused by the integrated circuit (FIG. 4A).
Step a) After a first resin film 41b is applied to an ASIC substrate 40b, exposure and development are carried out using a mask material to form the structure shown in FIG.
That is, a first pedestal is formed, which is composed of a groove forming portion 4Gb for forming a groove and an alignment mark forming portion 4Ab for forming an alignment mark recess.
As a result, the first resin coating 41b is disposed only on the portion that will become the first pedestal. At this time, the thickness of the first pedestal is 10 μm.

Step c) A curing heat treatment is performed at 280° C. for 1 hour to harden the first resin film 41c (FIG. 4(c)). Even at this point, the projections and recesses 401c of the ASIC substrate 40c remain transferred to the surface of the first resin film 41c that will become the first pedestal.
Step d) After applying resist to the entire ASIC board, exposure and development are carried out using a mask material to remove the resist on the first pedestal.

Step E) CMP is performed to flatten the first pedestal, forming the first pedestal 1A (FIG. 4(d)). The thickness of the first pedestal is 10 μm in step B), and even after the curing heat treatment, it is still about 8 μm thick, so there is no problem with CMP.
Step F) In order to form grooves and alignment marks, a second resin coating 42e having a thickness of 10 μm is applied onto the first pedestal 1A. Since the first pedestal 1A is flattened, the second pedestal 1B consisting of a groove forming portion 4Gf for forming the grooves and an alignment mark forming portion 4Af for forming the alignment marks is not affected by the unevenness 401e of the ASIC substrate 40e (FIG. 4(e)).

Step g) A curing heat treatment is performed at 280°C for 1 hour to harden the second resin coating 41f (Figure 4(g)). The heat treatment causes the grooves to deform from a rectangular parallelepiped shape (44Gf, 44Af) to an inverted trapezoid shape (44Gg, 44Ag) due to the stress generated during the curing heat treatment. The top surface of the second pedestal 1B remains flat. The depth of the groove is 8 μm.

Step H) In order to make the shape of the alignment mark recesses steeper, a resin is applied to the entire surface, and then exposure and development are performed using a mask to protect areas other than the areas where the alignment marks are to be formed with resist.
Using the second seat 1B of the alignment mark forming portion 4Ag as a mask, oxygen RIE is performed to excavate an alignment mark recess 44Ag in the first seat 1A, and the resist is peeled off (FIG. 4(g)). At this time, 18 alignment marks are formed.
Step I) A metal film was formed over the entire surface of the ASIC substrate (FIG. 4(h)). The thickness was 0.2 μm by metal deposition.

Step J) A resist was applied to the entire ASIC substrate, and exposure and development were carried out using a mask material in which a pattern for forming a lower coil in the groove and a pattern for protecting the alignment marks were arranged.
Step K) After plating the coil portion, the resist film is removed, and the metal film other than the coil portion is removed by etching. As a result, the metal film in the groove portion functions as the lower coil, and the metal film of the alignment mark functions as a reflective film. The width of the lower coil is 2.0 μm, and the thickness is 1.0 μm.

Process C) A CoFeB magnetic wire covered with 1 μm thick insulating glass is placed on the upper part of the lower coil of the groove with a tension of 50 kg/mm2, and after temporarily fixing it with adhesive, tape, etc., the magnetic wire is embedded in the groove with resin. Furthermore, this resin is hardened by a curing heat treatment at a temperature of 280° C., and the magnetic wire is fixed. At this time, the magnetic wire is heat-treated while tension is applied, so that the GSR characteristics can be improved.
Step S) To connect to the wiring of the magnetic wire electrodes, the insulating glass on both ends of the magnetic wire is removed by CF4-RIE to form conductive parts.

Process C) In order to eliminate the step between the groove and the wire, a positive resist resin film is applied, exposed, baked, developed, and then subjected to a curing heat treatment at 280°C for 1 hour to smooth out the shape of the upper part of the groove, after which a metal film is formed over the entire ASIC board and a resist is applied.
Process So) Exposure and development are carried out using a mask material on which a pattern for forming the upper coil of the groove and the lead wire (wiring) of the conductive part of the magnetic wire and a pattern for protecting the alignment part are arranged.
At this time, since the alignment mark has first base 1A and a reflective film, the signal strength is sufficient, and the connection part of the lower coil and the connection part of the upper coil can be aligned by automatic alignment without any problem.

Step T) After plating the coil portion, the resist film is removed and the metal film other than the coil portion is removed by etching. At this stage, the upper coil, electrodes, and lead wires (wiring) of the conductive portions of the magnetic wire are formed and function.
The upper coil has a width of 2.0 μm and a thickness of 1.0 μm. The coil connection portion consisting of the connection portion of the lower coil and the connection portion of the upper coil is formed with a line width of 2.0 μm and a coil pitch of 3.0 μm.

By using the above process, grooves and alignment marks can be simultaneously formed in the resin coating, and highly visible alignment marks can be formed on the resin coating, making it possible to integrally form a GSR element consisting of a fine pitch coil on an ASIC substrate.
FIG. 7 shows a SEM photograph (a) of a 3.0 μm coil pitch according to the present invention in comparison with a SEM photograph (b) of a conventional 5.5 μm coil pitch.

It becomes possible to integrally form a GSR element with a fine coil pitch on an ASIC substrate, which not only enables the GSR element to be made thinner and more compact, but also achieves even higher sensitivity.
This GSR sensor is expected to be applied to biomagnetism.

1: unevenness on the surface of the ASIC substrate 2: GSR element and alignment mark on the ASIC substrate 20: ASIC substrate, 201: unevenness on the ASIC substrate, 211: first resin coating (first pedestal 1A), 212: second resin coating (second pedestal 1B), 22: groove forming portion, 221: resin, 222: lower coil, 223: magnetic wire, 224: upper coil, 225: resin coating forming an R-shape at the bottom of the groove, 23: alignment mark forming portion, 231: alignment mark, 232: reflective film
3: Inverted trapezoid groove and alignment mark
30: ASIC substrate, 311: first resin coating (first base 1A), 312: second resin coating (second base 1B), 32: groove forming portion, 321: inverted trapezoid groove, 33: alignment mark forming portion, 331: elongated inverted trapezoid groove (alignment mark recess)

4a: uneven state of the surface of the ASIC substrate 40a: ASIC substrate, 401a: unevenness of the ASIC substrate 4b: ASIC substrate coated with a first resin coating 4Gb: groove formation portion, 4Ab: alignment mark formation portion 40b: ASIC substrate, 401b: unevenness of the ASIC substrate
4c: ASIC substrate subjected to first resin coating curing heat treatment 4Gc: groove forming portion, 4Ac: alignment mark forming portion 40c: ASIC substrate, 401c: unevenness of ASIC substrate, 41c: first resin coating subjected to curing treatment 4d: ASIC substrate subjected to CMP 4Gd: groove forming portion, 4Ad: alignment mark forming portion 40d: ASIC substrate, 401d: unevenness of ASIC substrate, 41d: first resin coating flattened after CMP (first pedestal 1A)
4e: ASIC substrate coated with second resin coating 4Ge: groove forming portion, 4Ae: alignment mark forming portion 40e: ASIC substrate, 41e: first resin coating (first pedestal 1A), 42e: second resin coating, 1B: second pedestal consisting of a flat surface 4f: ASIC substrate with a groove formed in the second resin coating 4Gf: groove forming portion, 4Af: alignment mark forming portion 40f: ASIC substrate, 401f: unevenness of the ASIC substrate, 41f: first resin coating (first pedestal 1A), 42f: cured second resin coating, 44Gf: rectangular groove, 44Af: elongated rectangular groove 4g: ASIC substrate with the second resin coating with the groove formed therein cured 4Gg: groove forming portion, 4Ag: alignment Alignment mark forming portion 40g: ASIC substrate, 401g: unevenness of ASIC substrate, 41g: first resin coating (first pedestal 1A), 42g: cured second dendritic coating, 44Gg: inverted trapezoid groove, 44Ag: elongated inverted trapezoid groove 4h: ASIC substrate on which metal film is formed 4Gh: groove forming portion, 4Ah: alignment mark forming portion 40h: ASIC substrate, 401h: unevenness of ASIC substrate, 41h: first resin coating (first pedestal 1A), 42h: cured second dendritic coating, 43h: resin coating forming R-shape of groove bottom, 44Gh: inverted trapezoid groove, 44Ah: alignment mark consisting of elongated inverted trapezoid groove 45G: metal film, 45A: reflective film consisting of metal film

5: Alignment mark before metal film formation 50: Substrate, 51: Alignment mark recess, 52: Mask alignment mark 501: Signal due to substrate unevenness, 511: Alignment mark recess signal, 512: Mask alignment mark signal 6: Alignment mark after metal film formation 60: Substrate, 61: Alignment mark recess, 62: Mask alignment mark 611: Alignment mark recess signal, 612: Mask alignment mark signal

The method for producing a GSR element of the present invention comprises the steps of:
A method for manufacturing a GSR element, which comprises a detection coil having a coil pitch of 5 μm or less, which is made up of a magnetic wire, a lower coil and an upper coil surrounding the magnetic wire, and electrode wiring, and is directly fabricated on a substrate of an application specific integrated circuit (hereinafter referred to as ASIC), comprising:
(1) applying a negative resist-based first resin coating onto the ASIC substrate to form a groove forming portion and an alignment mark forming portion first base made of a flat and hard resin;
(2) A second resin coating of a positive resist system having a thickness greater than the depth of the groove is applied onto the first pedestal to form a second pedestal, and a rectangular recess for forming an inverted trapezoid groove (hereinafter referred to as a groove) for arranging the magnetic wire is simultaneously formed in the groove forming portion of the second pedestal, and a recess for forming an alignment mark recess is simultaneously formed in the alignment mark forming portion, and the second pedestal is cured by a curing heat treatment to harden the second pedestal and form the inverted trapezoid groove and the alignment mark recess;
(3) applying a negative resist resin film to the groove portion, exposing and developing the resin film so that the resin film remains only in the groove portion, and forming an R-shape in the bottom of the groove by a curing heat treatment; and forming a metal film on the groove forming portion formed by the groove and on an alignment mark forming portion formed by an alignment mark recess;
(4) Using an alignment mark having high visibility, which is composed of the alignment mark recess on which the metal film of the alignment mark forming portion is formed and a reflective film formed on the flat surface of the alignment mark forming portion, a metal coating of the groove forming portion on which the metal film is formed is formed along the surface of the groove, forming the lower coil and an upper coil connection portion on the flat surface of the groove forming portion (hereinafter, the lower coil and the upper coil connection portion are referred to as the lower coil);
(5) disposing the magnetic wire on the lower coil in the groove, embedding the wire in the groove with resin and fixing the magnetic wire;
(6) forming the upper coil and the electrodes on the upper part of the resin using the alignment marks by an auto-alignment mechanism;
(7) The assembly of the GSR element, which is composed of the magnetic wire, the detection coil, and the electrodes, is separated into individual pieces.

The present invention relates to a method for manufacturing a GSR element using highly visible alignment marks in the process of integrating a magnetic field detection element with an application specific integrated circuit (hereinafter referred to as ASIC).

High-sensitivity magnetic sensors include Hall sensors, GMR sensors, TMR sensors, high-frequency carrier sensors, FG sensors, MI sensors, GSR sensors, etc. Of these sensors, Hall sensors, GMR sensors, TMR sensors, and carrier sensors have been made smaller and thinner by integrating the element with an ASIC, but improving detection sensitivity remains an issue.
On the other hand, FG sensors, MI sensors, and GSR sensors have high sensitivity, but the element and ASIC are arranged separately and joined by wire bonding, making it difficult to reduce the thickness of the sensors.

In order to solve this problem, the present inventors have worked on developing technology for forming a GSR element on the surface of an ASIC, and as a result have achieved a smaller, thinner sensor (Patent Document 1).
Patent Document 1 discloses a thin, highly sensitive magnetic sensor in which an insulating resist is applied to the ASIC surface, a groove is formed therein in which a magnetic wire is disposed, and a GSR element consisting of a magnetic wire, a detection coil surrounding the magnetic wire, and electrodes is integrally formed on the ASIC surface. However, the technology for its manufacturing method has not been disclosed. Furthermore, although the manufacturing technology has been improved up to the present, it has not been disclosed.

On the other hand, to increase the sensitivity of the sensor, it is necessary to form a fine pitch coil and increase the number of turns in the coil. However, the finer the coil pitch, the more precisely it is required to align the position of the ASIC board and the position of the mask. To achieve this precision, highly visible alignment marks can be formed at the same time as the grooves are formed, which is expected to improve alignment precision.

Generally, alignment marks are formed on a _SiO2 film formed on a flat portion, so that high visibility can be easily obtained. Methods for forming alignment marks are disclosed in Patent Documents 2, 3, and 4, but none of them form alignment marks on a photosensitive resin.

JP 2019-191016 A JP 2006-229132 A JP 2009-004793 A Patent No. 2016776 Patent No. 5747294 Patent No. 6438616 Patent No. 3693119 Patent No. 4529783 Patent No. 4835805

2018 IEICE The Development of a High Sensitive Micro Size Magnetic Sensor Named as GSR Sensor Exited by GHz Pulse Current p.325 2020 JMMN The development of micro-coil-on-ASIC type GSR sensor driven by GHz Pulse current p.5

When integrating a GSR element onto an ASIC substrate, it is necessary to form a coil that wraps around the magnetic wire near the wire, and the groove shape for arranging the magnetic wire must be an inverted trapezoid. If a groove is created in an insulating film such as SiO2 using RIE (Reactive Ion Etching), the shape becomes rectangular, making it difficult to form the lower coil along the groove.

The formation of this inverted trapezoidal groove can be achieved by masking and exposing the groove to a positive resist resin film, developing it, and then applying a curing heat treatment. In other words, a positive resist resin film is essential to forming an inverted trapezoidal groove. Also, in this process, alignment marks are formed at the same time as the grooves to improve alignment accuracy. Therefore, the alignment marks are formed on the resin film, not on SiO2 as in the past.

However, the surface of an ASIC board usually has 2-3 μm irregularities (Figure 1) caused by the integrated circuit wiring, and even if a resin film is applied to the thickness required for groove formation (approximately 5-15 μm), the irregularities are transferred and remain on the surface, making it difficult to obtain the flat resin film required for alignment mark formation.

On the other hand, to increase the sensitivity of the sensor, it is necessary to reduce the coil pitch to 5 μm or less and increase the number of coil turns. However, the finer the coil pitch, the more precisely it is required to align the position of the ASIC board and the position of the multiple masks. To achieve this precision, an auto-alignment mechanism is necessary. The auto-alignment mechanism depends on the degree of contrast of the alignment mark image. As mentioned above, if there are irregularities on the surface of the ASIC board, the signal is disturbed and the contrast of the mark image is distorted. Therefore, if the mark is misrecognized and an attempt is made to form a fine coil with a coil pitch of 5 μm or less, the connection positions of the two will be misaligned when forming the upper coil after forming the lower coil, resulting in a problem of poor connection between the coils.

The present invention solves these problems by providing a manufacturing method for directly connecting a magnetic field detection element to an application specific integrated circuit (hereinafter referred to as ASIC), in which grooves for arranging magnetic wires and alignment marks with excellent contrast are simultaneously formed on a resin coating on an ASIC substrate with unevenness of several microns, and multiple GSR elements with detection coils formed with a fine coil pitch of 5 μm or less are integrally formed on the ASIC substrate.

Instead of the conventional method of applying a resin coating once, the inventors devised a two-layer resin coating method in which resin coatings with different functions are applied in two separate steps, and discovered that grooves and alignment marks can be formed simultaneously on the resin coating.

Here, the cross-sectional view of the GSR element fabricated on the ASIC substrate according to the present invention and the alignment mark used in the fabrication will be explained with reference to Figure 2. Each is illustrated one by one so that the relationship between the two can be understood, and the invention will be explained in detail below.
Further, a plan view and a cross-sectional view of a groove forming portion and an alignment mark forming portion in a certain step of the manufacturing process will be described with reference to FIG .
As for the manufacture of the element alone, the present inventors have disclosed it in Japanese Patent No. 5747294 (Patent Documents 5 and 6) and presented it at an international academic conference (Non-Patent Documents 1 and 2), and Aichi Steel Corporation has disclosed Patent Documents 7, 8, and 9, etc., and it is a well-known technique.

First, the GSR element fabricated on the ASIC substrate and the alignment used in the fabrication will be described with reference to FIG.
The ASIC substrate 20 has an unevenness 201 of about 2 to 3 μm on its surface due to the integrated circuit wiring. Therefore, an alignment mark forming section 23 is required in addition to a normal groove forming section 22.

In the groove forming section (element forming section) 22, a first seat 211 is formed on the ASIC 20. An inverted trapezoidal groove 221 is formed in a second seat 212 constituting an element on its flat surface. A lower coil 222 is formed on the surface of the groove 221, and a magnetic wire 223 with an insulating glass coating is arranged on the upper part of the lower coil 222. The magnetic wire is fixed with resin and embedded in the groove 221.
An upper coil 224 is formed on the magnetic wire 223 via resin, and is connected to the lower coil 222 at both ends and wound around the magnetic wire 223 .
Electrodes are formed on both ends of the magnetic wire 223 and both ends of the surrounding coil.

In the alignment mark forming section 23, a first base 211 is formed on the ASIC 20. On the flat surface of the first base 211, a second base 212 constituting the alignment mark is formed, which has an alignment mark recess, which is a long, steep, pseudo-inverted trapezoid groove 231, and a metal film is formed on the surface of the recess. In addition, a reflective film made of a metal film is formed on the flat surface.

Use of these alignment marks enables accurate and precise alignment, and an auto-alignment mechanism enables formation of the lower coil and the upper coil with a coil pitch of 5 μm or less.
For example, when the coil pitch is 3 μm, if the coil width is 2.0 μm, the coil spacing is 1.0. Taking into account adjacent coils, accuracy of 0.5 μm or less is required.

Next, a groove forming portion and an alignment mark forming portion in a certain step of the manufacturing process will be described with reference to FIG.
1A is a plan view, and FIG. 1B is a cross-sectional view taken along line A1-A2 of the plan view of FIG.
A groove forming portion 32 and an alignment mark forming portion 33 are formed on an ASIC substrate 30. In the groove forming portion 32, a second pedestal consisting of an inverted trapezoid groove and a flat surface is formed on a first pedestal 311 having a flat upper surface.

The alignment mark section has an alignment mark recess, which is a long, inverted trapezoidal groove 331, formed on a first base 311 with a flat upper surface, and a second base 312 consisting of a flat surface.

The two-layer resin coating method of the present invention will now be described.
The first step is to form a first layer by applying a first resin film (negative resist) on the ASIC substrate having irregularities, place a flattened hard resin first pedestal under the inverted trapezoid groove and alignment mark, and remove the irregularities that occur in the first resin film. The irregularities on the other parts of the ASIC surface, where the first pedestal is not placed, are left as they are used as electrode wiring.

The second step is to apply a second resin film (positive resist) thicker than the depth of the groove onto the first pedestal to form a second layer, which becomes the second pedestal, and then simultaneously form an inverted trapezoid groove and a recess for an alignment mark in this second pedestal (the second resin film of the second layer), and then deposit a metal film on top of that.

Next, in each step, the first resin coating layer in the first step is preferably a polyimide-based negative resist because it is preferable to ensure that the top of the base is flat and that the edges of the base have a steep shape. However, a positive resist can also be used.
In addition, the second resin coating film, which is the second layer in the second step, is applied onto the planarized first pedestal, and it is necessary to use a positive resist in order to form an inverted trapezoidal groove after a curing heat treatment.

There was a concern about the adhesion between the first resin of the first layer, which was cured by heat treatment, and the second resin coating of the second layer, but this was resolved by confirming that the resins were firmly integrated even if they were different types. In addition, the alignment mark portion is formed at the same time as the groove portion, so it has an inverted trapezoid shape like the groove portion. Therefore, the inverted trapezoid second pedestal itself is used as a mask to dig into the first pedestal by RIE, thereby increasing the steepness of the alignment mark recess. Furthermore, the visibility of the alignment mark can be improved by using the metal film as a reflective film. By adopting a resin coating with a two-layer structure in this way, it is possible to remove unevenness that cannot be achieved with a one-layer structure.

In the first step, a first resin film is applied onto the uneven surface of the ASIC substrate to form first pedestals in the groove formation area and the alignment mark formation area, but unevenness occurs. Since the unevenness remains on the surface of the first pedestal even after the curing heat treatment, it is necessary to flatten the upper surface of the hardened first pedestal by CMP (Chemical-Mechanical Polishing).
This CMP may damage the electrodes of the ASIC, so it is preferable to apply a resist to the entire surface of the ASIC before CMP to protect the ASIC surface other than the pedestal, and then remove the resist with a resist remover after CMP to achieve flattening.

When the second resin coating is applied, the groove and the alignment mark recess are exposed to light using a mask, developed, and then cured with a heat treatment, the groove changes from a rectangular parallelepiped to an inverted trapezoid, and the alignment mark recess also changes from a rectangular parallelepiped to an inverted trapezoid. This is the effect of using a positive resist resin coating instead of a SiO2 coating. Since the first base has already been flattened, the groove surface and the alignment mark portion itself are free of irregularities.

Here, since the shape of the alignment mark recess also becomes an inverted trapezoid, in order to make the edge of the alignment mark portion steeper, the area other than the alignment mark portion is protected with resist, and the alignment mark portion is subjected to RIE using the inverted trapezoid second pedestal itself as a mask to engrave the first pedestal . At this time, since the second pedestal is also a resin coating, the etching selectivity of the RIE is almost the same. Therefore, the amount of engraving is preferably 0.5 to 1.5 μm. If it is 0.5 μm or less, the effect of making the edge steeper is small and no improvement in visibility is observed. If it is 1.5 μm or more, the film loss of the second pedestal becomes large, which affects visibility.

In this state, however, the unevenness on the ASIC board is visible through the first resin and the second resin, making it impossible to ensure the high visibility contrast required for alignment.
Therefore, by forming a metal film on the alignment mark to enhance the reflection function, the visibility of the alignment mark can be improved. If the first pedestal is not flattened, the unevenness of the ASIC substrate cannot be eliminated even if the metal film is formed, and sufficient visibility of the alignment mark cannot be ensured. In other words, flattening the pedestal and forming a metal film to enhance the reflection function are essential. On the other hand, since the metal film needs to be formed to form the lower coil in the inverted trapezoid groove, it is desirable that the metal film of the alignment mark portion that enhances the reflection function and that of the lower coil are the same metal film. In addition, before forming the metal film, a negative resist-based resin film is applied to the groove portion, exposed to light, and developed to leave the resin film only in the groove portion, and an R-shape is formed at the bottom of the groove by a curing heat treatment, thereby preventing disconnection of the metal film.

The two-layer resin coating method makes it possible to simultaneously form grooves and alignment marks, and to form highly visible alignment marks on the resin coating.
The thickness of the first resin film forming the first pedestal of the first layer is preferably three times or more the irregularities (usually about 2 μm to 3 μm) of the ASIC surface in order to perform CMP.
The film thickness of the second resin in the second layer must be thicker than the minimum groove depth in order to enable groove formation (groove depth of about 5 μm to 10 μm).

The present invention makes it possible to simultaneously form an inverted trapezoidal groove for placing magnetic wires and a highly visible alignment mark on a resin coating without damaging the ASIC substrate, and by using this alignment mark, it becomes possible to integrally form a GSR element with a fine coil pitch of 5 μm or less, or even around 3 μm, on the ASIC substrate.

FIG. 2 is a diagram showing the uneven state of the surface of an ASIC substrate; 1 is a conceptual diagram of a GSR element and alignment marks fabricated on an ASIC substrate by a two-layer resin coating method. 1A and 1B are a plan view and a cross-sectional view showing an inverted trapezoidal groove and an alignment mark on an ASIC substrate. 1A and 1B are flow diagrams showing cross-sectional views of a groove forming portion and an alignment mark for fabricating a GSR element. 13C and 13D are cross-sectional views of a flow diagram showing the fabrication of a groove forming portion and an alignment mark for fabricating a GSR element. 5 (e) and 6 (f) are flow diagrams showing cross-sectional views of a groove forming portion and an alignment mark for fabricating a GSR element. 7 (g) and 8 (h) are flow diagrams showing cross-sectional views of a groove forming portion and an alignment mark for fabricating a GSR element. FIG. 1A shows alignment marks on the surface of an ASIC substrate before a metal film is formed, and marks and uneven signals on the A1-A2 line. FIG. 1B is a diagram showing the signal of the alignment mark on the C1-C2 line on the surface of the ASIC substrate after the metal film has been formed. 1 is a SEM photograph showing a 3.0 μm coil pitch produced according to the present invention and a SEM photograph showing a 5.5 μm coil pitch of a comparative example. 13 is a diagram showing the uneven state of the surface of the first pedestal after the CMP is performed. FIG.

The method for producing a GSR element of the present invention comprises the steps of:
A method for manufacturing a GSR element, which comprises a detection coil having a coil pitch of 5 μm or less, which is made up of a magnetic wire, a lower coil and an upper coil surrounding the magnetic wire, and electrode wiring, and is directly fabricated on a substrate of an application specific integrated circuit (hereinafter referred to as ASIC), comprising:
(1) applying a negative resist-based first resin coating onto the ASIC substrate to form a first base in a groove forming portion and an alignment mark forming portion made of a flat and hard resin;
(2) A second resin coating of a positive resist system having a thickness greater than the depth of the groove is applied onto the first pedestal to form a second pedestal, and a rectangular recess for forming an inverted trapezoid groove (hereinafter referred to as a groove) for arranging the magnetic wire is simultaneously formed in the groove forming portion of the second pedestal, and a recess for forming an alignment mark recess is simultaneously formed in the alignment mark forming portion, and the second pedestal is cured by a curing heat treatment to harden the second pedestal and form the inverted trapezoid groove and the alignment mark recess;
(3) applying a negative resist resin film to the groove portion, exposing and developing the resin film so that the resin film remains only in the groove portion, and forming an R-shape in the bottom of the groove by a curing heat treatment; and forming a metal film on the groove forming portion formed by the groove and on an alignment mark forming portion formed by an alignment mark recess;
(4) Using an alignment mark having high visibility, which is composed of the alignment mark recess on which the metal film of the alignment mark forming portion is formed and a reflective film formed on the flat surface of the alignment mark forming portion, a metal coating of the groove forming portion on which the metal film is formed is formed along the surface of the groove, forming the lower coil and an upper coil connection portion on the flat surface of the groove forming portion (hereinafter, the lower coil and the upper coil connection portion are referred to as the lower coil);
(5) disposing the magnetic wire on the lower coil in the groove, embedding the wire in the groove with resin and fixing the magnetic wire;
(6) removing the insulating glass covering the wire in the wire electrode portion for joining the wire to the electrode wiring by CF ₄ -RIE;
(7) a process of applying a positive resist resin coating to the entire surface of the substrate, exposing and developing the coating to leave the positive resist resin coating only on the grooves and magnetic wires, and smoothing the stepped portions by performing a curing heat treatment;
(8) forming the upper coil and the electrode wiring on the upper part of the resin using the alignment marks by an auto-alignment mechanism;
(9) Dividing an element substrate, which is an assembly of elements each including the magnetic wire, the detection coil, and the electrode wiring, into individual pieces.
It is characterized by:

In addition, in the step (2) described in claim 1,
(2') A second resin coating of a positive resist system having a thickness greater than the depth of the groove is applied onto the first pedestal to form a second pedestal, and a rectangular recess for forming an inverted trapezoidal groove (hereinafter referred to as the groove) for positioning the magnetic wire is simultaneously formed in the groove forming portion of the second pedestal, and a long and narrow recess for forming a recess for an alignment mark is simultaneously formed in the alignment mark forming portion, and the groove and the recess for the alignment mark are formed while being hardened by a curing heat treatment, and further the recess for the alignment mark is formed by digging down to the first pedestal by RIE processing using the second pedestal as a mask .

(5') The magnetic wire is placed on top of the lower coil in the groove with a tension of 30 to 100 kg/mm2, the magnetic wire is embedded in the groove with resin, and tension heat treatment is performed at a temperature of 250 to 350°C to fix the magnetic wire and improve the GSR characteristics.

The thickness of the negative resist-based first resin coating is at least three times the irregularities on the ASIC substrate.

Hereinafter, the best mode for carrying out the invention will be described in detail for each step with reference to FIGS.
In the first paragraph, the present invention relates to a method for directly fabricating a GSR element consisting of a magnetic wire, a detection coil, and electrodes on an ASIC board. Note that a magnetic detection element consisting of a magnetic wire, a detection coil, and electrodes and having a coil pitch of 5 μm or less is included in the technical concept of the present invention.

<Step (1)>
The following description will be given with reference to Figs. 4(a) to 4(h) (Figs. 4 to 7; first (a) to eighth (h) of the flow chart) .
Reference numeral 4a indicates that unevenness 401a exists on the surface of the ASIC board 40a.
Hereinafter, the ASIC substrate will be denoted as 40x (x: b to h), the concaves and convexes as 401x (x: a to h), the groove formation portion as 4Gx (x: b to h), and the alignment mark formation portion as 4Ax (x: b to h).

In the step 4b, a negative resist-based first resin coating 41b is applied onto an ASIC substrate 40b, and then exposed and developed using a mask material by photolithography to form a first pedestal consisting of a groove forming section 4Gb for forming a groove for forming a GSR element and an alignment mark forming section 4Ab for forming an alignment mark. As a result, the first resin coating is disposed only on the portion that will become the first pedestal.
The irregularities 401b on the ASIC substrate 40b remain, by being transferred, on the first base made up of the groove forming portion 4Gb and the alignment mark forming portion 4Ab to which the first resin coating 41b is applied.

At this stage, the first resin film 41c, which serves as the first pedestal, is subjected to a curing heat treatment to harden the first resin film 41c. Even at this stage, the irregularities 401c on the ASIC 40c are transferred and remain on the surface of the first resin film 41c , which serves as the first pedestal.
The temperature for the curing heat treatment is 250 to 350° C. If the temperature is less than 250° C., the curing is insufficient, and there is a concern that the shape may change in a later process, whereas if the temperature exceeds 350° C., there is a concern that problems may occur in the ASIC circuit.

4d flattens the unevenness 401d remaining on the first resin coating 41d of the first base consisting of the groove forming portion 4Gc and the alignment mark forming portion 4Ac to which the unevenness 401c has been transferred and hardened, by CMP, to form a flat first base 1A consisting of the groove forming portion 4Gd and the alignment mark forming portion 4Ad.

In addition, in forming the first pedestal 1A, a resist may be applied to the entire surface of the ASIC substrate 40c, the resist on the first pedestal may be removed, the surface of the ASIC substrate other than the first pedestal may be protected, CMP may be performed to flatten the first pedestal, and the resist that was protecting the surface of the ASIC substrate other than the first pedestal may be peeled off.

The thickness of the first resin coating 41b that forms the first pedestal 1A is preferably at least three times the irregularities 401b on the surface of the ASIC substrate 40b on which the first pedestal is placed. If it is less than three times, the first pedestal itself will become thin before the irregularities 401c of the first pedestal are flattened by the CMP in this process.

FIG. 11 shows the irregularities on the surface of the first base 1A that has been planarized by CMP.
The 2 μm irregularities on the surface of the ASIC substrate shown in FIG. 1 were transferred and remained even after the first resin coating was applied and subjected to a curing heat treatment, but as shown in FIG. 11 , it can be seen that the irregularities have been flattened to 0.02 μm or less by CMP of the first base.
The next step (2) is carried out using the first base A1 flattened to 0.02 μm or less.

<Step (2)>
In order to form the grooves and alignment marks, a second resin coating 42e thicker than the groove depth is applied to the first pedestal 1A. Since the first pedestal 1A is flattened, the second pedestal 1B, which forms the grooves and alignment marks, is not affected by the unevenness 401e of the ASIC substrate 40e. In other words, the second pedestal 1B has a flat surface.

The thickness of the second resin coating 42e is 7 μm to 17 μm, depending on the diameter of the magnetic wire to be placed in the groove. After that, exposure and development are performed using a mask material in which a pattern of grooves and multiple alignment marks is arranged. At this time, the shape of the groove is a rectangular recess (rectangular parallelepiped shape). The alignment marks are recesses.

4f is a curing heat treatment to harden the second resin coating 42e. The curing heat treatment temperature is 250°C to 350°C. If it is less than 250°C, the hardening will be insufficient, and there is a concern that the shape will change in subsequent processes. If it exceeds 350°C, there is a concern that malfunctions will occur in the ASIC circuit.

After the heat treatment, the shape of the groove changes from a rectangular parallelepiped to an inverted trapezoid 4Gf due to stress generated during the curing heat treatment. The upper surface of the second pedestal 1B remains flat, and the groove depth is 5 μm to 15 μm.
Similarly, the alignment mark recess also has an inverted trapezoid shape 44Af.

4g is preferably performed by first protecting the area other than the alignment mark forming area 4Ag with resist, and then performing oxygen RIE using the second base 1B of the alignment mark area as a mask to excavate an alignment mark recess in the first base 1A, thereby making the shape of the alignment mark recess 44Ag steeper.

<Step (3)>
4h is formed by applying a negative resist resin coating to the grooves, exposing and developing the resin coating to leave it only in the grooves, and then forming an R-shape 43h at the bottom of the grooves by a curing heat treatment, and then forming a metal film over the entire surface of the ASIC substrate 40h. This metal film (45G, 45A) is used as a reflective film (44Ah, 45A) in the alignment mark area, forming multiple alignment marks with high visibility. The thickness of the metal film is 0.2 μm to 1 μm.

FIG. 8 shows the alignment mark forming portion 44Ag before the metal film is formed, the plane of the alignment mark of the mask, and the waveform (signal) along the line B1-B2.
1A shows a plan view of an alignment mark forming portion 44Ag consisting of an alignment mark recess 44Ag which is formed by applying a first resin coating 41b applied to the surface of an ASIC substrate 40a and then subjecting it to a curing heat treatment 41b, planarizing it by CMP, applying a second resin coating 42e onto the flat surface 1A, and subjecting it to a curing heat treatment, as well as the alignment mark of the mask.
(b) shows the waveform (signal) on line B1-B2 of (a).

FIG. 9 shows the alignment mark forming portion 44Ah after the metal film is formed, a plane of the alignment mark of the mask, and a waveform (signal) along the line C1-C2.
1A shows an alignment mark 44Ah formed by depositing a metal film in an alignment mark forming portion 44Ag consisting of an alignment mark recess 44Ag, a plane of a reflective film 45A, and the alignment mark of the mask.
(b) shows the waveform (signal) at line C1-C2 of (a).

Before the metal film is formed, a flat and hard first base 1A is formed with a first resin coating in the area where the groove and alignment mark are to be located, but the contrast required for alignment is not secured as shown in Figure 8 (a).
It was presumed that this was because the wiring on the ASIC board 40g was visible through the resin coatings (first resin coating and second resin coating), and further, a metal film was formed over the entire surface of the ASIC board 40h.

This metal film also functions as a reflective film 45A for the alignment mark. As shown in Fig. 9B , this alignment mark has high signal strength for both the alignment mark and the wafer mark, and there is no signal due to a step, so it can be seen that it can be recognized without problem by the auto-alignment mechanism.

<Step (4)>
Using the highly visible alignment marks and metal film formed in the above process, the lower coil is formed along the inverted trapezoidal groove through resist coating, exposure, development, and etching processes.
Here, the lower coil includes the coil formed on the bottom and side surfaces of the inverted trapezoidal groove, as well as the coil formed on the flat surface of the groove forming portion, which simultaneously forms a connection with the upper coil.

<Step (5)>
A magnetic wire covered with insulating glass is placed on the lower coil formed in the groove, and is then embedded and fixed in place with resin.
When fixing the magnetic wire, it is preferable to apply a tension of 30 to 100 kg/mm2 to the magnetic wire and fix the embedding resin by curing heat treatment at a temperature of 250 to 350° C. This improves the magnetic properties.
In addition, when using a magnetic wire that is not covered with insulating glass, it is preferable to apply an insulating resist to the surface of the lower coil before placing the magnetic wire, which makes it possible to prevent a short circuit between the lower coil and the metallic magnetic wire.

<Step (6)>
Using a highly visible alignment mark created by an auto-alignment mechanism on top of the resin that secures the magnetic wire, a 1-2 μm thick metal film is evaporated (or plated), resist is applied, exposed, developed, and etched to form an upper coil, producing the GSR element.
It is also preferable to form the electrodes and the wiring between the electrodes and the coil/magnetic wire at the same time. Prior to forming the wiring, the insulating glass coating on both ends of the magnetic wire is removed by CF4-RIE.

When forming the upper coil, the alignment accuracy between the alignment mark and the multiple masks is set to 1 μm or less, preferably 0.5 μm or less. At this time, the alignment mark has a first base 1A and a reflective film (metal film), so the signal strength is sufficient, and the lower coil and upper coil can be joined by auto-alignment without any problems.

FIG. 7 shows an SEM photograph of a 3.0 μm narrow pitch coil produced according to the present invention, together with a 5.5 μm pitch coil as a comparative example.
It is seen that a coil with a pitch of 3.0 μm can be formed without any misalignment between the upper coil and the lower coil.

The two-layer resin coating method is used to simultaneously form grooves and alignment marks in the resin coating on the ASIC substrate, and the manufacturing flow for a GSR element consisting of a narrow-pitch coil using highly visible alignment marks is described below with reference to Figures 4(a) to (h).

Step A) On the surface of the ASIC substrate 40a, there are irregularities 401a of several μm caused by the integrated circuit (FIG. 4A).
Step a) After a first resin film 41b is applied to an ASIC substrate 40b, exposure and development are carried out using a mask material to form the structure shown in FIG.
That is, a first pedestal is formed, which is composed of a groove forming portion 4Gb for forming a groove and an alignment mark forming portion 4Ab for forming an alignment mark recess.
As a result, the first resin coating 41b is disposed only on the portion that will become the first pedestal. At this time, the thickness of the first pedestal is 10 μm.

Step c) A curing heat treatment is performed at 280° C. for 1 hour to harden the first resin film 41c (FIG. 4(c)). Even at this point, the projections and recesses 401c of the ASIC substrate 40c remain transferred to the surface of the first resin film 41c that will become the first pedestal.
Step d) After applying resist to the entire ASIC board, exposure and development are carried out using a mask material to remove the resist on the first pedestal.

Step E) CMP is performed to flatten the first pedestal, forming the first pedestal 1A (FIG. 4(d)). The thickness of the first pedestal is 10 μm in step B), and even after the curing heat treatment, it is still about 8 μm thick, so there is no problem with CMP.
Step F) In order to form grooves and alignment marks, a second resin coating 42e having a thickness of 10 μm is applied onto the first pedestal 1A. Since the first pedestal 1A is flattened, the second pedestal 1B consisting of a groove forming portion 4Gf for forming the grooves and an alignment mark forming portion 4Af for forming the alignment marks is not affected by the unevenness 401e of the ASIC substrate 40e (FIG. 4(e)).

Step g) A curing heat treatment is performed at 280°C for 1 hour to harden the second resin coating 41f (Figure 4(g)). The heat treatment causes the grooves to deform from a rectangular parallelepiped shape (44Gf, 44Af) to an inverted trapezoid shape (44Gg, 44Ag) due to the stress generated during the curing heat treatment. The top surface of the second pedestal 1B remains flat. The depth of the groove is 8 μm.

Step H) In order to make the shape of the alignment mark recesses steeper, a resin is applied to the entire surface, and then exposure and development are performed using a mask to protect areas other than the areas where the alignment marks are to be formed with resist.
Using the second seat 1B of the alignment mark forming portion 4Ag as a mask, oxygen RIE is performed to excavate an alignment mark recess 44Ag in the first seat 1A, and the resist is peeled off (FIG. 4(g)). At this time, 18 alignment marks are formed.
Step I) A metal film was formed over the entire surface of the ASIC substrate (FIG. 4(h)). The thickness was 0.2 μm by metal deposition.

Step J) A resist was applied to the entire ASIC substrate, and exposure and development were carried out using a mask material in which a pattern for forming a lower coil in the groove and a pattern for protecting the alignment marks were arranged.
Step K) After plating the coil portion, the resist film is removed, and the metal film other than the coil portion is removed by etching. As a result, the metal film in the groove portion functions as the lower coil, and the metal film of the alignment mark functions as a reflective film. The width of the lower coil is 2.0 μm, and the thickness is 1.0 μm.

Process C) A CoFeB magnetic wire covered with 1 μm thick insulating glass is placed on the upper part of the lower coil of the groove with a tension of 50 kg/mm2, and after temporarily fixing it with adhesive, tape, etc., the magnetic wire is embedded in the groove with resin. Furthermore, this resin is hardened by a curing heat treatment at a temperature of 280° C., and the magnetic wire is fixed. At this time, the magnetic wire is heat-treated while tension is applied, so that the GSR characteristics can be improved.
Step S) To connect to the wiring of the magnetic wire electrodes, the insulating glass on both ends of the magnetic wire is removed by CF4-RIE to form conductive parts.

Process C) In order to eliminate the step between the groove and the wire, a positive resist resin film is applied, exposed, baked, developed, and then subjected to a curing heat treatment at 280°C for 1 hour to smooth out the shape of the upper part of the groove, after which a metal film is formed over the entire ASIC board and a resist is applied.
Process So) Exposure and development are carried out using a mask material on which a pattern for forming the upper coil of the groove and the lead wire (wiring) of the conductive part of the magnetic wire and a pattern for protecting the alignment part are arranged.
At this time, since the alignment mark has first base 1A and a reflective film, the signal strength is sufficient, and the connection part of the lower coil and the connection part of the upper coil can be aligned by automatic alignment without any problem.

Step T) After plating the coil portion, the resist film is removed and the metal film other than the coil portion is removed by etching. At this stage, the upper coil, electrodes, and lead wires (wiring) of the conductive portions of the magnetic wire are formed and function.
The upper coil has a width of 2.0 μm and a thickness of 1.0 μm. The coil connection portion consisting of the connection portion of the lower coil and the connection portion of the upper coil is formed with a line width of 2.0 μm and a coil pitch of 3.0 μm.

By using the above process, grooves and alignment marks can be simultaneously formed in the resin coating, and highly visible alignment marks can be formed on the resin coating, making it possible to integrally form a GSR element consisting of a fine pitch coil on an ASIC substrate.
FIG. 7 shows a SEM photograph (a) of a 3.0 μm coil pitch according to the present invention in comparison with a SEM photograph (b) of a conventional 5.5 μm coil pitch.

It becomes possible to integrally form a GSR element with a fine coil pitch on an ASIC substrate, which not only enables the GSR element to be made thinner and more compact, but also achieves even higher sensitivity.
This GSR sensor is expected to be applied to biomagnetism.

1: unevenness on the surface of the ASIC substrate 2: GSR element and alignment mark on the ASIC substrate 20: ASIC substrate, 201: unevenness on the ASIC substrate, 211: first resin coating (first pedestal 1A), 212: second resin coating (second pedestal 1B), 22: groove forming portion, 221: resin, 222: lower coil, 223: magnetic wire, 224: upper coil, 225: resin coating forming an R-shape at the bottom of the groove, 23: alignment mark forming portion, 231: alignment mark, 232: reflective film
3: Inverted trapezoid groove and alignment mark
30: ASIC substrate, 311: first resin coating (first base 1A), 312: second resin coating (second base 1B), 32: groove forming portion, 321: inverted trapezoid groove, 33: alignment mark forming portion, 331: elongated inverted trapezoid groove (alignment mark recess)

4a: uneven state of the surface of the ASIC substrate 40a: ASIC substrate, 401a: unevenness of the ASIC substrate 4b: ASIC substrate coated with a first resin coating 4Gb: groove formation portion, 4Ab: alignment mark formation portion 40b: ASIC substrate, 401b: unevenness of the ASIC substrate
4c: ASIC substrate subjected to first resin coating curing heat treatment 4Gc: groove forming portion 4Ac: alignment mark forming portion 40c: ASIC substrate 401c: unevenness of ASIC substrate 41c: first resin coating cured heat treatment
4d: ASIC substrate subjected to CMP; 4Gd: groove forming portion; 4Ad: alignment mark forming portion; 40d: ASIC substrate; 401d: unevenness of ASIC substrate; 41d: first resin coating film planarized after CMP (first pedestal 1A)
4e: ASIC substrate coated with second resin coating 4Ge: groove forming portion, 4Ae: alignment mark forming portion 40e: ASIC substrate, 41e: first resin coating (first pedestal 1A), 42e: second resin coating, 1B: second pedestal consisting of a flat surface 4f: ASIC substrate with a groove formed in the second resin coating 4Gf: groove forming portion, 4Af: alignment mark forming portion 40f: ASIC substrate, 401f: unevenness of the ASIC substrate, 41f: first resin coating (first pedestal 1A), 42f: second resin coating cured with heat , 44Gf: rectangular groove, 44Af: elongated rectangular groove 4g: ASIC substrate with the second resin coating with a groove formed therein cured with heat 4Gg: groove forming portion, 4Ag: alignment Alignment mark forming portion 40g: ASIC substrate, 401g: unevenness of ASIC substrate, 41g: first resin coating (first pedestal 1A), 42g: second resin coating subjected to curing heat treatment , 44Gg: inverted trapezoid groove, 44Ag: elongated inverted trapezoid groove 4h: ASIC substrate on which metal film is formed 4Gh: groove forming portion, 4Ah: alignment mark forming portion 40h: ASIC substrate, 401h: unevenness of ASIC substrate, 41h: first resin coating (first pedestal 1A), 42h: second resin coating subjected to curing heat treatment , 43h: resin coating forming R-shape of groove bottom, 44Gh: inverted trapezoid groove, 44Ah: alignment mark consisting of elongated inverted trapezoid groove 45G: metal film, 45A: reflective film consisting of metal film

5: Alignment mark before metal film formation 50: Substrate, 51: Alignment mark recess, 52: Mask alignment mark 501: Signal due to substrate unevenness, 511: Alignment mark recess signal, 512: Mask alignment mark signal 6: Alignment mark after metal film formation 60: Substrate, 61: Alignment mark recess, 62: Mask alignment mark 611: Alignment mark recess signal, 612: Mask alignment mark signal

Claims (4)

A method for manufacturing a GSR element, which comprises a detection coil having a coil pitch of 5 μm or less, which is made up of a magnetic wire, a lower coil and an upper coil surrounding the magnetic wire, and electrode wiring, and is directly fabricated on a substrate of an application specific integrated circuit (hereinafter referred to as ASIC), comprising:
(1) applying a negative resist-based first resin coating onto the ASIC substrate to form a first base in a groove forming portion and an alignment mark forming portion made of a flat and hard resin;
(2) A second resin coating of a positive resist system having a thickness greater than the depth of the groove is applied onto the first pedestal to form a second pedestal, and a rectangular recess for forming an inverted trapezoid groove (hereinafter referred to as a groove) for arranging the magnetic wire is simultaneously formed in the groove forming portion of the second pedestal, and a recess for forming an alignment mark recess is simultaneously formed in the alignment mark forming portion, and the second pedestal is cured by a curing heat treatment to harden the second pedestal and form the inverted trapezoid groove and the alignment mark recess;
(3) applying a negative resist resin film to the groove portion, exposing and developing the resin film so that the resin film remains only in the groove portion, and forming an R-shape in the bottom of the groove by a curing heat treatment; and forming a metal film on the groove forming portion formed by the groove and on an alignment mark forming portion formed by an alignment mark recess;
(4) Using an alignment mark having high visibility, which is composed of the alignment mark recess on which the metal film of the alignment mark forming portion is formed and a reflective film formed on the flat surface of the alignment mark forming portion, a metal coating of the groove forming portion on which the metal film is formed is formed along the surface of the groove, forming the lower coil and an upper coil connection portion on the flat surface of the groove forming portion (hereinafter, the lower coil and the upper coil connection portion are referred to as the lower coil);
(5) placing the magnetic wire on the lower coil in the groove under tension, temporarily fixing the magnetic wire in the groove with resin, and further fixing the magnetic wire in the groove by performing a curing heat treatment while still applying tension;
(6) removing the insulating glass covering the wire in the wire electrode portion for joining the wire to an electrode wiring by CF ₄ -RIE;
(7) a process of applying a positive resist resin coating to the entire surface of the substrate, exposing and developing the coating to leave the positive resist resin coating only on the grooves and magnetic wires, and smoothing the stepped portions by performing a curing heat treatment;
(8) forming the upper coil and the electrodes on the upper part of the resin using the alignment marks by an auto-alignment mechanism;
(9) A method for manufacturing a GSR element, comprising the steps of: dividing an element substrate, which is an assembly of elements each including the magnetic wire, the detection coil, and the electrodes, into individual pieces. In the step (2) according to claim 1,
(2') A method for manufacturing a GSR element, characterized in that a second resin coating of a positive resist system thicker than the groove depth is applied onto the first pedestal to form a second pedestal, a rectangular recess for forming an inverted trapezoidal groove (hereinafter referred to as the groove) for placing the magnetic wire is simultaneously formed in the groove forming portion of the second pedestal, and a recess for an alignment mark is simultaneously formed in the alignment mark forming portion, and the groove and the recess for the alignment mark are formed while being hardened by a curing heat treatment, and further the recess for the alignment mark is formed by performing RIE processing using the second pedestal as a mask to excavate the first pedestal. In the step (5) according to claim 1,
(5') A method for manufacturing a GSR element, comprising: placing the magnetic wire on top of the lower coil in the groove with a tension of 30 to 100 kg/mm2; embedding the magnetic wire in the groove with resin; and performing tension heat treatment at a temperature of 250 to 350°C to fix the magnetic wire while improving the GSR characteristics. In any one of claims 1 to 3,
A method for manufacturing a GSR element, characterized in that the thickness of the negative resist type first resin coating is at least three times the irregularities on the ASIC substrate.

Images