JP2024049218A - Semiconductor drive circuit and power conversion device - Google Patents

Abstract

[Problem] To reduce a voltage drop occurring during reverse current conduction of a switching element during a dead time period of a power conversion device, thereby reducing reverse conduction loss. [Solution] A power conversion device (e.g., a PFC circuit in a converter) includes an AC power source 21, a rectifier circuit 22, a choke coil 23, a normally-on switching element 24a and a switch 24b in a normally-on state in a first switch circuit 24, a normally-on switching element 25a and a switch 25b in a normally-on state in a second switch circuit 25, and drive circuits 26 and 27 for driving the switch circuits 24 and 25. The drive circuit 26 or 27 changes the amount of negative bias for turning off the switching element 24a or 25a based on information indicating that erroneous firing of the switching element 24a or 25a is likely to occur. [Selected Figure] Figure 1

Description

The present invention relates to a semiconductor drive circuit that drives a switching element and a power conversion device that uses the semiconductor drive circuit.

A power conversion device is a device that converts electrical energy, such as from alternating current (AC) to direct current (DC), from DC to AC, or AC frequency conversion, or DC power conversion. Various types of devices are known, such as AC/DC converters, DC/AC inverters, DC/DC converters, and converters with power factor correction circuits (hereinafter referred to as "PFC circuits").

For example, among Patent Documents 1 to 4, Patent Document 1 describes a driving method for a switching element in an inverter having a normally-on type switching element (a GaN transistor or a SiC transistor which has excellent switching speed and withstand voltage and low on-resistance) that is turned on when no voltage is applied to the gate.
Patent Document 2 describes a power conversion device (e.g., a phase shift circuit). Examples of normally-off GaN transistors and SiC transistors using compound semiconductors are described as switching elements constituting the phase shift circuit. In particular, GaN transistors have better electrical and physical properties than Si transistors, and are attracting attention as high-power, small-sized, and low-loss power semiconductor elements.

Patent Document 3 describes a switching power supply device including an inverter circuit in which a high-side (high level side) switch section having a normally-on type first switching element and a low-side (low level side) switch section having a normally-on type second switching element and a normally-off type third switching element connected in cascode (cascade connection) are connected in series.
Also, Patent Document 4 describes a power conversion device that includes a drive circuit for semiconductor switching elements, connects an AC system and a DC system, and controls the flow of power between the AC system and the DC system. As the semiconductor switching elements, a field effect transistor (hereinafter referred to as "FET") that turns on when the gate voltage is higher than a threshold voltage and turns off when the gate voltage is lower, an insulated gate bipolar transistor (IGBT), etc. are disclosed.

Figures 4(a), (b), and (c) show a conventional PFC circuit similar to the PFC circuit in the converter described in Patent Document 2, etc., where (a) is an overall circuit diagram of the PFC circuit, (b) is a circuit diagram of the drive circuit in (a), and (c) is an output voltage waveform diagram of the drive circuit in (b).

This PFC circuit has a rectifier circuit 2 that performs full-wave rectification of the AC power supplied from an AC power source 1, a choke coil 3 connected in series to the output side of the rectifier circuit 2, and a low-level (hereinafter referred to as "L level") switching element 4. A series circuit of a high-level (hereinafter referred to as "H level") switching element 5 for synchronous rectification and a smoothing capacitor 8 is connected in parallel to the switching element 4. A load 9 is connected to both electrodes of the capacitor 8. The switching elements 4 and 5 are, for example, normally-off GaN transistors, and their gates (G) are driven by drive circuits 6 and 7. When the gate of a normally-off GaN transistor is at L level (for example, 0 V or less), the drain (D)-source (S) is off, and when the gate is at H level, the drain (D)-source (S) is on.

When the switching element 4 is on and the switching element 5 is off, the current flows from the AC power source 1 to the rectifier circuit 2 to the choke coil 3 to the switching element 4 to the rectifier circuit 2 to the AC power source 1. When the switching element 4 is off and the switching element 5 is on, the current flows from the AC power source 1 to the rectifier circuit 2 to the choke coil 3 to the switching element 5 to the capacitor 8 and the load 9 to the rectifier circuit 2 to the AC power source 1. As a result, the AC power of the AC power source 1 is rectified by the rectifier circuit 2, and the power is boosted through the choke coil 3, the switching element 4, and the switching element 5, smoothed by the capacitor 8, and supplied to the load 9. By turning the switching element 4 on and off and turning the switching element 5 on and off in synchronization with this, the current is controlled, the phase is synchronized with the power supply voltage, and the waveform of the current flowing through the choke coil 3 is made closer to a sine wave. The sum of the current flowing through the switching element 4 and the forward current of the switching element 5 for synchronous rectification becomes the current flowing through the choke coil 3.

4B have the same circuit configuration, and are composed of a Zener circuit having a DC power supply 11, a resistor 12, a Zener diode 13, and a capacitor 14, and a pulse signal source 15. The Zener circuit generates a Zener voltage Vz higher than 0 V and supplies it to the sources (S) of the switching elements 4 and 5. The pulse signal source 15 inputs an output control signal that, for example, reduces the voltage error between a target voltage and an output voltage to zero, and pulse-width modulates (hereinafter referred to as "PWM") the output control signal with a carrier wave to generate a drive pulse GP with a peak value Vh higher than 0 V and supplies it to the gates (G) of the switching elements 4 and 5.
4C, in the output voltage waveforms of the drive circuits 6 and 7, the Zener voltage Vz corresponds to the negative bias amount of the gates when the switching elements 4 and 5 are off. The output voltages of the drive circuits 6 and 7 complementarily turn the switching elements 4 and 5 on and off with a certain dead time therebetween.

FIG. 5 is an operational waveform diagram of the PFC circuit of FIG.
Vgs1 is the gate-source voltage of the switching element 4 composed of a GaN transistor, Vgs2 is the gate-source voltage of the switching element 5 composed of a GaN transistor, Id2 is the reverse drain current flowing from the source to the drain of the switching element 5, and Vds2 is the drain-source voltage of the switching element 5. td1 and td2 are dead times during which the gate-source voltages Vgs1 and Vgs2 of the two switching elements 4 and 5 both become L level.

In FIG. 5, when the switching element 4 is turned on by the H level of the gate-source voltage Vgs1 and the switching element 5 is turned off by the L level of the gate-source voltage Vgs2, a current flows from the AC power source 1 to the rectifier circuit 2 to the choke coil 3 to the switching element 4 to the rectifier circuit 2 to the AC power source 1. In this state, when the gate-source voltage Vgs1 falls to the L level and the switching element 4 is turned off, and the transition to the dead time td1 period occurs in which the gate-source voltages Vgs1 and Vgs2 of the switching elements 4 and 5 are both at the L level, a reverse conduction current (-Id2) flows from the source to the drain of the switching element 5, and the drain-source voltage Vds2 falls to the L level (negative potential of 0 V or less), causing a reverse conduction voltage drop ΔV.

Next, when the gate-source voltage Vgs2 rises to H level and the switching element 5 is turned on, and the gate-source voltage Vgs1 is at L level and the switching element 4 is turned off, a current flows from the AC power source 1 to the rectifier circuit 2 to the choke coil 3 to the switching element 5 to the capacitor 8 and the load 9 to the rectifier circuit 2 to the AC power source 1. In this state, when the gate-source voltage Vgs2 falls to L level and the switching element 5 is turned off, and the transition to the dead time td2 period occurs in which the gate-source voltages Vgs1 and Vgs2 of the switching elements 4 and 5 are both at L level, a reverse conduction current (-Id2) flows from the source to the drain of the switching element 5, and the drain-source voltage Vds2 falls to L level (negative potential of 0 V or less), causing a reverse conduction voltage drop ΔV.

The GaN transistors that make up the switching elements 4 and 5 are used as elements capable of high-speed switching, but have a low gate threshold and may cause false ignition due to noise, etc. A specific example of false ignition is when the switching element 4 of the PFC circuit is hard switched (not zero-volt switching (hereinafter referred to as "ZVS")) and the drain voltage of the switching element 5 changes suddenly, causing the gate voltage to rise through the parasitic capacitance between the drain and gate of the switching element 5, and if this voltage exceeds the gate threshold, false ignition occurs. As a countermeasure to this, the gate voltage of the switching element 5 can be negatively biased when it is off to prevent false ignition.

JP 2004-242475 A International Publication No. WO 2012/153676 JP2018-088754A International Publication No. 2020/017506

The GaN transistors constituting the switching elements 4 and 5 of the PFC circuit in Figure 4 have the characteristic that when current flows from the source to the drain (reverse conduction), the negative gate bias is added to the original voltage drop between the source and drain. Therefore, as in the case of the switching element 5 for synchronous rectification in the PFC circuit, when current flows from the source to the drain of the switching element 5 (reverse conduction) during the dead times td1 and td2, as shown in Figure 5, there is a drawback in that the conduction loss increases due to the reverse conduction voltage drop ΔV.

The semiconductor drive circuit of the present invention includes a first switch circuit having a normally-on type first switching element and a normally-off type first switch connected in series between a positive power supply side and a negative power supply side, a second switch circuit having a normally-on type second switching element and a normally-off type second switch connected in series, the second switching element and the second switch being connected in parallel to the first switch circuit, a first drive circuit that drives the first switching element on/off during operation and sets the first switch to an on state during operation and an off state when a power supply is stopped, and a second drive circuit that drives the second switching element on/off complementarily with respect to the first switching element with a dead time during operation, and sets the second switch to an on state during operation and an off state when a power supply is stopped.
The first drive circuit and the second drive circuit change the amount of negative bias for turning off the first switching element or the second switching element based on information indicating that erroneous ignition of the first switching element or the second switching element is likely to occur.

In the above configuration, for example, the information that erroneous turning on of the first switching element or the second switching element is likely to occur is information that the load state is a heavy load.
Whether the load state is the heavy load state or not is determined by detecting a load current flowing through the load, and if the detection result exceeds a threshold current, the load is determined to be the heavy load state.
Whether the load state is the heavy load state or not is determined by detecting the switch circuit currents flowing through the first switch circuit and the second switch circuit, and if each of these detection results exceeds a threshold current, it is determined that the load state is the heavy load state.
When the load state is the heavy load state, the bias amount of the negative bias for turning off the first switching element or the second switching element may be increased.

When the load state is a light load, the bias amount of the negative bias for turning off the first switching element or the second switching element may be reduced.
The amount of the negative bias may be changed linearly.
The semiconductor drive circuit is a circuit including a converter having the first switch circuit and the second switch circuit.

The power conversion device of the present invention is characterized by using the semiconductor drive circuit.

According to the present invention, when there is a high possibility of erroneous firing due to noise caused by hard switching, the amount of negative bias for turning off the first or second switching element is changed based on information that indicates that the first or second switching element is more likely to erroneously fire. This makes it possible to prevent erroneous firing of the first or second switching element. In addition, by reducing the amount of negative bias under light loads, it is possible to reduce the voltage drop during reverse current conduction of the first or second switching element, which occurs during the dead time period of the power conversion device, and to reduce reverse conduction loss.

FIG. 1 is a diagram showing a power conversion device (for example, a PFC circuit in a converter) according to a first embodiment of the present invention. Operation waveform diagram of the PFC circuit in FIG. FIG. 1 shows a power conversion device (for example, a PFC circuit in a converter) according to a second embodiment of the present invention. A diagram showing a conventional PFC circuit. FIG. 4(a) is a waveform diagram showing the operation of the PFC circuit.

The mode for carrying out the present invention will become clear from the following description of the preferred embodiment when read in conjunction with the accompanying drawings, which are for illustrative purposes only and are not intended to limit the scope of the present invention.

(Configuration of the First Embodiment)
1(a) and (b) are diagrams showing a power conversion device (e.g., a PFC circuit in a converter) according to a first embodiment of the present invention, where (a) is an overall circuit diagram of the PFC circuit, and (b) is a circuit diagram of a drive circuit in (a).

The PFC circuit of FIG. 1(a) has a rectifier circuit 22 that performs full-wave rectification of the AC power supplied from the AC power source 21, as in the conventional PFC circuit of FIG. 4. The rectifier circuit 22 is composed of four rectifier diodes 22a, 22b, 22c, and 22d that are bridge-connected. Between the positive power supply side and the negative power supply side of the output of the rectifier circuit 22, a choke coil 23 and a first switch circuit 24 on the L level side are connected in series. A series circuit of a second switch circuit 25 on the H level side for synchronous rectification and a smoothing capacitor 28 is connected in parallel to the first switch circuit 24. A load 29 is connected to both electrodes of the capacitor 28. A first drive circuit 26 that drives the first switch circuit 24 on and off is connected to the first switch circuit 24, and a second drive circuit 27 that drives the second switch circuit 25 on and off is also connected to the second switch circuit 25.

The first switch circuit 24 has a normally-on type first switching element 24a and a normally-off type first switch 24b connected in series between the positive power supply side and the negative power supply side, and two voltage dividing resistors 24c and 24d connected in series to apply a voltage to keep the first switch 24b in an on state. The first switching element 24a is composed of a compound semiconductor element (e.g., a normally-on type GaN transistor), and its gate (G) is driven on/off by the first drive circuit 26. When the gate of the normally-on type GaN transistor is at H level (e.g., negative potential near 0 V), the drain (D)-source (S) is in an on state, and when the gate is at L level lower than the H level (e.g., negative potential lower than near 0 V), the drain-source is in an off state. The first switch 24b is composed of a semiconductor element such as a normally-off type FET, and when its gate (G) is at H level (e.g., a positive potential of several volts), the drain (D)-source (S) is in an ON state, and when the gate (G) is at an L level lower than the H level (e.g., a potential near 0 V), the drain-source is in an OFF state. The first drive circuit 26 is a circuit that drives the first switching element 24a on/off during operation, and sets the first switch 24b to an ON state during operation and an OFF state when the power supply is stopped.

The second switch circuit 25, like the first switch circuit 24, has a normally-on type second switching element 25a and a normally-off type second switch 25b connected in series to the positive power supply side, and two voltage dividing resistors 25c and 25d connected in series to apply a voltage to keep the second switch 25b in an on state at all times. The second switching element 25a is composed of a compound semiconductor element (e.g., a normally-on type GaN transistor), and the second switch 25b is composed of a semiconductor element such as a normally-off type FET. The second drive circuit 27 is a circuit that drives the second switching element 25a on/off in a complementary manner with respect to the first switching element 24a with dead times td1 and td2 during operation, and sets the second switch 25b to an on state during operation and to an off state when the power supply is stopped.

A current detection circuit 30 consisting of, for example, a shunt resistor is connected to the negative input side of the rectifier circuit 22. The current detection circuit 30 is a circuit that detects the load current Ir flowing through the shunt resistor. The current detection circuit 30 may also be composed of a Rogowski coil and an integrator, etc., as other circuit configurations. When a Rogowski coil is used, the current can be detected without contacting the connecting wire, there is no heat generation or hysteresis due to magnetic loss, and there is no magnetic saturation, making it possible to measure large currents.

The comparator 31 is connected to the output side of the current detection circuit 30. The comparator 31 compares the magnitude of the detected load current Ir with the threshold current Ith, and when the load current Ir is greater than the threshold current Ith, it determines that the load 29 is a "heavy load" and outputs an H-level current determination signal S31, and when the load current Ir is smaller than the threshold current Ith, it determines that the load 29 is a "light load" and outputs an L-level current determination signal S31. Two insulating circuits 32 and 33 are connected to the output side of the comparator 31. Each insulating circuit 32 and 33 insulates the current determination signal S31, outputs L-level control signals S32 and S33 when the load 29 is a "heavy load", and outputs H-level control signals S32 and S33 when the load 29 is a "light load", and feeds back to each drive circuit 26 and 27, respectively, and is composed of a pulse transformer, an insulating inverting amplifier, an L-level driver, etc.

The drive circuits 26 and 27 in FIG. 1(b) have the same circuit configuration and are composed of a DC power supply 41, a resistor 42, a Zener diode 43 having a Zener voltage Vz1, a Zener diode 44 having a Zener voltage Vz2 (where Vz2=Vz1 or Vz2≠Vz1), a normally-off short-circuit switch 45 that is turned on by an H-level control signal S32 (S33), an NPN transistor 46, a capacitor 47, and a dropper circuit that is a step-down circuit equipped with a discharge resistor 48 for the capacitor 47, a DC power supply 49 connected to the emitter (E) of the transistor 46, a normally-off switch 50, and a pulse signal source 51.

In the dropper circuit, a series circuit of a resistor 42 and Zener diodes 43 and 44, and a series circuit of a collector (C) and emitter (E) of a transistor 46 and a capacitor 47 are connected in parallel between the positive and negative electrodes of the DC power supply 41. A switch 45 is connected in parallel to the Zener diode 44. A discharge resistor 48 is connected in parallel to the capacitor 47 connected between the emitter of the transistor 46 and the negative electrode of the DC power supply 41. The connection point between the emitter of the transistor 46, the capacitor 47, and the discharge resistor 48 is connected to the source (S) of the switch 24b (25b). Furthermore, the negative and positive electrodes of the DC power supply 49 and a switch 50 are connected in series to the connection point between the emitter of the transistor 46, the capacitor 47, and the discharge resistor 48, and the switch 50 is connected to the gate (G) of the switch 24b (25b) via the voltage dividing resistor 24c (25c) in FIG. 1(a). The gate (G) of the switching element 24a (25a) is connected to the negative electrode of the discharge resistor 48 via a pulse signal source 51. The pulse signal source 51 has the function of inputting a frequency signal that, for example, reduces the voltage error between the target voltage and the output voltage to zero, PWMing the frequency signal with a carrier wave such as a triangular wave to generate a drive pulse GP with a peak value Vh higher than 0V, and supplying the drive pulse GP to the gate of the switching element 24a (25a).

In the drive circuit 26 (27) configured in this way, the switch 50 is turned on during operation, and the gate of the switch 24b (25b) becomes H level through the voltage dividing resistor 24c (25c) by the DC power supply 49, and the switch 24b (25b) becomes ON state. When the control signal S32 (S33) of L level is output from the insulation circuit 32 (33) during heavy load, the switch 45 remains OFF, and the Zener voltage Vz1 of the Zener diode 43 and the Zener voltage Vz2 of the Zener diode 44 are applied to the base of the transistor 46, and the DC output voltage (Vz1 + Vz2 - Vbe) of the dropper circuit is generated at the emitter of the transistor 46 (where Vbe is the base-emitter voltage of the transistor 46). Therefore, the amount of negative bias of the gate when the switching element 24a (25a) is OFF increases.

When the isolation circuit 32 (33) outputs an H-level control signal S32 (S33) under light load, the switch 45 turns on and the Zener diode 44 is shorted. When the Zener diode 44 is shorted, the Zener voltage Vz1 of the Zener diode 43 is applied to the base of the transistor 46, and the transistor 46 turns off. The output voltage (Vz1 + Vz2 - Vbe) on the emitter side of the transistor 46 is discharged with the discharge time constant of the capacitor 47 and the discharge resistor 48, and the output voltage on the emitter side changes to (Vz1 - Vbe). As a result, the amount of negative bias on the gate when the switching element 24a (25a) is off decreases.

(Operation of Example 1)
Fig. 2 is an operation waveform diagram of the PFC circuit of Fig. 1(a). Vgs1 is the gate-source voltage of the switching element 24a composed of a GaN transistor, Vgs2 is the gate-source voltage of the switching element 25a composed of a GaN transistor, Id2 is the forward drain current flowing from the drain to the source of the switching element 25a, and Vds2 is the drain-source voltage of the switching element 25a. td1 and td2 are dead times when the gate-source voltages Vgs1 and Vgs2 of the two switching elements 24a and 25a both become L level and are turned off.
The PFC circuit in FIG. 1 operates as follows (1) to (3) in the periods T1 to T3 shown in FIG.

(1) Period T1: In the case of a heavy load in which the switching element 24a transitions from on to off, the switching element 25a transitions from off to on, and the load current Ir is greater than the threshold current Ith When the drive circuits 26 and 27 operate, the switch 50 turns on, and the DC voltage of the DC power supply 49 is applied to the gates of the switches 24b and 25b via the voltage dividing resistors 24c and 25c, turning the switches 24b and 25b into the on state. The drive pulse GP output from the pulse signal source 51 is applied to the gates of the switching elements 24a and 25a.
Since the load current Ir is a heavy load larger than the threshold current Ith, the switch 45 in the drive circuits 26, 27 remains in the OFF state due to the L-level control signals S32, S33 output from the insulation circuits 32, 33. Then, the transistor 46 is turned on by the Zener voltage Vz1 of the Zener diode 43 and the Zener voltage Vz2 of the Zener diode 44. When the transistor 46 is turned on, the output voltage on the emitter side of the transistor 46 rises to (Vz1+Vz2-Vbe). This voltage is applied to the sources of the switching elements 24a, 25a via the switches 24b, 25b in the ON state. Due to the transition of the drive pulse GP between the H level and the L level, the gate-source voltage Vgs1 of the switching element 24a becomes the H level and the switching element 24a becomes the ON state, and the gate-source voltage Vgs2 of the switching element 25a becomes the L level and the switching element 24a becomes the OFF state due to the increase in the negative bias of the gate.
Therefore, a current flows through the path of the AC power supply 21 →the positive electrode of the rectifier circuit 22 →the choke coil 23 →the switching element 24 a and the switch 24 b in the switch circuit 24 that are in the ON state →the negative electrode of the rectifier circuit 22 →the AC power supply 21.

In this state, the gate-source voltage Vgs1 falls to the L level due to an increase in the negative bias of the gate, turning off the switching element 24a, and transition to the dead time td1 period in which the gate-source voltages Vgs1 and Vgs2 of the switching elements 24a and 25a are both at the L level. Then, a reverse conduction current (-Id2) flows from the source to the drain of the switching element 25a, and a load current Ir flows through the path of the AC power source 21 → the positive pole of the rectifier circuit 22 → the choke coil 23 → the switch 25b and the switching element 25a in the switch circuit 25 → the capacitor 28 and the load 29 → the negative pole of the rectifier circuit 22 → the AC power source 21. As a result, the AC power of the AC power source 21 is rectified by the rectifier circuit 22, and the power is boosted through the choke coil 23, the switch circuit 24, and the switch circuit 25, smoothed by the capacitor 28, and supplied to the load 29. When a reverse conduction current (-Id2) flows from the source to the drain of the switching element 25a, the drain-source voltage Vds2 falls to the L level (a potential below 0 V), causing a reverse conduction voltage drop ΔV.

After the dead time td1 has elapsed, the switching element 24a is in the OFF state, but the gate-source voltage Vgs2 rises to the H level, and the drain-source voltage Vds2 of the switching element 25a becomes approximately 0 V (to be precise, Id2 × Ron, where Ron is the ON resistance of the switching element 25a). Then, the load current Ir continues to flow through the path: AC power source 21 → positive electrode of the rectifier circuit 22 → choke coil 23 → switch 25b and switching element 25a in the switch circuit 25 → capacitor 28 and load 29 → negative electrode of the rectifier circuit 22 → AC power source 21.

Next, the gate-source voltage Vgs2 falls to the L level due to an increase in the negative bias of the gate, turning off the switching element 25a, and a transition occurs to the dead time td2 period in which the gate-source voltages Vgs1 and Vgs2 of the switching elements 24a and 25a are both at the L level. Then, a reverse conduction current (-Id2) continues to flow from the source to the drain of the switching element 25a, and the drain-source voltage Vds2 of the switching element 25a falls to the L level (a potential of 0 V or less), causing a reverse conduction voltage drop ΔV.

(2) Period T2: When the switching element 24a transitions from off to on, the switching element 25a maintains the off state, and the load current Ir changes to a light load smaller than the threshold current Ith After the dead time td2 period has elapsed, the switching element 25a is in the off state, but the gate-source voltage Vgs1 rises to the H level and the switching element 24a is turned on. As a result, a current flows through the following path: AC power supply 21 → positive electrode of the rectifier circuit 22 → choke coil 23 → switching element 24a and switch 24b in the switch circuit 24 → negative electrode of the rectifier circuit 22 → AC power supply 21. When the switching element 24a is turned on, gate noise NS is generated in the gate-source voltage Vgs2. At this time, since the gate-source voltage Vgs2 of the switching element 25a is negatively biased, it does not exceed the gate threshold value and does not erroneously ignite, so that the drain current Id2 does not flow (0 A), and the drain-source voltage Vds2 of the switching element 25a rises to the H level (positive potential).

When the load current Ir becomes a light load smaller than the threshold current Ith, the isolation circuits 32, 33 output H-level control signals S32, S33, turning on the switch 45 in the drive circuits 26, 27. When the switch 45 is turned on, the Zener diode 44 is shorted, and the Zener voltage Vz1 of the Zener diode 43 is applied to the base of the transistor 46, turning off the transistor 46. Then, the output voltage (Vz1 + Vz2 - Vbe) on the emitter side of the transistor 46 is discharged with the discharge time constant of the capacitor 47 and the discharge resistor 48, so that the output voltage on the emitter side changes to (Vz1 - Vbe). Therefore, the amount of negative bias of the gate when the switching element 24a (25a) is off decreases, and the gate-source voltage Vgs2 of the switching element 25a rises to a negative potential of 0V or less.

The gate-source voltage Vgs1 falls to the L level (negative potential of 0 V or less), and the gate-source voltages Vgs1 and Vgs2 of the switching elements 24a and 25a both transition to the dead time td1 period, which is at the L level (negative potential of 0 V or less). Then, due to the reverse conduction current (-Id2) flowing from the source to the drain of the switching element 25a, the drain-source voltage Vds2 of the switching element 25a falls from the H level (positive potential) to the L level (potential of 0 V or less). Next, the gate-source voltage Vgs2 of the switching element 25a rises to the H level, the drain current Id2 rises in the positive direction, and the drain-source voltage Vds2 remains at approximately 0 V. Thereafter, the gate-source voltage Vgs2 of the switching element 25a falls to the L level, and the gate-source voltages Vgs1 and Vgs2 of the switching elements 24a and 25a both transition to the dead time td2 period, where they are both at the L level (negative potential of 0 V or less). Then, due to the positive drain current Id2 flowing from the drain to the source of the switching element 25a, the drain-source voltage Vds2 rises from approximately 0 V to a positive potential.

(3) Period T3: When the switching element 24a transitions from off to on, the switching element 25a maintains the off state, and the load current Ir maintains a light load smaller than the threshold current Ith After the dead time td2 period has elapsed, the switching element 25a is in the off state, but the gate-source voltage Vgs1 rises to the H level and the switching element 24a is turned on. As a result, the drain current Id2 does not flow through the switching element 25a (0 A), and the drain-source voltage Vds2 rises to the H level. At this time, the voltage change amount ΔVds of the drain-source voltage Vds2 of the switching element 25a decreases, so that the gate voltage is prevented from rising through the drain-gate parasitic capacitance in the switching element 25a.

While the gate-source voltage Vgs2 of the switching element 25a maintains a negative voltage of 0V or less, the gate-source voltage Vgs1 falls to the L level (negative potential of 0V or less) to turn off the switching element 24a, and a transition is made to a dead time td1 period in which the gate-source voltages Vgs1 and Vgs2 of the switching elements 24a and 25a are both at the L level. Then, a negative drain current Id2 flows through the switching element 25a, and the drain-source voltage Vds2 falls to the L level (potential of 0V or less). The reverse conduction voltage drop ΔV occurring at this time is smaller than during periods T1 and T2.
Thereafter, the gate-source voltage Vgs2 rises to the H level, and the same operation as above is repeated.

(Effects of Example 1)
1, when there is a high possibility of erroneous firing due to noise NS caused by hard switching, the amount of negative bias of the gate for turning off the switching element 24a or 25a is changed based on information indicating that erroneous firing of the switching element 24a or 25a is likely to occur. This makes it possible to prevent erroneous firing of the switching element 24a or 25a. Furthermore, by reducing the amount of negative bias of the gate under light load conditions, it is possible to reduce the reverse conduction voltage drop ΔV that occurs during the dead time td1 period of the power conversion device when reverse current is conducted from the source to the drain of the switching element 24a or 25a, thereby reducing reverse conduction loss.

(Configuration of Example 2)
3 is a circuit diagram showing a power conversion device (for example, a PFC circuit in a converter) according to a second embodiment of the present invention. In this Fig. 3, elements common to those in Fig. 1 of the first embodiment are denoted by the same reference numerals.
3 in the second embodiment, a current detection circuit 30b similar to that in the first embodiment connected in series to the first switch circuit 24 and a current detection circuit 30c similar to that in the first embodiment connected in series to the second switch circuit 25 are provided instead of the current detection circuit 30 in the PFC circuit in FIG. 1(a) in the first embodiment. Comparators 31a and 31b similar to those in the first embodiment are connected to the output sides of the current detection circuits 30b and 30c, respectively, and a current determination signal S31a output from the comparator 31a is converted into a control signal S32 by an insulating circuit 32 similar to that in the first embodiment and is provided to the first drive circuit 26, and a current determination signal S31b output from the comparator 31b is converted into a control signal S33 by an insulating circuit 33 similar to that in the first embodiment and is provided to the second drive circuit 27.

(Operation of Example 2)
In the second embodiment, whether the load 29 is in a heavy load state or not is determined by detecting the switch circuit currents flowing through the switch circuits 24 and 25 by the current detection circuits 30b and 30c, and the current detection results are sent to the comparators 31a and 31b. If the current detection results exceed the threshold current Ith in the comparators 31a and 31b, the load is determined to be a heavy load, and H-level current determination signals S31a and S31b are output, and L-level control signals S32 and S33 output from the insulation circuits 32 and 33 are provided to the drive circuits 26 and 27. The drive circuits 26 and 27, etc., perform the same operations as those in the first embodiment.

(Effects of Example 2)
In the second embodiment, the current detection circuits 30b and 30c detect the switch circuit currents flowing through the switch circuits 24 and 25, respectively, and the comparators 31a and 31b determine whether the load 29 is in a heavy load state or not. This makes it possible to change the amount of negative bias for turning off the switching element 24a or 25a at a speed corresponding to the switching frequency, thereby providing a semiconductor drive circuit that has an advantageous effect in terms of control responsiveness. Other effects are substantially the same as those of the first embodiment.

(Modification of Examples 1 and 2)
The present invention is not limited to the above-mentioned first and second embodiments, and various uses and modifications are possible. Examples of the uses and modifications include the following (a) to (f).
(a) The present invention is also applicable to Si transistors other than GaN transistors as the switching elements 24a, 25a.
(b) In the semiconductor drive circuit of FIG. 1 or FIG. 3, the rectifier circuit 22 may be configured using bidirectional switches such as FETs instead of the rectifier diodes 22a to 22d.
(c) In the drive circuits 26 and 27 of the first embodiment, the amount of the negative bias for turning off the switching element 24a or 25a is changed based on information on whether the load 29 is in a heavy load state (for example, the load current Ir), but this is not limiting. Information on whether the load 29 is in a heavy load state may be detected from the input voltage, frequency, load voltage, drooping conditions, etc. other than the load current Ir.

(d) The drive circuits 26 and 27 in FIG. 1(b) may be modified to other circuit configurations. For example, an operational amplifier (hereinafter referred to as "op-amp") is provided instead of the resistor 42, the Zener diodes 43 and 44, and the switch 45. The op-amp changes the base voltage Vic of the transistor 46 that constitutes the dropper circuit based on the control signal S32 (S33) output from the insulation circuit 32 (33), and changes the output voltage (Vic-Vbe) of the dropper circuit. If modified to such a configuration, the amount of negative bias of the gate when the switching element 24a (25a) is off can be adjusted linearly. This allows the amount of negative bias to be adjusted to a level that does not cause the gate to erroneously turn on, for example, depending on the magnitude of noise NS, etc.
(e) The drive circuits 26 and 27 in Fig. 1B may be modified to have other circuit configurations. For example, a voltage source may be provided instead of the Zener diodes 43 and 44. Also, another transistor such as an FET may be used instead of the NPN transistor 46.
(f) The present invention can also be applied to other power conversion devices such as AC/DC power supply circuits and chopper circuits other than the PFC circuit in a converter.

21 AC power supply 22 Rectifier circuit 23 Choke coil 24, 25 Switch circuit 24a, 25a Switching element 24b, 25b Switch 26, 27 Drive circuit 28 Capacitor 29 Load 30, 30b, 30c Current detection circuit 31, 31a, 31b Comparator 32, 33 Isolation circuit

Claims (10)

a first switch circuit including a normally-on type first switching element and a normally-off type first switch connected in series between a positive power supply side and a negative power supply side;
a second switch circuit including a normally-on type second switching element and a normally-off type second switch connected in series, the second switching element and the second switch being connected in parallel to the first switch circuit;
a first drive circuit that drives the first switching element to turn on/off during operation and turns the first switch to an on state during operation and an off state when power is stopped;
a second drive circuit that drives the second switching element on/off in a complementary manner with respect to the first switching element with a dead time during operation, and sets the second switch to an on state during operation and to an off state when power is stopped;
In a semiconductor driving circuit comprising:
The first drive circuit and the second drive circuit are
changing an amount of a negative bias for turning off the first switching element or the second switching element based on information indicating that erroneous turning-on of the first switching element or the second switching element is likely to occur;
A semiconductor driver circuit comprising: Information on the likelihood of erroneous ignition of the first switching element or the second switching element occurring is as follows:
The load status is heavy load information.
2. The semiconductor drive circuit according to claim 1. Whether the load state is the heavy load or not is determined by
a load current flowing through the load is detected, and if the detected load current exceeds a threshold current, the load is determined to be heavy;
3. The semiconductor drive circuit according to claim 2. Whether the load state is the heavy load or not is determined by
detecting a switch circuit current flowing through each of the first switch circuit and the second switch circuit, and determining that the load is heavy when each of the detection results exceeds a threshold current;
3. The semiconductor drive circuit according to claim 2. When the load state is the heavy load state, the amount of the negative bias for turning off the first switching element or the second switching element is increased.
5. The semiconductor driver circuit according to claim 2, wherein the semiconductor driver circuit is a semiconductor device. When the load state is light, the amount of the negative bias for turning off the first switching element or the second switching element is reduced.
5. The semiconductor driver circuit according to claim 2, wherein the semiconductor driver circuit is a semiconductor device. The amount of the negative bias is changed linearly.
7. The semiconductor driver circuit according to claim 5 or 6. The semiconductor drive circuit includes:
a circuit including a converter having the first switch circuit and the second switch circuit;
8. The semiconductor driver circuit according to claim 1, wherein the first and second electrodes are electrically connected to the first and second electrodes. The first switching element and the second switching element are
A compound semiconductor device including a GaN transistor.
9. The semiconductor driver circuit according to claim 1, A semiconductor driving circuit according to any one of claims 1 to 9 is used.
A power conversion device comprising:

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