JP2024041688A - semiconductor equipment - Google Patents

Abstract

[Problem] To provide a three-dimensional stacked semiconductor device. [Solution] A semiconductor device 1 electrically connecting a plurality of semiconductor device groups 51, 52 consisting of a plurality of semiconductor devices 511-513, 521 having electrode terminals 60 on different XY coordinate planes includes planar wiring devices 21, 22 on one dielectric sheet 311, on which a plurality of electrical terminals 212 connecting with electrode terminals of any semiconductor device placed on one XY coordinate plane and a conductive pattern 213 connecting between the arbitrary electrical terminals are placed, a wiring pattern group 315 on one dielectric sheet, having a terminal array 312 having open ends in the vertical direction Z on the one dielectric sheet and connecting with a plurality of electrode terminals of any semiconductor device and a plurality of conductive patterns 313 continuing from the terminal array, a wiring pattern group 316 including a plurality of conductive patterns 314 extending at least in the vertical direction in a space outside the plane occupied by the electrode terminals of the semiconductor device group, and vertical wiring devices 31, 32 electrically connecting each wiring pattern group. [Selected Figure] FIG.

Description

The present invention relates to a semiconductor device in which a plurality of semiconductor devices are connected and mounted.

With the advent of IoT, AI, and 5G society, semiconductors to be applied to these industries are required to have multiple functions, higher functionality, smaller size, and lower cost. In order to meet such demands, various semiconductor device mounting forms have been introduced. Vertical wiring using through-silicon vias (TSVs), which is called three-dimensional (3D) stacking, is mainly used for connections between ICs of the same type, such as DRAMs. On the other hand, the most common connection technology between different types of ICs is a method called 2.5-dimensional (2.5D) stacking, in which multiple different types of ICs are mounted on the same package surface to form a system and form one device chip. This is called a System in a Package (SiP).

Packaging technology to achieve even higher density and miniaturization of SiP uses TSV technology to enable conduction between the upper and lower sides, and uses an interposer made of silicon or other material with fine wiring to connect fine terminals on the IC chip side. In many cases, a method is adopted in which a build-up wiring board or the like made of an organic base material is used as a wiring means to connect to the device PCB side (Patent Document 1). Furthermore, we apply high-density wiring technology using silicon substrates only to high-density signal connections between multiple ICs called silicon bridges, and embed these silicon substrates in organic material substrates to connect power supply and device interface signals, etc. A method using wiring within the board (Patent Document 2) has been put into practical use.

In this way, as a means to realize higher density and smaller size of SiP,
▲1▼Thin film wafer process as a means of realizing fine terminal connections and fine rewiring on the IC chip side,
▲2▼TSV technology as a means of transmission between the top and bottom of the silicon substrate,
▲3▼ The mainstream is to select and combine build-up organic substrate technologies as a means of increasing the wiring pitch and connecting to the device PCB terminals.

However, the characteristics and problems of the conventional methods typified by Patent Document 1 or Patent Document 2 are as shown below.
For one thing, as the number of ICs to be mounted increases or the number of input/output (I/O) terminals increases and the density increases, the number of wiring between terminals must increase or the number of layers must increase. This leads to an increase in manufacturing costs.
In addition, in order to increase the number of wires between the terminals, it is necessary to miniaturize the wires (for example, to a wire width of 2 μm class), which requires the use of a wafer manufacturing process, and the surface area of the silicon substrate. TSV technology is essential as a connection means on the back side, leading to increased manufacturing costs and decreased yield.
Furthermore, combining a wiring board made using wafer process or TSV technology with a board made using organic substrate technology can lead to deterioration of characteristics, increased manufacturing costs, and longer delivery times for development and manufacturing due to the mixture of different manufacturing processes. There is.

On the other hand, electroforming, a technology for forming fine shapes using so-called plating techniques, has recently been developed to be applied to a wide range of fields. As a means for connecting a large number of semiconductor device terminals, a wiring pattern sheet having terminals and wiring protruding perpendicularly to the semiconductor device terminal array plane and a wiring pattern sheet having common wiring outside the semiconductor device are connected. A method has been reported in which a plurality of semiconductor devices can be connected either horizontally or vertically (Patent Document 3, Patent Document 4). The invention has the advantage of eliminating the need for multilayer wiring boards while making fine wiring possible. However, this method has a problem in that it is difficult to deal with wiring that intersects on the same plane.

Furthermore, in a wiring device in which a plurality of electrical terminals connected to semiconductor device terminals installed on one plane and a conductive pattern connecting those electrical terminals are formed by electroforming or etching processing, two or more By having an intersection where a part of the conductive pattern intersects with a step in the Z direction, it is possible to create fine wiring that does not depend on the silicon process, while eliminating the need for multilayer wiring boards when connecting multiple semiconductor devices. By doing so, a device that provides a high-density wiring device at low cost has been introduced. (Patent Document 5) However, this method has a problem in that it is difficult to deal with semiconductor devices that are wired in a vertical direction.

Japanese Patent Application Publication No. 2009-110983 Japanese Patent Application Publication No. 2014-179613 Japanese Patent Application Publication No. 2021-1118341 JP 2021-121011 Publication Patent application No. 2022-109339

The present invention solves the problem of conventional multilayer substrates with fine wiring, and is a semiconductor device consisting of a plurality of semiconductor devices having electrode terminals at different coordinates on the XY coordinate plane in the vertical direction (Z direction). In a semiconductor device in which a group of devices are electrically connected to each other in a planar direction and a vertical direction, a plurality of electrical terminals connected to electrode terminals of the semiconductor devices and an arbitrary A conductive pattern connecting electrical terminals is formed on one dielectric sheet by electroforming or etching, and a wiring pattern including a plurality of intersecting wiring parts is formed on the single dielectric sheet in a planar direction. A wiring device, a terminal array having a vertically open end and connecting to a plurality of electrode terminals of an arbitrary semiconductor device, and a plurality of terminal arrays continuing from the terminal array as means for vertically interconnecting a plurality of semiconductor devices. a first wiring pattern group having a conductive pattern, and a second wiring pattern group including a plurality of conductive patterns installed in a space outside the plane occupied by the electrode terminals of the semiconductor device group and extending at least in a vertical direction; By combining a vertical wiring device with a configuration in which the first wiring pattern group and the second wiring pattern group are electrically connected, it is possible to perform fine wiring that does not depend on the silicon process, while also making it possible to By eliminating multilayer wiring boards for connecting semiconductor devices, a high-density wiring device can be provided at low cost.
The present invention makes it possible to simultaneously mount semiconductor devices such as a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), and a memory in multiple stages in the vertical direction, that is, in three-dimensional (3D) stacking. In such a system configuration, it is possible to realize downsizing and cost reduction.

The present invention provides a first semiconductor device group composed of a plurality of semiconductor devices having electrode terminals at arbitrary coordinates on an XY coordinate plane, and a direction perpendicular to the XY coordinate plane ( In a semiconductor device electrically connected to a second semiconductor device group consisting of a plurality of semiconductor devices having electrode terminals at arbitrary coordinates on an XY coordinate plane different in the Z direction),
A wiring device that electrically connects a plurality of semiconductor devices in the first or second semiconductor device group in an XY plane direction, the wiring device being connected to an electrode terminal of any of the semiconductor devices installed on one XY coordinate plane. a planar wiring device in which a plurality of electrical terminals and a conductive pattern connecting any of the electrical terminals are installed on one dielectric sheet;
A wiring device that electrically connects an arbitrary semiconductor device in the first semiconductor device group and an arbitrary semiconductor device in the second semiconductor device group in the vertical direction (Z direction), the wiring device including one dielectric material. a first wiring pattern group having a terminal array having an open end in the vertical direction on the sheet and connecting to a plurality of electrode terminals of an arbitrary semiconductor device, and a plurality of conductive patterns continuing from the terminal array; a second wiring pattern group that is installed in a space outside the plane occupied by the electrode terminals of the semiconductor device group and includes a plurality of conductive patterns extending at least in the vertical direction; and one or more vertical wiring devices electrically connected to the wiring pattern group;
A semiconductor device group consisting of a plurality of semiconductor devices having electrode terminals at different coordinates on an XY coordinate plane in the vertical direction (Z direction) is mounted vertically, and electrically connected in the planar and vertical directions. It becomes possible to connect.

Further, the first or second semiconductor device group and the electrodes are arranged at arbitrary coordinates on different XY coordinate planes in the perpendicular direction (Z direction) to the XY coordinate plane constituting the first or second semiconductor device group. In a semiconductor device electrically connected to a third and subsequent group of N (N is an integer) semiconductor devices each including a plurality of semiconductor devices having terminals,
A wiring device that electrically connects a plurality of semiconductor devices in the first, second, or third and subsequent semiconductor device groups in the XY plane direction, and wherein any of the semiconductor devices installed on one XY coordinate plane a planar wiring device in which a plurality of electrical terminals that connect to electrode terminals of a semiconductor device and a conductive pattern that connects any of the electrical terminals are installed on one dielectric sheet;
Any semiconductor device in the first semiconductor device group, any semiconductor device in the second semiconductor device group, and any semiconductor device in the third and subsequent semiconductor device groups are aligned in the vertical direction (Z direction). ), the wiring device includes a terminal array having a vertically open end and connecting to a plurality of electrode terminals of an arbitrary semiconductor device, and a plurality of conductive patterns continuing from the terminal array. and a second wiring pattern group including a plurality of conductive patterns installed in a space outside the plane occupied by the semiconductor device and extending at least in the vertical direction, the first wiring pattern and one or more vertical wiring devices electrically connecting any of the second wiring pattern group and the third and subsequent wiring pattern groups;
Semiconductor device groups consisting of a plurality of semiconductor devices having electrode terminals at different coordinates on the XY coordinate plane in the vertical direction (Z direction) are mounted in multiple stages in the vertical direction, and electrically connected in the planar and vertical directions. For example, it is possible to mount semiconductor devices such as a CPU, GPU, and memory at the same time, making it possible to realize miniaturization and cost reduction in system configurations such as high-performance computers. .

Further, in the planar wiring device or the vertical wiring device, since the electrical terminal and the conductive pattern are formed by plating or etching, it is possible to achieve fine wiring that does not depend on a silicon process while achieving high density. A wiring device can be provided at low cost.

Further, in any one of the planar wiring device or the vertical wiring device, a portion of the two or more conductive patterns has a wiring intersection portion that intersects with a step, and at least the wiring intersection portion Since the method has means for providing a dielectric film independently on the surface of each of the conductive patterns or commonly on the surfaces of a plurality of the conductive patterns, a plurality of cross wirings can be formed on a single dielectric sheet. , it is possible to eliminate the need for multiple layers in the conventional substrate.

Further, in any one of the planar wiring devices, since a part or all of the electrical terminal has a means for having a through hole, the terminal post can be inserted into the electrode terminal of the semiconductor device installed, so that connection is facilitated. Become.

According to the wiring device of the present invention, semiconductor device groups constituted by a plurality of semiconductor devices having electrode terminals at coordinates on an XY coordinate plane that are different in the vertical direction (Z direction) are electrically interconnected in the planar direction and the vertical direction. In a semiconductor device to be connected, as a means for interconnecting a plurality of semiconductor devices in a planar direction, a plurality of electrical terminals that are connected to electrode terminals of the semiconductor device and a conductive pattern that connects any of the electrical terminals are formed by electroforming. Or vertical wiring connection between a planar wiring device formed on one dielectric sheet by etching and a wiring pattern including a plurality of cross wiring parts on the single dielectric sheet, and multiple semiconductor devices. A first wiring pattern group having a vertically open end and connecting to a plurality of electrode terminals of an arbitrary semiconductor device, and a plurality of conductive patterns continuing from the terminal arrangement; a second wiring pattern group including a plurality of conductive patterns installed in a space outside the plane occupied by the electrode terminals of the semiconductor device group and extending at least in the vertical direction, the first wiring pattern group and the second wiring pattern group; By combining a vertical wiring device with a configuration in which a group of wiring patterns are electrically connected, it is possible to achieve fine wiring that does not depend on silicon processes, while eliminating the need for multilayer wiring boards when connecting multiple semiconductor devices. Therefore, a high-density wiring device can be provided at low cost.
Further, with the semiconductor device according to the present invention, semiconductor devices such as a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), and a memory can be simultaneously mounted in multiple stages in the vertical direction, that is, in three-dimensional (3D) stacking. This makes it possible to realize downsizing and cost reduction in system configurations such as computers.

A diagram showing the basic configuration of a semiconductor device according to the present invention FIG. 2 is a perspective view showing the structure of a planar directional wiring device according to the present invention; A diagram showing the basic structure of the vertical wiring device of the present invention A diagram showing the structure of a wiring intersection in a planar wiring device of the present invention A diagram showing the structure of a wiring intersection in a vertical wiring device of the present invention A diagram showing another embodiment of the structure of the wiring intersection part of the present invention FIG. 1 is a perspective view showing a semiconductor device according to an embodiment of the present invention;

Next, the semiconductor device of the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing the basic configuration of a semiconductor device according to the present invention.
In FIG. 1, 1 is a semiconductor device according to the present invention, and includes a first semiconductor device group 51 comprising a plurality of semiconductor devices 511, 512, and 513 having electrode terminals 60 at arbitrary coordinates on an XY coordinate plane; A second semiconductor device comprising a plurality of semiconductor devices 521 and the like having electrode terminals 60 at arbitrary coordinates on an XY coordinate plane that is different in the perpendicular direction (Z direction) to the XY coordinate plane having the first semiconductor device group 51. In the means for electrically connecting the semiconductor device group 52, the wiring device electrically connects a plurality of semiconductor devices in the first or second semiconductor device group 51, 52 in the XY plane direction, A plurality of electrical terminals 212 that connect to the electrode terminals 60 of any of the semiconductor devices installed on the XY coordinate plane and a conductive pattern 213 that connects any of the electrical terminals 212 are each formed of one dielectric sheet. 211, an arbitrary semiconductor device in the first semiconductor device group 51, and an arbitrary semiconductor device in the second semiconductor device group 52 in the vertical direction ( A wiring device electrically connected in the Z direction), which includes a terminal array 312 having an open end in the vertical direction on one dielectric sheet 311 and connecting to a plurality of electrode terminals of an arbitrary semiconductor device, and the terminals. A first wiring pattern group 315 having a plurality of conductive patterns 313 continuing from the array 312, and a plurality of conductive patterns installed in a space outside the plane occupied by the semiconductor device groups 51 and 52 and extending at least in the vertical direction. a second wiring pattern group 316 including a pattern 314, and one or more (in this figure, two wiring patterns) electrically connecting the first wiring pattern group 315 and the second wiring pattern group 316. ) Vertical wiring devices 31 and 32.
Although this figure shows an example in which the electrode terminals of the semiconductor devices 511 and 512 are connected, the target semiconductor devices and electrode terminals are not limited to this.

The planar wiring devices 21, 22 and the vertical wiring devices 31, 32 will be described in more detail with reference to FIGS.

FIG. 2 is a perspective view showing the structure of the planar wiring device according to the present invention, and also shows the relationship with the semiconductor device group 51. A plurality of the electrical terminals 212 that match the XY coordinates of the electrode terminals 60 installed on the three semiconductor devices 511, 512, 513 of the semiconductor device group 51 installed on one XY coordinate plane, and any of the A conductive pattern 213 connecting the electrical terminals 212 is installed on one dielectric sheet 211.

In the present invention, a terminal post 61 is installed on all the electrode terminals 60 to which the semiconductor device is connected, and is inserted into a through hole 214 provided in the electrical terminal 212 of the planar wiring device 21 and fixed. It is something to do. This enables electrical connection between the semiconductor devices 511, 512, and 513.

In the planar wiring device, the electrical terminal and the conductive pattern can be formed by plating (electroforming) or etching.

FIG. 3 is a diagram showing the basic structure of the vertical wiring device of the present invention. In FIG. 3, reference numeral 5 shows a part of a cross section of one semiconductor device, and terminal posts 61a to 61d are installed on an electrode terminal 6 formed on an electric circuit. Reference numeral 30 denotes a vertical wiring device, which includes terminal arrays 302a to 302d having open ends in the vertical direction at positions in contact with the terminal posts 61a to 61d provided on the electrode terminals 6 of the semiconductor device, and each of the terminal arrays. A first wiring pattern group 305 having a plurality of conductive patterns 303a to 303d continuing from 302a to 302d, and a plurality of conductive patterns extending at least perpendicularly to the out-of-plane space occupied by the semiconductor device 5. 304a to 304d, electrically connects the first wiring pattern group 305 and the second wiring pattern group 306, and is formed on one dielectric sheet 301. It is what was done.

For example, when the terminal array is connected to the tip of the terminal post 61a of the semiconductor device, the electrode terminal of another semiconductor device or other external electrically connected to a device (not shown).

In the vertical wiring device, the electrical terminal and the conductive pattern can be formed by plating (electroforming) or etching.

FIG. 4 is a diagram showing the structure of the wiring intersection in the planar wiring device of the present invention. The wiring intersection structure shown in FIG. 4 is mainly suitable for wiring intersection in the planar wiring device in the semiconductor device of the present invention, but is not limited thereto. In FIG. 4, 20 is a planar wiring device and shows one wiring intersection 205. Conductive patterns 203a and 203b intersect on one dielectric sheet 201. As shown in the cross section A-A, the conductive pattern 203b is a conductive pattern 203b1 that passes through the same surface (front surface) as the conductive pattern 203a at the wiring intersection 205, through a through portion 203b2, a conductive pattern 203b3 that passes through the back surface of the dielectric sheet 201, and a conductive pattern 203b5 that passes through the front surface again through a through portion 203b4. This avoids contact with the conductive pattern 203a.

FIG. 5 is a diagram showing the structure of a wiring intersection in the vertical wiring device of the present invention, and shows a method of connecting the first wiring pattern group 305 and the second wiring pattern group 306 in FIG. 3. It is. The wiring crossing structure shown in FIG. 5 is mainly suitable for wiring crossing in the vertical wiring device in the semiconductor device of the present invention, but is not limited thereto. In FIG. 5, the conductive patterns 303a to 303d in the first wiring pattern group 305 and the conductive patterns 304a to 304d in the second wiring pattern group 306 connected to electrode terminals of a semiconductor device are They are formed on one dielectric sheet 301 and electrically connected. The present invention is characterized in that a dielectric film 307 is provided at the connection portions between the conductive patterns 303a to 303d and the conductive patterns 304a to 304d. As shown in cross section BB, for example, by providing the dielectric film 307 in the connection between the conductive pattern 303a and the conductive pattern 304a, the conductive pattern 303a can be connected to the conductive patterns 304b to 304b. Contact with 304d can be avoided.

With this method, for example, by applying the second wiring pattern group 306 to a common signal line (bus wiring) of a plurality of CPUs, GPUs, etc., it can be used to connect a plurality of semiconductor devices.

FIG. 6 is a diagram showing another embodiment of the structure of the wiring intersection portion of the present invention. FIG. 6A shows an example in which a plurality of electrical terminal rows 2a to 24 and 2e to 2h installed on a dielectric sheet 201 are connected by conductive patterns 3a to 3d. When connected as shown in FIG. 6A, the conductive pattern 3a intersects with the conductive patterns 3c and 3d, and the conductive pattern 3b intersects with the conductive patterns 3c and 3d. In cross section CC shown in FIG. 6(b), a dielectric film 206 is formed on the surface of the conductor after the conductors of the conductive patterns 3a and 3b are formed. Thereby, the conductive patterns 3c and 3d crossing the upper portions of the conductive patterns 3a and 3b can be electrically independently wired.

Furthermore, by forming a dielectric film on the surface of the conductor after forming the conductor in the conductive patterns 3c and 3d, other wiring (not shown) can also cross over the conductive patterns 3c and 3d. .

FIG. 7 is a perspective view showing a semiconductor device according to an embodiment of the present invention, and is an example of a semiconductor device composed of four semiconductor device groups arranged at different positions in the vertical direction (Z direction). In FIG. 7, 51 is a first semiconductor device group composed of semiconductor devices 511 to 516, and 52 is on an XY coordinate plane that is different in the Z direction from the XY coordinate plane that constitutes the first semiconductor device group 51. A second semiconductor device group 53 consisting of a plurality of semiconductor devices 521, 524, etc. having electrode terminals at the coordinates of A third semiconductor device group 54 is composed of a plurality of semiconductor devices 531 and 534 having electrode terminals at different coordinates on the XY coordinate plane in the Z direction with respect to the coordinate plane, and 54 is the first semiconductor device group 51 Or a plurality of semiconductor devices 541, 544, etc. having electrode terminals at different coordinates on the XY coordinate plane in the Z direction with respect to the XY coordinate plane constituting the second semiconductor device group 52 or the third semiconductor device group 53. A fourth semiconductor device group is shown.

Reference numeral 21 denotes a planar wiring device that electrically connects the plurality of semiconductor devices 511 to 516 in the first semiconductor device group 51 in the XY plane direction, and connects the electrodes of the semiconductor devices on one XY coordinate plane. A plurality of electrical terminals 212 that connect to the terminals 60 and a conductive pattern 213 that connects any of the electrical terminals 212 are installed on one dielectric sheet 211.

22 is a planar wiring device that electrically connects the plurality of semiconductor devices 521, 524, etc. in the second semiconductor device group 52 in the XY plane direction, and connects the semiconductor devices on one XY coordinate plane. A plurality of electrical terminals 222 that connect to the electrode terminals 60 and a conductive pattern (not shown) that connects any of the electrical terminals 222 are installed on one dielectric sheet 221.

Reference numeral 23 denotes a planar wiring device that electrically connects the plurality of semiconductor devices 531, 534, etc. in the third semiconductor device group 53 in the XY plane direction, and on a single XY coordinate plane, a plurality of electrical terminals 232 that connect to the electrode terminals 60 of the semiconductor devices and a conductive pattern (not shown) that connects between any of the electrical terminals 232 are installed on a single dielectric sheet 231.

Similarly, 24 is a planar wiring device that electrically connects the plurality of semiconductor devices 541, 544, etc. in the fourth semiconductor device group 54 in the XY plane direction. A plurality of electrical terminals 242 that connect to the electrode terminals 60 of the semiconductor device and a conductive pattern (not shown) that connects any of the electrical terminals 242 are installed on one dielectric sheet 241.

On the other hand, 31 to 38 are vertical wiring devices, which connect any semiconductor device in the first semiconductor device group, any semiconductor device in the second semiconductor device group, and any semiconductor device in the third semiconductor device group. and any semiconductor device in the fourth semiconductor device group in the vertical direction (Z direction), the wiring device having an open end in the vertical direction and connecting the semiconductor device with any semiconductor device in the fourth semiconductor device group. a first wiring pattern group 315 having a terminal array 312 connected to a plurality of electrode terminals, and a plurality of conductive patterns 313 continuing from the terminal array 312; It consists of a second wiring pattern group 316 including a plurality of conductive patterns 314 extending in the vertical direction, and electrically connects the first wiring pattern group 315 and the second wiring pattern group 316. be.

In this embodiment, the vertical wiring devices 31, 32, 33, and 34 connect the semiconductor device 511 of the semiconductor device group 51, the semiconductor device 521 of the semiconductor device group 52, and the semiconductor device 531 of the semiconductor device group 53. The vertical wiring devices 35 , 36 , 37 , 38 connect the semiconductor devices 514 of the semiconductor device group 51 between the electrode terminals having the same XY coordinate values in the semiconductor devices 541 of the semiconductor device group 54 . and the electrode terminals having the same XY coordinate values in the semiconductor device 524 of the semiconductor device group 52, the semiconductor device 534 of the semiconductor device group 53, and the semiconductor device 544 of the semiconductor device group 54 are connected. However, the target semiconductor devices and electrode terminals are not limited to these.

Further, in this embodiment, the "space outside the plane occupied by the semiconductor device" in which the vertical wiring device is installed is realized by providing a common opening 217 in the center of the planar wiring device.

According to this embodiment, for example, the semiconductor device 511 in the semiconductor device group 51 is used as a CPU, the semiconductor devices 512 and 513 are used as a memory IC for the CPU, the semiconductor device 514 is used as a GPU, and the semiconductor devices 515 and 516 are used as a CPU. By using it as a memory IC for GPU, a computer system for image processing can be configured, and the planar wiring device is applied to the connection between the CPU and the memory IC, or the connection between the GPU and the memory IC, and The vertical wiring device can be applied to common signal bus wiring between multiple CPUs or between multiple GPUs, and the semiconductor device groups 52 to 54 have the same configuration as the semiconductor device group 51. As a result, a high-performance, large-capacity computer system can be constructed in a space-saving manner.

Further, the semiconductor device groups 51 to 54 may each be composed of different types of semiconductor devices. Further, although this embodiment is an example of a semiconductor device composed of four semiconductor device groups arranged at different positions in the vertical direction (Z direction), the number of semiconductor device groups stacked in the Z direction is not limited to this. .

As described above, according to the semiconductor device of the present invention, groups of semiconductor devices constituted by a plurality of semiconductor devices having electrode terminals at different coordinates on the XY coordinate plane in the vertical direction (Z direction) can be connected to each other in the plane direction. In a semiconductor device that is electrically connected in a vertical direction, as a means for interconnecting a plurality of semiconductor devices in a planar direction, a conductive device is used to connect a plurality of electrical terminals connected to an electrode terminal of a semiconductor device and any of the electrical terminals. A planar wiring device in which a wiring pattern is formed on a single dielectric sheet by electroforming or etching, and a wiring pattern including a plurality of intersecting wiring portions is formed on the single dielectric sheet; As a means for vertically wiring connecting devices, a terminal array having a vertically open end and connecting to a plurality of electrode terminals of an arbitrary semiconductor device, and a plurality of conductive patterns continuing from the terminal array. a second wiring pattern group including a plurality of conductive patterns installed in a space outside the plane occupied by electrode terminals of the semiconductor device group and extending at least in the vertical direction; By combining a vertical wiring device with a configuration in which a wiring pattern group and the second wiring pattern group are electrically connected, a wiring board for connecting a plurality of semiconductor devices while enabling fine wiring that does not depend on a silicon process. By eliminating multilayering, a high-density wiring device can be provided at low cost.

Further, the semiconductor device according to the present invention makes it possible to simultaneously mount semiconductor devices such as a CPU, GPU, and memory in multiple stages in the vertical direction, that is, in a three-dimensional (3D) stacked manner, in a system configuration such as a computer. It is possible to realize downsizing and cost reduction.

The present invention can be used in a semiconductor device in which a plurality of semiconductor devices are stacked horizontally or vertically.

1, 10 Semiconductor devices 20 to 24 Planar wiring devices 201, 211, 221, 231, 241 Dielectric sheets 202, 212, 222, 232, 242, 2a to 2h Electric terminals 203, 213 Conductive patterns 204, 214 Through holes 205, 215 Wiring intersection 206 Dielectric film 217 Openings 30-38 Vertical wiring devices 301, 311 Dielectric sheets 302, 312 Terminal arrays 303, 304, 313, 314, 3a-3d Conductive patterns 305-307, 315 , 316 Wiring pattern group 5, 511-516, 521, 524, 531, 534, 541, 544 Semiconductor devices 51-54 Semiconductor device group 6, 60 Electrode terminal 61 Terminal post

Claims (7)

In a semiconductor device electrically connecting a first semiconductor device group consisting of a plurality of semiconductor devices having electrode terminals at arbitrary coordinates on an XY coordinate plane, and a second semiconductor device group consisting of a plurality of semiconductor devices having electrode terminals at arbitrary coordinates on an XY coordinate plane different in a direction perpendicular (Z direction) to the XY coordinate plane having the first semiconductor device group, the semiconductor device comprises: a wiring device electrically connecting the plurality of semiconductor devices in the first or second semiconductor device group in an XY plane direction, the wiring device including a plurality of electrical terminals connected to the electrode terminals of any of the semiconductor devices arranged on a single XY coordinate plane and a conductive pattern connecting between the arbitrary electrical terminals arranged on a single dielectric sheet;
a wiring device for electrically connecting an arbitrary semiconductor device in the first semiconductor device group and an arbitrary semiconductor device in the second semiconductor device group in a vertical direction (Z direction), the wiring device comprising: a first wiring pattern group having a terminal array having open ends in the vertical direction on one dielectric sheet and connected to a plurality of electrode terminals of the arbitrary semiconductor device, and a plurality of conductive patterns continuing from the terminal array; and a second wiring pattern group disposed in a space outside a plane occupied by the electrode terminals of the semiconductor device group and including a plurality of conductive patterns extending at least in the vertical direction, the semiconductor device being configured with one or more vertical wiring devices electrically connecting the first wiring pattern group and the second wiring pattern group. The first or second semiconductor device group and electrode terminals at arbitrary coordinates on different XY coordinate planes in the perpendicular direction (Z direction) to the XY coordinate plane constituting the first or second semiconductor device group. In a semiconductor device electrically connected to a third and subsequent group of N (N is an integer) semiconductor devices constituted by a plurality of semiconductor devices having
A wiring device that electrically connects a plurality of semiconductor devices in the first, second, or third and subsequent semiconductor device groups in the XY plane direction, and wherein any of the semiconductor devices installed on one XY coordinate plane a planar wiring device in which a plurality of electrical terminals that connect to electrode terminals of a semiconductor device and a conductive pattern that connects any of the electrical terminals are installed on one dielectric sheet;
Any semiconductor device in the first semiconductor device group, any semiconductor device in the second semiconductor device group, and any semiconductor device in the third and subsequent semiconductor device groups are aligned in the vertical direction (Z direction). ), the wiring device includes a terminal array having a vertically open end and connecting to a plurality of electrode terminals of an arbitrary semiconductor device, and a plurality of conductive patterns continuing from the terminal array. and a second wiring pattern group including a plurality of conductive patterns installed in a space outside the plane occupied by the semiconductor device and extending at least in the vertical direction, the first wiring pattern and one or more vertical wiring devices electrically connecting the second wiring pattern group and any of the third and subsequent wiring pattern groups. 3. The semiconductor device according to claim 1, wherein in the planar wiring device or the vertical wiring device, the electrical terminal and the conductive pattern are formed by plating or etching. Any one of the planar wiring device or the vertical wiring device has a wiring intersection where two or more of the conductive patterns intersect with a step, and at least each of the wiring intersections has a step. 4. The semiconductor device according to claim 1, further comprising a dielectric film independently on the surface of the conductive pattern or commonly on the surfaces of a plurality of the conductive patterns. 5. The semiconductor device according to claim 1, wherein in any one of said planar wiring devices, a part or all of said electrical terminals have a through hole. 3. The planar wiring device is applied to at least a connection between a Central Processing Unit (CPU) and a memory IC, or a connection between a Graphics Processing Unit (GPU) and a memory IC. A semiconductor device according to any one of 3. The semiconductor device according to claim 1, wherein the vertical wiring device is applied to at least a common signal bus wiring of a plurality of CPUs or a plurality of GPUs.

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