JP2024027256A - Semiconductor device and semiconductor element - Google Patents

Abstract

To provide a semiconductor device and a semiconductor element capable of reducing parasitic inductance in wiring.SOLUTION: A semiconductor device A10 comprises: a first semiconductor element 31 that has a first gate electrode 311, a first electrode 312, and a second electrode 313; a second semiconductor element 32 that has a second gate electrode 321, a third electrode 322, and a fourth electrode 323; and a drive element 33 conductive to the first gate electrode 311 and the second gate electrode 321. When seen in a first direction, the first gate electrode 311 and the second gate electrode 321 are located between a first center C1 of the first semiconductor element 31 and a second center C2 of the second semiconductor element 32 in a second direction x. When seen in the first direction, the first gate electrode 311 and the second gate electrode 321 are located between the drive element 33 and the first and second centers C1 and C2 in a third direction y.SELECTED DRAWING: Figure 3

Description

The present disclosure relates to a semiconductor device and a semiconductor element.

Patent Document 1 discloses an example of a semiconductor device including a horizontally structured semiconductor element (HEMT). The semiconductor element has a first electrode and a second electrode. In this semiconductor device, a semiconductor element is bonded to a die pad. The first electrode and the second electrode are electrically connected to a plurality of terminal leads located around the die pad via wires.

In the semiconductor device disclosed in Patent Document 1, transmission of high-frequency electrical signals is sometimes required in order to achieve more efficient power conversion. To this end, it is required to reduce parasitic inductance in wiring that serves as a transmission path for the electrical signal.

JP2020-188085A

In view of the above-mentioned circumstances, an object of the present disclosure is to provide a semiconductor device and a semiconductor element that can reduce parasitic inductance in wiring.

A semiconductor device provided by a first aspect of the present disclosure includes a first semiconductor element having a first electrode, a second electrode, and a first gate electrode located on one side in a first direction; A second semiconductor having a third electrode, a fourth electrode, and a second gate electrode located on the side where the first electrode is located, and separated from the first semiconductor element in a second direction orthogonal to the first direction. the first gate electrode and the second semiconductor element, the first gate electrode and the second semiconductor element being located on one side of a third direction perpendicular to the first direction and the second direction with respect to the first semiconductor element and the second semiconductor element; a driving element that is electrically connected to two gate electrodes, and when viewed in the first direction, the first gate electrode and the second gate electrode are connected to a first center of the first semiconductor element in the second direction; The first gate electrode and the second gate electrode are located between the second center of the second semiconductor element and the drive element when viewed in the first direction. , located between the first center and the second center.

A semiconductor device provided by a second aspect of the present disclosure includes a main body, a first electrode, a second electrode, and a first electrode located on one side of the main body in the first direction and electrically connected to the main body. a gate electrode and a second gate electrode; when viewed in the first direction, the main body has a first edge extending in a second direction perpendicular to the first direction; a second edge extending in a third direction perpendicular to the second direction, the length of the first edge is smaller than the length of the second edge, and the first gate electrode and the second edge The gate electrodes are spaced apart from each other in the second direction, and when viewed in the first direction, the first gate electrode and the second gate electrode are located closer to the first edge than to the center of the main body. do.

According to the configuration of the semiconductor device and semiconductor element according to the present disclosure, it is possible to reduce parasitic inductance in wiring.

Other features and advantages of the present disclosure will become more apparent from the detailed description given below in conjunction with the accompanying drawings.

FIG. 1 is a plan view of a semiconductor device according to a first embodiment of the present disclosure. FIG. 2 is a plan view corresponding to FIG. 1, and the illustration of the fourth insulating layer, the plurality of first vias, the plurality of second vias, and the plurality of heat dissipation layers is omitted. FIG. 3 is a plan view corresponding to FIG. 2, and illustration of the third insulating layer and the plurality of intermediate layers is omitted. FIG. 4 is a plan view corresponding to FIG. 3, in which the second insulating layer is omitted and the first semiconductor element, the second semiconductor element, and the driving element are transparent. FIG. 5 is a bottom view of the semiconductor device shown in FIG. 1, with the cover layer being transparent. FIG. 6 is a sectional view taken along line VI-VI in FIG. 4. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 4. FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. 4. FIG. 9 is a sectional view taken along line IX-IX in FIG. 4. FIG. 10 is a cross-sectional view taken along line XX in FIG. 4. FIG. 11 is a partially enlarged view of FIG. 4. FIG. 12 is a sectional view taken along line XII-XII in FIG. 11. FIG. 13 is a plan view of a semiconductor device according to a second embodiment of the present disclosure. FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 13. FIG. 15 is a sectional view taken along line XV-XV in FIG. 13. FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 13. FIG. 17 is a plan view of a semiconductor device according to a third embodiment of the present disclosure. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 17. FIG. 19 is a sectional view taken along line XIX-XIX in FIG. 17. FIG. 20 is a sectional view taken along line XX-XX in FIG. 17. FIG. 21 is a plan view of a semiconductor device according to an embodiment of the present disclosure. FIG. 22 is a cross-sectional view taken along line XXII-XXII in FIG. 21. FIG. 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 21. FIG. 24 is a plan view of a semiconductor device according to a fourth embodiment of the present disclosure, and illustration of some components is omitted.

Embodiments for carrying out the present disclosure will be described based on the accompanying drawings.

[First embodiment]
A semiconductor device A10 according to a first embodiment of the present disclosure will be described based on FIGS. 1 to 12. The semiconductor device A10 includes a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, a fourth insulating layer 14, a first wiring 21, a second wiring 22, a third wiring 23, a fourth wiring 24, and a plurality of power wiring 25 , a plurality of control wirings 26 , a plurality of communication wirings 29 , a first semiconductor element 31 , a second semiconductor element 32 , a driving element 33 , and a plurality of connection wirings 39 . Further, the semiconductor device A10 includes a plurality of first vias 41, a plurality of second vias 42, a plurality of third vias 43, a plurality of fourth vias 44, a plurality of fifth vias 45, a plurality of terminals 51, a covering layer 52, It includes a plurality of heat dissipation layers 61 and a plurality of intermediate layers 62. The semiconductor device A10 is in the form of a resin package that is surface mounted on a wiring board.

Here, for convenience of understanding, FIG. 2 omits illustration of the fourth insulating layer 14, the plurality of first vias 41, the plurality of second vias 42, and the plurality of heat dissipation layers 61. For convenience of understanding, FIG. 3 omits illustration of the third insulating layer 13 and the plurality of intermediate layers 62 compared to FIG. 2 . For convenience of understanding, FIG. 4 omits the illustration of the second insulating layer 12 compared to FIG. 3, and shows the first semiconductor element 31, the second semiconductor element 32, and the drive element 33. In FIG. 4, the plurality of first semiconductor elements 31, second semiconductor elements 32, and drive elements 33 that are transmitted through the light are shown by imaginary lines (two-dot chain lines). In FIG. 5, for convenience of understanding, the cover layer 52 is shown. In FIG. 5, the transparent coating layer 52 is shown in phantom lines.

In the description of the semiconductor device A10, for convenience, the normal direction of the top surface 141 of the fourth insulating layer 14, which will be described later, will be referred to as a "first direction z." A direction perpendicular to the first direction z is called a "second direction x." A direction perpendicular to the first direction z and the second direction x is referred to as a "third direction y." As shown in FIG. 1, the semiconductor device A10 has a rectangular shape when viewed in the first direction z.

The semiconductor device A10 converts DC power supplied from the outside into AC power using the first semiconductor element 31 and the second semiconductor element 32. The semiconductor device A10 is used, for example, as an inverter for driving a motor. The semiconductor device A10 can be formed, for example, by the LDS (Laser Direct Structuring) method disclosed in US Patent Application Publication No. 2010/0019370.

The first insulating layer 11 is located between the first wiring 21 and the second wiring 22 in the first direction z, as shown in FIGS. 9 and 12. The first insulating layer 11 contains resin. The first insulating layer 11 has a bottom surface 111 facing in the first direction z. When mounting the semiconductor device A10 on a wiring board, the bottom surface 111 faces the wiring board.

As shown in FIGS. 6 to 8, the second insulating layer 12 is located between the first semiconductor element 31, the second semiconductor element 32, the driving element 33, and the first insulating layer 11 in the first direction z. . The second insulating layer 12 is in contact with the first insulating layer 11. The composition of the second insulating layer 12 is the same as that of the first insulating layer 11.

As shown in FIGS. 6 to 10, the third insulating layer 13 is located on the opposite side of the first insulating layer 11 with respect to the second insulating layer 12 in the first direction z. The third insulating layer 13 is in contact with the second insulating layer 12. The composition of the third insulating layer 13 is the same as that of the first insulating layer 11.

As shown in FIGS. 6 to 10, the fourth insulating layer 14 is located on the opposite side of the second insulating layer 12 with respect to the third insulating layer 13 in the first direction z. The fourth insulating layer 14 is in contact with the third insulating layer 13. The composition of the fourth insulating layer 14 is the same as that of the first insulating layer 11. The fourth insulating layer 14 has a top surface 141 facing opposite to the bottom surface 111 in the first direction z.

The first semiconductor element 31 faces the second insulating layer 12, as shown in FIGS. 6, 7, and 9. At least a portion of the second semiconductor element 32 is covered with the third insulating layer 13. The first semiconductor element 31 is a transistor (switching element) mainly used for power conversion. The first semiconductor element 31 is made of a material containing, for example, a nitride semiconductor. In the semiconductor device A10, the first semiconductor element 31 is a HEMT (High Electron Mobility Transistor) made of a material containing gallium nitride (GaN).

As shown in FIGS. 3 and 9, the first semiconductor element 31 has a first main surface 31A, two first gate electrodes 311, a plurality of first electrodes 312, and a plurality of second electrodes 313. The first main surface 31A faces the same side as the top surface 141 of the fourth insulating layer 14 in the first direction z. As shown in FIG. 3, the first main surface 31A of the first semiconductor element 31 has a first edge 31B. When viewed in the first direction z, the first edge 31B extends in the second direction x and is located closest to the drive element 33.

As shown in FIG. 9, the two first gate electrodes 311, the plurality of first electrodes 312, and the plurality of second electrodes 313 are arranged on the side opposite to the side where the first main surface 31A is located in the first direction z. To position. Therefore, the two first gate electrodes 311, the plurality of first electrodes 312, and the plurality of second electrodes 313 face the second insulating layer 12.

As shown in FIG. 3, each of the plurality of first electrodes 312 and the plurality of second electrodes 313 extends in the third direction y. Two second electrodes 313 among the plurality of second electrodes 313 are located on both sides of the plurality of first electrodes 312 in the third direction y. A current corresponding to the power converted by the first semiconductor element 31 flows through the plurality of first electrodes 312 . Therefore, the plurality of first electrodes 312 correspond to the source of the first semiconductor element 31. A current corresponding to the power before being converted by the first semiconductor element 31 flows through the plurality of second electrodes 313 . Therefore, the plurality of second electrodes 313 correspond to the drain of the first semiconductor element 31.

As shown in FIG. 3, the two first gate electrodes 311 are located on both sides of the first semiconductor element 31 in the third direction y. A gate voltage for driving the first semiconductor element 31 is applied to either of the two first gate electrodes 311. When viewed in the first direction z, the area of each of the two first gate electrodes 311 is smaller than the area of each of the plurality of first electrodes 312 and the plurality of second electrodes 313.

As shown in FIG. 3, when viewed in the first direction z, one of the two first gate electrodes 311 is located between the first center C1 of the first semiconductor element 31 and the second semiconductor element 32 in the second direction x. It is located between the second center C2 and the second center C2. When viewed in the first direction z, one of the two first gate electrodes 311 is located between the drive element 33 and the first center C1 and the second center C2 in the third direction y.

The second semiconductor element 32 faces the second insulating layer 12, as shown in FIGS. 6, 7, and 10. At least a portion of the second semiconductor element 32 is covered with the third insulating layer 13. The second semiconductor element 32 is separated from the first semiconductor element 31 in the second direction x. The first semiconductor element 31 is an element having the same structure and the same function as the second semiconductor element 32. Therefore, in the description of the first semiconductor element 31, content that overlaps with the description of the second semiconductor element 32 will be omitted.

As shown in FIGS. 3 and 10, the second semiconductor element 32 has a second main surface 32A, two second gate electrodes 321, a plurality of third electrodes 322, and a plurality of fourth electrodes 323. The second main surface 32A faces the same side as the top surface 141 of the fourth insulating layer 14 in the first direction z. As shown in FIG. 3, the second main surface 32A of the second semiconductor element 32 has a third edge 32B. When viewed in the first direction z, the third edge 32B extends in the second direction x and is located closest to the drive element 33.

As shown in FIG. 10, the two second gate electrodes 321, the plurality of third electrodes 322, and the plurality of fourth electrodes 323 are located on the opposite side of the second main surface 32A in the first direction z. To position. Therefore, the two second gate electrodes 321 , the plurality of third electrodes 322 , and the plurality of fourth electrodes 323 face the second insulating layer 12 . That is, the two second gate electrodes 321, the plurality of third electrodes 322, and the plurality of fourth electrodes 323 are located on the side where the plurality of first electrodes 312 of the first semiconductor element 31 are located in the first direction z. .

The structure and function of the two second gate electrodes 321 correspond to the structure and function of the two first gate electrodes 311 of the first semiconductor element 31. The structure and function of the plurality of third electrodes 322 correspond to the structure and function of the plurality of first electrodes 312 of the first semiconductor element 31. The structure and function of the plurality of fourth electrodes 323 correspond to the structure and function of the plurality of second electrodes 313 of the second semiconductor element 32.

As shown in FIG. 3, when viewed in the first direction z, one of the two second gate electrodes 321 is located between the first center C1 of the first semiconductor element 31 and the second semiconductor element 32 in the second direction x. It is located between the second center C2 and the second center C2. When viewed in the first direction z, one of the two second gate electrodes 321 is located between the drive element 33 and the first center C1 and the second center C2 in the third direction y.

As shown in FIG. 3, among the plurality of second electrodes 313 of the first semiconductor element 31, the second electrode 313 located closest to the first edge 31B of the first main surface 31A is The first electrode 312 is located closer to the drive element 33 than the first electrode 312 of the first electrode 312 . Further, among the plurality of second electrodes 313, the second electrode 313 located closest to the first edge 31B has a second It is located on the opposite side of the two second gate electrodes 321 of the semiconductor element 32.

As shown in FIG. 3, among the plurality of fourth electrodes 323 of the second semiconductor element 32, the fourth electrode 323 located closest to the third edge 32B of the second main surface 32A is a plurality of fourth electrodes 323 of the second semiconductor element 32. The third electrode 322 is located closer to the drive element 33 than the third electrode 322 of the third electrode 322 . Further, among the plurality of fourth electrodes 323, the fourth electrode 323 located closest to the third edge 32B is the first electrode with respect to the two second gate electrodes 321 of the second semiconductor element 32 in the second direction x. It is located on the opposite side of the two first gate electrodes 311 of the semiconductor element 31.

The drive element 33 faces the second insulating layer 12, as shown in FIGS. 2, 5, and 6. The drive element 33 is covered with the third insulating layer 13. The drive element 33 is located on one side of the first semiconductor element 31 and the second semiconductor element 32 in the third direction y. The drive element 33 is electrically connected to the first semiconductor element 31 and the second semiconductor element 32. The drive element 33 is a gate driver that applies a gate voltage to either one of the two second gate electrodes 321 of the second semiconductor element 32 and one of the two first gate electrodes 311 of the plurality of first semiconductor elements 31. The drive element 33 has a plurality of pads 331. The plurality of pads 331 face the second insulating layer 12.

As shown in FIG. 3, the drive element 33 has a second edge 33A. When viewed in the first direction z, the second edge 33A extends in the third direction y and is located closest to the first edge 31B of the first semiconductor element 31. As shown in FIG. 11, when viewed in the first direction z, the extension line EL1 of the second edge 33A intersects the first edge 31B.

As shown in FIG. 3, the drive element 33 has a fourth edge 33B. When viewed in the first direction z, the fourth edge 33B extends in the third direction y and is located closest to the third edge 32B of the second semiconductor element 32. As shown in FIG. 11, when viewed in the first direction z, the extension line EL2 of the fourth edge 33B intersects the third edge 32B.

The plurality of connection wires 39 are accommodated in the second insulating layer 12, as shown in FIGS. 6 to 10. As shown in FIG. 3, each of the plurality of connection wirings 39 overlaps one of the first semiconductor element 31, the second semiconductor element 32, and the drive element 33 when viewed in the first direction z. Each of the plurality of connection wirings 39 is connected to one of the first wiring 21 , the third wiring 23 , the plurality of power wirings 25 , and the plurality of control wirings 26 . The composition of the plurality of connection wires 39 is the same as the composition of the first wire 21.

As shown in FIGS. 3 and 4, the plurality of connection wires 39 include a plurality of first connection wires 39A, a plurality of second connection wires 39B, and a plurality of third connection wires 39C.

Each of the plurality of first connection wirings 39A is connected to one of the two first gate electrodes 311, the plurality of first electrodes 312, and the plurality of second electrodes 313 of the first semiconductor element 31. Each of the plurality of second connection wirings 39B is connected to one of the two second gate electrodes 321, the plurality of third electrodes 322, and the plurality of fourth electrodes 323 of the second semiconductor element 32. The plurality of third connection wirings 39C are individually connected to the plurality of pads 331 of the drive element 33.

The plurality of power wirings 25 are located between the first insulating layer 11 and the second insulating layer 12, as shown in FIGS. 6, 7, 9, and 10. At least a portion of each of the plurality of power lines 25 is accommodated in the second insulating layer 12. The composition of the plurality of power wirings 25 is the same as the composition of the first wiring 21.

As shown in FIG. 4, the plurality of power wirings 25 include a first power wiring 25A, a second power wiring 25B, and a third power wiring 25C. The plurality of first electrodes 312 of the first semiconductor element 31 are electrically connected to the first power wiring 25A via some of the plurality of first connection wirings 39A. The plurality of second electrodes 313 of the first semiconductor element 31 are electrically connected to the second power wiring 25B via some of the plurality of first connection wirings 39A. The plurality of third electrodes 322 of the second semiconductor element 32 are electrically connected to the second power wiring 25B via some of the plurality of second connection wirings 39B. The plurality of fourth electrodes 323 of the second semiconductor element 32 are electrically connected to the third power wiring 25C via some of the plurality of second connection wirings 39B.

The plurality of control wirings 26 are located between the first insulating layer 11 and the second insulating layer 12, as shown in FIGS. 8 and 10. At least a portion of each of the plurality of control wires 26 is accommodated in the second insulating layer 12. The composition of the plurality of control wirings 26 is the same as that of the first wiring 21. Each of the plurality of control wirings 26 is electrically connected to one of the plurality of pads 331 of the drive element 33 via one of the plurality of third connection wirings 39C.

The first wiring 21 is located between the first insulating layer 11 and the second insulating layer 12, as shown in FIG. At least a portion of the first wiring 21 is accommodated in the second insulating layer 12. The composition of the first wiring 21 includes at least copper (Cu). The first wiring 21 is electrically connected to one of the two first gate electrodes 311 of the first semiconductor element 31 via one of the plurality of first connection wirings 39A. Further, the first wiring 21 is electrically connected to one of the plurality of pads 331 of the drive element 33 via one of the plurality of third connection wirings 39C. In the first wiring 21, a current I1 flows from one of the plurality of pads 331 of the driving element 33 toward one of the two first gate electrodes 311 of the first semiconductor element 31.

As shown in FIG. 12, the second wiring 22 is located on the opposite side of the second insulating layer 12 with respect to the first insulating layer 11. At least a portion of the second wiring 22 is accommodated in the first insulating layer 11. The composition of the second wiring 22 is the same as that of the first wiring 21. The second wiring 22 is electrically connected to the plurality of first electrodes 312 of the first semiconductor element 31 via a first terminal 51A, which will be described later, and a first power wiring 25A. Further, the second wiring 22 is electrically connected to one of the plurality of pads 331 of the drive element 33 via one of the plurality of control wirings 26. In the second wiring 22, a current I2 flows from the plurality of first electrodes 312 of the first semiconductor element 31 toward one of the plurality of pads 331 of the drive element 33. Therefore, the direction of the current I2 is opposite to the direction of the current I1 flowing through the first wiring 21.

As shown in FIG. 11, the first wiring 21 overlaps the second wiring 22 when viewed in the first direction z. As shown in FIGS. 11 and 12, the distance D between the first wiring 21 and the second wiring 22 in the first direction z is different from the first direction z and the direction in which the current I1 flows in the first wiring 21. It is shorter than the first dimension B1 of the first wiring 21 in the orthogonal direction. Further, as shown in FIG. 11, the first dimension B1 is larger than the second dimension B2 of the second wiring 22 in the direction perpendicular to the first direction z and the direction in which the current I2 flows in the second wiring 22. is small.

The third wiring 23 is located between the first insulating layer 11 and the second insulating layer 12, as shown in FIG. At least a portion of the third wiring 23 is accommodated in the second insulating layer 12. The composition of the third wiring 23 is the same as that of the first wiring 21. The third wiring 23 is electrically connected to one of the two second gate electrodes 321 of the second semiconductor element 32 via one of the plurality of second connection wirings 39B. Further, the third wiring 23 is electrically connected to one of the plurality of pads 331 of the drive element 33 via one of the plurality of third connection wirings 39C. In the third wiring 23 , a current flows from one of the plurality of pads 331 of the driving element 33 toward one of the two second gate electrodes 321 of the second semiconductor element 32 .

As shown in FIG. 12, the fourth wiring 24 is located on the opposite side of the second insulating layer 12 with respect to the first insulating layer 11. At least a portion of the fourth wiring 24 is accommodated in the first insulating layer 11. The composition of the fourth wiring 24 is the same as that of the first wiring 21. The fourth wiring 24 is electrically connected to a plurality of third electrodes 322 of the second semiconductor element 32 via a second terminal 51B, which will be described later, and a second power wiring 25B. Further, the fourth wiring 24 is electrically connected to one of the plurality of pads 331 of the drive element 33 via one of the plurality of control wirings 26. In the fourth wiring 24 , a current flows from the plurality of third electrodes 322 of the second semiconductor element 32 toward any one of the plurality of pads 331 of the drive element 33 . Therefore, the direction of the current flowing through the fourth wiring 24 is opposite to the direction of the current flowing through the third wiring 23. The third wiring 23 overlaps the fourth wiring 24 when viewed in the first direction z.

As shown in FIG. 11, the conduction path length L1 of the first wiring 21 is longer than the conduction path length L2 of the third wiring 23. The conduction path length L1 is the length of the shortest path in the first wiring 21 among the conduction paths from any of the plurality of pads 331 of the drive element 33 to either of the two first gate electrodes 311 of the first semiconductor element 31. It is. The conduction path length L2 is the length of the shortest path in the second wiring 22 among the conduction paths from any of the plurality of pads 331 of the drive element 33 to either of the two first electrodes 312 of the second semiconductor element 32. It is.

The plurality of communication wirings 29 are accommodated in the first insulating layer 11, as shown in FIGS. 6 to 10. Each of the plurality of communication wirings 29 is connected to one of the first wiring 21 , the second wiring 22 , the plurality of power wirings 25 , and the plurality of control wirings 26 , the second wiring 22 , the fourth wiring 24 , and the plurality of terminals 51 and are connected to either. As shown in FIG. 5, the plurality of interconnections 29 are surrounded by the periphery of the bottom surface 111 of the first insulating layer 11 when viewed in the first direction z. The composition of the plurality of interconnections 29 is the same as the composition of the first interconnection 21.

As shown in FIGS. 4 and 5, the plurality of communication wirings 29 connect the plurality of first communication wirings 29A, the plurality of second communication wirings 29B, the plurality of third communication wirings 29C, and the plurality of fourth communication wirings 29D. include.

As shown in FIGS. 6 and 7, the plurality of first connection wirings 29A are connected to the first power wiring 25A and a first terminal 51A, which will be described later. The plurality of second connection wirings 29B. It is connected to the second power wiring 25B and a second terminal 51B, which will be described later. The plurality of third communication wirings 29C are connected to the third power wiring 25C and a third terminal 51C, which will be described later. As shown in FIGS. 8 to 10, each of the plurality of fourth connection wirings 29D is connected to one of the first wiring 21, the third wiring 23, and the plurality of control wirings 26, the second wiring 22, the fourth It is connected to the wiring 24 and to each of a plurality of control terminals 51D, which will be described later.

As shown in FIGS. 6 to 10, the plurality of terminals 51 are located on the opposite side of the second insulating layer 12 with respect to the first insulating layer 11. As shown in FIG. 5, each of the plurality of terminals 51 is connected to one of the plurality of connection wires 29. Thereby, each of the plurality of terminals 51 is electrically connected to at least one of the first semiconductor element 31, the second semiconductor element 32, and the drive element 33. The plurality of terminals 51 are in contact with the first insulating layer 11. In the semiconductor device A10, at least a portion of each of the plurality of terminals 51 is accommodated in the first insulating layer 11. The composition of the plurality of terminals 51 is the same as that of the first wiring 21.

As shown in FIG. 5, the plurality of terminals 51 include a first terminal 51A, a second terminal 51B, a third terminal 51C, and a plurality of control terminals 51D.

As shown in FIGS. 4 and 5, the first terminal 51A is electrically connected to the first power wiring 25A via a plurality of first connection wirings 29A. The second wiring 22 is connected to the first terminal 51A. The third terminal 51C is electrically connected to the second power wiring 25B via a plurality of third communication wirings 29C. DC power to be converted by the first semiconductor element 31 and the second semiconductor element 32 is input to the first terminal 51A and the third terminal 51C. The first terminal 51A is a negative electrode (N terminal). The third terminal 51C is a positive electrode (P terminal).

As shown in FIGS. 4 and 5, the second terminal 51B is electrically connected to the second power wiring 25B via a plurality of second connection wirings 29B. AC power converted by the first semiconductor element 31 and the second semiconductor element 32 is output from the second terminal 51B. The fourth wiring 24 is connected to the second terminal 51B.

Each of the plurality of control terminals 51D is electrically connected to any one of the first wiring 21, the third wiring 23, and the plurality of control wirings 26 via any one of the plurality of fourth communication wirings 29D. Therefore, each of the plurality of control terminals 51D is electrically connected to the drive element 33. Electric power for driving the drive element 33 is input to any one of the plurality of control terminals 51D. An electrical signal to the drive element 33 is input to one of the plurality of control terminals 51D. Further, an electrical signal from the drive element 33 is output from one of the plurality of control terminals 51D.

As shown in FIGS. 6 to 10, the covering layer 52 is located on the opposite side of the second insulating layer 12 with respect to the first insulating layer 11. The covering layer 52 covers the bottom surface 111 as a part of the first insulating layer 11 . Covering layer 52 is an insulator. The covering layer 52 is, for example, a solder resist. The second wiring 22 and the fourth wiring 24 are covered with a covering layer 52. The covering layer 52 is provided with a plurality of openings 521. The plurality of openings 521 penetrate the covering layer 52 in the first direction z. From each of the plurality of openings 521, one of the plurality of terminals 51 is exposed to the outside. Thereby, when mounting the semiconductor device A10 on a wiring board, each of the plurality of terminals 51 can be electrically bonded to the wiring board through solder.

The plurality of heat dissipation layers 61 are located on the opposite side of the second insulating layer 12 with respect to the third insulating layer 13, as shown in FIGS. 6, 7, 9, and 10. In the semiconductor device A10, at least a portion of each of the plurality of heat dissipation layers 61 is accommodated in the fourth insulating layer 14. The plurality of heat dissipation layers 61 are in contact with the fourth insulating layer 14 . The plurality of heat dissipation layers 61 are exposed to the outside from the top surface 141 of the fourth insulating layer 14 . The composition of the plurality of heat dissipation layers 61 is the same as the composition of the first wiring 21.

As shown in FIG. 1, the plurality of heat dissipation layers 61 include a first heat dissipation layer 61A and a second heat dissipation layer 61B. The first heat dissipation layer 61A and the second heat dissipation layer 61B are separated from each other in the second direction x. The first heat dissipation layer 61A overlaps the first semiconductor element 31 when viewed in the first direction z. The second heat dissipation layer 61B overlaps the second semiconductor element 32 when viewed in the first direction z.

As shown in FIGS. 6 to 10, the plurality of intermediate layers 62 are located on the opposite side of the second insulating layer 12 with respect to the third insulating layer 13, and the third insulating layer 13 and the plurality of heat dissipating layers 61 located between. At least a portion of each of the plurality of intermediate layers 62 is accommodated in the third insulating layer 13. The plurality of intermediate layers 62 are in contact with the fourth insulating layer 14 . Therefore, the fourth insulating layer 14 is located between the plurality of intermediate layers 62 and the plurality of heat dissipation layers 61. The composition of the plurality of intermediate layers 62 is the same as that of the first wiring 21.

As shown in FIG. 2, the plurality of intermediate layers 62 include a first intermediate layer 62A, a second intermediate layer 62B, and a third intermediate layer 62C. The first intermediate layer 62A and the second intermediate layer 62B are separated from each other in the second direction x. When viewed in the first direction z, the first intermediate layer 62A overlaps the first semiconductor element 31 and the first heat dissipation layer 61A. The first intermediate layer 62A is separated from the first semiconductor element 31. When viewed in the first direction z, the second intermediate layer 62B overlaps the second semiconductor element 32 and the second heat dissipation layer 61B. The second intermediate layer 62B is separated from the second semiconductor element 32. The third intermediate layer 62C is located between the first intermediate layer 62A and the second intermediate layer 62B in the second direction x. The third intermediate layer 62C overlaps the drive element 33 when viewed in the first direction z. The third intermediate layer 62C is separated from the drive element 33.

The plurality of first vias 41 are accommodated in the fourth insulating layer 14, as shown in FIG. The plurality of first vias 41 are connected to the first heat dissipation layer 61A and the first intermediate layer 62A. Thereby, the first intermediate layer 62A is electrically connected to the first heat dissipation layer 61A. The composition of the plurality of first vias 41 is the same as the composition of the first wiring 21.

The plurality of second vias 42 are accommodated in the fourth insulating layer 14, as shown in FIGS. 6 and 10. The plurality of second vias 42 are connected to the second heat dissipation layer 61B and the second intermediate layer 62B. Thereby, the second intermediate layer 62B is electrically connected to the second heat dissipation layer 61B. The composition of the plurality of second vias 42 is the same as the composition of the first wiring 21.

The plurality of third vias 43 are accommodated in the second insulating layer 12 and the third insulating layer 13, as shown in FIGS. 6 and 7. The plurality of third vias 43 are connected to the first intermediate layer 62A and the first power wiring 25A. Thereby, the first intermediate layer 62A is electrically connected to the first power wiring 25A. The composition of the plurality of third vias 43 is the same as the composition of the first wiring 21.

The plurality of fourth vias 44 are accommodated in the second insulating layer 12 and the third insulating layer 13, as shown in FIGS. 6 and 7. The plurality of fourth vias 44 are connected to the second intermediate layer 62B and the second power wiring 25B. Thereby, the second intermediate layer 62B is electrically connected to the second power wiring 25B. The composition of the plurality of fourth vias 44 is the same as the composition of the first wiring 21.

The plurality of fifth vias 45 are accommodated in the second insulating layer 12 and the third insulating layer 13, as shown in FIG. The plurality of fifth vias 45 are electrically connected to the second intermediate layer 62B and one of the plurality of control wirings 26.

Next, the effects of the semiconductor device A10 will be explained.

The semiconductor device A10 includes a first semiconductor element 31 having a first gate electrode 311, a first electrode 312, and a second electrode 313, and a second semiconductor element having a second gate electrode 321, a third electrode 322, and a fourth electrode 323. 32, and a drive element 33 electrically connected to the first gate electrode 311 and the second gate electrode 321. When viewed in the first direction z, the first gate electrode 311 and the second gate electrode 321 are located between the first center C1 of the first semiconductor element 31 and the second center C2 of the second semiconductor element 32 in the second direction x. located in between. When viewed in the first direction z, the first gate electrode 311 and the second gate electrode 321 are located between the drive element 33 and the first center C1 and the second center C2 in the third direction y. By adopting this configuration, each of the conduction path lengths L1 and L2 shown in FIG. 11 can be shortened. Therefore, according to this configuration, it is possible to reduce the parasitic inductance in the wiring of the semiconductor device A10.

The semiconductor device A10 further includes a first wiring 21 that connects the drive element 33 and the first gate electrode 311 of the first semiconductor element 31. The conduction path length L1 shown in FIG. 11 is set in the first wiring 21. A gate voltage for driving the first semiconductor element 31 is applied to the first gate electrode 311 . Therefore, since the parasitic inductance in the first wiring 21 is reduced by shortening the conduction path length L1, switching loss of the first semiconductor element 31 can be suppressed. The first gate electrode 311 and the drive element 33 overlap the first wiring 21 when viewed in the first direction z. As a result, the conduction path length L1 is further shortened, so that the parasitic inductance of the first wiring 21 can be further reduced.

The semiconductor device A10 further includes a third wiring 23 that connects the drive element 33 and the second gate electrode 321 of the second semiconductor element 32. The conduction path length L2 shown in FIG. 11 is set in the third wiring 23. A gate voltage for driving the second semiconductor element 32 is applied to the second gate electrode 321 . Therefore, the parasitic inductance in the third wiring 23 is reduced by shortening the conduction path length L2, so that switching loss of the second semiconductor element 32 can be suppressed. The second gate electrode 321 and the drive element 33 overlap the second wiring 22 when viewed in the first direction z. As a result, the conduction path length L2 is further shortened, so that the parasitic inductance of the third wiring 23 can be further reduced.

When viewed in the first direction z, the first semiconductor element 31 has a first edge 31B that extends in the second direction x and is located closest to the drive element 33. When viewed in the first direction z, the drive element 33 has a second edge 33A that extends in the third direction y and is located closest to the first edge 31B. When viewed in the first direction z, the extension line EL1 of the second edge 33A intersects the first edge 31B (see FIG. 11). By adopting this configuration, the conduction path length L1 shown in FIG. 11 can be efficiently shortened.

When viewed in the first direction z, the second semiconductor element 32 has a third edge 32B that extends in the second direction x and is located closest to the drive element 33. When viewed in the first direction z, the drive element 33 has a fourth edge 33B that extends in the third direction y and is located closest to the third edge 32B. When viewed in the first direction z, the extension line EL2 of the fourth edge 33B intersects the third edge 32B (see FIG. 11). By adopting this configuration, the conduction path length L2 shown in FIG. 11 can be efficiently shortened.

The first wiring 21 overlaps the second wiring 22 when viewed in the first direction z. Furthermore, the first dimension B1 of the first wiring 21 is shorter than the second dimension B2 of the second wiring 22 (the dimension in the direction perpendicular to the direction in which the current I2 flows in the first direction z and the second wiring 22). By adopting this configuration, the area of the first wiring 21 overlapping the second wiring 22 is further increased when viewed in the first direction z. As a result, the back electromotive force generated in the first wiring 21 due to the mutual inductance acting on the first wiring 21 and the second wiring 22 becomes larger. Therefore, the parasitic inductance in the first wiring 21 can be reduced more effectively.

The semiconductor device A10 further includes a first insulating layer 11 located between the first wiring 21 and the second wiring 22 in the first direction z. The first insulating layer 11 contains resin. At least a portion of the second wiring 22 is accommodated in the first insulating layer 11. By adopting this configuration, the distance D between the first wiring 21 and the second wiring 22 in the first direction z can be made shorter while ensuring electrical insulation between the first wiring 21 and the second wiring 22. . As a result, the mutual inductance acting on the first wiring 21 and the second wiring 22 becomes larger, so that the parasitic inductance in the first wiring 21 can be further reduced.

The semiconductor device A10 includes a second insulating layer 12 located between the first semiconductor element 31 and the first insulating layer 11 in the first direction z, and a second insulating layer 12 located opposite to the first insulating layer 11 with respect to the second insulating layer 12. It further includes a third insulating layer 13 located on the side. At least a portion of the first semiconductor element 31 is covered with the third insulating layer 13. The first wiring 21 is located between the first insulating layer 11 and the second insulating layer 12. By adopting this configuration, it is possible to suppress a decrease in dielectric strength voltage of the first semiconductor element 31 while arranging the first wiring 21 between the first semiconductor element 31 and the first insulating layer 11.

The semiconductor device A10 further includes a heat dissipation layer 61 located on the opposite side of the second insulating layer 12 with respect to the third insulating layer 13. The heat dissipation layer 61 is exposed to the outside. The heat dissipation layer 61 overlaps the first semiconductor element 31 when viewed in the first direction z. By adopting this configuration, the heat generated from the first semiconductor element 31 can be efficiently released to the outside.

The semiconductor device A10 further includes an intermediate layer 62 located on the opposite side of the second insulating layer 12 with respect to the third insulating layer 13 and between the third insulating layer 13 and the heat dissipation layer 61. The intermediate layer 62 is in contact with the third insulating layer 13 and is away from the first semiconductor element 31 . The intermediate layer 62 is electrically connected to one of the plurality of power wirings 25 to which the first semiconductor element 31 is electrically connected, and to the heat dissipation layer 61 . With this configuration, heat generated from the first semiconductor element 31 is conducted to the intermediate layer 62 via any one of the plurality of power wirings 25. In this case, the intermediate layer 62 overlaps the first semiconductor element 31 and the heat dissipation layer 61 when viewed in the first direction z. Therefore, the heat generated from the first semiconductor element 31 can be more smoothly conducted to the heat dissipation layer 61. Further, the intermediate layer 62 has the effect of reducing noise generated from the first semiconductor element 31 and noise entering the semiconductor device A10 from the outside.

[Second embodiment]
A semiconductor device A20 according to a second embodiment of the present disclosure will be described based on FIGS. 13 to 16. In these figures, the same or similar elements as those of the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanation will be omitted.

In the semiconductor device A20, the structure of the intermediate layer 62, the fourth insulating layer 14, the plurality of intermediate layers 62, the plurality of first vias 41, the plurality of second vias 42, the plurality of third vias 43, and the plurality of fourth The difference from the semiconductor device A10 is that the via 44 and the plurality of fifth vias 45 are not provided.

As shown in FIGS. 13 to 16, the third insulating layer 13 has a top surface 131 facing opposite to the bottom surface 111 of the first insulating layer 11 in the first direction z. At least a portion of each of the plurality of heat dissipation layers 61 is accommodated in the third insulating layer 13. The plurality of heat dissipation layers 61 are exposed to the outside from the top surface 131. Each of the plurality of heat dissipation layers 61 is electrically insulated from any of the plurality of power wirings 25 and the plurality of control wirings 26.

Next, the effects of the semiconductor device A20 will be explained.

The semiconductor device A20 includes a first semiconductor element 31 having a first gate electrode 311, a first electrode 312, and a second electrode 313, and a second semiconductor element having a second gate electrode 321, a third electrode 322, and a fourth electrode 323. 32, and a drive element 33 electrically connected to the first gate electrode 311 and the second gate electrode 321. When viewed in the first direction z, the first gate electrode 311 and the second gate electrode 321 are located between the first center C1 of the first semiconductor element 31 and the second center C2 of the second semiconductor element 32 in the second direction x. located in between. When viewed in the first direction z, the first gate electrode 311 and the second gate electrode 321 are located between the drive element 33 and the first center C1 and the second center C2 in the third direction y. Therefore, according to this configuration, even in the semiconductor device A20, it is possible to reduce the parasitic inductance in the wiring of the semiconductor device A20. Further, the semiconductor device A20 has the same configuration as the semiconductor device A10, so that the same effects as the semiconductor device A10 can be achieved.

The semiconductor device A20 does not include the fourth insulating layer 14 and the intermediate layer 62, unlike the semiconductor device A10. At least a portion of the heat dissipation layer 61 is accommodated in the third insulating layer 13. The heat dissipation layer 61 is in contact with the third insulating layer 13 and exposed to the outside from the third insulating layer 13 . By adopting this configuration, it is possible to reduce the size of the semiconductor device A20 in the first direction z while suppressing a decrease in the heat dissipation performance of the semiconductor device A20.

[Third embodiment]
A semiconductor device A30 according to a third embodiment of the present disclosure will be described based on FIGS. 17 to 20. In these figures, the same or similar elements as those of the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanation will be omitted.

The semiconductor device A30 differs from the semiconductor device A20 described above in the configuration of the third insulating layer 13 and the absence of the plurality of heat dissipation layers 61.

As shown in FIGS. 17 to 20, the first main surface 31A of the first semiconductor element 31 and the second main surface 32A of the second semiconductor element 32 are exposed to the outside from the top surface 131 of the third insulating layer 13. are doing. Each of the first main surface 31A and the second main surface 32A is flush with the top surface 131. Therefore, the dimension of the third insulating layer 13 in the first direction z is smaller than the dimension of the semiconductor device A20.

Next, the effects of the semiconductor device A30 will be explained.

The semiconductor device A30 includes a first semiconductor element 31 having a first gate electrode 311, a first electrode 312, and a second electrode 313, and a second semiconductor element having a second gate electrode 321, a third electrode 322, and a fourth electrode 323. 32, and a drive element 33 electrically connected to the first gate electrode 311 and the second gate electrode 321. When viewed in the first direction z, the first gate electrode 311 and the second gate electrode 321 are located between the first center C1 of the first semiconductor element 31 and the second center C2 of the second semiconductor element 32 in the second direction x. located in between. When viewed in the first direction z, the first gate electrode 311 and the second gate electrode 321 are located between the drive element 33 and the first center C1 and the second center C2 in the third direction y. Therefore, according to this configuration, even in the semiconductor device A30, it is possible to reduce the parasitic inductance in the wiring of the semiconductor device A30. Furthermore, the semiconductor device A30 has the same configuration as the semiconductor device A10, so that it can achieve the same effects as the semiconductor device A10.

The semiconductor device A30 does not include the heat dissipation layer 61, unlike the semiconductor device A20. The first main surface 31A of the first semiconductor element 31 is exposed to the outside from the third insulating layer 13. Further, the first main surface 31A is flush with the third insulating layer 13. By adopting this configuration, the dimensions of the semiconductor device A30 in the first direction z can be further reduced while suppressing a decrease in the heat dissipation performance of the semiconductor device A30.

[Semiconductor element]
A semiconductor device B according to an embodiment of the present disclosure will be described based on FIGS. 21 to 23. The semiconductor element B includes a main body 71 , a first gate electrode 72 , a second gate electrode 73 , a plurality of first electrodes 74 , and a plurality of second electrodes 75 .

The semiconductor element B, like the first semiconductor element 31 and the second semiconductor element 32 described above, is a transistor (switching element) mainly used for power conversion. More specifically, semiconductor element B is a HEMT made of a material containing gallium nitride.

As shown in FIG. 21, the main body portion 71 has a rectangular shape with the third direction y as the short side direction when viewed in the first direction z. The main body portion 71 includes a semiconductor substrate, a semiconductor layer, a rewiring layer (all not shown), and the like. The main body portion 71 has a first surface 711, a second surface 712, a first edge 713, and a second edge 714. The first surface 711 and the second surface 712 face opposite to each other in the first direction z. When viewed in the first direction z, the first edge 713 extends in the second direction x. When viewed in the first direction z, the second edge 714 extends in the third direction y. The length of the first edge 713 is smaller than the length of the second edge 714.

The first gate electrode 72, the second gate electrode 73, the plurality of first electrodes 74, and the plurality of second electrodes 75 have their first surfaces 711 located in the first direction z, as shown in FIGS. 22 and 23. located on the side. The first gate electrode 72 , the second gate electrode 73 , the plurality of first electrodes 74 , and the plurality of second electrodes 75 are electrically connected to the main body portion 71 .

As shown in FIG. 21, each of the plurality of first electrodes 74 and the plurality of second electrodes 75 extends in the third direction y. A current corresponding to the power converted by the semiconductor element B flows through the plurality of first electrodes 74 . Therefore, the plurality of first electrodes 74 correspond to the source of the semiconductor element B. A current corresponding to the power before being converted by the semiconductor element B flows through the plurality of second electrodes 75 . Therefore, the plurality of second electrodes 75 correspond to the drain of the semiconductor element B. Any one of the plurality of second electrodes 75 is located closer to the first edge 713 of the main body portion 71 than the plurality of first electrodes 74 .

As shown in FIG. 21, the first gate electrode 72 and the second gate electrode 73 are separated from each other in the second direction x. When viewed in the first direction z, the first gate electrode 72 and the second gate electrode 73 are located closer to the first edge 713 of the main body 71 than the center C of the main body 71 . A gate voltage for driving the semiconductor element B is applied to either the first gate electrode 72 or the second gate electrode 73. When viewed in the first direction z, the area of each of the first gate electrode 72 and the second gate electrode 73 is smaller than the area of each of the plurality of first electrodes 74 and the plurality of second electrodes 75. As shown in FIGS. 21 and 23, among the plurality of second electrodes 75, the second electrode 75 located closest to the first edge 713 is connected to the first gate electrode 72 and the second gate electrode 73 in the second direction x. including the part located between.

[Fourth embodiment]
Based on FIG. 24, a semiconductor device A40 according to a fourth embodiment of the present disclosure will be described. In these figures, the same or similar elements as those of the semiconductor device A10 described above are denoted by the same reference numerals, and redundant explanation will be omitted. Here, for the convenience of understanding, FIG. Illustration is omitted.

The semiconductor device A40 differs from the semiconductor device A10 in that it includes two semiconductor elements B instead of the first semiconductor element 31 and the second semiconductor element 32.

As shown in FIG. 24, one of the two semiconductor elements B is conductively connected to the first wiring 21, the first power wiring 25A, and the second power wiring 25B via a plurality of connection wirings 39. There is. A first gate electrode 72 of one semiconductor element B is electrically connected to the first wiring 21 .

As shown in FIG. 24, the other semiconductor element B of the two semiconductor elements B is conductively connected to the third wiring 23, the second power wiring 25B, and the third power wiring 25C via a plurality of connection wirings 39. There is. The second gate electrode 73 of the other semiconductor element B is electrically connected to the third wiring 23 .

Next, the effects of the semiconductor element B will be explained.

The semiconductor element B includes a main body 71 , a first gate electrode 72 , a second gate electrode 73 , a first electrode 74 , and a second electrode 75 . When viewed in the first direction z, the main body portion 71 has a first edge 713 extending in the second direction x and a second edge 714 extending in the third direction y. The length of the first edge 713 is smaller than the length of the second edge 714. The first gate electrode 72 and the second gate electrode 73 are separated from each other in the second direction x. When viewed in the first direction z, the first gate electrode 72 and the second gate electrode 73 are located closer to the first edge 713 than the center C of the main body portion 71 . By adopting this configuration, each of the conduction path lengths L1 and L2 shown in FIG. 11 can be shortened even in the semiconductor device A40 including the two semiconductor elements B shown in FIG. 24. Therefore, according to this configuration, it is possible to reduce the parasitic inductance in the wiring of the semiconductor device A40.

In the semiconductor device A40, when the two semiconductor elements B are conductively bonded to the first wiring 21, the third wiring 23, and the plurality of power wirings 25, one of the two semiconductor elements B is connected around the first direction z. No need to rotate. On the other hand, in the semiconductor device A10, if the first semiconductor element 31 and the second semiconductor element 32 are the same element, at the time of the above-mentioned conductive bonding, either the first semiconductor element 31 or the second semiconductor element 32 needs to be rotated around the first direction z.

The present disclosure is not limited to the embodiments described above. The specific configuration of each part of the present disclosure can be modified in various ways.

The present disclosure includes the embodiments described in the appendix below.
[Additional note 1]
a first semiconductor element having a first electrode, a second electrode, and a first gate electrode located on one side in a first direction;
The first semiconductor element has a third electrode, a fourth electrode, and a second gate electrode located on the side where the first electrode is located in the first direction, and in a second direction perpendicular to the first direction. a second semiconductor element separated from the
located on one side of a third direction perpendicular to the first direction and the second direction with respect to the first semiconductor element and the second semiconductor element, and the first gate electrode and the second gate electrode. a drive element that conducts to the
When viewed in the first direction, the first gate electrode and the second gate electrode are located between a first center of the first semiconductor element and a second center of the second semiconductor element in the second direction. It is located in
When viewed in the first direction, the first gate electrode and the second gate electrode are semiconductors located between the drive element and the first center and the second center in the third direction. Device.
[Additional note 2]
When viewed in the first direction, the first semiconductor element has a first edge that extends in the second direction and is located closest to the drive element;
When viewed in the first direction, the drive element has a second edge that extends in the third direction and is located closest to the first edge;
The semiconductor device according to appendix 1, wherein an extension line of the second edge intersects the first edge when viewed in the first direction.
[Additional note 3]
When viewed in the first direction, the second semiconductor element has a third edge that extends in the second direction and is located closest to the drive element;
When viewed in the first direction, the drive element has a fourth edge that extends in the third direction and is located closest to the third edge;
The semiconductor device according to appendix 2, wherein an extension line of the fourth edge intersects the third edge when viewed in the first direction.
[Additional note 4]
further comprising a first wiring that connects the drive element and the first gate electrode,
The semiconductor device according to appendix 3, wherein the first gate electrode overlaps the first wiring when viewed in the first direction.
[Additional note 5]
further comprising a first insulating layer located on the opposite side of the first semiconductor element with respect to the first wiring in the first direction,
The semiconductor device according to appendix 4, wherein the first wiring is in contact with the first insulating layer.
[Additional note 6]
further comprising a second wiring that connects the drive element and the first electrode,
The second wiring is located on the side where the first wiring is located with respect to the first insulating layer in the first direction,
The semiconductor device according to appendix 5, wherein the second wiring is in contact with the first insulating layer.
[Additional note 7]
The semiconductor device according to appendix 6, wherein the driving element overlaps the first wiring and the second wiring when viewed in the first direction.
[Additional note 8]
The semiconductor device according to appendix 7, wherein the second electrode is located closer to the drive element than the first electrode.
[Additional note 9]
The semiconductor device according to appendix 8, wherein the second electrode is located on the opposite side of the second gate electrode with respect to the first gate electrode in the second direction.
[Additional note 10]
The semiconductor device according to appendix 9, wherein the first wiring overlaps the second wiring when viewed in the first direction.
[Additional note 11]
further comprising a second insulating layer located between the first semiconductor element and the first insulating layer,
11. The semiconductor device according to any one of appendices 6 to 10, wherein at least a portion of each of the first wiring and the second wiring is accommodated in the second insulating layer.
[Additional note 12]
further comprising a plurality of power terminals located on the opposite side of the first wiring and the second wiring with respect to the first insulating layer,
The semiconductor device according to appendix 11, wherein each of the plurality of power terminals is electrically connected to at least one of the first electrode, the second electrode, the third electrode, and the fourth electrode.
[Additional note 13]
The semiconductor device according to appendix 12, wherein at least a portion of each of the plurality of power terminals is accommodated in the first insulating layer.
[Additional note 14]
further comprising a heat dissipation layer located on the opposite side of the second insulating layer with respect to the first semiconductor element,
The semiconductor device according to attachment 13, wherein the heat dissipation layer overlaps the first semiconductor element when viewed in the first direction.
[Additional note 15]
The main body and
A first electrode, a second electrode, a first gate electrode, and a second gate electrode located on one side of the main body in the first direction and electrically connected to the main body,
When viewed in the first direction, the main body portion has a first edge extending in a second direction perpendicular to the first direction, and a third direction extending in a third direction perpendicular to the first direction and the second direction. an extending second edge;
The length of the first edge is smaller than the length of the second edge,
the first gate electrode and the second gate electrode are separated from each other in the second direction;
When viewed in the first direction, the first gate electrode and the second gate electrode are located closer to the first edge than to the center of the main body.
[Additional note 16]
The semiconductor device according to attachment 15, wherein the second electrode is located closer to the first edge than the first electrode.
[Additional note 17]
17. The semiconductor device according to appendix 16, wherein the second electrode includes a portion located between the first gate electrode and the second gate electrode in the second direction.

A10, A20, A30, A40: Semiconductor device B: Semiconductor element 11: First insulating layer 111: Bottom surface 12: Second insulating layer 13: Third insulating layer 14: Fourth insulating layer 141: Top surface 21: First wiring 22: Second wiring 23: Third wiring 24: Fourth wiring 25: Power wiring 25A: First power wiring 25B: Second power wiring 25C: Third power wiring 26: Control wiring 29: Communication wiring 29A: First communication Wiring 29B: Second connection wiring 29C: Third connection wiring 29D: Fourth connection wiring 31: First semiconductor element 31A: First main surface 31B: First edge 311: First gate electrode 312: First electrode 313: First 2 electrodes 32: Second semiconductor element 32A: Second main surface 32B: Third edge 321: Second gate electrode 322: Third electrode 323: Fourth electrode 33: Drive element 33A: Second edge 33B: Fourth edge 331 : Pad 39: Connection wiring 39A: First connection wiring 39B: Second connection wiring 39C: Third connection wiring 41: First via 42: Second via 43: Third via 44: Fourth via 45: Fifth via 51 : Terminal 51A: First terminal 51B: Second terminal 51C: Third terminal 51D: Control terminal 52: Covering layer 521: Opening 61: Heat dissipation layer 61A: First heat dissipation layer 61B: Second heat dissipation layer 62: Intermediate layer 62A: First intermediate layer 62B: Second intermediate layer 62C: Third intermediate layer 71: Main body 711: First surface 712: Second surface 713: First edge 714: Second edge 72: First gate electrode 73: Second Gate electrode 74: First electrode 75: Second electrode z: First direction x: Second direction y: Third direction

Claims (17)

a first semiconductor element having a first electrode, a second electrode, and a first gate electrode located on one side in a first direction;
The first semiconductor element has a third electrode, a fourth electrode, and a second gate electrode located on the side where the first electrode is located in the first direction, and in a second direction perpendicular to the first direction. a second semiconductor element separated from the
located on one side of a third direction perpendicular to the first direction and the second direction with respect to the first semiconductor element and the second semiconductor element, and the first gate electrode and the second gate electrode. a drive element that conducts to the
When viewed in the first direction, the first gate electrode and the second gate electrode are located between a first center of the first semiconductor element and a second center of the second semiconductor element in the second direction. It is located in
When viewed in the first direction, the first gate electrode and the second gate electrode are semiconductors located between the drive element and the first center and the second center in the third direction. Device. When viewed in the first direction, the first semiconductor element has a first edge that extends in the second direction and is located closest to the drive element;
When viewed in the first direction, the drive element has a second edge that extends in the third direction and is located closest to the first edge;
The semiconductor device according to claim 1, wherein an extension line of the second edge intersects the first edge when viewed in the first direction. When viewed in the first direction, the second semiconductor element has a third edge that extends in the second direction and is located closest to the drive element;
When viewed in the first direction, the drive element has a fourth edge that extends in the third direction and is located closest to the third edge;
3. The semiconductor device according to claim 2, wherein an extension line of the fourth edge intersects the third edge when viewed in the first direction. further comprising a first wiring that connects the drive element and the first gate electrode,
4. The semiconductor device according to claim 3, wherein the first gate electrode overlaps the first wiring when viewed in the first direction. further comprising a first insulating layer located on the opposite side of the first semiconductor element with respect to the first wiring in the first direction,
5. The semiconductor device according to claim 4, wherein the first wiring is in contact with the first insulating layer. further comprising a second wiring that connects the drive element and the first electrode,
The second wiring is located on the side where the first wiring is located with respect to the first insulating layer in the first direction,
6. The semiconductor device according to claim 5, wherein the second wiring is in contact with the first insulating layer. 7. The semiconductor device according to claim 6, wherein the driving element overlaps the first wiring and the second wiring when viewed in the first direction. The semiconductor device according to claim 7, wherein the second electrode is located closer to the drive element than the first electrode. 9. The semiconductor device according to claim 8, wherein the second electrode is located on the opposite side of the second gate electrode with respect to the first gate electrode in the second direction. 10. The semiconductor device according to claim 9, wherein the first wiring overlaps the second wiring when viewed in the first direction. further comprising a second insulating layer located between the first semiconductor element and the first insulating layer,
11. The semiconductor device according to claim 6, wherein at least a portion of each of the first wiring and the second wiring is accommodated in the second insulating layer. further comprising a plurality of power terminals located on the opposite side of the first wiring and the second wiring with respect to the first insulating layer,
12. The semiconductor device according to claim 11, wherein each of the plurality of power terminals is electrically connected to at least one of the first electrode, the second electrode, the third electrode, and the fourth electrode. 13. The semiconductor device according to claim 12, wherein at least a portion of each of the plurality of power terminals is accommodated in the first insulating layer. further comprising a heat dissipation layer located on the opposite side of the second insulating layer with respect to the first semiconductor element,
14. The semiconductor device according to claim 13, wherein the heat dissipation layer overlaps the first semiconductor element when viewed in the first direction. The main body and
a first electrode, a second electrode, a first gate electrode, and a second gate electrode located on one side of the main body in the first direction and electrically connected to the main body;
When viewed in the first direction, the main body portion has a first edge extending in a second direction perpendicular to the first direction, and a third direction extending in a third direction perpendicular to the first direction and the second direction. an extending second edge;
The length of the first edge is smaller than the length of the second edge,
the first gate electrode and the second gate electrode are separated from each other in the second direction;
When viewed in the first direction, the first gate electrode and the second gate electrode are located closer to the first edge than to the center of the main body. 16. The semiconductor device according to claim 15, wherein the second electrode is located closer to the first edge than the first electrode. 17. The semiconductor device according to claim 16, wherein the second electrode includes a portion located between the first gate electrode and the second gate electrode in the second direction.

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