JP2024024874A - Information processing system, processing method, and program - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a slave circuit which can suppress an increase in a circuit scale so as to detect a problem, in an information processing system.

SOLUTION: A slave circuit communicates with a bus master through a bus. The slave circuit comprises: generation means which generates an ECC error related to output of a memory when a writing signal inputted to the memory from the bus master is an ON state; and detection means which detects a problem on the basis of the ECC error generated by the generation means when a state of a reading signal at the time of reading of the memory changes into the state of the writing signal due to the problem.

SELECTED DRAWING: Figure 6

COPYRIGHT: (C)2024,JPO&INPIT

Description

The present disclosure relates to a slave circuit, an information processing system, a processing method, and a program.

One way to detect failures in slave circuits made of semiconductor integrated circuits is to duplicate all circuits to be detected, constantly compare outputs, and determine an error if the comparison results show a mismatch. There is one that notifies the bus master of an interrupt signal. As a related technique, Patent Document 1 discloses a technique related to failure detection in a semiconductor integrated circuit.

Japanese Patent Application Publication No. 2014-174670

However, when all the circuits whose failures are to be detected are duplicated, the circuit scale increases due to the duplicated circuits, as shown in FIG. 9, for example. Therefore, there is a need for technology that can suppress increases in circuit scale and detect defects in information processing systems.

One of the objectives of each aspect of the present disclosure is to provide a slave circuit, an information processing system, a processing method, and a program that can solve the above problems.

In order to achieve the above object, according to one aspect of the present disclosure, the slave circuit is a slave circuit that communicates with a bus master via a bus, and wherein a write signal input to a memory from the bus master is turned on. generation means for generating an ECC error regarding the output of the memory when the state is the same, and the ECC error generated by the generation means when the state of the read signal when reading the memory becomes the state of the write signal due to a malfunction. detection means for detecting the malfunction based on.

In order to achieve the above object, according to another aspect of the present disclosure, an information processing system includes the above slave circuit and a bus master that communicates with the slave circuit via a bus.

In order to achieve the above object, according to another aspect of the present disclosure, a processing method is a processing method executed by a slave circuit that communicates with a bus master via a bus, the processing method being performed by a slave circuit that receives input from the bus master to a memory. generating an ECC error regarding the output of the memory when a write signal is in an on state; and generating the ECC error when the read signal when reading the memory becomes the write signal state due to a malfunction. detecting the malfunction based on an error.

In order to achieve the above object, according to another aspect of the present disclosure, a program causes a computer included in a slave circuit that communicates with a bus master via a bus to receive a write signal input to a memory from the bus master. generating an ECC error regarding the output of the memory when the memory is in an on state; and based on the ECC error generated when the state of the read signal when reading the memory becomes the state of the write signal due to a malfunction. Detecting defects and executing them.

According to each aspect of the present disclosure, it is possible to suppress an increase in circuit scale and detect a malfunction in an information processing system.

1 is a diagram illustrating an example of a configuration of an information processing system according to a first embodiment of the present disclosure. 1 is a diagram illustrating an example of a configuration of a memory output inverting circuit according to a first embodiment of the present disclosure. FIG. FIG. 2 is a first diagram showing an example of a timing chart of signals and data in the information processing system according to the first embodiment of the present disclosure. FIG. 2 is a second diagram showing an example of a timing chart of signals and data in the information processing system according to the first embodiment of the present disclosure. FIG. 7 is a diagram illustrating an example of a configuration of a memory output inverting circuit according to a second embodiment of the present disclosure. FIG. 2 is a diagram illustrating the minimum configuration of a slave circuit according to an embodiment of the present disclosure. FIG. 3 is a diagram illustrating an example of a processing flow of a slave circuit with a minimum configuration according to an embodiment of the present disclosure. FIG. 1 is a schematic block diagram showing the configuration of a computer according to at least one embodiment. FIG. 3 is a diagram showing an example of a duplicated circuit.

Hereinafter, embodiments will be described in detail with reference to the drawings.
<First embodiment>
FIG. 1 is a diagram illustrating an example of the configuration of an information processing system 100 according to a first embodiment of the present disclosure. The information processing system 100 includes a bus master 1, a bus 2, and a slave circuit 20, as shown in FIG.
Bus 2 propagates various signals between bus master 1 and slave circuit 20. The bus master 1 outputs a request signal 3 to the slave circuit 20, a memory write/read control circuit 4, which will be described later, and a memory 6 via the bus 2. The request signal 3 is configured according to the bus specifications. For example, the request signal 3 includes a bus valid signal, a type signal, an identifier (ID), data, and an address. The bus valid signal is a signal indicating the presence or absence of a signal on the bus. For example, the bus valid signal becomes a high level signal when there is a signal, and becomes a low level signal when there is no signal. The type signal is a signal including a signal indicating writing or reading. The identifier is a signal indicating a number for distinguishing each request. Note that specific examples of the bus valid signal, type signal, and identifier (ID) are illustrated in FIG. 4, which will be described later. The bus master 1 also receives a response signal, which will be described later, from the slave circuit 20. The bus master 1 is a functional macro that allows a CPU (Central Processing Unit), DMA (Direct Memory Access), etc. to perform data transfer by itself.

The slave circuit 20 includes a memory write/read control circuit 4 , a memory 6 , a retiming circuit 7 , a memory output inversion circuit 10 , an ECC (Error Correction Code) error detection circuit 12 , and a response signal generation circuit 14 .

Memory write/read control circuit 4 receives request signal 3 . The memory write/read control circuit 4 generates a memory write/read control signal 5 from the request signal 3. Memory write/read control signal 5 indicates write control or read control. The memory write/read control signal 5 is, for example, a 1-bit signal. The memory write/read control circuit 4 outputs the generated memory write/read control signal 5 to the memory 6 and the retiming circuit 7.

The memory 6 receives a request signal 3 and a memory write/read control signal 5 . When the write/read control signal is for writing, the memory 6 writes data into the memory specified by the address. Further, when the write/read control signal is for reading, the memory 6 outputs the data in the memory specified by the address to the memory output inverting circuit 10 as memory output data 8.

Retiming circuit 7 receives write/read control signal 5 . The retiming circuit 7 performs retiming processing to synchronize the received write/read control signal 5 with the memory output data 8 output from the memory 6. The retiming circuit 7 outputs a retimed memory write/read control signal 9, which is a signal after the retiming process, to the memory output inversion circuit 10.

The memory output inversion circuit 10 is a circuit that inverts 2 bits of input data when the memory write/read control signal 9 is for writing. FIG. 2 is a diagram illustrating an example of the configuration of the memory output inverting circuit 10 according to the first embodiment of the present disclosure. The memory output inversion circuit 10 includes exclusive ORs 101a and 101b, as shown in FIG. Each of exclusive ORs 101a and 101b receives memory output data 8 and memory write/read control signal 9 after retiming.

The data width of memory output data 8 is assumed to be n bits. The exclusive OR 101a outputs the lower n-2 bits of the memory output data 8 to the ECC error detection circuit 12 without any processing. Further, the exclusive OR 101a performs the exclusive OR 101a for the n-1 bit of the memory output data 8 and the memory write/read control signal 9 after retiming. Calculate exclusive OR. Then, the exclusive OR 101a outputs the operation result to the ECC error detection circuit 12. Further, the exclusive OR 101a is an exclusive OR of the n-th bit of the memory output data 8 and the memory write/read control signal 9 after retiming in the exclusive OR 101b. Calculate. Then, the exclusive OR 101a outputs the operation result to the ECC error detection circuit 12. Note that the data output by the exclusive OR 101a is the memory output inversion circuit output, which is data obtained by inverting the (n-1)th bit and the nth bit of the memory output data 8 when the memory write/read control signal is on the write side. The data becomes 11.

ECC error detection circuit 12 receives memory output inversion circuit output data 11. The ECC error detection circuit 12 detects code errors in data of 1 bit and 2 bits or more. Furthermore, when the ECC error detection circuit 12 detects a code error in 1-bit data, it performs error correction for the 1-bit error. Then, the ECC error detection circuit 12 outputs the ECC error 13 to the response signal generation circuit 14. ECC error 13 is a 1-bit signal indicating whether ECC is correct or incorrect.

The response signal generation circuit 14 receives the ECC error 13. The response signal generation circuit 14 generates a response signal 15 for notifying the ECC error 13. The response signal 15 is a signal generated according to bus specifications. The response signal 15 is a signal including, for example, a bus valid signal, data, an identifier (ID), and an error notification. The response signal generation circuit 14 outputs the generated response signal 15 to the bus master 1 via the bus 2.

FIG. 3 is a first diagram showing an example of a timing chart of signals and data in the information processing system 100 according to the first embodiment of the present disclosure. FIG. 4 is a second diagram illustrating an example of a timing chart of signals and data in the information processing system 100 according to the first embodiment of the present disclosure. FIG. 3 is a timing chart when no failure occurs in the slave circuit 20. Further, FIG. 4 is a timing chart when a failure occurs in the slave circuit 20.

First, a timing chart when no failure occurs in the slave circuit 20 shown in FIG. 3 will be described. Note that the signal names in FIG. 3 correspond to the signal names in FIG. 1.

The bus master 1 outputs the request signal 3 to the memory write/read control circuit 4 (step S1) between times T1 and T3. In FIG. 3, the request signal 3 includes a bus valid signal, a type signal, and an identifier (ID). The type signal is write at times T1 and T2, and read at time T3. The memory write/read control circuit 4 generates the memory write/read control signal 5 with a delay of one clock with respect to the request signal 3 (step S2). The memory write/read control signal 5 indicates writing when it is “1” and reading when it is “0”. Note that the memory write/read control circuit 4 may generate the memory write/read control signal 5 without delaying the request signal 3.

Data is written into the memory 6 at times T2 and T3 according to the memory write/read control signal 5, and data is read out at time T4 (step S3). Data is read from the memory 6 with a one-clock delay relative to the request signal 3, and the memory 6 outputs the read data to the memory output inversion circuit 10 at time T5.

The memory output inversion circuit 10 inverts 2 bits of the data of the memory output data 8 according to the memory write/read control signal 9 after retiming (step S4). In the example shown in FIG. 3, the memory output inversion circuit 10 inverts data at times T3 and T4.

The ECC error detection circuit 12 outputs the ECC error 13 to the response signal generation circuit 14 at times T3 and T4. The response signal generation circuit 14 generates the response signal 15 at times T4, T5, and T6 delayed by one clock with respect to the ECC error 13, and notifies the bus master 1 of the ECC error of the response signal 15 at times T4 and T5. do. When the identifier (ID) of the response signal 15 is 0 or 1, the response signal generation circuit 14 is notified of the ECC error of the response signal 15. However, the type signal of request signal 3 is write. Therefore, the bus master 1 ignores the ECC error notified from the response signal generation circuit 14.

Next, a timing chart when a failure occurs in the slave circuit 20 shown in FIG. 4 will be described. A failure in the slave circuit 20 is a failure in which the memory write/read control circuit 4 performs a read of the memory write/read control signal 5 as a write.

Since the memory write/read control signal 5 is always a write, the memory output inverting circuit 10 always generates 2-bit inverted memory output inverting circuit output data 11, and sends the generated memory output inverting circuit output data 11 to the ECC error detection circuit. Output to 12. Therefore, the response signal generation circuit 14 notifies the bus master 1 of the ECC error of the response signal 15 at times T4, T5, and T6. When the identifier (ID) is 2, the type signal of the request signal 3 is read, and the bus master 1 detects an ECC error notification and detects that the memory write/read control signal 5 has failed from reading to writing. .

The information processing system 100 according to the first embodiment of the present disclosure has been described above. In the information processing system 100, the slave circuit 20 communicates with the bus master 1 via the bus 2. An ECC error detection circuit 12 (an example of a generation means) generates an ECC error 13 regarding the output of the memory 6 when a request signal 3 (an example of a write signal) input from the bus master 1 to the memory 6 is in an on state. do. The response signal generation circuit 14 (an example of a detection means) detects the ECC error generated by the ECC error detection circuit 12 when the state of the read signal at the time of reading from the memory 6 becomes the state of the request signal 3 due to a malfunction. The defect is detected based on No. 13. By doing so, in the information processing system, it is possible to suppress an increase in circuit scale and detect a malfunction.

<Second embodiment>
The information processing system 100 according to the second embodiment of the present disclosure includes a bus master 1, a bus 2, and a slave circuit 20, like the information processing system 100 according to the first embodiment of the present disclosure shown in FIG. The information processing system 100 according to the second embodiment of the present disclosure differs from the information processing system 100 according to the first embodiment of the present disclosure in the memory output inversion circuit 10.

FIG. 5 is a diagram illustrating an example of the configuration of the memory output inverting circuit 10 according to the second embodiment of the present disclosure. The memory output inversion circuit 10 according to the second embodiment of the present disclosure includes an exclusive OR 101b, as shown in FIG.

The exclusive OR 101b calculates the exclusive OR of the n-th bit of the memory output data 8 and the retimed memory write/read control signal 9, and outputs the calculation result to the ECC error detection circuit 12. In this case, the memory output inversion circuit 10 inverts one bit of the memory output data 8 output from the memory 6. Therefore, the ECC error detection circuit 12 outputs an ECC error 13, which is a 1-bit error, to the response signal generation circuit 14.

The response signal generation circuit 14 outputs the response signal 15 as an ECC error to the bus master in the case of the ECC error 13 which is a 1-bit error, as in the case of the ECC error 13 which is a 2-bit error. Note that in the case of ECC error 13, which is a 1-bit error, the ECC error detection circuit 12 performs error correction. Therefore, in the case of the memory output inversion circuit 10 according to the second embodiment, data errors can be eliminated.

The information processing system 100 according to the second embodiment of the present disclosure has been described above. In the information processing system 100, the memory output inversion circuit 10 includes an exclusive OR 101b. The exclusive OR 101b calculates the exclusive OR of the n-th bit of the memory output data 8 and the retimed memory write/read control signal 9, and outputs the calculation result to the ECC error detection circuit 12. By doing so, data errors can be eliminated in the memory output inverting circuit 10 according to the second embodiment.

FIG. 6 is a diagram showing the minimum configuration of the slave circuit 20 according to the embodiment of the present disclosure. The slave circuit 20 communicates with the bus master via the bus. The slave circuit 20 includes an ECC error detection circuit 12 (an example of a generation means) and a response signal generation circuit 14 (an example of a detection means). The ECC error detection circuit 12 generates an ECC error regarding the output of the memory when a request signal (an example of a write signal) input from the bus master to the memory is in an on state. The response signal generation circuit detects the malfunction based on the ECC error generated by the ECC error detection circuit 12 when the state of the read signal when reading the memory becomes the request signal state due to a malfunction.

FIG. 7 is a diagram illustrating an example of a processing flow of the slave circuit 20 with the minimum configuration according to the embodiment of the present disclosure. Next, processing of the slave circuit 20 with the minimum configuration according to the embodiment of the present disclosure will be described with reference to FIG. 7.

In a slave circuit 20 that communicates with a bus master via a bus, an ECC error detection circuit 12 detects an error related to the output of the memory when a request signal (an example of a write signal) input from the bus master to the memory is in an on state. An ECC error is generated (step S101). The response signal generation circuit detects the malfunction based on the ECC error generated by the ECC error detection circuit 12 when the state of the read signal when reading the memory becomes the request signal state due to a malfunction ( Step S102).

The slave circuit 20 with the minimum configuration according to the embodiment of the present disclosure has been described above. With this slave circuit 20, it is possible to suppress an increase in circuit scale and detect a malfunction in an information processing system.

Note that the order of the processing in the embodiment of the present disclosure may be changed as long as appropriate processing is performed.

Although the embodiment of the present disclosure has been described, the above-described information processing system 100, bus master 1, slave circuit 20, and other control devices may have a computer system inside. The above-described processing steps are stored in a computer-readable recording medium in the form of a program, and the above-mentioned processing is performed by reading and executing this program by the computer. A specific example of a computer is shown below.

FIG. 8 is a schematic block diagram showing the configuration of a computer according to at least one embodiment. The computer 50 includes a CPU 60, a main memory 70, a storage 80, and an interface 90, as shown in FIG. For example, each of the above-described information processing system 100, bus master 1, slave circuit 20, and other control devices is implemented in the computer 50. The operations of each processing section described above are stored in the storage 80 in the form of a program. The CPU 60 reads the program from the storage 80, expands it to the main memory 70, and executes the above processing according to the program. Further, the CPU 60 secures storage areas corresponding to each of the above-mentioned storage units in the main memory 70 according to the program.

Examples of the storage 80 include a HDD (Hard Disk Drive), an SSD (Solid State Drive), a magnetic disk, a magneto-optical disk, a CD-ROM (Compact Disc Read Only Memory), and a DVD-ROM (Digital Versatile). (Disc Read Only Memory) , semiconductor memory, etc. Storage 80 may be an internal medium connected directly to the bus of computer 50, or may be an external medium connected to computer 50 via interface 90 or a communication line. Furthermore, when this program is distributed to the computer 50 via a communication line, the computer 50 that received the distribution may develop the program in the main memory 70 and execute the above processing. In at least one embodiment, storage 80 is a non-transitory tangible storage medium.

Further, the program may realize some of the functions described above. Furthermore, the program may be a file that can realize the above-described functions in combination with a program already recorded in the computer system, a so-called difference file (difference program).

Although several embodiments of the disclosure have been described, these embodiments are examples and do not limit the scope of the disclosure. Various additions, omissions, substitutions, and changes may be made to these embodiments without departing from the spirit of the disclosure.

Note that a part or all of the above embodiment may be described as in the following supplementary notes, but is not limited to the following.

(Additional note 1)
A slave circuit that communicates with a bus master via a bus,
Generating means for generating an ECC error regarding the output of the memory when a write signal input to the memory from the bus master is in an on state;
detection means for detecting the malfunction based on the ECC error generated by the generation means when the state of the read signal when reading the memory becomes the write signal state due to a malfunction;
A slave circuit with.

(Additional note 2)
When the type signal indicating the type of processing for the memory includes a signal indicating writing, the detecting means detects the defect and outputs the detection result to the bus master via the bus.
Slave circuit described in Appendix 1.

(Additional note 3)
The detection means includes:
outputting the detection result including a bus valid signal indicating the presence or absence of a signal on the bus to the bus master;
Slave circuit described in Appendix 2.

(Additional note 4)
inverting means for inverting memory output data output by the memory and outputting the inverted data to the generating means;
Equipped with
The generating means is
generating the ECC error based on the inverted data output by the inverting means;
The slave circuit according to any one of Supplementary notes 1 to 3.

(Appendix 5)
A slave circuit according to any one of Supplementary notes 1 to 4,
a bus master that communicates with the slave circuit via a bus;
An information processing system equipped with.

(Appendix 6)
A processing method executed by a slave circuit that communicates with a bus master via a bus,
generating an ECC error regarding the output of the memory when a write signal input to the memory from the bus master is in an on state;
Detecting the malfunction based on the ECC error generated when the state of the read signal when reading the memory becomes the write signal state due to a malfunction;
processing methods including;

(Appendix 7)
In the computer owned by the slave circuit that communicates with the bus master via the bus,
generating an ECC error regarding the output of the memory when a write signal input to the memory from the bus master is in an on state;
Detecting the malfunction based on the ECC error generated when the state of the read signal when reading the memory becomes the write signal state due to a malfunction;
A program to run.

1... Bus master 2... Bus 4... Memory write/read control circuit 6... Memory 7... Retiming circuit 10... Memory output inversion circuit 12... ECC error detection circuit 14. ...Response signal generation circuit 50...Computer 60...CPU
70... Main memory 80... Storage 90... Interface 100... Information processing system

The present disclosure relates to an information processing system, a processing method, and a program.

One of the objectives of each aspect of the present disclosure is to provide an information processing system, a processing method, and a program that can solve the above problems.

In order to achieve the above object, according to another aspect of the present disclosure, an information processing system provides a write signal input from a bus master that communicates with a slave circuit via a bus to a memory in the slave circuit. an ECC error detection circuit that generates an ECC error regarding the output of the memory when the is on, and a response that is notified when a failure occurs in which the state of the read signal when reading the memory becomes the state of the write signal. The bus master detects the malfunction based on the ECC error generated by the ECC error detection circuit of the signal, and ignores the ECC error of the response signal notified in response to the write signal when reading the memory. and .

In order to achieve the above object, according to another aspect of the present disclosure, a processing method includes a processing method in which a write signal input to a memory in the slave circuit from a bus master that communicates with the slave circuit via a bus is provided. Generating an ECC error regarding the output of the memory when the memory is in an on state, and generating a response signal to be notified when a malfunction occurs in which the state of the read signal when reading the memory becomes the state of the write signal. The method includes detecting the malfunction based on the ECC error, and ignoring the ECC error for a write signal when reading the memory .

In order to achieve the above object, according to another aspect of the present disclosure, a program causes a computer to write data that is input to a memory in the slave circuit from a bus master that communicates with the slave circuit via a bus. generating an ECC error regarding the output of the memory when the signal is in an on state; and generating a response signal to be notified when a problem occurs in which the state of the read signal when reading the memory becomes the state of the write signal. The defect is detected based on the generated ECC error, and the ECC error for a write signal when reading the memory is ignored.

Claims (7)

A slave circuit that communicates with a bus master via a bus,
Generating means for generating an ECC error regarding the output of the memory when a write signal input to the memory from the bus master is in an on state;
detection means for detecting the malfunction based on the ECC error generated by the generation means when the state of the read signal when reading the memory becomes the write signal state due to a malfunction;
A slave circuit with. When the type signal indicating the type of processing for the memory includes a signal indicating writing, the detecting means detects the defect and outputs the detection result to the bus master via the bus.
The slave circuit according to claim 1. The detection means includes:
outputting the detection result including a bus valid signal indicating the presence or absence of a signal on the bus to the bus master;
The slave circuit according to claim 2. inverting means for inverting memory output data output by the memory and outputting the inverted data to the generating means;
Equipped with
The generating means is
generating the ECC error based on the inverted data output by the inverting means;
The slave circuit according to claim 1. A slave circuit according to any one of claims 1 to 4,
a bus master that communicates with the slave circuit via a bus;
An information processing system equipped with. A processing method executed by a slave circuit that communicates with a bus master via a bus,
generating an ECC error regarding the output of the memory when a write signal input to the memory from the bus master is in an on state;
Detecting the malfunction based on the ECC error generated when the state of the read signal when reading the memory becomes the write signal state due to a malfunction;
processing methods including; In the computer owned by the slave circuit that communicates with the bus master via the bus,
generating an ECC error regarding the output of the memory when a write signal input to the memory from the bus master is in an on state;
Detecting the malfunction based on the ECC error generated when the state of the read signal when reading the memory becomes the write signal state due to a malfunction;
A program stored in the bus master that causes the bus master to execute the program.

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