JP2024003932A - Electrooptical device, electronic apparatus, and method for manufacturing electrooptical device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an electrooptical device that prevents cracks in a light shielding layer 13a in a peripheral area F.

SOLUTION: A liquid crystal device 100 comprises: a substrate 10a that has, in a peripheral area F as the outside of a display area E, a first area Fa, a second area Fb, and a step part 91a or a step part 93a as a first step between the first area Fa and the second area Fb; a TFT 30 as a transistor; a light shielding layer 13a that is provided between the layers of the substrate 10a and the TFT 30, and includes refractory metal or metal silicide. The first area Fa is higher than the second area Fb in a thickness direction of the substrate 10a. In plan view, the light shielding layer 13a is provided in a portion overlapping the first area Fa, and is not provided in a portion overlapping the step part 91a or the step part 93a.

SELECTED DRAWING: Figure 4A

COPYRIGHT: (C)2024,JPO&INPIT

Description

The present invention relates to an electro-optical device, an electronic device including the electro-optical device, and a method for manufacturing an electro-optical device.

Conventionally, an electro-optical device disclosed in Patent Document 1 has been known.
In Patent Document 1, an electro-optical device includes a pixel electrode, a TFT (Thin Film Transistor) as a pixel transistor, and a data line arranged between the pixel electrode and the TFT and supplying an image signal to the pixel electrode via the TFT. , a scanning line arranged between the TFT and the substrate and supplying a scanning signal to the gate electrode of the TFT, and a laminated capacitor arranged between the scanning line and the substrate and electrically connected to the pixel electrode. and a holding capacity. The scanning line is a light shielding layer disposed between the substrate and the TFT, and has a two-layer structure in which a film made of WSi (tungsten silicide) is laminated on a conductive polysilicon film.

JP2020-38248A

In electro-optical devices, as a method of suppressing a decrease in storage capacitance due to increase in capacity or miniaturization of storage capacitance, for example, forming a trench in a substrate and forming a storage capacitor in the trench is being considered. .
When forming a storage capacitor in a trench provided in a substrate, alignment marks are required to align the photomask in order to form the electrodes and dielectric film that make up the storage capacitor in alignment with the trench position. Since such an alignment mark is formed in the peripheral area outside the display area in the same process as the trench, the alignment mark also has the same structure as the trench.
Further, a monitor pattern may be formed in the peripheral region to indirectly monitor the trench formation state. Since such a monitor pattern is also formed in the same process as the trench, it has the same structure as the trench.

If a light-shielding layer is provided so as to overlap such alignment marks and monitor patterns in a plan view, cracks may occur in the light-shielding layer because the light-shielding layer is in the same layer as the scanning line and contains WSi like the scanning line. It was found that there is a possibility that cracks may affect peripheral circuits provided near alignment marks and monitor patterns.

An electro-optical device according to one aspect of the present application includes, outside a display area, a first area, a second area, a substrate having a first step between the first area and the second area, and a transistor. , a light shielding layer provided between the substrate and the transistor and containing a high melting point metal or metal silicide, the first region being higher than the second region in the thickness direction of the substrate, and the first region being higher than the second region in the thickness direction of the substrate; The layer is provided in a portion that overlaps with the first region in plan view, and is not provided in a portion that overlaps with the first step.

An electronic device according to one aspect of the present application includes the electro-optical device described above.

A method for manufacturing an electro-optical device according to one aspect of the present application includes a step of forming steps corresponding to each other in a display area of a substrate and an outside of the display area; The steps include forming a light shielding layer containing a melting point metal or metal silicide, and forming a transistor in the display area. forming the step between the first region and the second region by forming a second region lower than the first region in the thickness direction of the substrate, and forming the light shielding layer; Outside the display area, the light shielding layer is formed in a portion that overlaps with the first region in plan view, and is not formed in a portion that overlaps with the step between the first region and the second region.

1 is a schematic plan view of a liquid crystal device according to Embodiment 1. FIG. FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. 1. An enlarged view of the upper right part of FIG. 1. FIG. 4 is a cross-sectional view of the element substrate along the IVA-IVA line in FIG. 3. FIG. 4 is a cross-sectional view of the element substrate taken along the IVB-IVB line in FIG. 3. FIG. 3 is a flowchart diagram of the manufacturing process of the element substrate. FIG. 4B is a cross-sectional view showing one step of the element substrate in FIG. 4A. FIG. 4B is a cross-sectional view showing one step of the element substrate of FIG. 4B. FIG. 4B is a cross-sectional view showing one step of the element substrate in FIG. 4A. FIG. 4B is a cross-sectional view showing one step of the element substrate of FIG. 4B. FIG. 4B is a cross-sectional view showing one step of the element substrate in FIG. 4A. FIG. 4B is a cross-sectional view showing one step of the element substrate of FIG. 4B. FIG. 4B is a cross-sectional view showing one step of the element substrate in FIG. 4A. FIG. 4B is a cross-sectional view showing one step of the element substrate of FIG. 4B. FIG. 4B is a cross-sectional view showing one step of the element substrate in FIG. 4A. FIG. 4B is a cross-sectional view showing one step of the element substrate in FIG. 4A. FIG. 4B is a cross-sectional view showing one step of the element substrate of FIG. 4B. FIG. 3 is a cross-sectional view of an element substrate according to Embodiment 2. FIG. 3 is a schematic configuration diagram of a projection display device according to a third embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
Here, in each of the following figures, the scale of each member is made different from the actual size in order to make each member recognizable.
Furthermore, in each figure, an X-axis, a Y-axis, and a Z-axis are illustrated as three axes orthogonal to each other, as necessary. Further, the direction along the X axis is defined as the X direction, the direction along the Y axis is defined as the Y direction, and the direction along the Z axis is defined as the Z direction or the thickness direction.
In addition, the plane that includes the X and Y axes is called the XY plane, and viewing the XY plane in the +Z direction or -Z direction is called planar view or planar view, and viewing the XY plane in the direction perpendicular to the cross section that includes the Z axis. This is called a cross-sectional view or cross-sectional view.

Furthermore, in the following description, for example, when referring to a substrate, the expression "on a substrate" refers to a case in which the device is placed in contact with the substrate, or a case in which it is placed on top of the substrate via an element such as another structure. , or a case in which a part is placed in contact with a substrate and a part is placed through another element.

1. Embodiment 1
In this embodiment, an active drive type liquid crystal device including a TFT for each pixel will be exemplified as an electro-optical device. This liquid crystal device can be suitably used as a light modulation device, for example, in a projection display device as an electronic device to be described later.

1.1. Overview of Structure of Liquid Crystal Device The structure of a liquid crystal device as an electro-optical device according to this embodiment will be described with reference to FIGS. 1 to 3. FIG. 1 is a schematic plan view showing the configuration of a transmissive liquid crystal device as an electro-optical device according to a first embodiment. FIG. 2 is a schematic cross-sectional view showing the structure of the liquid crystal device taken along line II-II in FIG. FIG. 3 is an enlarged view of the upper right portion of FIG.

As shown in FIGS. 1 and 2, the liquid crystal device 100 of the present embodiment includes an element substrate 10, a counter substrate 20 disposed opposite to the element substrate 10, and sandwiched between the element substrate 10 and the counter substrate 20. It has a liquid crystal layer 5 as an electro-optic layer. The liquid crystal layer 5 is made of liquid crystal having positive or negative dielectric anisotropy.

As the substrate 10a of the element substrate 10, for example, a glass substrate, a quartz substrate, or the like is used. For the substrate 20a of the counter substrate 20, for example, a transparent substrate such as a glass substrate or a quartz substrate is used. The element substrate 10 has a larger shape in plan view than the counter substrate 20. The element substrate 10 and the counter substrate 20 are bonded to each other via a sealing material 6 disposed along the outer edge of the counter substrate 20.

A display area E including a plurality of pixels P arranged in a matrix is provided inside the sealing material 6. The outside of the display area E is the peripheral area F. In the peripheral area F, between the sealing material 6 and the display area E, a parting part 23 made of a light-shielding material is provided along the outer edge of the display area E.

The peripheral region F of the element substrate 10 is provided with a terminal portion in which a plurality of external connection terminals 43 are arranged. In the peripheral region F, a data line drive circuit 47 is provided between the first side K1 along the terminal portion and the sealing material 6. Further, in the peripheral area F, a test circuit 41 is provided between the sealing material 6 and the display area E along the second side K2 opposite to the first side K1.

In the peripheral region F, a scanning line drive circuit 45 is provided between the sealing material 6 and the display region E along the third side K3 and the fourth side K4, which are perpendicular to the first side K1 and opposite to each other. ing. Note that the number of scanning line drive circuits 45 does not need to be two, and may be configured with only one. Further, in the peripheral region F, a plurality of wirings 49 are provided.

As shown in FIG. 3, in the peripheral region F, a monitor pattern 91 and an alignment mark 93 are provided between the fourth side K4 of the substrate 10a and the sealing material 6.
The monitor pattern 91 is a monitor pattern for level difference measurement that is formed in the same process as the trench when providing the trench, which will be described later, on the substrate 10a.
The alignment mark 93 is, for example, an alignment mark for a photomask used to form a capacitor electrode in accordance with the trench position and to form other structures. The alignment mark 93 is formed in a pattern depending on the exposure device used.

Note that the monitor pattern 91 and/or the alignment mark 93 may be provided at multiple locations on the substrate 10a. In addition, when forming capacitor electrodes and the like on a large substrate made up of a plurality of substrates 10a, the monitor pattern 91 and/or alignment mark 93 should be placed at one location on each substrate 10a, or at one location on each of the plurality of substrates 10a. It is also possible to have a configuration in which they are provided in different locations.

As shown in FIG. 2, on the surface of the substrate 10a on the liquid crystal layer 5 side, a light-transmissive pixel electrode 11 provided for each pixel P, a TFT 30 as a transistor, a scanning line drive circuit 45, a wiring 49, and a pixel An alignment film 12 covering the electrode 11 is provided. The TFT 30 and the pixel electrode 11 are constituent elements of the pixel P. The element substrate 10 includes a substrate 10a, a pixel electrode 11 provided on the substrate 10a, a TFT 30, a scanning line drive circuit 45, a wiring 49, and an alignment film 12.

A parting portion 23, an insulating layer 25, a counter electrode 21 as a common electrode, and an alignment film 22 covering the counter electrode 21 are provided on the surface of the substrate 20a on the liquid crystal layer 5 side. The counter substrate 20 in this embodiment includes a substrate 20a, a parting portion 23, an insulating layer 25, a counter electrode 21, and an alignment film 22. In this embodiment, an example is shown in which the common electrode is provided as the counter electrode 21 on the counter substrate 20 side, but the common electrode may be provided on the element substrate 10 side.

The insulating layer 25 is made of, for example, an inorganic material such as silicon oxide (SiO ₂ ) having optical transparency.
The counter electrode 21 is electrically connected to the upper and lower conductive portions 7 provided at the four corners of the counter substrate 20 . The upper and lower conductive portions 7 are electrically connected to a common wiring 18 on the element substrate 10 side, which serves as a capacitive wiring to be described later.

The pixel electrode 11 and the counter electrode 21 are made of a transparent conductive film such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The alignment film 12 and the alignment film 22 are selected based on the optical design of the liquid crystal device 100. Examples of materials for forming the alignment films 12 and 22 include inorganic alignment films such as silicon oxide, and organic alignment films such as polyimide.

Such a liquid crystal device 100 has a normally white mode in which the light transmittance of the pixel P when no voltage is applied is higher than the transmittance when no voltage is applied, and the transmittance of the pixel P when no voltage is applied is A normally black mode optical design is adopted, which has a lower transmittance than when a voltage is applied.
In the liquid crystal device 100, polarizing elements (not shown) are arranged on each of the incident side and the output side of the light L according to the optical design.

In this embodiment, an example will be described in which an inorganic alignment film is used as the alignment films 12 and 22, a liquid crystal having negative dielectric anisotropy is used as the liquid crystal layer 5, and a normally black mode optical design is applied.

1.2. Outline of Configuration of Element Substrate Next, the cross-sectional configuration of the display area E and peripheral area F of the element substrate 10 will be described with reference to FIGS. 4A and 4B. 4A is a cross-sectional view taken along the line IVA-IVA in FIG. 3, and FIG. 4B is a cross-sectional view taken along the line IVB-IVB in FIG. Note that illustration of the alignment film 12 is omitted in FIGS. 4A and 4B.

As shown in FIGS. 4A and 4B, a trench 10c is provided in the display area E of the substrate 10a, and a monitor pattern 91 and an alignment mark 93 are provided in the peripheral area F.
The trench 10c is a recess provided in the substrate 10a, and has a step portion 10ca as a second step.

As shown in FIG. 4A, the monitor pattern 91 has a recess 91b recessed in the thickness direction in the substrate 10a. Recess 91b has the same depth as trench 10c. In this embodiment, the area corresponding to the recess 91b of the monitor pattern 91 is the second area Fb, and the area in the peripheral area F excluding the second area Fb is the first area Fa. The first region Fa is a region located higher than the second region Fb in the thickness direction of the substrate 10a. In other words, the second region Fb is a region located lower than the first region Fa in the thickness direction of the substrate 10a.

Furthermore, a step portion 91a serving as a first step is provided between the first region Fa and the second region Fb. Step portion 91a corresponds to step portion 10ca of trench 10c. Specifically, the stepped portion 91a has the same height difference as the stepped portion 10ca. In this embodiment, the portion where the step portion 91a and the bottom of the monitor pattern 91 connect is formed smoothly, but it may be formed in the same shape as the trench 10c.

In the peripheral region F, a light shielding layer 13a is provided in the first region Fa. The light shielding layer 13a is provided so as not to overlap the stepped portion 91a.

As shown in FIG. 4B, the alignment mark 93 has a plurality of recesses 93b recessed in the thickness direction in the substrate 10a. Recess 93b has approximately the same depth as trench 10c. In this embodiment, in plan view, the area corresponding to the recess 93b of the alignment mark 93 is the second area Fb, and the area in the peripheral area F excluding the second area Fb is the first area Fa.

Furthermore, a step portion 93a serving as a first step is provided between the first region Fa and the second region Fb. Step portion 93a corresponds to step portion 10ca of trench 10c. Specifically, the step portion 93a has substantially the same height difference as the step portion 10ca.

In the peripheral region F, a light shielding layer 13a is provided in the first region Fa. The light shielding layer 13a is provided so as not to overlap the stepped portion 93a in plan view. In addition, in this embodiment, the light shielding layer 13a does not overlap with the second region Fb in plan view, but may be provided so as to overlap with the second region Fb.

As shown in FIGS. 4A and 4B, the element substrate 10 has a structure in which a plurality of functional layers are stacked on a base substrate 10a.
Specifically, on the substrate 10a, a first conductive layer, a second conductive layer, a third conductive layer 13x, a semiconductor layer 31, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, and pixel electrode 11 are stacked in this order.

The first conductive layer includes a second capacitive electrode 62 of the capacitive element 60.
The second conductive layer includes the first capacitive electrode 61 of the capacitive element 60.
The third conductive layer 13x includes a scanning line 13 and a light shielding layer 13a.
The fourth conductive layer includes the gate electrode 32 of the TFT 30, the second relay electrode 82, and the fifth relay electrode 85.
The fifth conductive layer includes a relay electrode 50.
The sixth conductive layer includes the data line 16 and the fourth relay electrode 84.
The seventh conductive layer includes a common wiring 18 as a capacitive wiring and a third relay electrode 83.

A dielectric film 63 is provided between the second capacitor electrode 62 of the first conductive layer and the first capacitor electrode 61 of the second conductive layer.
A first interlayer insulating layer 71 is provided between the second conductive layer and the third conductive layer 13x.
A second interlayer insulating layer 72 is provided between the third conductive layer 13x and the semiconductor layer 31.
A gate insulating film 33 is provided between the semiconductor layer 31 and the gate electrode 32 of the fourth conductive layer.
A third interlayer insulating layer 73 is provided between the fourth conductive layer and the fifth conductive layer.
A fourth interlayer insulating layer 74 is provided between the fifth conductive layer and the sixth conductive layer.
A fifth interlayer insulating layer 75 is provided between the sixth conductive layer and the seventh conductive layer.
A sixth interlayer insulating layer 76 is provided between the seventh conductive layer and the pixel electrode 11.

As shown in FIGS. 4A and 4B, a trench 10c is provided in the substrate 10a. By providing a portion of the capacitive element 60 inside the trench 10c, the capacitance is increased.
The capacitive element 60 includes a first capacitive electrode 61 disposed on the scanning line 13 side, a second capacitive electrode 62 disposed on the substrate 10a side, and a dielectric between the first capacitive electrode 61 and the second capacitive electrode 62. It has a film 63.

The second capacitor electrode 62 is electrically connected to the pixel electrode 11.
The second capacitor electrode 62 is electrically connected to the fifth relay electrode 85 via a contact hole C3 provided in the second interlayer insulating layer 72 and the first interlayer insulating layer 71.
The fifth relay electrode 85 is connected to the drain region 31d of the semiconductor layer 31 and is electrically connected to the relay electrode 50 via a contact hole C5 provided in the third interlayer insulating layer 73.

The relay electrode 50 is electrically connected to the fourth relay electrode 84 via a contact hole C8 provided in the fourth interlayer insulating layer 74.
The fourth relay electrode 84 is electrically connected to the third relay electrode 83 via a contact hole C10 provided in the fifth interlayer insulating layer 75.
The third relay electrode 83 is electrically connected to the pixel electrode 11 via a contact hole C20 provided in the sixth interlayer insulating layer 76.

The data line 16 is electrically connected to the source region of the TFT 30 via a contact hole (not shown) provided in the fourth interlayer insulating layer 74 and the third interlayer insulating layer 73.
The common wiring 18 is electrically connected to the first capacitor electrode 61 via a relay electrode and a second relay electrode 82 (not shown).

1.3. Outline of method for manufacturing a liquid crystal device Next, a method for manufacturing the liquid crystal device 100 according to the present embodiment will be described. Note that the following description will be made with reference to FIGS. 5 to 11B. FIG. 5 is a flowchart of the manufacturing process of the element substrate. 6A, FIG. 7A, FIG. 8A, FIG. 9A, FIG. 10, and FIG. 11A are cross-sectional views corresponding to each manufacturing process of the element substrate in FIG. 4A, and FIG. 6B, FIG. 7B, FIG. 8B, FIG. 9B, and FIG. 11B is a cross-sectional view corresponding to each manufacturing process of the element substrate of FIG. 4B.

The element substrate 10 is basically formed using known semiconductor methods such as low pressure CVD (Chemical Vapor Deposition), normal pressure CVD, plasma CVD, photolithography, sputtering, etching, and CMP (Chemical Mechanical Planarization). It can be manufactured by using the methods used in the process or by combining these methods. Although a preferred manufacturing method will be mainly described below, other manufacturing methods may be used as long as they can form an equivalent structure and satisfy the functions and characteristics of the configuration.

In step S1, as shown in FIG. 6A, trenches 10c are formed in the display area E and recesses 91b are formed in the peripheral area F in the substrate 10a. Note that the trench 10c and the recess 91b may be formed by forming an interlayer insulating layer on the substrate 10a, and forming the trench 10c and the recess 91b in the interlayer insulating layer or in the interlayer insulating layer and the substrate 10a.

Further, as shown in FIG. 6B, in step S1, a plurality of recesses 93b are formed in the peripheral region F at the same time as the trench 10c and the recess 91b. Note that, similarly to the trench 10c and the recess 91b, the recess 93b is formed by forming an interlayer insulating layer on the substrate 10a, and forming the recess 93b in the interlayer insulating layer or in the interlayer insulating layer and the substrate 10a. Good too.

In step S2, as shown in FIGS. 7A and 7B, a capacitive element 60 is formed in the trench 10c.
First, a second capacitor electrode 62 made of a conductive polysilicon film is formed on the substrate 10a including the inner wall of the trench 10c. The second capacitor electrode 62 is formed by forming a first conductive layer made of deposited polysilicon containing phosphorus to a thickness of 50 to 100 nm on the substrate 10a, and then patterning it into a desired shape by dry etching. It is formed.

After forming the second capacitor electrode 62, an oxide film island 71a covering a part of the second capacitor electrode 62 is formed. The oxide film islands 71a are formed by forming a silicon oxide film such as a TEOS (Tetraethyl Orthosilicate) film or an HTO (High Temperature Oxide) film to a thickness of about 100 nm, and then patterning the film. The oxide film island 71a is placed at a position where a contact hole C3 (described later) is provided, and functions as an etching stopper film for protecting the second capacitor electrode 62 when patterning the first capacitor electrode 61 (described later).

On the second capacitor electrode 62, a silicon oxide (SiO ₂ ) film, a silicon nitride (SiN) film, a metal oxide film (HfO ₂ , ZrO ₂ ), or the like is formed to a thickness of 20 nm as a dielectric film 63 . After that, a second conductive layer made of deposited polysilicon containing phosphorus is formed on the dielectric film 63 to a thickness of 50 nm to 100 nm, and then patterned by dry etching, thereby forming the dielectric film 63 and the first capacitor. An electrode 61 is formed.

In step S3, a first interlayer insulating layer 71 is formed.
As shown in FIGS. 7A and 7B, the first interlayer insulating layer 71 is made of a silicon oxide film made of TEOS, for example, and is formed on the first capacitor electrode 61 and the display area E and peripheral area F of the substrate 10a. It is formed to have a film thickness of 400 nm to 600 nm.
In the first interlayer insulating layer 71, a recess 71b reflecting the shape of the trench 10c is formed at a position overlapping the trench 10c in plan view. Furthermore, a recess 71c reflecting the shape of the recess 91b is formed at a position overlapping the recess 91b in plan view. Further, a recess 71d reflecting the shape of the recess 93b is formed at a position overlapping the recess 93b in plan view.

In step S4, a third conductive layer 13x is formed.
As shown in FIGS. 8A and 8B, a third conductive layer 13x made of a tungsten silicide (WSi) film is formed on the first interlayer insulating layer 71 to a thickness of 100 nm to 400 nm.
Note that the material of the third conductive layer 13x is preferably a tungsten silicide film, but other materials may also be used. For example, the material of the third conductive layer 13x may be metal silicide containing at least one of Ti, Cr, Ta, Mo, and Pd, or at least one of Ti, Cr, W, Ta, Mo, and Pd. High melting point metals can be used. Further, a multilayer structure of these materials may be used.

In the third conductive layer 13x, a recess 13b reflecting the shape of the recess 71b is formed at a position overlapping the trench 10c and the recess 71b. Furthermore, a recess 13c reflecting the shape of the recess 71c is formed at a position overlapping the recess 91b and the recess 71c. Further, a recess 13d reflecting the shape of the recess 71d is formed at a position overlapping the recess 93b and the recess 71d in plan view.

In step S5, the scanning line 13 and the light shielding layer 13a are formed.
As shown in FIGS. 9A and 9B, the third conductive layer 13x is patterned to form the scanning line 13 and the light shielding layer 13a. In the peripheral region F, the light shielding layer 13a is formed so as not to overlap the stepped portion 91a and the stepped portion 93a in plan view.

In step S6, a sacrificial film 19 is formed.
As shown in FIG. 10, the sacrificial film 19 is formed to cover the scanning line 13 and the light shielding layer 13a. The sacrificial film 19 is made of, for example, a silicon oxide film made of TEOS.

In step S7, the light shielding layer 13a is heat treated.
By heat-treating the light-shielding layer 13a made of a tungsten silicide (WSi) film, the amorphous light-shielding layer 13a transitions to a polycrystalline state. Stress can be alleviated by crystallizing the light shielding layer 13a. As described above, the light shielding layer 13a is provided so as not to overlap the stepped portion 91a and the stepped portion 93a in plan view. Therefore, the light shielding layer 13a overlaps the stepped portions 91a and 93a in a plan view, thereby suppressing the occurrence of cracks.

In step S8, the sacrificial film 19 is removed.
As shown in FIGS. 11A and 11B, when the sacrificial film 19 is removed by wet etching, an over-etched portion 71y is formed in the first interlayer insulating layer 71. Note that the over-etched portion 71y is formed only in the portion where over-etching occurs when the sacrificial film 19 is removed.

In step S9, the semiconductor layer 31 of the TFT 30 is formed.
As shown in FIGS. 4A and 4B, first, a second interlayer insulating layer 72 made of a TEOS film is formed on the scanning line 13 and the light shielding layer 13a.
After that, a semiconductor layer 31 of the TFT 30 is formed. The semiconductor layer 31 is made of polysilicon, and is formed by depositing amorphous silicon on the second interlayer insulating layer 72 and then performing heat treatment.

In step S10, the gate electrode 32 is formed.
First, a gate insulating film 33 is formed on the semiconductor layer 31. The gate insulating film 33 is made of an HTO film, and is formed on the semiconductor layer 31 to a thickness of 30 nm to 100 nm.

Next, contact holes C1, C3, and C4 are formed.
The contact hole C1 penetrates through the gate insulating film 33 and the second interlayer insulating layer 72, and exposes the scanning line 13 at the bottom of the contact hole C1.
The contact hole C3 penetrates through the gate insulating film 33, the second interlayer insulating layer 72, the first interlayer insulating layer 71, and the oxide film island 71a, and connects the second capacitive electrode of the capacitive element 60 to the bottom of the contact hole C3. 62 is exposed. Note that the drain region 31d of the semiconductor layer 31 is exposed inside the contact hole C3.
Contact hole C4 penetrates gate insulating film 33, second interlayer insulating layer 72, and first interlayer insulating layer 71, and exposes first capacitor electrode 61 of capacitor element 60 at the bottom of contact hole C4.

Next, a fourth conductive layer having a two-layer structure consisting of a conductive polysilicon film and a tungsten silicide film, which is a light-shielding conductive film, is formed on the gate insulating film 33 and inside the contact holes C1, C3, and C4. Form.
After forming the fourth conductive layer, the fourth conductive layer is patterned to form the gate electrode 32, the second relay electrode 82, and the fifth relay electrode 85.

Gate electrode 32 is electrically connected to scanning line 13 via contact hole C1.
The second relay electrode 82 is electrically connected to the first capacitive electrode 61 of the capacitive element 60 via the contact hole C4.
The fifth relay electrode 85 is electrically connected to the second capacitive electrode 62 of the capacitive element 60 via the contact hole C3.

In step S11, the relay electrode 50 is formed.
First, a third interlayer insulating layer 73 is formed. The third interlayer insulating layer 73 is made of a TEOS film, and is formed on the gate electrode 32, the second relay electrode 82, and the fifth relay electrode 85 to a thickness of 200 nm to 400 nm.
Next, a contact hole C5 is formed. Contact hole C5 is formed to penetrate third interlayer insulating layer 73 and expose fifth relay electrode 85.

Next, a fifth conductive layer made of a metal film such as a tungsten silicide film, which is a light-shielding conductive film, is formed to a thickness of 100 nm to 400 nm on the third interlayer insulating layer 73 and inside the contact hole C5. Thereafter, the fifth conductive layer is patterned to form the relay electrode 50.
Relay electrode 50 is electrically connected to fifth relay electrode 85 via contact hole C5. Thereby, the relay electrode 50 is electrically connected to the second capacitive electrode 62 of the capacitive element 60 via the fifth relay electrode 85.

In step S12, data lines 16 are formed.
First, a fourth interlayer insulating layer 74 is formed. The fourth interlayer insulating layer 74 is made of a TEOS film, and is formed on the relay electrode 50 and the third interlayer insulating layer 73 to a thickness of 500 nm to 1000 nm.

Next, a contact hole C8 is formed in the fourth interlayer insulating layer 74. Contact hole C8 penetrates fourth interlayer insulating layer 74 and exposes relay electrode 50 at the bottom of contact hole C8.

Next, inside the fourth interlayer insulating layer 74 and the contact hole C8, a sixth conductive layer consisting of a multilayer film in which an aluminum alloy film or a titanium nitride film and an aluminum film are laminated in two to four layers is formed. .
Thereafter, the data line 16 and the fourth relay electrode 84 are formed by patterning the sixth conductive layer.
Data line 16 is electrically connected to the source region of semiconductor layer 31.
The fourth relay electrode 84 is formed inside the contact hole C8 and is electrically connected to the relay electrode 50 exposed at the bottom of the contact hole C8.

In step S13, the common wiring 18 is formed.
First, a fifth interlayer insulating layer 75 is formed. The fifth interlayer insulating layer 75 is made of a TEOS film and is formed on the data line 16 and the fourth relay electrode 84 to a thickness of 500 nm to 1000 nm.
Next, a contact hole C10 is formed in the fifth interlayer insulating layer 75. The contact hole C10 penetrates the fifth interlayer insulating layer 75 and exposes the fourth relay electrode 84 at the bottom of the contact hole C10.

Next, a seventh conductive layer consisting of a multilayer film in which an aluminum alloy film or a titanium nitride film and an aluminum film are laminated in two to four layers is formed on the fifth interlayer insulating layer 75 and inside the contact hole C10. do.
After forming the seventh conductive layer, the common wiring 18 and the third relay electrode 83 are formed by patterning the seventh conductive layer.
The third relay electrode 83 is formed inside the contact hole C10 and is electrically connected to the fourth relay electrode 84 exposed at the bottom of the contact hole C10.

In step S14, the pixel electrode 11 is formed.
First, a sixth interlayer insulating layer 76 is formed. The sixth interlayer insulating layer 76 is made of a TEOS film, and is formed on the common wiring 18 and the third relay electrode 83 to a thickness of 500 nm to 1000 nm.
Next, a contact hole C20 is formed in the sixth interlayer insulating layer 76. The contact hole C20 penetrates the sixth interlayer insulating layer 76 and exposes the third relay electrode 83 at the bottom of the contact hole C20.
Next, ITO is formed into a film on the sixth interlayer insulating layer 76 and inside the contact hole C20, and is patterned to form the pixel electrode 11.

Note that in the manufacturing method according to this embodiment, the steps from step S6 to step S8 may be omitted. Even if steps S6 to S8 are omitted, by providing the light shielding layer 13a so as not to overlap the stepped portions 91a and 93a in plan view, cracks will not occur in the light shielding layer 13a during the heat treatment in step S9. This can be prevented from occurring.
If steps S6 to S8 are omitted, the portion 71y cut by over-etching is not formed in the first interlayer insulating layer 71.

1.4. Modifications The embodiments illustrated above can be modified in various ways. Specific modifications that can be applied to the above-described embodiments are illustrated below. Two or more aspects arbitrarily selected from the examples below may be combined as appropriate to the extent that they do not contradict each other.

In the above-described embodiment, the scanning line 13 is formed by the third conductive layer 13x, but when forming the scanning line 13 in a separate layer, in the display area E, a position overlapping with the recess 71b in plan view may be formed. The third conductive layer 13x may be removed by patterning. In this case, in step S5 described above, the third conductive layer 13x in the display area E is patterned so as not to overlap the trench 10c and the recess 71b in plan view. The scanning line 13 can be formed such that the gate electrode 32 functions as the scanning line 13, for example.

In the embodiment described above, the capacitive element 60 is formed in the trench 10c, but a configuration may be adopted in which only the trench 10c is provided and the capacitive element 60 is not provided.

The shape of trench 10c is not limited to the shape shown in the drawings. For example, the depth, width, and shape of the trench 10c in plan view are not limited as long as the trench 10c has a step such that the recess 71b is formed.

In the embodiment described above, the trench 10c is formed in the display area E, but a configuration may be adopted in which the trench 10c is not provided. In this modification, when the recess 71b is provided, the third conductive layer 13x that overlaps the step of the recess 71b in plan view may be removed by patterning.
In this case, the shape of the recess 71b does not depend on the trench 10c. Therefore, the shape of the recess 71b is not limited by the depth, width, or shape of the recess 71b when viewed from above, as long as it has a step that may cause cracks.

As described above, according to the liquid crystal device 100 as an electro-optical device of this embodiment, the following effects can be obtained.
In the liquid crystal device 100 of the present embodiment, in the peripheral area F as the outside of the display area E, a first area Fa, a second area Fb, and a first step difference between the first area Fa and the second area Fb are provided. A substrate 10a having a stepped portion 91a or a stepped portion 93a, a TFT 30 as a transistor, and a light shielding layer 13a provided between the substrate 10a and the TFT 30 and containing at least WSi as metal silicide. Fa is higher than the second region Fb in the thickness direction of the substrate 10a, and the light shielding layer 13a is provided in a portion that overlaps with the first region Fa and is provided in a portion that overlaps with the stepped portion 91a or the stepped portion 93a in plan view. Not yet.

In this way, in the liquid crystal device 100 of the present embodiment, the light shielding layer 13a, which is provided between the substrate 10a and the TFT 30 and includes at least WSi, is provided in a portion that overlaps with the first region Fa in a plan view, and is provided in the stepped portion 91a. Alternatively, it is not provided in a portion overlapping with the stepped portion 93a. Therefore, generation of cracks in the light shielding layer 13a can be suppressed.

Furthermore, in the liquid crystal device 100 of this embodiment, the stepped portion 91a is a part of the recessed portion 91b provided in the substrate 10a. Alternatively, the stepped portion 93a is a part of the recessed portion 93b provided in the substrate 10a.
Therefore, when the stepped portion 91a or the stepped portion 93a is provided on the substrate 10a, it is possible to suppress the occurrence of cracks in the light shielding layer 13a.

In the liquid crystal device 100 of this embodiment, the high melting point metal includes at least one of Ti, Cr, W, Ta, Mo, and Pd.
Therefore, even if a high-melting point metal containing at least one of Ti, Cr, W, Ta, Mo, and Pd is used as the light-shielding layer 13a, it is possible to suppress the occurrence of cracks in the light-shielding layer 13a.

In the liquid crystal device 100 of this embodiment, the metal silicide includes at least one of Ti, Cr, W, Ta, Mo, and Pd.
Therefore, even if metal silicide containing at least one of Ti, Cr, W, Ta, Mo, and Pd is used as the light-shielding layer 13a, it is possible to suppress the occurrence of cracks in the light-shielding layer 13a.

In the liquid crystal device 100 of this embodiment, the step portion 91a is also a part of the monitor pattern 91 for measuring the step.
Therefore, when the monitor pattern 91 has the stepped portion 91a, it is possible to suppress the occurrence of cracks in the light shielding layer 13a.

In the liquid crystal device 100 of this embodiment, the stepped portion 93a is also a part of the alignment mark 93.
Therefore, when the alignment mark 93 has the stepped portion 93a, it is possible to suppress the occurrence of cracks in the light shielding layer 13a.

The liquid crystal device 100 of this embodiment further includes a capacitive element 60 provided in the step portion 10ca as a second step in the display area E, and the step portion 91a or the step portion 93a corresponds to the step portion 10ca. ing.
Therefore, when the monitor pattern 91 has the stepped portion 91a or when the alignment mark 93 has the stepped portion 93a, it is possible to suppress the generation of cracks in the light shielding layer 13a.

In the liquid crystal device 100 of this embodiment, the stepped portion 10ca is also a part of the trench 10c as a recess provided in the substrate 10a.
Therefore, even when the trench 10c having the stepped portion 10ca is provided in the substrate 10a, it is possible to suppress the occurrence of cracks in the light shielding layer 13a in the peripheral region F.

The manufacturing method of the liquid crystal device 100 as an electro-optical device of the present embodiment includes a step portion 10ca and a step portion 91a or a step portion 91a or Step S1 as a step of forming the stepped portion 93a, Step S5 as a step of forming a light shielding layer 13a containing at least WSi in the display area E and the peripheral area F, and forming a TFT 30 as a transistor in the display area E. The step of forming the step includes forming a first area Fa and a second area Fb lower than the first area Fa in the thickness direction of the substrate 10a on the outside of the display area E. The step of forming the step portion 91a or the step portion 93a between the first region Fa and the second region Fb and forming the light shielding layer includes the step of forming the light shielding layer 13a in the peripheral region F in plan view. , is formed in a portion that overlaps with the first region Fa, and is not formed in a portion that overlaps with the stepped portion 91a or the stepped portion 93a between the first region Fa and the second region Fb.

As described above, according to the manufacturing method of the liquid crystal device 100 of the present embodiment, the light shielding layer 13a containing at least WSi as metal silicide is provided in the portion overlapping with the first region Fa in plan view, and is provided in the stepped portion 91a or the stepped portion It is not provided in the portion overlapping with the portion 93a. Therefore, it is possible to manufacture the liquid crystal device 100 that can suppress the occurrence of cracks in the light shielding layer 13a.

2. Embodiment 2
FIG. 12 is a cross-sectional view of the element substrate according to the second embodiment. FIG. 12 is a cross-sectional view taken at the same position as FIG. 4B of the first embodiment.
Embodiment 2 is characterized in that the substrate 10a does not include the trench 10c and the monitor pattern 91 for indirectly monitoring the formation of the trench 10c, and that a part of the capacitive element 60 is formed in the trench 10c. This embodiment differs from the first embodiment in that it is not. In the following description, the same reference numerals will be used for the same configurations as in the first embodiment, and redundant description will be omitted.

The capacitive element 60 has a third capacitive electrode 65, a dielectric film 64, a second capacitive electrode 62, a dielectric film 63, and a first capacitive electrode 61, and is made of a five-layer laminate in which each structure is laminated from the substrate 10a side. configured.
A step portion 71z serving as a second step is formed at the end of the stacked body constituting the capacitive element 60.

In this embodiment, the alignment mark 95 is composed of a recess 95b, which is an opening provided in the five-layer stack that constitutes the capacitive element 60, and a first interlayer insulating layer 71 that fills the recess 95b.
In plan view, the area corresponding to the recess 95b of the alignment mark 95 is the second area Fb, and the area in the peripheral area F excluding the second area Fb is the first area Fa. Further, a step portion 95a serving as a first step is provided between the first region Fa and the second region Fb of the first interlayer insulating layer 71.
In the peripheral region F, a light shielding layer 13a is provided in the first region Fa. Further, similarly to the first embodiment, the light shielding layer 13a is provided so as not to overlap the stepped portion 95a in plan view.

As described above, according to the liquid crystal device 100 as an electro-optical device of this embodiment, in addition to the effects of Embodiment 1, the following effects can be obtained.

In the liquid crystal device 100 of this embodiment, the step portion 95a as the first step is a part of the recess 95b, which is an opening provided in a five-layer laminate as a laminate stacked on the substrate 10a.
Therefore, for example, when the alignment mark 95 has the stepped portion 95a, it is possible to suppress the occurrence of cracks in the light shielding layer 13a.

In the liquid crystal device 100 of the present embodiment, the step portion 71z as the second step includes the third capacitor electrode 65, the dielectric film 64, the second capacitor electrode 62, the dielectric film 63, and the third capacitor electrode 65 as a laminate stacked on the substrate 10a. 1. This is a part of the 1-capacitor electrode 61.
Therefore, when the capacitive element 60 is composed of the third capacitive electrode 65, the dielectric film 64, the second capacitive electrode 62, the dielectric film 63, and the first capacitive electrode 61 as a laminate, cracks may occur in the light shielding layer 13a. can be suppressed.

3. Embodiment 3
FIG. 13 is a schematic configuration diagram showing the configuration of a projection type display device as an electronic device according to this embodiment. In this embodiment, a projection type display apparatus 1000 including a liquid crystal device 100 as an electro-optical device described above will be exemplified as a projection type display apparatus 1000.

As shown in FIG. 13, a projection display device 1000 as an electronic device of this embodiment includes a lamp unit 1001 as a light source, dichroic mirrors 1011 and 1012 as a color separation optical system, a liquid crystal device 100B that supports blue light, A liquid crystal device 100G compatible with green light, a liquid crystal device 100R compatible with red light, three reflecting mirrors 1111, 1112, 1113, three relay lenses 1121, 1122, 1123, a dichroic prism 1130 as a color synthesis optical system, A projection lens 1140 is provided as a projection optical system.

The lamp unit 1001 employs, for example, a discharge type light source. The method of the light source is not limited to this, and a solid state light source such as a light emitting diode or a laser may be used.

Light emitted from the lamp unit 1001 is separated by two dichroic mirrors 1011 and 1012 into three colored lights each having a different wavelength range. The three colored lights are approximately red light, approximately green light, and approximately blue light. In the following description, the substantially red light is also referred to as red light R, the substantially green light is also referred to as green light G, and the substantially blue light is also referred to as blue light B.

Dichroic mirror 1011 transmits red light R and reflects green light G and blue light B, which have shorter wavelengths than red light R. The red light R transmitted through the dichroic mirror 1011 is reflected by the reflection mirror 1111 and enters the liquid crystal device 100R. The green light G reflected by the dichroic mirror 1011 is reflected by the dichroic mirror 1012, and then enters the liquid crystal device 100G. The blue light B reflected by the dichroic mirror 1011 passes through the dichroic mirror 1012 and is emitted to the relay lens system 1120.

Relay lens system 1120 includes relay lenses 1121, 1122, 1123 and reflection mirrors 1112, 1113. Since the blue light B has a longer optical path than the green light G and the red light R, the luminous flux tends to be large. Therefore, the relay lens 1122 is used to suppress the expansion of the luminous flux. The blue light B incident on the relay lens system 1120 is reflected by the reflecting mirror 1112 and is converged near the relay lens 1122 by the relay lens 1121 . Then, the blue light B passes through the reflection mirror 1113 and the relay lens 1123 and enters the liquid crystal device 100B.

The liquid crystal device 100 as an electro-optical device according to the first embodiment or the second embodiment is applied to the liquid crystal devices 100R, 100G, and 100B that are light modulation devices in the projection display device 1000.

Each of the liquid crystal devices 100R, 100G, and 100B is electrically connected to the upper circuit of the projection display device 1000. As a result, image signals Dx specifying the gradation levels of red light R, green light G, and blue light B are respectively supplied from external circuits and processed by the upper circuit. As a result, the liquid crystal devices 100R, 100G, and 100B are driven, and their respective color lights are modulated.

The red light R, green light G, and blue light B modulated by the liquid crystal devices 100R, 100G, and 100B enter the dichroic prism 1130 from three directions. The dichroic prism 1130 combines the incident red light R, green light G, and blue light B. In the dichroic prism 1130, red light R and blue light B are reflected at 90 degrees, and green light G is transmitted. Therefore, the red light R, the green light G, and the blue light B are combined as display light for displaying a color image, and are emitted toward the projection lens 1140.

The projection lens 1140 is arranged facing outside of the projection display device 1000. The display light is magnified and emitted through the projection lens 1140, and is projected onto the screen 1200, which is the projection target.

In this embodiment, although the projection display device 1000 is illustrated as an electronic device, the electronic device to which the liquid crystal device 100 is applied is not limited to this. For example, it may be applied to electronic devices such as projection-type HUDs (Head-Up Displays), HMDs (Head Mounted Displays), personal computers, digital cameras, and liquid crystal televisions.
As described above, according to the projection display device 1000 of this embodiment, in addition to the effects of each of the embodiments described above, the following effects can be obtained.
A projection display device 1000 as an electronic device includes a liquid crystal device 100 as an electro-optical device according to each of the embodiments described above.

According to this configuration, it is possible to suppress the occurrence of cracks in the light shielding layer 13a of the liquid crystal device 100, thereby suppressing the occurrence of quality defects caused by cracks, thereby providing an electronic device capable of high-quality display. Can be done.

Further, in the above embodiment, a transmissive liquid crystal device is exemplified as the liquid crystal device 100 as an electro-optical device, but the liquid crystal device 100 may be a reflective liquid crystal device or an LCOS (Liquid crystal on silicon) liquid crystal device. You can also use it as

5... Liquid crystal layer, 6... Seal material, 7... Vertical conduction part, 10... Element substrate, 10a... Substrate, 10c... Trench, 10ca... Step portion, 11... Pixel electrode, 12... Alignment film, 13... Scanning line, 13a ...Light shielding layer, 13b, 13c, 13d...Concave portion, 13x...Third conductive layer, 16...Data line, 18...Common wiring, 19...Sacrificial film, 20...Counter substrate, 20a...Substrate, 21...Counter electrode, 30... TFT, 31... Semiconductor layer, 31d... Drain region, 32... Gate electrode, 33... Gate insulating film, 41... Inspection circuit, 43... External connection terminal, 45... Scanning line drive circuit, 47... Data line drive circuit, 49... Wiring, 50... Relay electrode, 60... Capacitive element, 61... First capacitive electrode, 62... Second capacitive electrode, 63, 64... Dielectric film, 65... Third capacitive electrode, 71... First interlayer insulating layer, 71b, 71c, 71d... recessed part, 71y... over-etched part, 71z... step part, 72... second interlayer insulating layer, 73... third interlayer insulating layer, 74... fourth interlayer insulating layer, 75... fifth interlayer insulating layer , 76... Sixth interlayer insulating layer, 82... Second relay electrode, 83... Third relay electrode, 84... Fourth relay electrode, 85... Fifth relay electrode, 91... Monitor pattern, 91a... Step part, 91b... Concave part , 93, 95... Alignment mark, 93a, 95a... Step portion, 93b, 95b... Concave portion, 100, 100B, 100G, 100R... Liquid crystal device, 1000... Projection type display device, 1001... Lamp unit, 1011, 1012... Dichroic mirror , 1111, 1112, 1113... Reflection mirror, 1120... Relay lens system, 1130... Dichroic prism, 1140... Projection lens, 1200... Screen, C1, C3, C4, C5, C8, C10, C20... Contact hole, E... Display Area, F...peripheral area, Fa...first area, Fb...second area.

Claims (11)

A substrate having a first region, a second region, and a first step between the first region and the second region outside a display region;
transistor and
a light shielding layer provided between the substrate and the transistor and containing a high melting point metal or metal silicide;
the first region is higher than the second region in the thickness direction of the substrate;
The light shielding layer is provided in a portion overlapping with the first region and not provided in a portion overlapping with the first step, in a plan view.
Electro-optical device. The high melting point metal includes at least one of Ti, Cr, W, Ta, Mo, and Pd,
The metal silicide includes at least one of Ti, Cr, W, Ta, Mo, and Pd.
The electro-optical device according to claim 1. The first step is a part of a recess provided in the substrate,
The electro-optical device according to claim 1. The first step is a part of a recess provided in a laminate stacked on the substrate.
The electro-optical device according to claim 1. The first level difference is part of a monitor pattern for measuring the level difference,
The electro-optical device according to claim 1. the first step is part of an alignment mark;
The electro-optical device according to claim 1. In the display area, a capacitive element provided at a second step,
The first step corresponds to the second step,
The electro-optical device according to claim 1. the second step is a part of a recess provided in the substrate;
The electro-optical device according to claim 7. the second step is a part of a laminate stacked on the substrate;
The electro-optical device according to claim 7. An electronic device comprising the electro-optical device according to any one of claims 1 to 9. forming mutually corresponding steps in a display area of the substrate and outside the display area;
forming a light shielding layer containing a high melting point metal or metal silicide in the display area and outside the display area;
forming a transistor in the display area,
In the step of forming the step, a first region and a second region lower than the first region in the thickness direction of the substrate are formed outside the display region. forming the step between the two regions;
The step of forming the light shielding layer includes forming the light shielding layer outside the display area in a portion overlapping with the first region in plan view, and forming the light shielding layer in the area between the first region and the second region. Do not form in areas that overlap with steps.
A method for manufacturing an electro-optical device.

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