JP2023184003A - Electro-optical device, electronic apparatus, and method of manufacturing electro-optical device - Google Patents

Abstract

To provide an electro-optical device that has low wiring resistance and is easy to be manufactured.SOLUTION: A liquid crystal device 100 includes: a substrate 10a; a capacitive element 60; a scanning line 13; a fifth relay electrode 85 connecting a drain region 31d and a second capacitive electrode 62; a light shielding film 50 connected to the fifth relay electrode 85; a fourth relay electrode 84 connected to the light shielding film 50; a fourth interlayer insulating layer 74 provided between the light shielding film 50 and the fourth relay electrode 84; a data line 16 connected to a source region 31s; a third interlayer insulating layer 73 on which a recess H1 is formed; a fourth interlayer insulating layer 74F that is provided along the third interlayer insulating layer 73 and is the same layer as the fourth interlayer insulating layer 74; and a scanning line driving circuit 45 that has an output wiring 14 which overlaps the recess H1 in a plan view and is connected to the scanning line 13 via a contact hole C30 formed by penetrating the third interlayer insulating layer 73 and the fourth interlayer insulating layer 74F, and that supplies a scanning signal SC to the scanning line 13 via the output wiring 14.SELECTED DRAWING: Figure 5

Description

The present invention relates to an electro-optical device, an electronic device including the electro-optical device, and a method for manufacturing an electro-optical device.

Conventionally, an electro-optical device disclosed in Patent Document 1 has been known.
In Patent Document 1, an electro-optical device includes a pixel region and a peripheral region. In the pixel region, a pixel electrode, a TFT (Thin Film Transistor) as a pixel transistor, and a data line arranged between the pixel electrode and the TFT and supplying an image signal to the pixel electrode via the TFT, A scanning line arranged between the TFT and the substrate and supplying a scanning signal to the gate electrode of the TFT, and a storage capacitor arranged between the scanning line and the substrate and electrically connected to the pixel electrode. . The peripheral area includes a scanning line drive circuit that supplies scanning signals to the scanning lines. The scanning line and the gate electrode have a two-layer structure in which a tungsten silicide film is laminated on a polysilicon film.

JP2020-38248A

When the scanning signal supplied from the scanning line drive circuit is relayed through the relay electrode of the gate electrode layer and supplied to the scanning line, the gate electrode layer and the scanning line each have a laminated structure of a polysilicon film and a tungsten silicide film. Therefore, the wiring resistance becomes high. The reason why the wiring resistance increases is because the contact resistance between the tungsten silicide film and the polysilicon film is high, and as the wiring resistance increases, the delay of the scanning signal increases and the ON period of the TFT becomes shorter. There are concerns that this will happen.
Therefore, there has been a need to develop a connection structure with low wiring resistance. Furthermore, the connection structure was required to be easy to make.

An electro-optical device according to one aspect of the present application includes: a substrate, a transistor, a scanning line provided between the substrate and the transistor, a capacitive element provided between the substrate and the scanning line; a first conductive member that electrically connects one source/drain region of the transistor and one electrode of the capacitor through a first contact hole; a second conductive member electrically connected to the second conductive member through a third contact hole, and a third conductive member electrically connected to the second conductive member through a third contact hole; and between the second conductive member and the third conductive member. a fourth conductive member electrically connected to the other source/drain region of the transistor via a fourth contact hole; and a second insulating layer in which a first opening is formed. , a third insulating layer that is provided along the second insulating layer and is the same layer as the first insulating layer; and a third insulating layer that overlaps the first opening in plan view, and the second insulating layer and the third insulating layer. a scanning line drive circuit having a wiring electrically connected to the scanning line through a second opening formed through the metal wiring, and supplying a scanning signal to the scanning line via the metal wiring; Equipped with.

An electronic device according to one aspect of the present application includes the electro-optical device described above.

A method for manufacturing an electro-optical device according to one aspect of the present application includes a step of forming a capacitive element on a substrate, a step of forming a scanning line that overlaps the capacitive element in a cross-sectional view, and a step of forming a scanning line in a cross-sectional view. forming a first opening in the second insulating layer; and forming a third insulating layer along the first opening in cross-sectional view. forming a second opening that penetrates the third insulating layer and the second insulating layer and exposes the scanning line; The method includes the step of forming wiring to which scanning signals from the line drive circuit are supplied.

1 is a schematic plan view of a liquid crystal device according to Embodiment 1. FIG. FIG. 2 is a schematic cross-sectional view taken along line II-II in FIG. 1. FIG. 2 is an equivalent circuit diagram showing the electrical configuration of a liquid crystal device. FIG. 2 is a plan view of area G in FIG. 1; 5 is a cross-sectional view of the element substrate taken along the line VV in FIG. 4. FIG. 5 is a cross-sectional view of the element substrate taken along line VI-VI in FIG. 4. FIG. 3 is a flowchart diagram of the manufacturing process of the element substrate. FIG. 3 is a flowchart diagram of the manufacturing process of the element substrate. FIG. 6 is a cross-sectional view showing one step of the element substrate of FIG. 5; FIG. 6 is a cross-sectional view showing one step of the element substrate of FIG. 5; FIG. 6 is a cross-sectional view showing one step of the element substrate of FIG. 5; FIG. 6 is a cross-sectional view showing one step of the element substrate of FIG. 5; FIG. 6 is a cross-sectional view showing one step of the element substrate of FIG. 5; FIG. 6 is a cross-sectional view showing one step of the element substrate of FIG. 5; FIG. 6 is a cross-sectional view showing one step of the element substrate of FIG. 5; FIG. 3 is a cross-sectional view of an element substrate according to Embodiment 2. 16 is a cross-sectional view showing one process of the element substrate of FIG. 15. FIG. 16 is a cross-sectional view showing one process of the element substrate of FIG. 15. FIG. 16 is a cross-sectional view showing one process of the element substrate of FIG. 15. FIG. 16 is a cross-sectional view showing one process of the element substrate of FIG. 15. FIG. FIG. 3 is a schematic configuration diagram of a projection display device according to a third embodiment.

Embodiments of the present invention will be described below with reference to the drawings.
Here, in each of the following figures, the scale of each member is made different from the actual size in order to make each member recognizable.
Furthermore, in each figure, an X-axis, a Y-axis, and a Z-axis are illustrated as three axes orthogonal to each other, as necessary. Further, one direction along the X axis is referred to as an X1 direction, and a direction opposite to the X1 direction is referred to as an X2 direction. Similarly, one direction along the Y axis is referred to as the Y1 direction, and the direction opposite to the Y1 direction is referred to as the Y2 direction. One direction along the Z axis is referred to as the Z1 direction, and the direction opposite to the Z1 direction is referred to as the Z2 direction. In addition, in this specification, when the X1 direction or the X2 direction is not distinguished, it is written as the X direction, and when the Y1 direction or the Y2 direction is not distinguished, it is written as the Y direction.
In addition, the plane that includes the X and Y axes is also called the "XY plane," and viewing the XY plane in the Z1 direction or Z2 direction is called a "planar view" or "planar view," and the cross section that includes the Z axis is A ``cross-sectional view'' or ``cross-sectional view'' refers to a view from the vertical direction.

Furthermore, in the following description, for example, with respect to a substrate, the expression "on the substrate" means that when it is placed in contact with the substrate, it is placed on top of the substrate via an element such as another structure. This represents either a case in which a part is placed on a substrate, or a part is placed in contact with a substrate, and a part is placed via another element.

Furthermore, "one source/drain region of the transistor" refers to either the source region or the drain region of the transistor, and "the other source/drain region of the transistor" refers to either the source region or the drain region of the transistor. shall refer to the other. This is because when the direction of current flowing through a transistor is reversed, the source and drain regions are swapped. In the following description, the source/drain region connected to the pixel electrode side will be referred to as a drain region, and the source/drain region connected to the data line side will be referred to as a source region.

1. Embodiment 1
In this embodiment, an active drive type liquid crystal device including a TFT for each pixel will be exemplified as an electro-optical device. This liquid crystal device can be suitably used as a light modulation device, for example, in a projection display device as an electronic device to be described later.

1.1. Overview of Structure of Liquid Crystal Device The structure of a liquid crystal device as an electro-optical device according to this embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a schematic plan view showing the configuration of a transmissive liquid crystal device as an electro-optical device according to a first embodiment. FIG. 2 is a schematic cross-sectional view showing the structure of the liquid crystal device taken along line II-II in FIG.

As shown in FIGS. 1 and 2, the liquid crystal device 100 of the present embodiment includes an element substrate 10, a counter substrate 20 disposed opposite to the element substrate 10, and sandwiched between the element substrate 10 and the counter substrate 20. It has a liquid crystal layer 5 as an electro-optic layer. The liquid crystal layer 5 is made of liquid crystal having positive or negative dielectric anisotropy.

As the substrate 10a of the element substrate 10, for example, a glass substrate, a quartz substrate, or the like is used. For the substrate 20a of the counter substrate 20, for example, a transparent substrate such as a glass substrate or a quartz substrate is used. The element substrate 10 has a larger shape in plan view than the counter substrate 20. The element substrate 10 and the counter substrate 20 are bonded to each other via a sealing material 6 disposed along the outer edge of the counter substrate 20.

A display area E including a plurality of pixels P arranged in a matrix is provided inside the sealing material 6. The outside of the display area E is the peripheral area F. In the peripheral area F, between the sealing material 6 and the display area E, a parting part 23 made of a light-shielding material is provided along the outer edge of the display area E.

The peripheral region F of the element substrate 10 is provided with a terminal portion in which a plurality of external connection terminals 43 are arranged. In the peripheral region F, a data line drive circuit 47 is provided between the first side K1 along the terminal portion and the sealing material 6. Further, in the peripheral area F, a test circuit 41 is provided between the sealing material 6 and the display area E along the second side K2 opposite to the first side K1.

In the peripheral region F, a scanning line drive circuit 45 is provided between the sealing material 6 and the display region E along the third side K3 and the fourth side K4, which are perpendicular to the first side K1 and opposite to each other. ing. Note that the number of scanning line drive circuits 45 does not need to be two, and may be configured with only one. Further, in the peripheral region F, a plurality of wirings 49 are provided.

As shown in FIG. 2, on the surface of the substrate 10a on the liquid crystal layer 5 side, a light-transmissive pixel electrode 11 provided for each pixel P, a TFT 30 as a transistor, a scanning line drive circuit 45, a wiring 49, and a pixel An alignment film 12 covering the electrode 11 is provided. The TFT 30 and the pixel electrode 11 are constituent elements of the pixel P. The element substrate 10 includes a substrate 10a, a pixel electrode 11 provided on the substrate 10a, a TFT 30, a scanning line drive circuit 45, a wiring 49, and an alignment film 12.

A parting portion 23, an insulating layer 25, a counter electrode 21 as a common electrode, and an alignment film 22 covering the counter electrode 21 are provided on the surface of the substrate 20a on the liquid crystal layer 5 side. The counter substrate 20 in this embodiment includes a substrate 20a, a parting portion 23, an insulating layer 25, a counter electrode 21, and an alignment film 22. In this embodiment, an example is shown in which the common electrode is provided as the counter electrode 21 on the counter substrate 20 side, but the common electrode may be provided on the element substrate 10 side.

As shown in FIG. 1, the scanning line drive circuit 45 and the inspection circuit 41 overlap the parting section 23 in a plan view. The parting section 23 blocks the light L from a laser light source (not shown) that is incident from the counter substrate 20 side so that it does not enter the peripheral circuits provided in the peripheral area F, such as the scanning line drive circuit 45, so that the light L does not enter the peripheral circuits. to prevent it from malfunctioning.

The insulating layer 25 is made of, for example, an inorganic material such as silicon oxide (SiO ₂ ) having optical transparency. The insulating layer 25 covers the parting portion 23 and is provided so that the surface on the liquid crystal layer 5 side is flat.

The counter electrode 21 covers the insulating layer 25 and is electrically connected to the vertical conductive portions 7 provided at the four corners of the counter substrate 20 . The upper and lower conductive portions 7 are electrically connected to a common wiring 18 on the element substrate 10 side, which serves as a capacitive wiring to be described later.

The pixel electrode 11 and the counter electrode 21 are made of a transparent conductive film such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide). The alignment film 12 and the alignment film 22 are selected based on the optical design of the liquid crystal device 100. Examples of materials for forming the alignment films 12 and 22 include inorganic alignment films such as silicon oxide, and organic alignment films such as polyimide.

Such a liquid crystal device 100 has a normally white mode in which the light transmittance of the pixel P when no voltage is applied is higher than the transmittance when no voltage is applied, and the transmittance of the pixel P when no voltage is applied is A normally black mode optical design is adopted, which has a lower transmittance than when a voltage is applied. In the liquid crystal device 100, polarizing elements (not shown) are arranged on each of the light incident side and the light output side according to the optical design.

In this embodiment, an example will be described in which an inorganic alignment film is used as the alignment films 12 and 22, a liquid crystal having negative dielectric anisotropy is used as the liquid crystal layer 5, and a normally black mode optical design is applied.

1.2. Overview of Electrical Configuration of Liquid Crystal Device Next, the electrical configuration of the liquid crystal device 100 will be described with reference to FIG. FIG. 3 is an equivalent circuit diagram showing the electrical configuration of the liquid crystal device.

As shown in FIG. 3, the liquid crystal device 100 has m scanning lines 13, n data lines 16, and n common wiring lines 18 on the substrate 10a of the element substrate 10. The scanning line 13 extends in the X1 direction. The data line 16 and the common wiring 18 extend in the Y1 direction.

The scanning line drive circuit 45 includes a transfer circuit 451, m output circuits 452, and m output wirings 14. The transfer circuit 451 generates m systems of transfer signals by sequentially shifting the start pulse SP in synchronization with the clock signal CLK.
The m systems of transfer signals are input to corresponding output circuits 452, and the output circuits 452 output scanning signals SC to the scanning lines 13 via the output wiring 14 based on the transfer signals.

The scanning line 13 is connected to the output wiring 14 of the scanning line driving circuit 45, and supplies scanning signals SC1, SC2, . . . , SCm supplied from the scanning line driving circuit 45 to each pixel P. In this embodiment, two scanning line drive circuits 45 are connected to both ends of the scanning line 13. Note that the connection between the two scanning line drive circuits 45 and the scanning line 13 is not limited to this. For example, one of the two scanning line drive circuits 45 is connected to the odd-numbered scanning line 13, and the other is connected to the scanning line 13 in an odd row. , may be connected to the even-numbered scanning lines 13.

The area defined by the scanning line 13 and the data line 16 becomes a pixel P. The pixel P is provided with a pixel electrode 11, a TFT 30, and a capacitor 60.
The scanning line 13 is electrically connected to the gate electrode 32 of the TFT 30, and the data line 16 is electrically connected to the source region 31s serving as the other source/drain region of the TFT 30. The scanning line 13 has a function of controlling on/off of the TFTs 30 provided in the same row all at once. The pixel electrode 11 is electrically connected to a drain region 31d serving as one source/drain region of the TFT 30.

The data line 16 is electrically connected to a data line drive circuit 47, and supplies image signals D1, D2, . . . , Dn supplied from the data line drive circuit 47 to the pixels P.
The scanning line 13 is electrically connected to a scanning line driving circuit 45, and supplies scanning signals SC1, SC2, . . . , SCm supplied from the scanning line driving circuit 45 to each pixel P.

The image signals D1 to Dn supplied from the data line driving circuit 47 to the data lines 16 may be supplied line-sequentially in this order, and may be supplied to a plurality of data lines 16 adjacent to each other for each group. May be supplied. The scanning line drive circuit 45 supplies the scanning signals SC1 to SCm to the scanning lines 13 in a line-sequential manner at a predetermined timing.

When the scanning signal SC1 is input to the TFT 30, the TFT 30 is turned on for a certain period of time. Thereby, the image signal D1 supplied from the data line 16 is written into the pixel electrode 11 at a predetermined timing. The image signal D1 at a predetermined level written into the liquid crystal layer 5 via the pixel electrode 11 is held for a certain period of time between the pixel electrode 11 and the counter electrode 21 which is arranged to face each other via the liquid crystal layer 5. .

In order to prevent the held image signal D1 from leaking, a capacitive element 60 is electrically connected to a liquid crystal capacitor provided between the pixel electrode 11 and the counter electrode 21. One electrode of the capacitive element 60 is electrically connected to the drain region 31d of the TFT 30 and the pixel electrode 11, and the other electrode of the capacitive element 60 is electrically connected to the common wiring 18 to which a constant common potential is applied. It is connected to the.

1.3. Outline of Structure of Element Substrate Next, the planar structure and cross-sectional structure of the pixel P on the element substrate 10 will be described with reference to FIGS. 4, 5, and 6. FIG. 4 is a plan view corresponding to a region G that is part of the display region E and peripheral region F in FIG. 5 is a sectional view taken along line VV in FIG. 4, and FIG. 6 is a sectional view taken along line VI-VI in FIG. 4. Note that illustration of the alignment film 12 is omitted in FIGS. 5 and 6.

As shown in FIG. 4, in the display area E, the scanning line 13 extends along the X direction as the first direction so as to shield light between two pixel electrodes 11 adjacent in the Y direction as the second direction. provided. Furthermore, the scanning line 13 has an overhanging portion 13a that overhangs in the Y1 direction and the Y2 direction at a location where the four pixel electrodes 11 face each other. A TFT 30 is provided at a position overlapping the protruding portion 13a in plan view. The TFT 30 is electrically connected to the pixel electrode 11 via a contact hole C20 serving as a pixel contact.

In the peripheral region F, the scanning line 13 has a wide portion 13b that is wide in the Y direction, and the wide portion 13b overlaps the output wiring 14 as a metal wiring in a plan view.
The output wiring 14 is an output line for the scanning signal SC of the scanning line drive circuit 45. The output wiring 14 has a width wider than the contact hole C30 in plan view, and extends along the X direction. Note that the width of the output wiring 14 is the length of the output wiring 14 in the Y direction.

As shown in FIGS. 5 and 6, the output wiring 14 is provided in a layer above the scanning line 13. The output wiring 14 is provided along a recess H2 provided in the fourth interlayer insulating layer 74F between the output wiring 14 and the scanning line 13, and has a contact hole as a second opening provided at the bottom of the recess H2. It is electrically connected to the scanning line 13 by making ohmic contact with the scanning line 13 via C30. Note that the recess H2 is provided along the recess H1 serving as the first opening.

As shown in FIG. 4, the scanning line 13 has multiple widths in the X direction. Note that the width of the scanning line 13 is the length of the scanning line 13 in the Y direction. The width of the protruding portion 13a of the scanning line 13 is the width W1. The width of the wide portion 13b of the scanning line 13 is the width W2. The width of the scanning line 13 between two adjacent extensions 13a in the X direction is one of width W3, width W4, and width W5. The width W3 is the width of the portion adjacent to the contact hole C20 in the Y direction, the width W5 is the width of the portion adjacent to the overhang portion 13a, and the width W4 is the width of the portion adjacent to the contact hole C20 in the Y direction. This is the width of the portion extending along opposite sides. Width W6 is the width between the overhanging portion 13a and the wide portion 13b.

In this embodiment, width W3 is narrower than width W4, width W4 is narrower than width W5, width W5 is narrower than width W1, and width W1 is narrower than width W2. Further, the width W6 has the same width as the width W4. Note that the width W1 of the projecting portion 13a may be the same as the width W2 of the wide portion 13b, or may be wider than the width W2. This is because the overhanging portion 13a is a portion that functions as a light shielding film of the TFT 30, and therefore is formed to be as wide as possible.

In the scanning line 13, the length of the part having the width W4 is longer than the other width parts in the X direction, so the average value of the width of the scanning line 13 is equal to or greater than the width W4. It's a little wide. Therefore, the width W2 of the wide portion 13b is wider than the width W3, the width W4, the width W6, the average value of the widths of the scanning lines 13, the width W5, and the width W1. Since the wide portion 13b is arranged in the peripheral region F, the aperture ratio does not decrease even if the width W2 of the wide portion 13b is increased. Therefore, the width W2 of the wide portion 13b can be made wider than the width of other portions of the scanning line 13.

As shown in FIGS. 5 and 6, the element substrate 10 has a structure in which a plurality of functional layers are stacked on a base substrate 10a.
Specifically, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, a fifth conductive layer, a sixth conductive layer, a seventh conductive layer, and a pixel electrode 11 are provided on the substrate 10a. , are stacked in this order.

The first conductive layer includes a second capacitive electrode 62 as one electrode of the capacitive element 60.
The second conductive layer includes a first capacitive electrode 61 as the other electrode of the capacitive element 60.
The third conductive layer includes scanning lines 13 as a light shielding member.
The fourth conductive layer includes the semiconductor layer 31 of the TFT 30, the gate electrode 32 of the TFT 30, a second relay electrode 82 as a conductive member, and a fifth relay electrode 85 as a first conductive member.
The fifth conductive layer includes a light shielding film 50 as a second conductive member.
The sixth conductive layer includes a data line 16 as a fourth conductive member, a first relay electrode 81 , a fourth relay electrode 84 as a third conductive member, and an output wiring 14 .
The seventh conductive layer includes a common wiring 18 as a capacitive wiring and a third relay electrode 83.

A dielectric film 63 is provided between the second capacitor electrode 62 of the first conductive layer and the first capacitor electrode 61 of the second conductive layer.
A first interlayer insulating layer 71 is provided between the second conductive layer and the third conductive layer.
A second interlayer insulating layer 72 is provided between the third conductive layer and the semiconductor layer 31.
A gate insulating film 33 is provided between the semiconductor layer 31 and the gate electrode 32 of the fourth conductive layer.
A third interlayer insulating layer 73 as a second insulating layer is provided between the fourth conductive layer and the fifth conductive layer. Note that in this embodiment, the second insulating layer includes a second interlayer insulating layer 72 and a gate insulating film 33.
A fourth interlayer insulating layer 74 as a first insulating layer and a fourth interlayer insulating layer 74F as a third insulating layer are provided between the fifth conductive layer and the sixth conductive layer. Note that the fourth interlayer insulating layer 74F is a part of the fourth interlayer insulating layer 74, and is a portion located in the peripheral region F.
A fifth interlayer insulating layer 75 is provided between the sixth conductive layer and the seventh conductive layer. A sixth interlayer insulating layer 76 is provided between the seventh conductive layer and the pixel electrode 11.

As shown in FIG. 5, a trench 10c is provided in the substrate 10a. A portion of the capacitive element 60 is provided inside the trench 10c to increase the capacitance.
The capacitive element 60 has a first capacitive electrode 61 disposed on the scanning line 13 side and a second capacitive electrode 62 as one electrode disposed on the substrate 10a side.
The fifth relay electrode 85 is electrically connected to the drain region 31d of the TFT 30 and via a contact hole C3 as a first contact hole provided in the second interlayer insulating layer 72 and the first interlayer insulating layer 71. , are electrically connected to the second capacitive electrode 62 of the capacitive element 60.

The light shielding film 50 is electrically connected to the fifth relay electrode 85 via a contact hole C5 as a second contact hole provided in the third interlayer insulating layer 73.
The fourth relay electrode 84 is electrically connected to the light shielding film 50 via a contact hole C8 as a third contact hole provided in the fourth interlayer insulating layer 74.
The third relay electrode 83 is electrically connected to the fourth relay electrode 84 via a contact hole C10 provided in the fifth interlayer insulating layer 75.
The pixel electrode 11 is electrically connected to the third relay electrode 83 via a contact hole C20 provided in the sixth interlayer insulating layer 76.

As shown in FIG. 6, the data line 16 is electrically connected to the source region 31s of the TFT 30 via a contact hole C6 as a fourth contact hole provided in the fourth interlayer insulating layer 74 and the third interlayer insulating layer 73. It is connected to the.
The output wiring 14 is provided in the sixth conductive layer in the same layer as the data line 16.

The fourth interlayer insulating layer 74F is provided along the inner surface of the recess H1 so as to fill the recess H1 provided in the third interlayer insulating layer 73, the gate insulating film 33, and the second interlayer insulating layer 72. There is.
Three recesses H1, H2, and contact holes C30 are provided between the output wiring 14 and the scanning line 13, but the number of recesses H1, H2, and contact holes C30 is four each. The number may be greater than or equal to two.

1.4. Outline of method for manufacturing a liquid crystal device Next, a method for manufacturing the liquid crystal device 100 according to the present embodiment will be described. Note that the following description will be made with reference to FIGS. 7A to 14. 7A and 7B are flowcharts of the manufacturing process of the element substrate. 8 to 14 are cross-sectional views corresponding to each manufacturing process of the element substrate of FIG. 5, respectively.

The element substrate 10 is basically formed using known semiconductor methods such as low pressure CVD (Chemical Vapor Deposition), normal pressure CVD, plasma CVD, photolithography, sputtering, etching, and CMP (Chemical Mechanical Planarization). It can be manufactured by using the methods used in the process or by combining these methods. Although a preferred manufacturing method will be mainly described below, other manufacturing methods may be used as long as they can form an equivalent structure and satisfy the functions and characteristics of the configuration.

In FIG. 7A, in step S1, a trench 10c is formed in the substrate 10a. Note that the trench 10c may be formed by forming an interlayer insulating layer on the substrate 10a, and providing the trench 10c in the interlayer insulating layer or in the interlayer insulating layer and the substrate 10a.

In step S2, capacitive element 60 is formed in trench 10c.
First, a second capacitor electrode 62 made of a conductive polysilicon film is formed on the substrate 10a including the inner wall of the trench 10c. A first conductive layer made of deposited polysilicon containing phosphorus is formed on the substrate 10a to a thickness of 50 nm to 100 nm, and then patterned into a desired shape by dry etching to form the second capacitor electrode 62. ,It is formed.

After forming the second capacitor electrode 62, an oxide film island 71a covering a part of the second capacitor electrode 62 is formed. The oxide film islands 71a are formed by forming a silicon oxide film such as a TEOS (Tetraethyl Orthosilicate) film or an HTO (High Temperature Oxide) film to a thickness of about 100 nm, and then patterning the film. The oxide film island 71a is placed at a position where a contact hole C3 (described later) is provided, and functions as an etching stopper film for protecting the second capacitor electrode 62 when patterning the first capacitor electrode 61 (described later).

On the second capacitor electrode 62, a silicon oxide (SiO ₂ ) film, a silicon nitride (SiN) film, a metal oxide film (HfO ₂ , ZrO ₂ ), or the like is formed to a thickness of 20 nm as a dielectric film 63 . After that, a second conductive layer made of deposited polysilicon containing phosphorus is formed on the dielectric film 63 to a thickness of 50 nm to 100 nm, and then patterned by dry etching to form the first capacitor electrode 61. do.

In step S3, a first interlayer insulating layer 71 is formed. FIG. 8 is a cross-sectional view of the element substrate in FIG. 5 corresponding to step S3.
As shown in FIG. 8, the first interlayer insulating layer 71 is made of a silicon oxide film made of TEOS, for example, and is formed on the first capacitor electrode 61 and the display area E and peripheral area F of the substrate 10a with a thickness of 400 nm to 600 nm. It is formed to a film thickness of .

In step S4, scanning lines 13 are formed. FIG. 9 is a cross-sectional view of the element substrate of FIG. 5 corresponding to step S4.
As shown in FIG. 9, a third conductive layer made of a tungsten silicide (WSi) film is formed to a thickness of 100 nm to 400 nm on the first interlayer insulating layer 71, and then patterned to form the scanning line 13. form. The scanning line 13 has a light blocking property.
As shown in FIG. 4, the scanning line 13 is patterned to have a protruding portion 13a in the display area E. Furthermore, the scanning line 13 is patterned to have a wide portion 13b in the peripheral region F. As mentioned above, the width of the scanning line 13 is such that the width W2 of the peripheral area F is larger than the width W3, the width W4, the width W6 in the display area E, the average value of the width of the scanning line 13, the width W5, and the width W1. , is patterned to become wider.

In step S5, a second interlayer insulating layer 72 is formed. As shown in FIG. 10, the second interlayer insulating layer 72 is made of, for example, a TEOS film, and is formed on the scanning line 13 to a thickness of 200 nm to 600 nm.
In step S6, the semiconductor layer 31 of the TFT 30 is formed. As shown in FIG. 10, the semiconductor layer 31 is made of polysilicon and is formed by depositing amorphous silicon on the second interlayer insulating layer 72 and then subjecting it to heat treatment.

In step S7, contact holes C1, C2, C3, and C4 are formed.
As shown in FIG. 10, a gate insulating film 33 is formed on the semiconductor layer 31. After that, contact holes C1, C2, C3, and C4 are formed.
The gate insulating film 33 is made of an HTO film, and is formed on the semiconductor layer 31 to a thickness of 30 nm to 100 nm.

The contact holes C1 and C2 penetrate the gate insulating film 33 and the second interlayer insulating layer 72 to expose the scanning line 13 at the bottom of the contact holes C1 and C2.
The contact hole C3 penetrates through the gate insulating film 33, the second interlayer insulating layer 72, the first interlayer insulating layer 71, and the oxide film island 71a, and connects the second capacitive electrode of the capacitive element 60 to the bottom of the contact hole C3. 62 is exposed. Note that the drain region 31d of the semiconductor layer 31 is exposed inside the contact hole C3. Further, at the entrance of the contact hole C3, a part of the gate insulating film 33 covering the drain region 31d of the semiconductor layer 31 is peeled off, leaving the drain region 31d of the semiconductor layer 31 exposed.

Contact hole C4 penetrates gate insulating film 33, second interlayer insulating layer 72, and first interlayer insulating layer 71, and exposes first capacitor electrode 61 of capacitor element 60 at the bottom of contact hole C4.

In step S8, the gate electrode 32, the second relay electrode 82, and the fifth relay electrode 85 are formed.
First, on the gate insulating film 33 and inside the contact holes C1, C2, C3, and C4, a fourth conductive layer having a two-layer structure consisting of a conductive polysilicon film and a tungsten silicide film that is a light-shielding conductive film is formed. form. Since the contact holes C3 and C4 are contact holes with a high aspect ratio, a deposited polysilicon film containing phosphorus is first formed, taking into consideration the ability to wrap around the inside of the contact holes C3 and C4. A tungsten silicide film, which is a light-shielding conductive film, is then laminated.

After forming the fourth conductive layer, the fourth conductive layer is patterned to form the gate electrode 32, the second relay electrode 82, and the fifth relay electrode 85. Furthermore, the gate electrode 32 is electrically connected to the scanning line 13 via contact holes C1 and C2.

The second relay electrode 82 is electrically connected to the first capacitive electrode 61 of the capacitive element 60 via the contact hole C4.
The fifth relay electrode 85 is electrically connected to the second capacitive electrode 62 of the capacitive element 60 via the contact hole C3.

In step S9, a third interlayer insulating layer 73 is formed. FIG. 10 is a cross-sectional view of the element substrate of FIG. 5 corresponding to step S9.
The third interlayer insulating layer 73 is made of a TEOS film, and is formed on the gate electrode 32, the second relay electrode 82, and the fifth relay electrode 85 to a thickness of 200 nm to 400 nm.

Through the steps from step S3 to step S9, in the peripheral region F, the first interlayer insulating layer 71, the scanning line 13, the second interlayer insulating layer 72, the gate insulating film 33, and the third interlayer insulating layer are formed on the substrate 10a. 73 are stacked in this order.

In step S10, a recess H1 and a contact hole C5 are formed. FIG. 11 is a cross-sectional view of the element substrate of FIG. 5 corresponding to step S10.
In this embodiment, the recess H1 and the contact hole C5 are formed in the same process.
As shown in FIG. 11, the recess H1 is formed to penetrate the third interlayer insulating layer 73 and the gate insulating film 33 to a depth halfway in the thickness direction of the second interlayer insulating layer 72. Three recesses H1 are formed at predetermined intervals at positions overlapping the wide portions 13b of the scanning lines 13 in plan view. Note that the number of recesses H1 is not limited to three.
Contact hole C5 is formed to penetrate third interlayer insulating layer 73 and expose fifth relay electrode 85.

In step S11, a light shielding film 50 is formed.
First, a fifth conductive layer made of a metal film such as a tungsten silicide film, which is a light-shielding conductive film, is formed to a thickness of 100 nm to 400 nm on the third interlayer insulating layer 73 and inside the contact hole C5. Thereafter, the fifth conductive layer is patterned to form a light shielding film 50.
The light shielding film 50 is electrically connected to the fifth relay electrode 85 via the contact hole C5. Thereby, the light shielding film 50 is electrically connected to the second capacitive electrode 62 of the capacitive element 60 via the fifth relay electrode 85.

In step S12, a fourth interlayer insulating layer 74 is formed. FIG. 12 is a cross-sectional view of the element substrate of FIG. 5 corresponding to step S12.
The fourth interlayer insulating layer 74 is made of a TEOS film and is formed on the light shielding film 50 and the third interlayer insulating layer 73 to a thickness of 500 nm to 1000 nm.

The fourth interlayer insulating layer 74F is a portion of the fourth interlayer insulating layer 74 provided in the peripheral region F. As shown in FIG. 12, in the peripheral region F, the fourth interlayer insulating layer 74F is formed along the inner surface of the recess H1. As a result, the fourth interlayer insulating layer 74F is formed to have a recess H2 that reflects the shape of the recess H1.

In step S13, contact holes C30, C6, C7, and C8 are formed. FIG. 13 is a cross-sectional view of the element substrate of FIG. 5 corresponding to step S13.
As shown in FIG. 13, the contact hole C30 is provided at the bottom of the recess H2, passes through the fourth interlayer insulating layer 74F and the second interlayer insulating layer 72, and forms a wide scanning line 13 at the bottom of the contact hole C30. The portion 13b is exposed.

As shown in FIG. 6, the contact hole C6 penetrates the fourth interlayer insulating layer 74 and the third interlayer insulating layer 73 to expose the source region 31s of the TFT 30 at the bottom of the contact hole C6.
As shown in FIG. 13, the contact hole C7 penetrates the fourth interlayer insulating layer 74 and the third interlayer insulating layer 73 to expose the second relay electrode 82 at the bottom of the contact hole C7.
Contact hole C8 penetrates fourth interlayer insulating layer 74 and exposes light shielding film 50 at the bottom of contact hole C8.

In step S14, the output wiring 14, the data line 16, the first relay electrode 81, and the fourth relay electrode 84 are formed. FIG. 14 is a cross-sectional view of the element substrate of FIG. 5 corresponding to step S14.
First, a multilayer film in which an aluminum alloy film or a titanium nitride film and an aluminum film are laminated in two to four layers is formed on the fourth interlayer insulating layers 74, 74F and inside the contact holes C30, C6, C7, and C8. A sixth conductive layer is formed.

After forming the sixth conductive layer, the output wiring 14, the data line 16, the first relay electrode 81, and the fourth relay electrode 84 are formed by patterning the sixth conductive layer.
As shown in FIG. 14, the output wiring 14 is formed on the inner surface of the recess H2 and the contact hole C30, and is electrically connected to the wide portion 13b of the scanning line 13 exposed at the bottom of the contact hole C30. . Note that the output wiring 14 is the output line of the scanning line drive circuit 45 as described above, and is connected to the output circuit 452 of the scanning signal SC of the scanning line drive circuit 45.
Thereby, the scanning signal SC output from the scanning line drive circuit 45 is supplied to the scanning line 13 via the output wiring 14.

The data line 16 is formed inside the contact hole C6 and is electrically connected to the source region 31s of the semiconductor layer 31 exposed at the bottom of the contact hole C6.
The first relay electrode 81 is formed inside the contact hole C7 and is electrically connected to the second relay electrode 82 exposed at the bottom of the contact hole C7.
The fourth relay electrode 84 is formed inside the contact hole C8 and is electrically connected to the light shielding film 50 exposed at the bottom of the contact hole C8.

In step S15, a fifth interlayer insulating layer 75 is formed.
The fifth interlayer insulating layer 75 is made of a TEOS film and is formed on the output wiring 14, the data line 16, the first relay electrode 81, and the fourth relay electrode 84 to a thickness of 500 nm to 1000 nm.

In step S16, the common wiring 18 and the third relay electrode 83 are formed.
First, contact holes C9 and C10 are formed in the fifth interlayer insulating layer 75.
Contact hole C9 penetrates fifth interlayer insulating layer 75 and exposes first relay electrode 81 at the bottom of contact hole C9.
The contact hole C10 penetrates the fifth interlayer insulating layer 75 and exposes the fourth relay electrode 84 at the bottom of the contact hole C10.

Next, on the fifth interlayer insulating layer 75 and inside the contact holes C9 and C10, a seventh conductive layer is formed of a multilayer film in which an aluminum alloy film or a titanium nitride film and an aluminum film are laminated in two to four layers. form.
After forming the seventh conductive layer, the common wiring 18 and the third relay electrode 83 are formed by patterning the seventh conductive layer.
The third relay electrode 83 is formed inside the contact hole C10 and is electrically connected to the fourth relay electrode 84 exposed at the bottom of the contact hole C10.

In step S17, a sixth interlayer insulating layer 76 is formed.
The sixth interlayer insulating layer 76 is made of a TEOS film, and is formed on the common wiring 18 and the third relay electrode 83 to a thickness of 500 nm to 1000 nm.

In step S18, the pixel electrode 11 is formed.
First, a contact hole C20 is formed in the sixth interlayer insulating layer 76. The contact hole C20 penetrates the sixth interlayer insulating layer 76 and exposes the third relay electrode 83 at the bottom of the contact hole C20.
Next, ITO is formed into a film on the sixth interlayer insulating layer 76 and inside the contact hole C20, and is patterned to form the pixel electrode 11 for each pixel P.

As described above, according to the liquid crystal device 100 as an electro-optical device of this embodiment, the following effects can be obtained.
The liquid crystal device 100 of this embodiment includes a substrate 10a as a substrate, a TFT 30 as a transistor, a scanning line 13 provided between the substrate 10a and the TFT 30, and a scanning line 13 provided between the substrate 10a and the scanning line 13. The capacitive element 60, the drain region 31d as one source/drain region of the TFT 30, and the second capacitive electrode 62 as one electrode of the capacitive element 60 are electrically connected through a contact hole C3 as a first contact hole. a fifth relay electrode 85 as a first conductive member to be connected; a light shielding film 50 as a second conductive member electrically connected to the fifth relay electrode 85 via a contact hole C5 as a second contact hole; A fourth relay electrode 84 as a third conductive member is electrically connected to the light shielding film 50 via a contact hole C8 as a third contact hole, and a fourth relay electrode 84 is provided between the light shielding film 50 and the fourth relay electrode 84. As a fourth conductive member electrically connected to the fourth interlayer insulating layer 74 as the first insulating layer and the source region 31s as the other source/drain region of the TFT 30 via the contact hole C6 as the fourth contact hole. data line 16, a third interlayer insulating layer 73 as a second insulating layer in which a recess H1 as a first opening is formed, and a third interlayer insulating layer 73, which is provided along the third interlayer insulating layer 73 and is the same as the first insulating layer. The fourth interlayer insulating layer 74F serves as a third insulating layer, and the second opening is formed to overlap the recess H1 in plan view and penetrate through the third interlayer insulating layer 73 and the fourth interlayer insulating layer 74F. a scanning line drive circuit 45 having an output wiring 14 as a wiring electrically connected to the scanning line 13 via a contact hole C30, and supplying a scanning signal SC to the scanning line 13 via the output wiring 14; Equipped with.

As described above, in the liquid crystal device 100 of the present embodiment, the recess H1 as the first opening is provided in the third interlayer insulating layer 73 as the second insulating layer, and the recess H1 is overlapped with the recess H1 in plan view. The output wiring 14 of the scanning line drive circuit 45 is electrically connected to the scanning line 13 through the contact hole C30 as a second opening formed by penetrating the fourth interlayer insulating layer 74F as the third insulating layer. Connect to. Therefore, the wiring resistance between the scanning line drive circuit 45 and the scanning line 13 can be reduced. Furthermore, the structure can be easily manufactured.

Further, in the liquid crystal device 100 of this embodiment, the output wiring 14 as a wiring is a metal wiring.
Therefore, the wiring resistance of the output wiring 14 can be lowered.

In the liquid crystal device 100 of the present embodiment, the scanning line 13 has a wide portion 13b as a portion overlapping with the output wiring 14 as the wiring of the scanning line drive circuit 45 in a plan view, and a wide portion 13b as a portion overlapping with the TFT 30 in a plan view. The contact hole C30 has a width W2 wider than the overhang portion 13a and extends along the X direction as the first direction, and a plurality of contact holes C30 are provided along the X direction.
In this way, by making the width W2 of the wide portion 13b of the scanning line 13 wider than the width W1 of the overhanging portion 13a, the wiring resistance of the scanning line 13 can be lowered, and the structure can be easily manufactured. can.

In the liquid crystal device 100 of the present embodiment, the output wiring 14 as the wiring has a width wider than the contact hole C30 as the second opening in the Y direction as the second direction intersecting the X direction as the first direction. It extends along the X direction and is electrically connected to the scanning line 13 via a plurality of contact holes C30.
In this way, by making the width of the output wiring 14 wider than the contact hole C30, the wiring resistance of the output wiring 14 can be lowered, and a structure that is easy to manufacture can be achieved.

In the liquid crystal device 100 of the present embodiment, the scanning line 13 has a wide portion 13b as a portion overlapping with the output wiring 14 as the wiring of the scanning line drive circuit 45 in a plan view, and a wide portion 13b as a portion overlapping with the TFT 30 in a plan view. The contact hole C30 has a width W2 wider than the width W6 between the overhanging part 13a and the wide part 13b, and extends along the X direction, and a plurality of contact holes C30 serving as second openings are provided along the X direction. .
In this way, by making the width W2 of the wide portion 13b of the scanning line 13 wider than the width W6 and by providing a plurality of contact holes C30, the wiring resistance of the scanning line 13 can be lowered and it can be easily manufactured. It can be a structure.

In the liquid crystal device 100 of the present embodiment, the scanning line 13 is wider than the average width of the scanning line 13 in the wide portion 13b, which is a portion that overlaps the output wiring 14 as the wiring of the scanning line drive circuit 45 in a plan view. The contact holes C30 have a wide width and extend along the first direction, and a plurality of contact holes C30 serving as second openings are provided along the X direction.
In this way, the wiring resistance of the scanning line 13 can be lowered by making the width W2 of the wide portion 13b of the scanning line 13 wider than the average width of the scanning line 13 and by providing a plurality of contact holes C30. It is possible to create a structure that is easy to manufacture.

In the liquid crystal device 100 of the present embodiment, the output wiring 14 as the wiring has a width wider than the contact hole C30 as the second opening in the Y direction as the second direction intersecting the X direction as the first direction. , and extends along the X direction, and is electrically connected to the scanning line 13 via a plurality of contact holes C30.
Therefore, wiring resistance can be reduced.

The method for manufacturing the liquid crystal device 100 as an electro-optical device of this embodiment includes a step of forming a capacitive element 60 on a substrate 10a, a step of forming a scanning line 13 that overlaps the capacitive element 60 in a cross-sectional view, and a step of forming a capacitive element 60 on a substrate 10a. A step of forming a third interlayer insulating layer 73 as a second insulating layer that overlaps the scanning line 13 when viewed, a step of forming a recess H1 as a first opening in the third interlayer insulating layer 73, and a step of forming a recess H1 as a first opening in a cross-sectional view. , a step of forming a fourth interlayer insulating layer 74F as a third insulating layer along the recess H1, and a step of penetrating the fourth interlayer insulating layer 74F and the third interlayer insulating layer 73 to expose the scanning line 13. 2. A step of forming a contact hole C30 as an opening, and an output wiring 14 as a metal wiring connected to the scanning line 13 and supplied with the scanning signal SC from the scanning line drive circuit 45 via the contact hole C30. and a step of forming.

As described above, the method for manufacturing the liquid crystal device 100 of the present embodiment provides the recess H1 as the first opening in the third interlayer insulating layer 73 as the second insulating layer, and the third interlayer insulating layer 73 and the third insulating layer A contact hole C30 is provided as a second opening that penetrates the fourth interlayer insulating layer 74F and exposes the scanning line 13. Connect to line 13. Therefore, since the output wiring 14 and the scanning line 13 can be connected without providing a separate process for connecting the output wiring 14 and the scanning line 13, the structure can be easily manufactured. Furthermore, a structure with low wiring resistance can be achieved.

2. Embodiment 2
Next, an element substrate according to Embodiment 2 will be described with reference to FIGS. 15 to 19. FIG. 15 is a cross-sectional view of the element substrate according to the second embodiment. 16 to 19 are cross-sectional views corresponding to each manufacturing process of the element substrate of FIG. 15, respectively.

The second embodiment differs from the first embodiment in that the output wiring 14 is in ohmic contact with both the scanning line 13 and the gate electrode 32 in the peripheral region F. Therefore, in the second embodiment, the scanning signal SC supplied from the output wiring 14 is directly supplied to both the scanning line 13 and the gate electrode 32 in the peripheral region F.
In the following description, the same reference numerals will be used for the same configurations as in the first embodiment, and redundant description will be omitted.

As shown in FIG. 15, in the peripheral region F, the output wiring 14 is provided in the sixth conductive layer in the same layer as the data line 16.
The output wiring 14 is a portion provided on the inner wall of the contact hole C40 as a second opening provided in the fourth interlayer insulating layer 74F, the third interlayer insulating layer 73, the gate insulating film 33, and the second interlayer insulating layer 72. has.

The contact hole C40 exposes the gate electrode 32 and the scanning line 13 on its inner wall, and the output wiring 14 is electrically connected to the gate electrode 32 and the scanning line 13 exposed on the inner wall of the contact hole C40. Three contact holes C40 are provided along the X direction between the output wiring 14 and the scanning line 13, but the number may be four or more or two or less.

FIG. 16 is a cross-sectional view of the element substrate of FIG. 15 corresponding to step S10 of FIG. 7B.
The recess H1 and the contact hole C5 are formed in the same process as in the first embodiment.
In this embodiment, the gate electrode 32 is formed in the peripheral region F to have the same shape as the wide portion 13b of the scanning line 13 in plan view. Further, an opening is formed in the gate electrode 32 corresponding to the location where the recess H1 is formed. Note that in the peripheral region F, the gate electrode 32 may be formed in an island shape.

FIG. 17 is a cross-sectional view of the element substrate of FIG. 15 corresponding to step S12 of FIG. 7B.
As shown in FIG. 17, the fourth interlayer insulating layer 74F is formed in the peripheral region F along the recess H1. As a result, the fourth interlayer insulating layer 74F is formed to have a recess H2 that reflects the shape of the recess H1.

FIG. 18 is a cross-sectional view of the element substrate of FIG. 15 corresponding to step S13 of FIG. 7B.
As shown in FIG. 18, a contact hole C40 exposing the gate electrode 32 and the wide portion 13b of the scanning line 13 is formed at the position where the recess H1 and the recess H2 are provided.
The contact hole C40 exposes the wide portion 13b of the scanning line 13 by expanding the recess H2 and the recess H1. Therefore, a part of the contact hole C40 corresponds to the recess H1 as the first opening.
Contact hole C40 is formed in the same process as contact holes C6, C7, and C8.

FIG. 19 is a cross-sectional view of the element substrate of FIG. 15 corresponding to step S14 of FIG. 7B.
As shown in FIG. 19, the output wiring 14 is formed along the inner surface of the contact hole C40 to electrically connect the gate electrode 32 exposed inside the contact hole C40 and the wide portion 13b of the scanning line 13. connected to.
Thereby, the scanning signal SC output from the scanning line drive circuit 45 is directly supplied to both the gate electrode 32 and the scanning line 13 via the output wiring 14.

As described above, according to the liquid crystal device 100 as an electro-optical device of this embodiment, in addition to the effects of Embodiment 1, the following effects can be obtained.

In the liquid crystal device 100 of the present embodiment, the fourth interlayer insulating layer 74F as the third insulating layer has a region that overlaps with the gate electrode 32 in a plan view, and the output wiring 14 as the wiring has a region that overlaps with the gate electrode 32 in a plan view. It is electrically connected to the scanning line 13.
In this way, since the output wiring 14 is electrically connected to the gate electrode 32 and the scanning line 13, the wiring resistance can be reduced.

3. Embodiment 3
FIG. 20 is a schematic configuration diagram showing the configuration of a projection type display device as an electronic device according to this embodiment. In this embodiment, an electronic device including the liquid crystal device 100 as the electro-optical device described above will be described using a projection display device 1000 as an example.

As shown in FIG. 20, a projection display device 1000 as an electronic device of this embodiment includes a lamp unit 1001 as a light source, dichroic mirrors 1011 and 1012 as a color separation optical system, a liquid crystal device 100B that supports blue light, A liquid crystal device 100G compatible with green light, a liquid crystal device 100R compatible with red light, three reflecting mirrors 1111, 1112, 1113, three relay lenses 1121, 1122, 1123, a dichroic prism 1130 as a color synthesis optical system, A projection lens 1140 is provided as a projection optical system.

The lamp unit 1001 employs, for example, a discharge type light source. The method of the light source is not limited to this, and a solid state light source such as a light emitting diode or a laser may be used.

Light emitted from the lamp unit 1001 is separated by two dichroic mirrors 1011 and 1012 into three colored lights each having a different wavelength range. The three colored lights are approximately red light, approximately green light, and approximately blue light. In the following description, the substantially red light is also referred to as red light R, the substantially green light is also referred to as green light G, and the substantially blue light is also referred to as blue light B.

Dichroic mirror 1011 transmits red light R and reflects green light G and blue light B, which have shorter wavelengths than red light R. The red light R transmitted through the dichroic mirror 1011 is reflected by the reflection mirror 1111 and enters the liquid crystal device 100R. The green light G reflected by the dichroic mirror 1011 is reflected by the dichroic mirror 1012, and then enters the liquid crystal device 100G. The blue light B reflected by the dichroic mirror 1011 passes through the dichroic mirror 1012 and is emitted to the relay lens system 1120.

Relay lens system 1120 includes relay lenses 1121, 1122, 1123 and reflection mirrors 1112, 1113. Since the blue light B has a longer optical path than the green light G and the red light R, the luminous flux tends to be large. Therefore, the relay lens 1122 is used to suppress the expansion of the luminous flux. The blue light B incident on the relay lens system 1120 is reflected by the reflecting mirror 1112 and is converged near the relay lens 1122 by the relay lens 1121 . Then, the blue light B passes through the reflection mirror 1113 and the relay lens 1123 and enters the liquid crystal device 100B.

The liquid crystal device 100 as an electro-optical device according to the first embodiment or the second embodiment is applied to the liquid crystal devices 100R, 100G, and 100B that are light modulation devices in the projection display device 1000.

Each of the liquid crystal devices 100R, 100G, and 100B is electrically connected to the upper circuit of the projection display device 1000. As a result, image signals Dx specifying the gradation levels of red light R, green light G, and blue light B are supplied from external circuits and processed by the upper circuit. As a result, the liquid crystal devices 100R, 100G, and 100B are driven, and their respective color lights are modulated.

The red light R, green light G, and blue light B modulated by the liquid crystal devices 100R, 100G, and 100B enter the dichroic prism 1130 from three directions. The dichroic prism 1130 combines the incident red light R, green light G, and blue light B. In the dichroic prism 1130, red light R and blue light B are reflected at 90 degrees, and green light G is transmitted. Therefore, the red light R, the green light G, and the blue light B are combined as display light for displaying a color image, and are emitted toward the projection lens 1140.

The projection lens 1140 is arranged facing outside of the projection display device 1000. The display light is magnified and emitted through the projection lens 1140, and is projected onto the screen 1200, which is the projection target.

In this embodiment, although the projection display device 1000 is illustrated as an electronic device, the electronic device to which the liquid crystal device 100 is applied is not limited to this. For example, it may be applied to electronic devices such as projection-type HUDs (Head-Up Displays), HMDs (Head Mounted Displays), personal computers, digital cameras, and liquid crystal televisions.

As described above, according to the projection display device 1000 of this embodiment, in addition to the effects of each of the embodiments described above, the following effects can be obtained.
A projection display device 1000 as an electronic device includes a liquid crystal device 100 as an electro-optical device according to each of the embodiments described above.

According to this configuration, an electronic device capable of high-quality display can be provided.

Further, in the above embodiment, a transmissive liquid crystal device is exemplified as the liquid crystal device 100 as an electro-optical device, but the liquid crystal device 100 may be a reflective liquid crystal device or an LCOS (Liquid crystal on silicon) liquid crystal device. You can also use it as

5... Liquid crystal layer, 6... Seal material, 7... Vertical conduction part, 10... Element substrate, 10a... Substrate, 11... Pixel electrode, 12... Alignment film, 13... Scanning line, 13a... Overhanging part, 13b... Wide part, 14... Output wiring, 16... Data line, 18... Common wiring, 20... Counter substrate, 20a... Substrate, 21... Counter electrode, 30... TFT, 31... Semiconductor layer, 31d... Drain region, 31s... Source region, 32... Gate electrode, 33... Gate insulating film, 41... Inspection circuit, 43... External connection terminal, 45... Scanning line drive circuit, 451... Transfer circuit, 452... Output circuit, 47... Data line drive circuit, 49... Wiring, 50... Light shielding film, 60... Capacitive element, 61... First capacitive electrode, 62... Second capacitive electrode, 63... Dielectric film, 71... First interlayer insulating layer, 71a... Oxide film island, 72... Second interlayer insulating layer, 73... Third interlayer insulating layer, 74, 74F... Fourth interlayer insulating layer, 75... Fifth interlayer insulating layer, 76... Sixth interlayer insulating layer, 81... First relay electrode, 82... Second relay electrode, 83... Third relay electrode, 84... Fourth relay electrode, 85... Fifth relay electrode, 100, 100B, 100G, 100R... Liquid crystal device, 1000... Projection type display device, 1001... Lamp unit, 1011, 1012... Dichroic mirror, 1111 , 1112, 1113... Reflection mirror, 1120... Relay lens system, 1130... Dichroic prism, 1140... Projection lens, 1200... Screen, C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, C20, C30, C40...Contact hole, D1...Image signal, H1, H2...Concave portion, SC...Scanning signal.

Claims (10)

A substrate and
transistor and
a scanning line provided between the substrate and the transistor;
a capacitive element provided between the substrate and the scanning line;
a first conductive member that electrically connects one source/drain region of the transistor and one electrode of the capacitor through a first contact hole;
a second conductive member electrically connected to the first conductive member via a second contact hole;
a third conductive member electrically connected to the second conductive member via a third contact hole;
a first insulating layer provided between the second conductive member and the third conductive member;
a fourth conductive member electrically connected to the other source/drain region of the transistor via a fourth contact hole;
a second insulating layer in which a first opening is formed;
a third insulating layer provided along the second insulating layer and being the same layer as the first insulating layer;
The wiring includes a wiring that overlaps the first opening in a plan view and is electrically connected to the scanning line through a second opening formed by penetrating the second insulating layer and the third insulating layer. and a scanning line drive circuit that supplies a scanning signal to the scanning line via the metal wiring. The wiring is metal wiring,
The electro-optical device according to claim 1. The scanning line extends along the first direction with a width wider in a portion overlapping with the wiring of the scanning line drive circuit in plan view than in a portion overlapping with the transistor in plan view, and A plurality of openings are provided along the first direction,
The electro-optical device according to claim 1. The wiring has a width wider than the second opening in a second direction intersecting the first direction, and extends along the first direction through the plurality of second openings. electrically connected to the scanning line,
The electro-optical device according to claim 3. The width of the scanning line is greater than the width between the portion overlapping with the transistor in plan view and the portion overlapping with the wiring of the scanning line drive circuit in plan view, in a portion overlapping with the wiring of the scanning line drive circuit in plan view. has a wide width and extends along the first direction, and a plurality of the second openings are provided along the first direction.
The electro-optical device according to claim 1. The scanning line extends along the first direction with a width wider than the average width of the scanning line in a portion overlapping with the wiring of the scanning line drive circuit in a plan view, and A plurality of openings are provided along the first direction,
The electro-optical device according to claim 1. The wiring has a width wider than the second opening in a second direction intersecting the first direction, and extends along the first direction through the plurality of second openings. electrically connected to the scanning line,
The electro-optical device according to claim 5. The third insulating layer has a region that overlaps with the gate electrode in a plan view, and the wiring is electrically connected to the gate electrode and the scanning line.
The electro-optical device according to claim 2. An electronic device comprising the electro-optical device according to any one of claims 1 to 8. a step of forming a capacitive element on the substrate;
forming a scanning line that overlaps the capacitive element in a cross-sectional view;
forming a second insulating layer that overlaps the scanning line in a cross-sectional view;
forming a first opening in the second insulating layer;
forming a third insulating layer along the first opening in cross-sectional view;
forming a second opening that penetrates the third insulating layer and the second insulating layer and exposes the scanning line;
forming a wiring connected to the scanning line and supplied with a scanning signal from a scanning line driving circuit through the second opening;
A method for manufacturing an electro-optical device.

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