JP2023552994A5 - - Google Patents

Info

Publication number
JP2023552994A5
JP2023552994A5 JP2023533832A JP2023533832A JP2023552994A5 JP 2023552994 A5 JP2023552994 A5 JP 2023552994A5 JP 2023533832 A JP2023533832 A JP 2023533832A JP 2023533832 A JP2023533832 A JP 2023533832A JP 2023552994 A5 JP2023552994 A5 JP 2023552994A5
Authority
JP
Japan
Prior art keywords
matrix
codeword
configurable logic
bits
aforementioned
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2023533832A
Other languages
English (en)
Japanese (ja)
Other versions
JP2023552994A (ja
Filing date
Publication date
Priority claimed from US17/116,952 external-priority patent/US11734114B2/en
Application filed filed Critical
Publication of JP2023552994A publication Critical patent/JP2023552994A/ja
Publication of JP2023552994A5 publication Critical patent/JP2023552994A5/ja
Pending legal-status Critical Current

Links

JP2023533832A 2020-12-09 2021-12-07 プログラム可能な誤り訂正コードの符号化及び復号論理 Pending JP2023552994A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/116,952 US11734114B2 (en) 2020-12-09 2020-12-09 Programmable error correction code encoding and decoding logic
US17/116,952 2020-12-09
PCT/US2021/062201 WO2022125545A1 (en) 2020-12-09 2021-12-07 Programmable error correction code encoding and decoding logic

Publications (2)

Publication Number Publication Date
JP2023552994A JP2023552994A (ja) 2023-12-20
JP2023552994A5 true JP2023552994A5 (enExample) 2024-11-18

Family

ID=81848049

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023533832A Pending JP2023552994A (ja) 2020-12-09 2021-12-07 プログラム可能な誤り訂正コードの符号化及び復号論理

Country Status (6)

Country Link
US (1) US11734114B2 (enExample)
EP (1) EP4260467A4 (enExample)
JP (1) JP2023552994A (enExample)
KR (1) KR20230116051A (enExample)
CN (1) CN116615718A (enExample)
WO (1) WO2022125545A1 (enExample)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12099411B2 (en) * 2022-10-14 2024-09-24 SK Hynix Inc. Error processing circuit, memory and operation method of the memory

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5444719A (en) 1993-01-26 1995-08-22 International Business Machines Corporation Adjustable error-correction composite Reed-Solomon encoder/syndrome generator
JP2007104708A (ja) * 2006-11-27 2007-04-19 Renesas Technology Corp データ処理方法
WO2009004773A1 (ja) * 2007-06-29 2009-01-08 Mitsubishi Electric Corporation 検査行列生成装置、検査行列生成方法、符号化器、送信装置、復号器及び受信装置
US20110138249A1 (en) 2008-09-11 2011-06-09 Infineon Technologies Ag Apparatus and Method for Detecting an Error Within a Plurality of Coded Binary Words Coded by an Error Correction Code
JP2010199811A (ja) * 2009-02-24 2010-09-09 Fanuc Ltd 制御装置のメモリシステム
US8533572B2 (en) 2010-09-24 2013-09-10 Intel Corporation Error correcting code logic for processor caches that uses a common set of check bits
US8539321B2 (en) 2010-11-10 2013-09-17 Infineon Technologies Ag Apparatus and method for correcting at least one bit error within a coded bit sequence
US8990657B2 (en) * 2011-06-14 2015-03-24 Freescale Semiconductor, Inc. Selective masking for error correction
JP5770026B2 (ja) * 2011-06-20 2015-08-26 ルネサスエレクトロニクス株式会社 半導体装置
US8856629B2 (en) 2012-09-07 2014-10-07 Infineon Technologies Ag Device and method for testing a circuit to be tested
KR20170004693A (ko) * 2015-07-03 2017-01-11 에스케이하이닉스 주식회사 메모리 장치의 컨트롤러 및 그 동작 방법
US9965352B2 (en) * 2015-11-20 2018-05-08 Qualcomm Incorporated Separate link and array error correction in a memory system
KR102479212B1 (ko) 2016-08-17 2022-12-20 삼성전자주식회사 반도체 메모리 장치, 이를 포함하는 메모리 시스템 및 이의 동작 방법
KR102629405B1 (ko) * 2018-11-09 2024-01-25 삼성전자주식회사 반도체 메모리 장치, 메모리 시스템 및 반도체 메모리 장치의 동작 방법
US11012094B2 (en) * 2018-12-13 2021-05-18 Ati Technologies Ulc Encoder with mask based galois multipliers
US11237907B2 (en) * 2020-05-29 2022-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Processing-in-memory instruction set with homomorphic error correction

Similar Documents

Publication Publication Date Title
US11740960B2 (en) Detection and correction of data bit errors using error correction codes
JP4988731B2 (ja) フラッシュエラー訂正
US12181968B2 (en) System and method of reducing logic for multi-bit error correcting codes
KR920000828B1 (ko) 가로아체(Galois field)연산장치
US4856003A (en) Error correction code encoder
US20050138533A1 (en) Encoding/decoding device using a reed-solomon encoder/decoder
CN110071727B (zh) 编码方法、译码方法、纠错方法及装置
JP5805727B2 (ja) 縮退故障を有するメモリセルに対応するためのデータ符号化及び復号化
CN105553485A (zh) 基于fpga的bch编解码装置及其编解码方法
US10567007B2 (en) Device and method of processing a data word using checkbits
JP2023552994A5 (enExample)
US9191029B2 (en) Additional error correction apparatus and method
JP2016187099A5 (ja) データ処理回路及びエラー訂正方法
US10367529B2 (en) List decode circuits
CN117254823B (zh) 一种并行rs编码方法、装置、系统及计算机存储介质
US20060010363A1 (en) Method and system for correcting low latency errors in read and write non volatile memories, particularly of the flash type
CN108847851A (zh) 一种二元bch码伴随式矩阵的实现方法
JPH07226687A (ja) 誤り訂正処理装置
TWI551058B (zh) 最小－總和演算法之低密度奇偶校驗碼解碼器及其解碼方法
US12411617B1 (en) Memory system including ECC engine
CN119853709B (zh) Dvb-s2高速并行bch码译码器及其译码方法
CN117632577B (zh) 一种基于bch编码的快速ecc纠错电路
CN106067825B (zh) Bch预搜索电路、bch解码电路、bch预搜索方法及bch纠错方法
CN206077362U (zh) Bch预搜索电路及bch解码电路
JP2024123586A (ja) 演算回路、メモリシステムおよび制御方法