JP2023552994A - プログラム可能な誤り訂正コードの符号化及び復号論理 - Google Patents

プログラム可能な誤り訂正コードの符号化及び復号論理 Download PDF

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Publication number
JP2023552994A
JP2023552994A JP2023533832A JP2023533832A JP2023552994A JP 2023552994 A JP2023552994 A JP 2023552994A JP 2023533832 A JP2023533832 A JP 2023533832A JP 2023533832 A JP2023533832 A JP 2023533832A JP 2023552994 A JP2023552994 A JP 2023552994A
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data
bits
ecc
code word
matrix
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JP2023533832A
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JP2023552994A5 (enExample
Inventor
ヴィー． ラ フェトラ ロス
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Advanced Micro Devices Inc
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Advanced Micro Devices Inc
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Publication of JP2023552994A publication Critical patent/JP2023552994A/ja
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03 - H03M13/35
    • H03M13/45—Soft decoding, i.e. using symbol reliability information
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
    • H03M13/13—Linear codes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/61—Aspects and characteristics of methods and arrangements for error correction or error detection, not provided for otherwise
    • H03M13/615—Use of computational or mathematical techniques
    • H03M13/616—Matrix operations, especially for generator matrices or check matrices, e.g. column or row permutations
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6513—Support of multiple code types, e.g. unified decoder for LDPC and turbo codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6508—Flexibility, adaptability, parametrability and configurability of the implementation
    • H03M13/6516—Support of multiple code parameters, e.g. generalized Reed-Solomon decoder for a variety of generator polynomials or Galois fields
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6575—Implementations based on combinatorial logic, e.g. Boolean circuits

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Probability & Statistics with Applications (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Quality & Reliability (AREA)
  • General Engineering & Computer Science (AREA)
  • Algebra (AREA)
  • Computing Systems (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Error Detection And Correction (AREA)
JP2023533832A 2020-12-09 2021-12-07 プログラム可能な誤り訂正コードの符号化及び復号論理 Pending JP2023552994A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/116,952 US11734114B2 (en) 2020-12-09 2020-12-09 Programmable error correction code encoding and decoding logic
US17/116,952 2020-12-09
PCT/US2021/062201 WO2022125545A1 (en) 2020-12-09 2021-12-07 Programmable error correction code encoding and decoding logic

Publications (2)

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JP2023552994A true JP2023552994A (ja) 2023-12-20
JP2023552994A5 JP2023552994A5 (enExample) 2024-11-18

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JP2023533832A Pending JP2023552994A (ja) 2020-12-09 2021-12-07 プログラム可能な誤り訂正コードの符号化及び復号論理

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US (1) US11734114B2 (enExample)
EP (1) EP4260467A4 (enExample)
JP (1) JP2023552994A (enExample)
KR (1) KR20230116051A (enExample)
CN (1) CN116615718A (enExample)
WO (1) WO2022125545A1 (enExample)

Families Citing this family (1)

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Publication number Priority date Publication date Assignee Title
US12099411B2 (en) * 2022-10-14 2024-09-24 SK Hynix Inc. Error processing circuit, memory and operation method of the memory

Citations (3)

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JP2007104708A (ja) * 2006-11-27 2007-04-19 Renesas Technology Corp データ処理方法
WO2009004773A1 (ja) * 2007-06-29 2009-01-08 Mitsubishi Electric Corporation 検査行列生成装置、検査行列生成方法、符号化器、送信装置、復号器及び受信装置
JP2010199811A (ja) * 2009-02-24 2010-09-09 Fanuc Ltd 制御装置のメモリシステム

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US5444719A (en) 1993-01-26 1995-08-22 International Business Machines Corporation Adjustable error-correction composite Reed-Solomon encoder/syndrome generator
US20110138249A1 (en) 2008-09-11 2011-06-09 Infineon Technologies Ag Apparatus and Method for Detecting an Error Within a Plurality of Coded Binary Words Coded by an Error Correction Code
US8533572B2 (en) 2010-09-24 2013-09-10 Intel Corporation Error correcting code logic for processor caches that uses a common set of check bits
US8539321B2 (en) 2010-11-10 2013-09-17 Infineon Technologies Ag Apparatus and method for correcting at least one bit error within a coded bit sequence
US8990657B2 (en) * 2011-06-14 2015-03-24 Freescale Semiconductor, Inc. Selective masking for error correction
JP5770026B2 (ja) * 2011-06-20 2015-08-26 ルネサスエレクトロニクス株式会社 半導体装置
US8856629B2 (en) 2012-09-07 2014-10-07 Infineon Technologies Ag Device and method for testing a circuit to be tested
KR20170004693A (ko) * 2015-07-03 2017-01-11 에스케이하이닉스 주식회사 메모리 장치의 컨트롤러 및 그 동작 방법
US9965352B2 (en) * 2015-11-20 2018-05-08 Qualcomm Incorporated Separate link and array error correction in a memory system
KR102479212B1 (ko) 2016-08-17 2022-12-20 삼성전자주식회사 반도체 메모리 장치, 이를 포함하는 메모리 시스템 및 이의 동작 방법
KR102629405B1 (ko) * 2018-11-09 2024-01-25 삼성전자주식회사 반도체 메모리 장치, 메모리 시스템 및 반도체 메모리 장치의 동작 방법
US11012094B2 (en) * 2018-12-13 2021-05-18 Ati Technologies Ulc Encoder with mask based galois multipliers
US11237907B2 (en) * 2020-05-29 2022-02-01 Taiwan Semiconductor Manufacturing Company, Ltd. Processing-in-memory instruction set with homomorphic error correction

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Publication number Priority date Publication date Assignee Title
JP2007104708A (ja) * 2006-11-27 2007-04-19 Renesas Technology Corp データ処理方法
WO2009004773A1 (ja) * 2007-06-29 2009-01-08 Mitsubishi Electric Corporation 検査行列生成装置、検査行列生成方法、符号化器、送信装置、復号器及び受信装置
JP2010199811A (ja) * 2009-02-24 2010-09-09 Fanuc Ltd 制御装置のメモリシステム

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
水島 永雅 他: "組み込みシステムにおけるＢＣＨ符号の汎用エンコーダの開発", 電子情報通信学会技術研究報告, vol. 第112巻, 第215号, JPN6025040946, 20 September 2012 (2012-09-20), JP, pages 31 - 36, ISSN: 0005828840 *

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Publication number Publication date
US20220179741A1 (en) 2022-06-09
WO2022125545A1 (en) 2022-06-16
US11734114B2 (en) 2023-08-22
CN116615718A (zh) 2023-08-18
KR20230116051A (ko) 2023-08-03
EP4260467A4 (en) 2024-10-09
EP4260467A1 (en) 2023-10-18

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