JP2023548392A5 - - Google Patents
Info
- Publication number
- JP2023548392A5 JP2023548392A5 JP2023527314A JP2023527314A JP2023548392A5 JP 2023548392 A5 JP2023548392 A5 JP 2023548392A5 JP 2023527314 A JP2023527314 A JP 2023527314A JP 2023527314 A JP2023527314 A JP 2023527314A JP 2023548392 A5 JP2023548392 A5 JP 2023548392A5
- Authority
- JP
- Japan
- Prior art keywords
- dpe
- programmable
- circuit elements
- interconnection circuit
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US17/092,875 | 2020-11-09 | ||
| US17/092,875 US11270051B1 (en) | 2020-11-09 | 2020-11-09 | Model-based design and partitioning for heterogeneous integrated circuits |
| PCT/US2021/042138 WO2022098401A1 (en) | 2020-11-09 | 2021-07-19 | Model-based design and partitioning for heterogeneous integrated circuits |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2023548392A JP2023548392A (ja) | 2023-11-16 |
| JP2023548392A5 true JP2023548392A5 (https=) | 2024-07-30 |
| JP7796124B2 JP7796124B2 (ja) | 2026-01-08 |
Family
ID=77274826
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2023527314A Active JP7796124B2 (ja) | 2020-11-09 | 2021-07-19 | 異種集積回路のためのモデルベース設計および区分 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US11270051B1 (https=) |
| EP (1) | EP4241195A1 (https=) |
| JP (1) | JP7796124B2 (https=) |
| KR (1) | KR20230097191A (https=) |
| CN (1) | CN116457789A (https=) |
| WO (1) | WO2022098401A1 (https=) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10802807B1 (en) * | 2019-05-23 | 2020-10-13 | Xilinx, Inc. | Control and reconfiguration of data flow graphs on heterogeneous computing platform |
| US12339785B2 (en) | 2023-12-01 | 2025-06-24 | Hewlett Packard Enterprise Development Lp | Graph cache |
| CN118760560B (zh) * | 2024-09-09 | 2024-12-17 | 上海燧原智能科技有限公司 | 异构集成电路模块的api生成方法、装置、设备及介质 |
Family Cites Families (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5854929A (en) * | 1996-03-08 | 1998-12-29 | Interuniversitair Micro-Elektronica Centrum (Imec Vzw) | Method of generating code for programmable processors, code generator and application thereof |
| GB9828381D0 (en) | 1998-12-22 | 1999-02-17 | Isis Innovation | Hardware/software codesign system |
| US6964029B2 (en) | 2002-10-31 | 2005-11-08 | Src Computers, Inc. | System and method for partitioning control-dataflow graph representations |
| US7155708B2 (en) | 2002-10-31 | 2006-12-26 | Src Computers, Inc. | Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation |
| JP4165712B2 (ja) * | 2004-11-10 | 2008-10-15 | シャープ株式会社 | データフローグラフの同一サブグラフ検出装置、高位合成装置、データフローグラフの同一サブグラフ検出方法、データフローグラフの同一サブグラフ検出制御プログラムおよび可読記録媒体 |
| JP4562679B2 (ja) | 2006-03-30 | 2010-10-13 | 三洋電機株式会社 | データフローグラフ生成装置 |
| JP5605435B2 (ja) * | 2010-04-09 | 2014-10-15 | 日本電気株式会社 | 設計空間探索を加速する方法及び装置 |
| US20190138373A1 (en) * | 2017-10-27 | 2019-05-09 | Wave Computing, Inc. | Multithreaded data flow processing within a reconfigurable fabric |
| US10747690B2 (en) | 2018-04-03 | 2020-08-18 | Xilinx, Inc. | Device with data processing engine array |
| US10586003B1 (en) | 2018-08-21 | 2020-03-10 | Xilinx, Inc. | Circuit design using high level synthesis and linked hardware description language libraries |
| US10783295B1 (en) | 2019-04-30 | 2020-09-22 | Xilinx, Inc. | Netlist partitioning for designs targeting a data processing engine array |
| US10628622B1 (en) | 2019-05-10 | 2020-04-21 | Xilinx, Inc. | Stream FIFO insertion in a compilation flow for a heterogeneous multi-core architecture |
| US10891414B2 (en) | 2019-05-23 | 2021-01-12 | Xilinx, Inc. | Hardware-software design flow for heterogeneous and programmable devices |
| US11188312B2 (en) | 2019-05-23 | 2021-11-30 | Xilinx, Inc. | Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices |
| US10891132B2 (en) | 2019-05-23 | 2021-01-12 | Xilinx, Inc. | Flow convergence during hardware-software design for heterogeneous and programmable devices |
| US10802807B1 (en) * | 2019-05-23 | 2020-10-13 | Xilinx, Inc. | Control and reconfiguration of data flow graphs on heterogeneous computing platform |
-
2020
- 2020-11-09 US US17/092,875 patent/US11270051B1/en active Active
-
2021
- 2021-07-19 JP JP2023527314A patent/JP7796124B2/ja active Active
- 2021-07-19 CN CN202180075124.4A patent/CN116457789A/zh active Pending
- 2021-07-19 WO PCT/US2021/042138 patent/WO2022098401A1/en not_active Ceased
- 2021-07-19 EP EP21752616.9A patent/EP4241195A1/en active Pending
- 2021-07-19 KR KR1020237019079A patent/KR20230097191A/ko active Pending
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