JP7796124B2 - 異種集積回路のためのモデルベース設計および区分 - Google Patents

異種集積回路のためのモデルベース設計および区分

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Publication number
JP7796124B2
JP7796124B2 JP2023527314A JP2023527314A JP7796124B2 JP 7796124 B2 JP7796124 B2 JP 7796124B2 JP 2023527314 A JP2023527314 A JP 2023527314A JP 2023527314 A JP2023527314 A JP 2023527314A JP 7796124 B2 JP7796124 B2 JP 7796124B2
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program code
systems
nodes
model
hll
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Japanese (ja)
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JP2023548392A5 (https=
JP2023548392A (ja
Inventor
アヴィナーシュ ソマリンガ サレシュ，
アリ ベブーディアン，
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Xilinx Inc
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Xilinx Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G06F30/3953—Routing detailed
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/02—System on chip [SoC] design
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/08—Intellectual property [IP] blocks or IP cores
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2117/00—Details relating to the type or aim of the circuit design
    • G06F2117/08—HW-SW co-design, e.g. HW-SW partitioning

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Architecture (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Stored Programmes (AREA)
JP2023527314A 2020-11-09 2021-07-19 異種集積回路のためのモデルベース設計および区分 Active JP7796124B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US17/092,875 2020-11-09
US17/092,875 US11270051B1 (en) 2020-11-09 2020-11-09 Model-based design and partitioning for heterogeneous integrated circuits
PCT/US2021/042138 WO2022098401A1 (en) 2020-11-09 2021-07-19 Model-based design and partitioning for heterogeneous integrated circuits

Publications (3)

Publication Number Publication Date
JP2023548392A JP2023548392A (ja) 2023-11-16
JP2023548392A5 JP2023548392A5 (https=) 2024-07-30
JP7796124B2 true JP7796124B2 (ja) 2026-01-08

Family

ID=77274826

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2023527314A Active JP7796124B2 (ja) 2020-11-09 2021-07-19 異種集積回路のためのモデルベース設計および区分

Country Status (6)

Country Link
US (1) US11270051B1 (https=)
EP (1) EP4241195A1 (https=)
JP (1) JP7796124B2 (https=)
KR (1) KR20230097191A (https=)
CN (1) CN116457789A (https=)
WO (1) WO2022098401A1 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10802807B1 (en) * 2019-05-23 2020-10-13 Xilinx, Inc. Control and reconfiguration of data flow graphs on heterogeneous computing platform
US12339785B2 (en) 2023-12-01 2025-06-24 Hewlett Packard Enterprise Development Lp Graph cache
CN118760560B (zh) * 2024-09-09 2024-12-17 上海燧原智能科技有限公司 异构集成电路模块的api生成方法、装置、设备及介质

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WO2000038087A1 (en) 1998-12-22 2000-06-29 Celoxica Limited Hardware/software codesign system
JP2006505057A (ja) 2002-10-31 2006-02-09 エス・アール・シィ・コンピューターズ・インコーポレイテッド 制御データフローグラフ表現を区分化するためのシステムおよび方法
JP2007272395A (ja) 2006-03-30 2007-10-18 Sanyo Electric Co Ltd データフローグラフ生成装置、集積回路の設定データ生成装置、処理装置、及び集積回路
US10628622B1 (en) 2019-05-10 2020-04-21 Xilinx, Inc. Stream FIFO insertion in a compilation flow for a heterogeneous multi-core architecture
US10783295B1 (en) 2019-04-30 2020-09-22 Xilinx, Inc. Netlist partitioning for designs targeting a data processing engine array

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US5854929A (en) * 1996-03-08 1998-12-29 Interuniversitair Micro-Elektronica Centrum (Imec Vzw) Method of generating code for programmable processors, code generator and application thereof
US7155708B2 (en) 2002-10-31 2006-12-26 Src Computers, Inc. Debugging and performance profiling using control-dataflow graph representations with reconfigurable hardware emulation
JP4165712B2 (ja) * 2004-11-10 2008-10-15 シャープ株式会社 データフローグラフの同一サブグラフ検出装置、高位合成装置、データフローグラフの同一サブグラフ検出方法、データフローグラフの同一サブグラフ検出制御プログラムおよび可読記録媒体
JP5605435B2 (ja) * 2010-04-09 2014-10-15 日本電気株式会社 設計空間探索を加速する方法及び装置
US20190138373A1 (en) * 2017-10-27 2019-05-09 Wave Computing, Inc. Multithreaded data flow processing within a reconfigurable fabric
US10747690B2 (en) 2018-04-03 2020-08-18 Xilinx, Inc. Device with data processing engine array
US10586003B1 (en) 2018-08-21 2020-03-10 Xilinx, Inc. Circuit design using high level synthesis and linked hardware description language libraries
US10891414B2 (en) 2019-05-23 2021-01-12 Xilinx, Inc. Hardware-software design flow for heterogeneous and programmable devices
US11188312B2 (en) 2019-05-23 2021-11-30 Xilinx, Inc. Hardware-software design flow with high-level synthesis for heterogeneous and programmable devices
US10891132B2 (en) 2019-05-23 2021-01-12 Xilinx, Inc. Flow convergence during hardware-software design for heterogeneous and programmable devices
US10802807B1 (en) * 2019-05-23 2020-10-13 Xilinx, Inc. Control and reconfiguration of data flow graphs on heterogeneous computing platform

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000038087A1 (en) 1998-12-22 2000-06-29 Celoxica Limited Hardware/software codesign system
JP2006505057A (ja) 2002-10-31 2006-02-09 エス・アール・シィ・コンピューターズ・インコーポレイテッド 制御データフローグラフ表現を区分化するためのシステムおよび方法
JP2007272395A (ja) 2006-03-30 2007-10-18 Sanyo Electric Co Ltd データフローグラフ生成装置、集積回路の設定データ生成装置、処理装置、及び集積回路
US10783295B1 (en) 2019-04-30 2020-09-22 Xilinx, Inc. Netlist partitioning for designs targeting a data processing engine array
US10628622B1 (en) 2019-05-10 2020-04-21 Xilinx, Inc. Stream FIFO insertion in a compilation flow for a heterogeneous multi-core architecture

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ROQUIER, G. et al.，Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs，Journal of Electrical and Computer Engineering [online]，2012年，Volume 2012，pp. 1-11，[検索日 2025.06.02]，取得先 <https://onlinelibrary.wiley.com/doi/full/10.1155/2012/484962>
STREIT, Franz-Josef et al.，Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs，2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig) [online]，IEEE，2018年，[検索日 2025.06.02]，取得先 <https://ieeexplore.ieee.org/document/8641736>

Also Published As

Publication number Publication date
US11270051B1 (en) 2022-03-08
EP4241195A1 (en) 2023-09-13
CN116457789A (zh) 2023-07-18
WO2022098401A1 (en) 2022-05-12
KR20230097191A (ko) 2023-06-30
JP2023548392A (ja) 2023-11-16

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