JP2023541206A - Clock source circuits, cases, and multi-case cascade systems - Google Patents

Abstract

A clock source circuit (10), a case (20), and a multi-case cascade system (30) are provided. The clock source circuit (10) includes a reference signal generation circuit (110), a clock signal generation circuit (120), a programmable gate array (130), and a synchronization signal generation circuit (140). When the clock source circuit (10) is operating, it provides a first reference signal, a second reference signal, a first clock signal, a first trigger signal, and a synchronization signal to the slot (22) to generate a clock. It is possible to realize the functions of the source board. The clock source circuit (10) can realize the function of a clock source board depending on the circuit form, and can improve the integration of the case (20) by saving the space occupied by the clock source board. can. [Selection diagram] Figure 1

Description

TECHNICAL FIELD This application relates to the technical field of clock circuits, and more particularly to clock source circuits, cases, and multi-case cascade systems.

The PXIe case is a case in which extended measurement is performed using the pcie (peripheral component interconnect express, high-speed serial computer expansion bus standard) communication method. A PXIe case generally has a plurality of slots and a backplane, and provides electrical connections between the slots via the backplane.

In the prior art, PXIe cases typically include system timing slots. The system timing slot is used for inserting a clock source board. A clock source board provides clock signals to other slots in the PXIe case.

In the process of implementing the prior art, the inventors of the present invention discovered that the clock source board occupies a large space, which is disadvantageous for integrating the PXIe case.

In view of this, it is necessary to provide a clock source circuit, a case, and a multi-case cascade system to solve the problem that the clock source board in the conventional technology occupies a large space, which is disadvantageous to the integration of PXIe cases. .

A clock source circuit used to connect to a slot in the case,
a reference signal generation circuit connected to the slot for generating and transmitting a first reference signal and a second reference signal to the slot;
a clock signal generation circuit connected between the reference signal generation circuit and the slot to obtain the first reference signal and the second reference signal, generate a first clock signal, and transmit it to the slot; and,
connected to the reference signal generation circuit and the clock signal generation circuit, and further connected to the slot, and acquires the first reference signal, the second reference signal, and the first clock signal and transmits them to the slot. a programmable gate array for generating a first trigger signal and a source synchronization signal;
A synchronization signal generation circuit is connected between the programmable gate array and the slot to obtain the source synchronization signal, generate a synchronization signal, and transmit the generated synchronization signal to the slot.

In one embodiment, the reference signal generation circuit includes:
a constant temperature crystal oscillator for outputting the first pulse signal;
a first clock generator connected to the constant temperature crystal resonator to obtain the first pulse signal and generate the first reference signal and the second reference signal.

In one embodiment, the clock source circuit includes:
An input end is connected to the reference signal generation circuit via a first cable, an output end is connected to the slot and the clock signal generation circuit, and acquires the first reference signal and calculates jitter with respect to the first reference signal. a first clock chip for removing, synchronizing, and expanding;
An input end is connected to the reference signal generation circuit via a second cable, an output end is connected to the slot and the clock signal generation circuit, and acquires the second reference signal and calculates jitter with respect to the second reference signal. and a second clock chip for performing removal, synchronization, and expansion.

In one embodiment, the first cable and the second cable are of the same length.

In one embodiment, the clock signal generation circuit includes:
a second clock generator connected between the reference signal generation circuit and the slot to obtain the first reference signal and the second reference signal, generate a first clock signal, and transmit it to the slot; The vessel and
a voltage controlled oscillator connected to the second clock generator and configured to output a second pulse signal to the second clock generator.

In one embodiment, the first reference signal and the reference signal are in phase.

In one embodiment, the case has several slots, and the first reference signal and the second reference signal have equal transmission distances from the reference signal generation circuit to any of the slots.

A case,
some slots and
a clock source circuit according to any of the embodiments above, connected to some of the slots.

A multi-case cascade system comprising a plurality of cases as described in the above embodiments, the plurality of cases comprising one master case and several slave cases,
The master case and the slave case share the reference signal generation circuit of the master case.

In one embodiment, the clock source circuit has an input end connected to the reference signal generation circuit via a first cable, an output end connected to the slot and the clock signal generation circuit, and the clock source circuit outputs the first reference signal. a first clock chip for acquiring and performing jitter removal, synchronization, and expansion on the first reference signal; an input end is connected to the reference signal generation circuit via a second cable; a second clock chip connected to the slot and the clock signal generation circuit for acquiring the second reference signal and performing jitter removal, synchronization, and expansion on the second reference signal;
The reference signal generation circuit of the master case is connected to the first clock chip of any of the cases and outputs the first reference signal,
The reference signal generation circuit of the master case is connected to the second clock chip of any of the cases and outputs the second reference signal,
an electrical connection distance between the reference signal generation circuit of the master case and any of the first clock chips; and an electrical connection distance between the reference signal generation circuit of the master case and any of the second clock chips. It is equal to the connection distance.

In one embodiment, the multi-case cascade system further includes a first synchronization buffer and a second synchronization buffer, wherein the first synchronization buffer and the second synchronization buffer are respectively connected to the programmable gate array of the master case. ,
the first synchronization buffers are respectively connected to any of the first clock chips such that the programmable gate array of the master case places any of the first clock chips through the first synchronization buffers;
The second synchronous buffers are respectively connected to any of the second clock chips such that the programmable gate array of the master case places any of the second clock chips through the second synchronous buffers. .

The above clock source circuit is connected to the slot of the case and includes a reference signal generation circuit, a clock signal generation circuit, a programmable gate array, and a synchronization signal generation circuit. When the clock source circuit is operating, the reference signal generation circuit can generate and transmit a first reference signal and a second reference signal to the slot and clock signal generation circuit. The clock signal generation circuit can generate a first clock signal based on the first reference signal and the second reference signal and transmit it to the slot. The programmable gate array can obtain the first reference signal, the second reference signal, and the first clock signal to generate a first trigger signal and a source synchronization signal, and communicate the first trigger signal to the slot. The synchronization signal generation circuit can obtain the source synchronization signal, generate a synchronization signal, and transmit the synchronization signal to the slot. Thereby, the clock source circuit provides the first reference signal, the second reference signal, the first clock signal, the first trigger signal, and the synchronization signal to the slot to realize the function of the clock source board. is possible. The clock source circuit can realize the function of a clock source board depending on the circuit type, and can improve the integration of the case by saving the space occupied by the clock source board.

In order to more clearly explain the technical solutions in the embodiments of the present application or the prior art, the drawings used in the embodiments of the present application or the prior art will be briefly described. It is clear that the attached drawings are only some examples of the present application and that it is possible for a person skilled in the art to derive other drawings from these drawings without expending inventive effort.

FIG. 2 is a schematic structural diagram of a clock source circuit in an embodiment of the present application. FIG. 3 is a schematic structural diagram of a clock source circuit in another embodiment of the present application. FIG. 7 is a schematic structural diagram of a clock source circuit in still another embodiment of the present application. FIG. 2 is a schematic diagram of a circuit configuration of a case in an embodiment of the present application. FIG. 2 is a schematic diagram of the connection relationship of a multi-case cascade system in an embodiment of the present application. FIG. 3 is a schematic diagram of the connection relationship of a multi-case cascade system in another embodiment of the present application.

In order to more clearly understand the above objects, features, and advantages of the present application, specific embodiments of the present application will be described in detail below with reference to the drawings. Numerous specific details are set forth in the following description to provide a thorough understanding of the present application. However, this application can be implemented in many ways other than those described herein, and similar modifications can be made by those skilled in the art without departing from the spirit of this application, and therefore, this application It is not limited to the specific examples disclosed below.

In this specification, the numbers themselves assigned to parts, such as "first", "second", etc., are used only to distinguish the objects being described and do not have any ordering or technical meaning. . The terms "connection" and "coupling" referred to in this application include both direct and indirect connections (coupling), unless otherwise specified. In the description of this application, it should be understood that the terms "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", " Directions or positional relationships such as "bottom", "inside", "outside", "clockwise", "counterclockwise", etc. are shown based on the drawings and are used to facilitate explanation of the present application. This application is for ease of explanation only and is not intended to imply or imply that the devices or elements referred to have a particular orientation or must be constructed or operated in a particular orientation. It should not be construed as limiting.

In this application, unless there is a clear provision or limitation otherwise, the first feature being "above" or "below" the second feature does not mean that the first feature and the second feature may be in direct contact with each other. , the first feature and the second feature may be in indirect contact via an intermediate medium. Furthermore, the fact that the first feature is "above", "above", and "on the top surface" of the second feature means that the first feature is directly above or diagonally above the second feature, or the first feature is located horizontally to the second feature. It may simply indicate that the height is greater than the second feature. The fact that the first feature is “below”, “below”, or “on the underside” of the second feature means that the first feature is directly below or diagonally below the second feature, or the horizontal height of the first feature is It may simply indicate that it is smaller than the second feature.

The present application provides a clock source circuit and a case and multi-case cascade system including the clock source circuit. The clock source circuit can realize the function of a clock source board depending on the circuit type, and can improve the integration of the case by saving the space occupied by the clock source board. In embodiments herein, any connection between two electronic devices or/and circuits refers to an electrical connection. By electrical connection is meant that the connection enables the transmission of electrical signals between two electronic devices or/and circuits.

In one embodiment, the present application provides a clock source circuit 10 that supplies multiple types of clock signals to the slot 22 of the case 20 by being connected to the slot 22 of the case 20, as shown in FIG. The clock source circuit 10 includes a reference signal generation circuit 110, a clock signal generation circuit 120, a programmable gate array 130, and a synchronization signal generation circuit 140.

The reference signal generation circuit 110 is used to generate a first reference signal and a second reference signal. By being connected to the slot 22, the reference signal generation circuit 110 can transmit the generated first reference signal and second reference signal to the slot 22. The first reference signal and the second reference signal are one of the clock signals for providing a reference clock. In embodiments of the present application, the first reference signal and the second reference signal may be pulse signals with different frequencies. For example, the frequency of the first reference signal may be 10 MHz, and the frequency of the second reference signal may be 100 MHz.

Clock signal generation circuit 120 is connected between reference signal generation circuit 110 and slot 22. In other words, the clock signal generation circuit 120 can acquire the first reference signal and the second reference signal generated by the reference signal generation circuit 110 by having its input end connected to the reference signal generation circuit 110. The clock signal generation circuit 120 is used to generate a first clock signal based on the first reference signal and the second reference signal. The first clock signal can be used for accurate timekeeping to provide fast switching LVPECL (Low Voltage Positive Emitter-Couple Logic). The clock signal generation circuit 120 outputs the first clock signal to the slot 22 by having its output end connected to the slot 22 .

The programmable gate array 130 (FPGA: Field-Programmable Gate Array) is connected to the reference signal generation circuit 110 to obtain the first reference signal and the second reference signal generated by the reference signal generation circuit 110. The programmable gate array 130 is further connected to the clock signal generation circuit 120 to obtain the first clock signal generated by the clock signal generation circuit 120. After obtaining the first reference signal, the second reference signal, and the first clock signal, the programmable gate array 130 generates the first trigger signal and the first trigger signal based on the first reference signal, the second reference signal, and the first clock signal. A source synchronization signal can be generated. Here, the first trigger signal is for enabling information transmission and triggering from the programmable gate array 130 to the slot 22. For example, in the embodiment shown in FIG. 1, programmable gate array 130 may send a first trigger signal to slot 22 if it is needed to interact with slot 22. After slot 22 obtains the first trigger signal, it may send a second trigger signal to programmable gate array 130. That is, the second trigger signal is a feedback signal of the first trigger signal. The programmable gate array 130 is further connected to the slot 22 to output the generated first trigger signal to the slot 22 and obtain a second trigger signal fed back by the slot 22.

Synchronous signal generation circuit 140 is connected between programmable gate array 130 and slot 22. In other words, the input terminal of the synchronization signal generation circuit 140 is connected to the programmable gate array 130, so that the synchronization signal generation circuit 140 can obtain the source synchronization signal generated and output by the programmable gate array 130. After acquiring the source synchronization signal, the synchronization signal generation circuit 140 can generate the synchronization signal based on the source synchronization signal. The synchronization signal generation circuit 140 outputs the generated synchronization signal to the slot 22 by having an output end connected to the slot 22 . The synchronization signal may define a phase relationship between the first reference signal and the second reference signal. In the present embodiment, the synchronization signal generation circuit 140 may be an ADCLK954 type clock distributor.

When the clock source circuit 10 of the present application is operating, the reference signal generation circuit 110 can generate a first reference signal and a second reference signal and transmit them to the slot 22 and the clock signal generation circuit 120. The clock signal generation circuit 120 may generate a first clock signal based on the first reference signal and the second reference signal, and may transmit the first clock signal to the slot 22 . Programmable gate array 130 can obtain the first reference signal, the second reference signal, and the first clock signal to generate a first trigger signal and a source synchronization signal, and communicate the first trigger signal to slot 22 . can. The synchronization signal generation circuit 140 can obtain the source synchronization signal, generate a synchronization signal, and transmit the synchronization signal to the slot 22 . As a result, the clock source circuit 10 provides the first reference signal, the second reference signal, the first clock signal, the first trigger signal, and the synchronization signal to the slot 22, and the slot 22 receives the first trigger signal. It is possible to obtain the second trigger signal fed back based on the clock source board and realize the function of the clock source board. The clock source circuit 10 can realize the function of a clock source board depending on the circuit type, and the integration of the case 20 can be improved by saving the space occupied by the clock source board.

In addition, in the above embodiment, in order to facilitate understanding, the slot 22 was introduced to explain the connection method and operation procedure of the clock source circuit 10 of the present application. However, in actual applications, the clock source circuit 10 of the present application may not include the slot 22 of the case 20. In other words, the slot 22 is an environmental element of the clock source circuit 10 of the present application, and whether it is introduced or not should not be understood as a limitation on the protection scope of the clock source circuit 10 of the present application.

In one embodiment, as shown in FIG. 2, in the clock source circuit 10 of the present application, the reference signal generation circuit 110 may include a constant temperature crystal oscillator 112 and a first clock generator 114.

Specifically, the constant temperature crystal oscillator 112 (OCXO: Oven Controlled Crystal Oscillator) is a constant temperature crystal oscillator for outputting a stable first pulse signal. The first pulse signal is for providing a reference to the first clock generator 114.

The first clock generator 114 is connected to the constant temperature crystal oscillator 112 and is used to obtain the first pulse signal and generate the first reference signal and the second reference signal. The first clock generator 114 may include two phase locked loops (PLLs) therein. A first clock generator 114 comprising two phase-locked loops can generate a first reference signal and a second reference signal with the same phase based on the first pulse signal. In the present embodiment, the first clock generator 114 may be a low noise clock generator of the LMK03318 type. The first reference signal has the same frequency as the first pulse signal. The second reference signal may be a differential signal. For example, the constant temperature crystal resonator 112 can output a first pulse signal with a frequency of 10 MHz to the first clock generator 114. The frequency of the first reference signal generated by the first clock generator 114 is 10 MHz, and the frequency of the second reference signal generated by the first clock generator 114 is 100 MHz. The first reference signal has good compatibility. The second reference signal is a high frequency reference clock signal with low jitter and high stability and accuracy. By outputting the first pulse signal from the constant temperature crystal resonator 112 to the first clock generator 114, the output frequency of the first clock generator 114 can be made more accurate and stable.

In one embodiment, still shown in FIG. 2, the clock source circuit 10 of the present application may further include a first clock chip 150 and a second clock chip 160.

Specifically, the first clock chip 150 is connected between the reference signal generation circuit 110 and the slot 22 and between the reference signal generation circuit 110 and the clock signal generation circuit 120. The first reference signal generated at 110 may be used for jitter removal, synchronization, and enhancement. Here, expansion of the first reference signal refers to obtaining a plurality of first reference signals having the same phase, frequency, etc. by copying one first reference signal. When the first reference signal is generated by the reference signal generation circuit 110, the first reference signal is expanded into a plurality of first reference signals via the first clock chip 150 and output to the slot 22 and the clock signal generation circuit 120. Ru.

The second clock chip 160 is also connected between the reference signal generation circuit 110 and the slot 22 and between the reference signal generation circuit 110 and the clock signal generation circuit 120, and is connected to the clock signal generated by the reference signal generation circuit 110. It is used for jitter removal, synchronization, and enhancement for the second reference signal. Here, the extension of the second reference signal refers to obtaining a plurality of second reference signals having the same phase, frequency, etc. by copying one second reference signal. When the second reference signal is generated by the reference signal generation circuit 110, the second reference signal is expanded into a plurality of second reference signals via the second clock chip 160, and outputted to the slot 22 and the clock signal generation circuit 120. Ru.

More specifically, the input end of the first clock chip 150 may be connected to the reference signal generation circuit 110 via the first cable 152; The first clock generator 114 may be connected to the first clock generator 114 via the first clock generator 114 . An output end of the first clock chip 150 may be connected to the slot 22 and the clock signal generation circuit 120. The input end of the second clock chip 160 may be connected to the reference signal generation circuit 110 via the second cable 162, that is, the input end of the second clock chip 160 may be connected to the first clock via the second cable 162. It may be connected to a generator 114. An output end of the second clock chip 160 may be connected to the slot 22 and the clock signal generation circuit 120. In embodiments of the present application, first cable 152 and second cable 162 may be coaxial cables of the same length. By making the first cable 152 and the second cable 162 the same length, it is possible to ensure that there is no delay during transmission of the first reference signal and the second reference signal. In the present embodiment, the first clock chip 150 and the second clock chip 160 may be LMK04808 type clock chips that have jitter removal, synchronization, and extension functions for the clock signal.

It should be understood that in the embodiment shown in FIG. 2, the connections between programmable gate array 130 and reference signal generation circuit 110 and clock signal generation circuit 120 are not shown. According to the description of the embodiments of the present application, the first clock chip 150 may be connected between the reference signal generation circuit 110 and the programmable gate array 130. In other words, the input end of the first clock chip 150 is connected to the reference signal generation circuit 110 through the first cable 152, that is, connected to the first clock generator 114 through the first cable 152. Since the output terminal of the first clock chip 150 is connected to the programmable gate array 130, the first reference signal obtained by the programmable gate array 130 has already undergone jitter removal and synchronization. Similarly, the second clock chip 160 is also connected between the reference signal generation circuit 110 and the programmable gate array 130. In other words, the input end of the second clock chip 160 is connected to the reference signal generation circuit 110 via the second cable 162, that is, connected to the first clock generator 114 via the second cable 162. Since the output terminal of the second clock chip 160 is connected to the programmable gate array 130, the second reference signal obtained by the programmable gate array 130 has already undergone jitter removal and synchronization.

In one embodiment, still shown in FIG. 2, the clock signal generation circuit 120 of the clock source circuit 10 of the present application includes a second clock generator 122 and a voltage controlled oscillator 124.

Specifically, the voltage-controlled oscillator 124 (VCXO: Voltage-Controlled Crystal Oscillator) is a crystal oscillator that controls the output frequency of a crystal resonator using a voltage. In the present embodiment, voltage controlled oscillator 124 is used to output the second pulse signal. The voltage controlled oscillator 124 may output a second pulse signal to the second clock generator 122 by being connected to the second clock generator 122 . The second pulse signal is for providing a reference to the second clock generator 122.

A second clock generator 122 is connected to the voltage controlled oscillator 124 to obtain a second pulse signal. Further, the second clock generator 122 is connected between the reference signal generation circuit 110 and the slot 22 to obtain the first reference signal and the second reference signal. The second clock generator 122 may generate a first clock signal based on the first reference signal, the second reference signal, and the second pulse signal, and may output the first clock signal to the slot 22 . In the present embodiment, the second clock generator 122 may be an HMC7044 type clock generator. In embodiments not shown in FIG. 2, second clock generator 122 may be coupled to programmable gate array 130 to output a first clock signal to programmable gate array 130 in accordance with the description herein. . The first clock signal can be used for accurate timekeeping to provide fast switching LVPECL.

In one embodiment, the case 20 to which the clock source circuit 10 of the present application is applied may have several slots 22. Here, some means one or more integers. In the embodiment of the present application, when the case 20 has several slots 22, the transmission distance of the first reference signal and the second reference signal from the reference signal generation circuit 110 to any one of the slots 22 is equal.

Specifically, if the case 20 has several slots 22, the first reference signal needs to be transmitted from the reference signal generation circuit 110 to each slot 22. The second reference signal also needs to be transmitted from the reference signal generation circuit 110 to each slot 22. In the embodiment of the present application, the transmission distance of the first reference signal from the reference signal generation circuit 110 to each slot 22 is equal, and the transmission distance of the second reference signal from the reference signal generation circuit 110 to each slot 22 is equal. equal.

In one embodiment, as shown in FIG. 3, the clock source circuit 10 of the present application also interacts between the programmable gate array 130 and the slot 22 by a third trigger signal.

Specifically, in embodiments of the present application, when only interaction by the third trigger signal is selected between the programmable gate array 130 and the slot 22, the first reference signal, the second reference signal, and the first clock signal is no longer output to slot 22. At this time, the first reference signal is generated by the reference signal generation circuit 110, expanded by the first clock chip 150, and output to the second clock generator 122 and the programmable gate array 130. The second reference signal is generated by the reference signal generation circuit 110, expanded by the second clock chip 160, and output to the second clock generator 122 and the programmable gate array 130. The second clock generator 122 may generate a first clock signal based on the first reference signal, the second reference signal, and the second pulse signal, and may output the first clock signal to the programmable gate array 130 . The programmable gate array 130 generates an upstream signal based on the first reference signal, the second reference signal, and the first clock signal, and outputs it to the slot 22 . After acquiring the upstream signal, the slot 22 generates a downstream signal and feeds it back to the programmable gate array 130 . In the embodiment shown in FIG. 3, the upstream signal and the downstream signal are collectively expressed as a third trigger signal. The third trigger signal can also achieve some interaction between the programmable gate array 130 and the slot 22. The interaction between the programmable gate array 130 and the slot 22 is faster and more stable when the first trigger signal and the second trigger signal are used rather than the third trigger signal.

It should be noted that when the clock source circuit 10 of the present application is operating, the interaction between the programmable gate array 130 and the slot 22 can be performed only by the first trigger signal and the second trigger signal. On the other hand, the interaction between the programmable gate array 130 and the slot 22 may be performed only by the third trigger signal. Furthermore, the interaction between the programmable gate array 130 and the slot 22 may be performed by a third trigger signal in addition to the first trigger signal and the second trigger signal.

The operation process of the clock source circuit 10 of the present application will be described below from a specific example with reference to FIG.

When the clock source circuit 10 of the present application is operating, the constant temperature crystal oscillator 112 stably outputs the first pulse signal of 10 MHz to provide a reference to the first clock generator 114 and generate the first clock signal. The output frequency of generator 114 can be made more accurate and stable. The first clock generator 114 may be a clock generator of the LMK03318 type with two phase-locked loops. The two phase-locked loops allow the output signal of the first clock generator 114 to have the same phase as the input signal. The first clock generator 114 simultaneously outputs a first reference signal with a frequency of 10 MHz and a second reference signal with a frequency of 100 MHz. Here, the second reference signal is a differential signal, and thereby the noise resistance of the clock source circuit 10 can be improved.

The first reference signal is transmitted to the first clock chip 150 via a first cable 152 . The second reference signal is transmitted to the second clock chip 160 via a second cable 162. The first cable 152 and the second cable 162 are coaxial cables of the same length, thereby ensuring that there is no transmission delay between the first reference signal and the second reference signal. The first clock chip 150 and the second clock chip 160 may be LMK04808 type clock chips.

Case 20 may have several slots 22. After acquiring the first reference signal, the first clock chip 150 removes jitter by performing phase adjustment on the first reference signal. At the same time, the first clock chip 150 synchronizes and extends the first reference signal, thereby dividing the first reference signal into several slots 22 of the case 20, the second clock chip 150, and so on. It may also be communicated to clock generator 122 and programmable gate array 130. After acquiring the second reference signal, the second clock chip 160 removes jitter by performing phase adjustment on the second reference signal. At the same time, the second clock chip 160 synchronizes and extends the second reference signal, thereby dividing the second reference signal into several slots 22 of the case 20 and the second clock chip 160, respectively. It may also be communicated to clock generator 122 and programmable gate array 130.

The first reference signal and the second reference signal communicated to each slot 22 are used to provide a reference clock. Here, the first reference signal is a low jitter reference signal with a frequency of 10 MHz. In the present embodiment, the wiring lengths from the first clock chip 150 to either slot 22 are equal, thereby ensuring that the first reference signal received in each slot 22 is of equal phase. The low frequency first reference signal has good compatibility. The second reference signal is a high frequency reference clock with a frequency of 100 MHz. The phase of the second reference signal and the phase of the first reference signal are precisely aligned. The second reference signal has newer jitter than the first reference signal. Similarly, the wiring lengths from the second clock chip 160 to either slot 22 are equal, thereby ensuring that the second reference signal received in each slot 22 is of equal phase.

The second clock generator 122 receives the first reference signal, the second reference signal, and the second pulse signal from the voltage controlled oscillator 124, generates a first clock signal, and transmits the first clock signal to each slot 22 of the case 20. do. The first clock signal is used for accurate timekeeping to provide fast switching LVPECL. The first clock signal is also communicated to programmable gate array 130. The second clock generator 122 may be an HMC7044 type clock generator.

After acquiring the first reference signal, the second reference signal, and the first clock signal, the programmable gate array 130 generates a high-speed and high-quality trigger signal, that is, a first trigger signal. Programmable gate array 130 transmits a first trigger signal to each slot 22 of case 20 . Upon receiving the first trigger signal, the slot 22 feeds back a second trigger signal to the programmable gate array 130, thereby achieving interaction between the slot 22 and the programmable gate array 130.

After obtaining the first reference signal, the second reference signal, and the first clock signal, the programmable gate array 130 further generates a source synchronization signal. Programmable gate array 130 transmits the source synchronization signal to synchronization signal generation circuit 140. The synchronization signal generation circuit 140 can convert the source synchronization signal into a synchronization signal and transmit it to each slot 22. The synchronization signal may define a phase relationship between the first reference signal and the second reference signal. The synchronization signal generation circuit 140 may be an ADCLK954 type clock distributor.

In one embodiment, the present application further provides a case 20, as shown in FIG. 4, including several slots 22 and a clock source circuit 10 according to any one of the embodiments described above.

Specifically, the clock source circuit 10 is connected to the slot 22. The clock source circuit 10 may include a reference signal generation circuit 110, a clock signal generation circuit 120, a programmable gate array 130, and a synchronization signal generation circuit 140. The reference signal generation circuit 110 is connected to the slot 22 to generate a first reference signal and a second reference signal and transmit them to the slot 22. The clock signal generation circuit 120 is connected between the reference signal generation circuit 110 and the slot 22 to acquire the first reference signal and the second reference signal, generate the first clock signal, and transmit it to the slot 22. used. Programmable gate array 130 is connected to reference signal generation circuit 110 and clock signal generation circuit 120. The programmable gate array 130 is further connected to the slot 22 to obtain a first reference signal, a second reference signal, and a first clock signal to generate a first trigger signal and a source synchronization signal, and to generate a first trigger signal and a source synchronization signal. The signal is transmitted to slot 22. The synchronization signal generation circuit 140 is connected between the programmable gate array 130 and the slot 22 to obtain a source synchronization signal, generate a synchronization signal, and transmit it to the slot 22 .

In one embodiment, the present application further provides a multi-case cascade system 30. The multi-case cascade system 30 includes a plurality of cases 20 such as the embodiments described above. Here, plurality means two or more integers. The multiple cases 20 include one master case 32 and multiple slave cases 34. Here, some means one or more integers. Master case 32 and slave case 34 share reference signal generation circuit 110 of master case 32.

Specifically, for any case 20, the programmable gate array 130 in the case 20 is connected to the reference signal generation circuit 110 of the case 20, and controls the reference signal generation circuit 110 to operate. For this purpose, a command can be issued to the reference signal generation circuit 110. For a multi-case cascade system 30, the programmable gate arrays 130 of multiple cases 20 may be interconnected to allow interaction of information.

Each case 20 may be provided with a dip switch, and the user determines whether the case 20 is to be a master case 32 or a slave case 34 via the dip switch. The programmable gate array 130 of the master case 32 controls the reference signal generation circuit 110 of the master case 32 to operate, and supplies the first reference signal and the second reference signal to the clock signal generation circuit 120 and the programmable gate array 130 of the master case 32. A reference signal is provided, and the clock signal generation circuit 120 and the programmable gate array 130 of the slave case 34 are caused to provide the first reference signal and the second reference signal. The programmable gate array 130 of the slave case 34 controls the reference signal generation circuit 110 of the slave case 34 so as not to operate.

In one embodiment, as shown in FIG. 5, in the multi-case cascade system 30 of the present application, for each case 20, its clock source circuit 10 further includes a first clock chip 150 and a second clock chip 160.

Specifically, the input end of the first clock chip 150 is connected to the reference signal generation circuit 110 via the first cable 152 to obtain the first reference signal, remove jitter from the first reference signal, and remove jitter from the first reference signal. Perform synchronization and expansion. An output end of the first clock chip 150 is connected to the slot 22, the clock signal generation circuit 120, and the programmable gate array 130. The input end of the second clock chip 160 is connected to the reference signal generation circuit 110 via a second cable 162 to obtain a second reference signal, and performs jitter removal, synchronization, and expansion on the second reference signal. I do. An output end of the second clock chip 160 is connected to the slot 22, the clock signal generation circuit 120, and the programmable gate array 130. In other words, in any case 20, the first reference signal obtained by the slot 22, the clock signal generation circuit 120, and the programmable gate array 130 is output by the first clock chip 150. The second reference signal obtained by the slot 22, the clock signal generation circuit 120, and the programmable gate array 130 is output by the second clock chip 160.

As shown in FIG. 5, the reference signal generation circuit 110 includes a constant temperature crystal resonator 112 and a first clock generator 114 connected to the constant temperature crystal resonator 112 and for outputting a first reference signal and a second reference signal. and may include. As a result, the first clock chip 150 of each slave case 34 is connected to the first clock generator 114 of the master case 32, thereby acquiring the first reference signal and transmitting the clock to the slot 22 of the slave case 34. It can be output to the signal generation circuit 120 and the programmable gate array 130. The second clock chip 160 of each slave case 34 is connected to the first clock generator 114 of the master case 32 to obtain the second reference signal and connect the slot 22 of the slave case 34 to the clock signal generation circuit. 120 and a programmable gate array 130. At the same time, the first clock chip 150 of the master case 32 is also connected to the first clock generator 114 of the master case 32 to obtain a first reference signal. A second clock chip 160 of master case 32 is also connected to first clock generator 114 of master case 32 to obtain a second reference signal.

In the embodiment of the present application, the electrical connection distance between the reference signal generation circuit 110 of the master case 32 and any first clock chip 150, and the electrical connection distance between the reference signal generation circuit 110 of the master case 32 and any second clock chip The electrical connection distance with the chip 160 is equal. In other words, the wiring distance between the first clock generator 114 of the master case 32 and any first clock chip 150, and the wiring distance between the first clock generator 114 of the master case 32 and any second clock chip 160. The wiring distance between is equal.

In one embodiment, as shown in FIG. 6, the multi-case cascade system 30 of the present application further includes a first synchronization buffer 170 and a second synchronization buffer 180.

The first synchronous buffer 170 is connected to the programmable gate array 130 of the master case 32 and is controlled by the programmable gate array 130 . The first synchronization buffer 170 is further connected to the first clock chip 150 of any case 20, so that all the first clock chips 150 are arranged so that the first reference signal of each case 20 has the same phase. . The second synchronous buffer 180 is connected to the programmable gate array 130 of the master case 32 and is controlled by the programmable gate array 130 . The second synchronization buffer 180 is further connected to the second clock chip 160 of any case 20, so that all the second clock chips 160 are arranged so that the second reference signal of each case 20 has the same phase. .

Based on the multi-case cascade system 30 of the present application, the present application further provides a control method for the multi-case cascade system 30. The control method is applied to each case 20 in the multi-case cascade system 30 and includes the following steps.

In S100, an input command including either a first input command or a second input command is obtained.

In S210, if the input command is the first input command, the programmable gate array 130 controls the reference signal generation circuit 110 to operate, thereby outputting the first reference signal and the second reference signal.

In S220, if the input command is the second input command, the programmable gate array 130 controls the reference signal generation circuit 110 to stop operating.

Specifically, the input command here may be a control command input by the user via a dip switch. A user can determine whether case 20 is to be designated as master case 32 or slave case 34 by inputting a command via a dip switch. In the embodiment of the present application, the case 20 that has received the first input command is the master case 32, and the case 20 that has received the second input command is the slave case 34. As a result, in the master case 32 that has received the first input command, the programmable gate array 130 controls the reference signal generation circuit 110 to operate, thereby outputting the first reference signal and the second reference signal. In the slave case 34 that receives the second input command, the programmable gate array 130 controls the reference signal generation circuit 110 to stop operating, and acquires the first reference signal and the second reference signal from the master case 32. do.

Further, in step S210, specifically, when the input command is the first input command, the programmable gate array 130 controls the reference signal generation circuit 110 to operate, thereby transmitting the first reference signal to the first clock chip. 150 and outputting a second reference signal to the second clock chip 160.

Specifically, in step S220, when the input command is the second input command, the programmable gate array 130 controls the operation of the reference signal generation circuit 110 to be stopped, and the first clock chip 150 controls the operation of the master case 32. The method includes obtaining a first reference signal and obtaining a second reference signal for the master case 32 by the second clock chip 160 .

Specifically, both the first clock chip 150 and the second clock chip 160 of each case 20 are connected to the reference signal generation circuit 110 of the master case 32. The first clock chip 150 of each case 20 obtains the first reference signal output by the reference signal generation circuit 110 of the master case 32 . The second clock chip 160 of each case 20 obtains the second reference signal output by the reference signal generation circuit 110 of the master case 32 .

Furthermore, the following is included after step S220.

In step S300, if the input command is the first command, the programmable gate array 130 controls the first synchronization buffer 170 to arrange each first clock chip 150, and controls the first synchronization buffer 170 to arrange each second clock chip 160. The second synchronization buffer 180 is controlled.

Specifically, when the case 20 is a master case 32, the programmable gate array 130 of the master case 32 arranges the first synchronization buffer 170 of the master case 32 to arrange the first clock chip 150 of each case 20. Control. The programmable gate array 130 of the master case 32 controls the second synchronous buffer 180 of the master case 32 to position the second clock chip 160 of each case 20 .

Hereinafter, the operation process of the multi-case cascade system 30 of the present application will be described from a specific example with reference to FIG.

Multi-case cascade system 30 includes multiple cases 20 that are cascaded. A dip switch may be provided on the backplane of each case 20, and the user defines the case 20 as a master case 32 or a slave case 34 via the dip switch.

When multi-case cascade system 30 is operating, programmable gate array 130 in each case 20 reads the dip switches to determine whether this case 20 is master case 32 or slave case 34. In the case of the slave case 34, the programmable gate array 130 controls the reference signal generation circuit 110 to stop operating. In the case of the master case 32, the programmable gate array 130 controls the reference signal generation circuit 110 to operate.

When the reference signal generation circuit 110 of the master case 32 operates, it outputs a plurality of first reference signals and second reference signals to the first clock chip 150 and the second clock chip of each case 20 via coaxial cables of the same length. to the chip 160. On the other hand, the programmable gate array 130 of the master case 32 arranges each first clock chip 150 through a first synchronization buffer 170 and arranges each second clock chip 160 through a second synchronization buffer 180. The first clock chip 150 and the second clock chip 160 in each case 20 are operated. When the first clock chip 150 and the second clock chip 160 in each case 20 operate, they output a first reference signal, a second reference signal, a first clock signal, and a first trigger signal to the slot 22 . Obtain a second trigger signal to be fed back.

The technical features of the embodiments described above can be combined arbitrarily, and for the sake of brevity, not all possible combinations of the technical features of the embodiments described above are described. Unless a combination of technical features is inconsistent, it should be considered to be within the scope of this specification.

The above examples merely illustrate some embodiments of the present application, and although the description thereof is specific and detailed, it should not be understood as limiting the scope of the invention of the present application. It should be noted that many variations and improvements are possible to those skilled in the art without departing from the spirit of the present application, and these are included within the protection scope of the present application. Therefore, the scope of protection of this patent shall be defined in the appended claims.

10 clock source circuit 110 reference signal generation circuit 112 constant temperature crystal oscillator 114 first clock generator 120 clock signal generation circuit 122 second clock generator 124 voltage controlled oscillator 130 programmable gate array 140 synchronization signal generation circuit 150 first clock chip 152 First cable 160 Second clock chip 162 Second cable 170 First synchronization buffer 180 Second synchronization buffer 20 Case 22 Slot 30 Multi-case cascade system 32 Master case 34 Slave case

Claims (11)

A clock source circuit used to connect to a slot in the case,
a reference signal generation circuit connected to the slot for generating and transmitting a first reference signal and a second reference signal to the slot;
a clock signal generation circuit connected between the reference signal generation circuit and the slot to obtain the first reference signal and the second reference signal, generate a first clock signal, and transmit it to the slot; and,
connected to the reference signal generation circuit and the clock signal generation circuit, and further connected to the slot, and acquires the first reference signal, the second reference signal, and the first clock signal and transmits them to the slot. a programmable gate array for generating a first trigger signal and a source synchronization signal;
A clock source comprising: a synchronization signal generation circuit connected between the programmable gate array and the slot to obtain the source synchronization signal, generate a synchronization signal, and transmit it to the slot. circuit. The reference signal generation circuit includes:
a constant temperature crystal oscillator for outputting the first pulse signal;
A first clock generator connected to the constant temperature crystal resonator and configured to acquire the first pulse signal and generate the first reference signal and the second reference signal. The clock source circuit according to item 1. An input end is connected to the reference signal generation circuit via a first cable, an output end is connected to the slot and the clock signal generation circuit, and acquires the first reference signal and calculates jitter with respect to the first reference signal. a first clock chip for removing, synchronizing, and expanding;
An input end is connected to the reference signal generation circuit via a second cable, an output end is connected to the slot and the clock signal generation circuit, and acquires the second reference signal and calculates jitter with respect to the second reference signal. The clock source circuit of claim 1, further comprising a second clock chip for performing removal, synchronization, and expansion. 4. The clock source circuit according to claim 3, wherein the first cable and the second cable have the same length. The clock signal generation circuit includes:
a second clock generator connected between the reference signal generation circuit and the slot to obtain the first reference signal and the second reference signal, generate a first clock signal, and transmit it to the slot; The vessel and
2. The clock source circuit according to claim 1, further comprising a voltage controlled oscillator connected to the second clock generator and configured to output a second pulse signal to the second clock generator. 2. The clock source circuit according to claim 1, wherein the first reference signal and the second reference signal have the same phase. 2. The case has several slots, and the first reference signal and the second reference signal have the same transmission distance from the reference signal generation circuit to any of the slots. The clock source circuit described in . some slots and
A case characterized in that it includes a clock source circuit according to any one of claims 1 to 7, connected to several of the slots. The method includes a plurality of cases according to claim 8, the plurality of cases comprising one master case and several slave cases,
The multi-case cascade system is characterized in that the master case and the slave case share a reference signal generation circuit of the master case. The clock source circuit has an input end connected to the reference signal generation circuit via a first cable, an output end connected to the slot and the clock signal generation circuit, acquires the first reference signal, and outputs the first reference signal. a first clock chip for removing jitter, synchronizing, and extending a first reference signal; an input end is connected to the reference signal generation circuit via a second cable; an output end is connected to the slot and the clock signal; a second clock chip connected to a generation circuit for acquiring the second reference signal and performing jitter removal, synchronization, and expansion on the second reference signal;
The reference signal generation circuit of the master case is connected to the first clock chip of any of the cases and outputs the first reference signal,
The reference signal generation circuit of the master case is connected to the second clock chip of any of the cases and outputs the second reference signal,
an electrical connection distance between the reference signal generation circuit of the master case and any of the first clock chips; and an electrical connection distance between the reference signal generation circuit of the master case and any of the second clock chips. The multi-case cascade system according to claim 9, characterized in that the connection distances are equal. further comprising a first synchronization buffer and a second synchronization buffer, the first synchronization buffer and the second synchronization buffer being respectively connected to the programmable gate array of the master case;
the first synchronization buffers are respectively connected to any of the first clock chips such that the programmable gate array of the master case places any of the first clock chips through the first synchronization buffers;
The second synchronous buffers are respectively connected to any of the second clock chips such that the programmable gate array of the master case places any of the second clock chips through the second synchronous buffers. The multi-case cascade system according to claim 10.

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