JP2023508458A - ステージングバッファのアービトレーション - Google Patents

ステージングバッファのアービトレーション Download PDF

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Publication number
JP2023508458A
JP2023508458A JP2022539320A JP2022539320A JP2023508458A JP 2023508458 A JP2023508458 A JP 2023508458A JP 2022539320 A JP2022539320 A JP 2022539320A JP 2022539320 A JP2022539320 A JP 2022539320A JP 2023508458 A JP2023508458 A JP 2023508458A
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Japan
Prior art keywords
memory access
access request
selecting
memory
requests
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Pending
Application number
JP2022539320A
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English (en)
Japanese (ja)
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JP2023508458A5 (https=
Inventor
アール． マグロ ジェームズ
バラクリシュナン ケダーナシュ
エヌ． バルガバ ラビンドラ
シェン グァンハオ
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Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2023508458A publication Critical patent/JP2023508458A/ja
Publication of JP2023508458A5 publication Critical patent/JP2023508458A5/ja
Pending legal-status Critical Current

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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0879—Burst mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0882—Page mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1021—Hit rate improvement

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System (AREA)
JP2022539320A 2019-12-27 2020-12-18 ステージングバッファのアービトレーション Pending JP2023508458A (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/728,152 2019-12-27
US16/728,152 US20210200694A1 (en) 2019-12-27 2019-12-27 Staging buffer arbitration
PCT/US2020/066029 WO2021133675A1 (en) 2019-12-27 2020-12-18 Staging buffer arbitration

Publications (2)

Publication Number Publication Date
JP2023508458A true JP2023508458A (ja) 2023-03-02
JP2023508458A5 JP2023508458A5 (https=) 2023-12-20

Family

ID=74186949

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022539320A Pending JP2023508458A (ja) 2019-12-27 2020-12-18 ステージングバッファのアービトレーション

Country Status (6)

Country Link
US (1) US20210200694A1 (https=)
EP (1) EP4081906A1 (https=)
JP (1) JP2023508458A (https=)
KR (1) KR20220113735A (https=)
CN (1) CN114868116A (https=)
WO (1) WO2021133675A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12541325B2 (en) * 2022-07-14 2026-02-03 Xilinx, Inc. Memory controller with a preprocessor
CN115185866B (zh) * 2022-07-25 2026-02-24 Oppo广东移动通信有限公司 一种内存控制器、访问内存的控制方法及存储设备

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005525652A (ja) * 2002-05-14 2005-08-25 マイクロン テクノロジー インコーポレイテッド アウトオブオーダｄｒａｍシーケンサ
JP2013524388A (ja) * 2010-04-14 2013-06-17 クアルコム，インコーポレイテッド アクセスレイテンシを低減するバスアービトレーション技法
WO2019125563A1 (en) * 2017-12-21 2019-06-27 Advanced Micro Devices, Inc. Scheduling memory requests for a ganged memory device

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US6523098B1 (en) * 1999-12-22 2003-02-18 Intel Corporation Mechanism for efficient low priority write draining
US8271746B1 (en) * 2006-11-03 2012-09-18 Nvidia Corporation Tiering of linear clients
US8001338B2 (en) * 2007-08-21 2011-08-16 Microsoft Corporation Multi-level DRAM controller to manage access to DRAM
US8180975B2 (en) * 2008-02-26 2012-05-15 Microsoft Corporation Controlling interference in shared memory systems using parallelism-aware batch scheduling
US8266389B2 (en) * 2009-04-29 2012-09-11 Advanced Micro Devices, Inc. Hierarchical memory arbitration technique for disparate sources
US8615629B2 (en) * 2010-01-18 2013-12-24 Marvell International Ltd. Access scheduler
GB2533808B (en) * 2014-12-31 2021-08-11 Advanced Risc Mach Ltd An apparatus and method for issuing access requests to a memory controller
US9830086B2 (en) * 2016-03-03 2017-11-28 Samsung Electronics Co., Ltd. Hybrid memory controller for arbitrating access to volatile and non-volatile memories in a hybrid memory group
US10852956B1 (en) * 2016-06-30 2020-12-01 Cadence Design Systems, Inc. Structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and burst reordering
US10402120B2 (en) * 2016-07-15 2019-09-03 Advanced Micro Devices, Inc. Memory controller arbiter with streak and read/write transaction management
US10037150B2 (en) * 2016-07-15 2018-07-31 Advanced Micro Devices, Inc. Memory controller with virtual controller mode
US10152434B2 (en) * 2016-12-20 2018-12-11 Advanced Micro Devices, Inc. Efficient arbitration for memory accesses
US10466904B2 (en) * 2017-03-24 2019-11-05 Western Digital Technologies, Inc. System and method for processing and arbitrating submission and completion queues
US10198369B2 (en) * 2017-03-24 2019-02-05 Advanced Micro Devices, Inc. Dynamic memory remapping to reduce row-buffer conflicts
US10534565B1 (en) * 2018-04-11 2020-01-14 Cadence Design Systems, Inc. Programmable, area-optimized bank group rotation system for memory devices
US12253961B2 (en) * 2019-12-27 2025-03-18 Advanced Micro Devices, Inc. Staging memory access requests

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005525652A (ja) * 2002-05-14 2005-08-25 マイクロン テクノロジー インコーポレイテッド アウトオブオーダｄｒａｍシーケンサ
JP2013524388A (ja) * 2010-04-14 2013-06-17 クアルコム，インコーポレイテッド アクセスレイテンシを低減するバスアービトレーション技法
WO2019125563A1 (en) * 2017-12-21 2019-06-27 Advanced Micro Devices, Inc. Scheduling memory requests for a ganged memory device

Also Published As

Publication number Publication date
US20210200694A1 (en) 2021-07-01
KR20220113735A (ko) 2022-08-16
CN114868116A (zh) 2022-08-05
EP4081906A1 (en) 2022-11-02
WO2021133675A1 (en) 2021-07-01

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