CN114868116A - 暂存缓冲区仲裁 - Google Patents

暂存缓冲区仲裁 Download PDF

Info

Publication number
CN114868116A
CN114868116A CN202080090465.4A CN202080090465A CN114868116A CN 114868116 A CN114868116 A CN 114868116A CN 202080090465 A CN202080090465 A CN 202080090465A CN 114868116 A CN114868116 A CN 114868116A
Authority
CN
China
Prior art keywords
memory access
access request
memory
selecting
page
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202080090465.4A
Other languages
English (en)
Chinese (zh)
Inventor
詹姆斯·R·马格罗
凯达尔纳特·巴拉里斯南
拉温德拉·N·巴尔加瓦
沈冠豪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of CN114868116A publication Critical patent/CN114868116A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1621—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by maintaining request order
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0879—Burst mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G06F12/0882—Page mode
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1673—Details of memory controller using buffers
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1021—Hit rate improvement

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Memory System (AREA)
CN202080090465.4A 2019-12-27 2020-12-18 暂存缓冲区仲裁 Pending CN114868116A (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/728,152 2019-12-27
US16/728,152 US20210200694A1 (en) 2019-12-27 2019-12-27 Staging buffer arbitration
PCT/US2020/066029 WO2021133675A1 (en) 2019-12-27 2020-12-18 Staging buffer arbitration

Publications (1)

Publication Number Publication Date
CN114868116A true CN114868116A (zh) 2022-08-05

Family

ID=74186949

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202080090465.4A Pending CN114868116A (zh) 2019-12-27 2020-12-18 暂存缓冲区仲裁

Country Status (6)

Country Link
US (1) US20210200694A1 (https=)
EP (1) EP4081906A1 (https=)
JP (1) JP2023508458A (https=)
KR (1) KR20220113735A (https=)
CN (1) CN114868116A (https=)
WO (1) WO2021133675A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12541325B2 (en) * 2022-07-14 2026-02-03 Xilinx, Inc. Memory controller with a preprocessor
CN115185866B (zh) * 2022-07-25 2026-02-24 Oppo广东移动通信有限公司 一种内存控制器、访问内存的控制方法及存储设备

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090055580A1 (en) * 2007-08-21 2009-02-26 Microsoft Corporation Multi-level dram controller to manage access to dram
CN107153511A (zh) * 2016-03-03 2017-09-12 三星电子株式会社 存储节点、混合存储器控制器及控制混合存储器组的方法
US20180173649A1 (en) * 2016-12-20 2018-06-21 Advanced Micro Devices, Inc. Efficient arbitration for memory accesses
CN109564556A (zh) * 2016-07-15 2019-04-02 超威半导体公司 具有条纹和读取/写入事务管理的存储器控制器仲裁器
CN110088725A (zh) * 2017-03-24 2019-08-02 西部数据技术公司 用于对提交队列和完成队列进行处理并做出仲裁的系统和方法
CN114846454A (zh) * 2019-12-27 2022-08-02 超威半导体公司 对存储器访问请求进行暂存

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6523098B1 (en) * 1999-12-22 2003-02-18 Intel Corporation Mechanism for efficient low priority write draining
US7149857B2 (en) * 2002-05-14 2006-12-12 Micron Technology, Inc. Out of order DRAM sequencer
US8271746B1 (en) * 2006-11-03 2012-09-18 Nvidia Corporation Tiering of linear clients
US8180975B2 (en) * 2008-02-26 2012-05-15 Microsoft Corporation Controlling interference in shared memory systems using parallelism-aware batch scheduling
US8266389B2 (en) * 2009-04-29 2012-09-11 Advanced Micro Devices, Inc. Hierarchical memory arbitration technique for disparate sources
US8615629B2 (en) * 2010-01-18 2013-12-24 Marvell International Ltd. Access scheduler
US8539129B2 (en) * 2010-04-14 2013-09-17 Qualcomm Incorporated Bus arbitration techniques to reduce access latency
GB2533808B (en) * 2014-12-31 2021-08-11 Advanced Risc Mach Ltd An apparatus and method for issuing access requests to a memory controller
US10852956B1 (en) * 2016-06-30 2020-12-01 Cadence Design Systems, Inc. Structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and burst reordering
US10037150B2 (en) * 2016-07-15 2018-07-31 Advanced Micro Devices, Inc. Memory controller with virtual controller mode
US10198369B2 (en) * 2017-03-24 2019-02-05 Advanced Micro Devices, Inc. Dynamic memory remapping to reduce row-buffer conflicts
US11422707B2 (en) * 2017-12-21 2022-08-23 Advanced Micro Devices, Inc. Scheduling memory requests for a ganged memory device
US10534565B1 (en) * 2018-04-11 2020-01-14 Cadence Design Systems, Inc. Programmable, area-optimized bank group rotation system for memory devices

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090055580A1 (en) * 2007-08-21 2009-02-26 Microsoft Corporation Multi-level dram controller to manage access to dram
CN107153511A (zh) * 2016-03-03 2017-09-12 三星电子株式会社 存储节点、混合存储器控制器及控制混合存储器组的方法
CN109564556A (zh) * 2016-07-15 2019-04-02 超威半导体公司 具有条纹和读取/写入事务管理的存储器控制器仲裁器
US20180173649A1 (en) * 2016-12-20 2018-06-21 Advanced Micro Devices, Inc. Efficient arbitration for memory accesses
CN110088725A (zh) * 2017-03-24 2019-08-02 西部数据技术公司 用于对提交队列和完成队列进行处理并做出仲裁的系统和方法
CN114846454A (zh) * 2019-12-27 2022-08-02 超威半导体公司 对存储器访问请求进行暂存

Also Published As

Publication number Publication date
US20210200694A1 (en) 2021-07-01
JP2023508458A (ja) 2023-03-02
KR20220113735A (ko) 2022-08-16
EP4081906A1 (en) 2022-11-02
WO2021133675A1 (en) 2021-07-01

Similar Documents

Publication Publication Date Title
CN114846454B (zh) 对存储器访问请求进行暂存
US10067883B2 (en) Using an access increment number to control a duration during which tracks remain in cache
US20190056870A1 (en) Reducing solid state Storage device read tail latency
US9858203B2 (en) Page replacement algorithms for use with solid-state drives
US11620219B2 (en) Storage drive dependent track removal in a cache for storage
US9569364B1 (en) Multiple history based micro partition prefetch optimization
US10956042B2 (en) Tiering data compression within a storage system
US9886394B2 (en) Migrating buffer for direct memory access in a computer system
CN114868116A (zh) 暂存缓冲区仲裁
CN114586003B (zh) 使用页级跟踪的加载顺序队列的推测执行
US11055218B2 (en) Apparatus and methods for accelerating tasks during storage caching/tiering in a computing environment
CN115427938B (zh) 使用复合存储器命令的存储器操作
CN119903010B (zh) 访问控制方法、装置及服务器
US11853209B2 (en) Shared memory workloads using existing network fabrics

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20220805

WD01 Invention patent application deemed withdrawn after publication