JP2023508458A5 - - Google Patents
Info
- Publication number
- JP2023508458A5 JP2023508458A5 JP2022539320A JP2022539320A JP2023508458A5 JP 2023508458 A5 JP2023508458 A5 JP 2023508458A5 JP 2022539320 A JP2022539320 A JP 2022539320A JP 2022539320 A JP2022539320 A JP 2022539320A JP 2023508458 A5 JP2023508458 A5 JP 2023508458A5
- Authority
- JP
- Japan
- Prior art keywords
- memory access
- access requests
- selecting
- aforementioned
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/728,152 | 2019-12-27 | ||
| US16/728,152 US20210200694A1 (en) | 2019-12-27 | 2019-12-27 | Staging buffer arbitration |
| PCT/US2020/066029 WO2021133675A1 (en) | 2019-12-27 | 2020-12-18 | Staging buffer arbitration |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2023508458A JP2023508458A (ja) | 2023-03-02 |
| JP2023508458A5 true JP2023508458A5 (https=) | 2023-12-20 |
Family
ID=74186949
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2022539320A Pending JP2023508458A (ja) | 2019-12-27 | 2020-12-18 | ステージングバッファのアービトレーション |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US20210200694A1 (https=) |
| EP (1) | EP4081906A1 (https=) |
| JP (1) | JP2023508458A (https=) |
| KR (1) | KR20220113735A (https=) |
| CN (1) | CN114868116A (https=) |
| WO (1) | WO2021133675A1 (https=) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US12541325B2 (en) * | 2022-07-14 | 2026-02-03 | Xilinx, Inc. | Memory controller with a preprocessor |
| CN115185866B (zh) * | 2022-07-25 | 2026-02-24 | Oppo广东移动通信有限公司 | 一种内存控制器、访问内存的控制方法及存储设备 |
Family Cites Families (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6523098B1 (en) * | 1999-12-22 | 2003-02-18 | Intel Corporation | Mechanism for efficient low priority write draining |
| US7149857B2 (en) * | 2002-05-14 | 2006-12-12 | Micron Technology, Inc. | Out of order DRAM sequencer |
| US8271746B1 (en) * | 2006-11-03 | 2012-09-18 | Nvidia Corporation | Tiering of linear clients |
| US8001338B2 (en) * | 2007-08-21 | 2011-08-16 | Microsoft Corporation | Multi-level DRAM controller to manage access to DRAM |
| US8180975B2 (en) * | 2008-02-26 | 2012-05-15 | Microsoft Corporation | Controlling interference in shared memory systems using parallelism-aware batch scheduling |
| US8266389B2 (en) * | 2009-04-29 | 2012-09-11 | Advanced Micro Devices, Inc. | Hierarchical memory arbitration technique for disparate sources |
| US8615629B2 (en) * | 2010-01-18 | 2013-12-24 | Marvell International Ltd. | Access scheduler |
| US8539129B2 (en) * | 2010-04-14 | 2013-09-17 | Qualcomm Incorporated | Bus arbitration techniques to reduce access latency |
| GB2533808B (en) * | 2014-12-31 | 2021-08-11 | Advanced Risc Mach Ltd | An apparatus and method for issuing access requests to a memory controller |
| US9830086B2 (en) * | 2016-03-03 | 2017-11-28 | Samsung Electronics Co., Ltd. | Hybrid memory controller for arbitrating access to volatile and non-volatile memories in a hybrid memory group |
| US10852956B1 (en) * | 2016-06-30 | 2020-12-01 | Cadence Design Systems, Inc. | Structure of a high-bandwidth-memory command queue of a memory controller with external per-bank refresh and burst reordering |
| US10402120B2 (en) * | 2016-07-15 | 2019-09-03 | Advanced Micro Devices, Inc. | Memory controller arbiter with streak and read/write transaction management |
| US10037150B2 (en) * | 2016-07-15 | 2018-07-31 | Advanced Micro Devices, Inc. | Memory controller with virtual controller mode |
| US10152434B2 (en) * | 2016-12-20 | 2018-12-11 | Advanced Micro Devices, Inc. | Efficient arbitration for memory accesses |
| US10466904B2 (en) * | 2017-03-24 | 2019-11-05 | Western Digital Technologies, Inc. | System and method for processing and arbitrating submission and completion queues |
| US10198369B2 (en) * | 2017-03-24 | 2019-02-05 | Advanced Micro Devices, Inc. | Dynamic memory remapping to reduce row-buffer conflicts |
| US11422707B2 (en) * | 2017-12-21 | 2022-08-23 | Advanced Micro Devices, Inc. | Scheduling memory requests for a ganged memory device |
| US10534565B1 (en) * | 2018-04-11 | 2020-01-14 | Cadence Design Systems, Inc. | Programmable, area-optimized bank group rotation system for memory devices |
| US12253961B2 (en) * | 2019-12-27 | 2025-03-18 | Advanced Micro Devices, Inc. | Staging memory access requests |
-
2019
- 2019-12-27 US US16/728,152 patent/US20210200694A1/en not_active Abandoned
-
2020
- 2020-12-18 EP EP20842489.5A patent/EP4081906A1/en not_active Withdrawn
- 2020-12-18 JP JP2022539320A patent/JP2023508458A/ja active Pending
- 2020-12-18 WO PCT/US2020/066029 patent/WO2021133675A1/en not_active Ceased
- 2020-12-18 CN CN202080090465.4A patent/CN114868116A/zh active Pending
- 2020-12-18 KR KR1020227022686A patent/KR20220113735A/ko not_active Ceased
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