JP2023507997A - セキュリティ関連プロセスのセキュアな実行のための方法 - Google Patents
セキュリティ関連プロセスのセキュアな実行のための方法 Download PDFInfo
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- JP2023507997A JP2023507997A JP2022537502A JP2022537502A JP2023507997A JP 2023507997 A JP2023507997 A JP 2023507997A JP 2022537502 A JP2022537502 A JP 2022537502A JP 2022537502 A JP2022537502 A JP 2022537502A JP 2023507997 A JP2023507997 A JP 2023507997A
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- memory
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- 238000000034 method Methods 0.000 title claims abstract description 54
- 206010000117 Abnormal behaviour Diseases 0.000 claims description 4
- 238000004590 computer program Methods 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 5
- 230000006399 behavior Effects 0.000 description 3
- 238000001514 detection method Methods 0.000 description 3
- 230000002547 anomalous effect Effects 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 241000699670 Mus sp. Species 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/75—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation
- G06F21/755—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by inhibiting the analysis of circuitry or operation with measures against power attack
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/78—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data
- G06F21/79—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure storage of data in semiconductor storage media, e.g. directly-addressable memories
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/14—Protection against unauthorised use of memory or access to memory
- G06F12/1416—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights
- G06F12/1425—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block
- G06F12/1441—Protection against unauthorised use of memory or access to memory by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights the protection being physical, e.g. cell, word, block for a range
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/52—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow
- G06F21/54—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems during program execution, e.g. stack integrity ; Preventing unwanted data erasure; Buffer overflow by adding security routines or objects to programs
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/55—Detecting local intrusion or implementing counter-measures
- G06F21/554—Detecting local intrusion or implementing counter-measures involving event detection and direct action
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Software Systems (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Power Engineering (AREA)
- Storage Device Security (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Read Only Memory (AREA)
Abstract
Description
- 第1のメモリ行を開くことと、
- 前記第1のメモリチャージポンプをチャージすることと、
- 第2のメモリからの前記セキュリティデータに基づいて、セキュリティ関連プロセスの前記第1の操作を行うことと、
- 前記チャージされたチャージポンプを使用して前記開かれた第1のメモリ行内の前記メモリ領域の前記プログラミング操作を行うことと
を含む、方法に関する。
・ NVMプログラミングを準備する操作が実行される構成ステップ(CPU実行)。
・ プログラムされるべき行が開かれる行オープニングステップ。このステップの期間はT1と呼ばれる。
・ 第1のメモリのチャージングポンプがチャージされるポンプチャージングステップ。このステップの期間はT2と呼ばれる。
・ NVMプログラミングがチャージされたチャージポンプを使用して行われるプログラミングステップ。このステップの期間はT3と呼ばれる。
・ プログラムされた行が閉じられる行クロージングステップ。このステップの期間はT4と呼ばれる。
Claims (8)
- システム(100)の第1のメモリ(103)の第1のメモリ行内のメモリ領域の少なくとも第1の操作および引き続くプログラミング操作を含み、前記システム(100)の第2のメモリ(104)に記憶されたセキュリティデータを入力として使用する、セキュリティ関連プロセスを実行するための方法であって、前記第1のメモリが不揮発性メモリであり、前記システムが第1のメモリチャージポンプ(108)を備え、前記方法は、前記セキュリティ関連プロセスの実行がトリガされると、
第1のメモリ行を開くこと(S2)と、
前記第1のメモリチャージポンプをチャージすること(S3)と、
第2のメモリからの前記セキュリティデータに基づいて、セキュリティ関連プロセスの前記第1の操作を行うこと(S4)と、
前記チャージされたチャージポンプを使用して前記開かれた第1のメモリ行内の前記メモリ領域の前記プログラミング操作を行うこと(S5)と
を含む、方法。 - 第1のメモリチャージポンプをチャージすることまたは第1のメモリ行を開くことの前に前記セキュリティデータを第1のメモリから第2のメモリへコピーすること(S1)を含む、請求項1に記載の方法。
- 前記システムが、ハードウェアセキュリティセンサを備え、またはソフトウェア対策を実行するために構成されており、前記プログラミング操作が、前記ハードウェアセキュリティセンサまたは前記ソフトウェア対策により検出されたいくつかの異常な挙動をログする恒久セキュリティカウンタを、前記第1のメモリに書き込むことを含む、請求項1または2に記載の方法。
- 前記第2のメモリ(104)が、キャッシュメモリ、ランダムアクセスメモリ(RAM)、不揮発性メモリ(NVM)または読み出し専用メモリ(ROM)のうちである、請求項1から3のいずれかに記載の方法。
- 前記第1のメモリチャージポンプは、システムの電流消費量の目に見えるスパイクを誘起しないように予め定められた頻度でチャージされる、請求項1から4のいずれかに記載の方法。
- 少なくとも1つのコンピュータのメモリへと直接ロード可能なコンピュータプログラム製品であって、前記製品がコンピュータ上で実行されるときに請求項1から5のいずれか一項に記載の方法のステップを行うためのソフトウェアコード命令を含む、コンピュータプログラム製品。
- 少なくとも1つのプロセッサ(101)、第1のメモリ(103)、第1のメモリチャージポンプ(108)および第2のメモリ(104)を備えるシステム(100)により実行されたときに請求項1から5のいずれか一項に記載の方法のステップを行う実行可能なコンピュータコードを記憶する非一時的なコンピュータ可読媒体。
- 請求項1から5のいずれか一項に記載の方法のステップを行うように構成された、プロセッサ(101)、第1のメモリ(103)、第1のメモリチャージポンプ(108)および第2のメモリ(104)を備えるシステム(100)。
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP19306678.4 | 2019-12-18 | ||
EP19306678.4A EP3839750A1 (en) | 2019-12-18 | 2019-12-18 | Method for secure executing of a security related process |
PCT/EP2020/086662 WO2021122907A1 (en) | 2019-12-18 | 2020-12-17 | Method for secure executing of a security related process |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2023507997A true JP2023507997A (ja) | 2023-02-28 |
JP7383156B2 JP7383156B2 (ja) | 2023-11-17 |
Family
ID=69650517
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2022537502A Active JP7383156B2 (ja) | 2019-12-18 | 2020-12-17 | セキュリティ関連プロセスのセキュアな実行のための方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20230019987A1 (ja) |
EP (2) | EP3839750A1 (ja) |
JP (1) | JP7383156B2 (ja) |
KR (1) | KR20220146422A (ja) |
WO (1) | WO2021122907A1 (ja) |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000112829A (ja) * | 1998-09-30 | 2000-04-21 | Sanyo Electric Co Ltd | 不揮発性メモリのデータ保護装置 |
US20120151608A1 (en) * | 2010-12-14 | 2012-06-14 | Oberthur Technologies | Systems and methods for securing the power supply of command means of a microcircuit card in case of attack |
JP2016004371A (ja) * | 2014-06-16 | 2016-01-12 | 大日本印刷株式会社 | Icチップ、異常検知処理方法、及びプログラム |
US20190050602A1 (en) * | 2017-08-14 | 2019-02-14 | Western Digital Technologies, Inc. | Non-volatile Memory Device With Secure Read |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6216224B1 (en) * | 1998-06-05 | 2001-04-10 | Micron Technology Inc. | Method for read only memory shadowing |
US7613051B2 (en) * | 2007-03-14 | 2009-11-03 | Apple Inc. | Interleaving charge pumps for programmable memories |
US8925098B2 (en) * | 2012-11-15 | 2014-12-30 | Elwha Llc | Data security and access tracking in memory |
US10534554B2 (en) * | 2017-10-13 | 2020-01-14 | Silicon Storage Technology, Inc. | Anti-hacking mechanisms for flash memory device |
US20220269759A1 (en) * | 2021-02-09 | 2022-08-25 | The Trustees Of Princeton University | Devices and methods for smartphone impostor detection using behavioral and environmental data |
KR20230029113A (ko) * | 2021-08-23 | 2023-03-03 | 삼성전자주식회사 | 전자 장치 |
-
2019
- 2019-12-18 EP EP19306678.4A patent/EP3839750A1/en not_active Withdrawn
-
2020
- 2020-12-17 JP JP2022537502A patent/JP7383156B2/ja active Active
- 2020-12-17 US US17/783,686 patent/US20230019987A1/en active Pending
- 2020-12-17 EP EP20823878.2A patent/EP4078425A1/en active Pending
- 2020-12-17 WO PCT/EP2020/086662 patent/WO2021122907A1/en unknown
- 2020-12-17 KR KR1020227024766A patent/KR20220146422A/ko not_active Application Discontinuation
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000112829A (ja) * | 1998-09-30 | 2000-04-21 | Sanyo Electric Co Ltd | 不揮発性メモリのデータ保護装置 |
US20120151608A1 (en) * | 2010-12-14 | 2012-06-14 | Oberthur Technologies | Systems and methods for securing the power supply of command means of a microcircuit card in case of attack |
EP2466528A1 (fr) * | 2010-12-14 | 2012-06-20 | Oberthur Technologies | Sécurisation de l'alimentation de moyens de commande d'une carte à microcircuit en cas d'attaque |
JP2012128860A (ja) * | 2010-12-14 | 2012-07-05 | Oberthur Technologies | 攻撃の場合のマイクロ回路カードの指令手段の電源の安全確保 |
JP2016004371A (ja) * | 2014-06-16 | 2016-01-12 | 大日本印刷株式会社 | Icチップ、異常検知処理方法、及びプログラム |
US20190050602A1 (en) * | 2017-08-14 | 2019-02-14 | Western Digital Technologies, Inc. | Non-volatile Memory Device With Secure Read |
Also Published As
Publication number | Publication date |
---|---|
US20230019987A1 (en) | 2023-01-19 |
WO2021122907A1 (en) | 2021-06-24 |
JP7383156B2 (ja) | 2023-11-17 |
EP4078425A1 (en) | 2022-10-26 |
KR20220146422A (ko) | 2022-11-01 |
EP3839750A1 (en) | 2021-06-23 |
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