JP2023505783A5 - - Google Patents

Info

Publication number
JP2023505783A5
JP2023505783A5 JP2022534186A JP2022534186A JP2023505783A5 JP 2023505783 A5 JP2023505783 A5 JP 2023505783A5 JP 2022534186 A JP2022534186 A JP 2022534186A JP 2022534186 A JP2022534186 A JP 2022534186A JP 2023505783 A5 JP2023505783 A5 JP 2023505783A5
Authority
JP
Japan
Prior art keywords
packet
input packet
input
output
gpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2022534186A
Other languages
English (en)
Japanese (ja)
Other versions
JP7528217B2 (ja
JP2023505783A (ja
Filing date
Publication date
Priority claimed from US16/713,472 external-priority patent/US11210757B2/en
Application filed filed Critical
Publication of JP2023505783A publication Critical patent/JP2023505783A/ja
Publication of JP2023505783A5 publication Critical patent/JP2023505783A5/ja
Application granted granted Critical
Publication of JP7528217B2 publication Critical patent/JP7528217B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2022534186A 2019-12-13 2020-12-09 Ｇｐｕパケット集約システム Active JP7528217B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/713,472 2019-12-13
US16/713,472 US11210757B2 (en) 2019-12-13 2019-12-13 GPU packet aggregation system
PCT/US2020/063923 WO2021119072A1 (en) 2019-12-13 2020-12-09 Gpu packet aggregation system

Publications (3)

Publication Number Publication Date
JP2023505783A JP2023505783A (ja) 2023-02-13
JP2023505783A5 true JP2023505783A5 (https=) 2023-11-28
JP7528217B2 JP7528217B2 (ja) 2024-08-05

Family

ID=76316977

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2022534186A Active JP7528217B2 (ja) 2019-12-13 2020-12-09 Ｇｐｕパケット集約システム

Country Status (6)

Country Link
US (1) US11210757B2 (https=)
EP (1) EP4073639B1 (https=)
JP (1) JP7528217B2 (https=)
KR (1) KR102709341B1 (https=)
CN (1) CN114902181A (https=)
WO (1) WO2021119072A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12106112B2 (en) * 2020-12-03 2024-10-01 Intel Corporation Methods and apparatus to generate graphics processing unit long instruction traces
CN113626369B (zh) * 2021-08-14 2023-05-26 苏州浪潮智能科技有限公司 一种多节点集群环形通信的方法、装置、设备及可读介质

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100628619B1 (ko) * 2000-07-10 2006-09-26 마쯔시다덴기산교 가부시키가이샤 복수의 디코드 장치 및 방법
WO2005053216A2 (en) * 2003-11-25 2005-06-09 Dg2L Technologies Methods and systems for reliable distribution of media over a network
US7209139B1 (en) * 2005-01-07 2007-04-24 Electronic Arts Efficient rendering of similar objects in a three-dimensional graphics engine
US7839876B1 (en) 2006-01-25 2010-11-23 Marvell International Ltd. Packet aggregation
CN101471826B (zh) * 2007-12-27 2012-12-12 华为技术有限公司 命令行接口的测试方法及装置
US8374986B2 (en) 2008-05-15 2013-02-12 Exegy Incorporated Method and system for accelerated stream processing
JP2010055214A (ja) 2008-08-26 2010-03-11 Sanyo Electric Co Ltd データ処理装置
EP2596470A1 (en) * 2010-07-19 2013-05-29 Advanced Micro Devices, Inc. Data processing using on-chip memory in multiple processing units
CN102323917B (zh) * 2011-09-06 2013-05-15 中国人民解放军国防科学技术大学 一种基于共享内存实现多进程共享gpu的方法
US20130155077A1 (en) * 2011-12-14 2013-06-20 Advanced Micro Devices, Inc. Policies for Shader Resource Allocation in a Shader Core
US20130162661A1 (en) * 2011-12-21 2013-06-27 Nvidia Corporation System and method for long running compute using buffers as timeslices
US9509616B1 (en) * 2014-11-24 2016-11-29 Amazon Technologies, Inc. Congestion sensitive path-balancing
KR102287402B1 (ko) * 2015-03-23 2021-08-06 삼성전자주식회사 버스 인터페이스 장치, 이를 포함하는 반도체 집적회로 장치 및 상기 장치의 동작 방법
US9830731B2 (en) 2015-04-01 2017-11-28 Mediatek Inc. Methods of a graphics-processing unit for tile-based rendering of a display area and graphics-processing apparatus
US10320695B2 (en) 2015-05-29 2019-06-11 Advanced Micro Devices, Inc. Message aggregation, combining and compression for efficient data communications in GPU-based clusters
US20170300361A1 (en) * 2016-04-15 2017-10-19 Intel Corporation Employing out of order queues for better gpu utilization
JP7100624B2 (ja) * 2016-08-29 2022-07-13 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 優先プリミティブバッチのビニング及びソートを用いたハイブリッドレンダリング
US10572258B2 (en) * 2017-04-01 2020-02-25 Intel Corporation Transitionary pre-emption for virtual reality related contexts
CN110223216B (zh) * 2019-06-11 2023-01-17 西安芯瞳半导体技术有限公司 一种基于并行plb的数据处理方法、装置及计算机存储介质
CN110415161B (zh) * 2019-07-19 2023-06-27 龙芯中科(合肥)技术有限公司 图形处理方法、装置、设备及存储介质

Similar Documents

Publication Publication Date Title
US8554968B1 (en) Interrupt technique for a nonvolatile memory controller
US7953915B2 (en) Interrupt dispatching method in multi-core environment and multi-core processor
CN107046508B (zh) 报文接收方法及网络设备
US8843663B2 (en) Data transmission device and method for merging multiple commands
CN110442463B (zh) Tee系统中的数据传输方法和装置
JP2010512577A5 (https=)
JPH0836877A (ja) キュー装置
WO2014082421A1 (zh) 一种众核处理器进程间相互通信的方法、装置及系统
JP2009540681A (ja) データ通信フロー制御の装置および方法
JP2023505783A5 (https=)
JP2022518340A5 (https=)
JP2015225574A (ja) 制御装置、制御方法及びプログラム
CN104380272A (zh) 用于中断结合的装置和方法
EP3585017A2 (en) Technologies for providing adaptive polling of packet queues
CN104270287B (zh) 一种报文乱序检测方法及装置
US9467526B2 (en) Network communication using intermediation processor
US11550694B2 (en) Packet backpressure detection method, apparatus, and device
CN102750245A (zh) 报文接收方法、报文接收模块、装置及系统
CN109800202B (zh) 一种基于pcie的数据传输系统、方法及装置
CN102521177B (zh) 中断处理方法及装置、中央处理器以及处理设备
JP7528217B2 (ja) Ｇｐｕパケット集約システム
CN115237349A (zh) 数据读写控制方法、控制装置、计算机存储介质和电子设备
US8006006B2 (en) System and method for aggregating transmit completion interrupts
US20210297510A1 (en) Efficient packet processing for express data paths
CN105099932B (zh) 基于直通转发技术的调度方法及装置