KR102709341B1 - Gpu 패킷 집계 시스템 - Google Patents

Gpu 패킷 집계 시스템 Download PDF

Info

Publication number
KR102709341B1
KR102709341B1 KR1020227019998A KR20227019998A KR102709341B1 KR 102709341 B1 KR102709341 B1 KR 102709341B1 KR 1020227019998 A KR1020227019998 A KR 1020227019998A KR 20227019998 A KR20227019998 A KR 20227019998A KR 102709341 B1 KR102709341 B1 KR 102709341B1
Authority
KR
South Korea
Prior art keywords
packet
output
input
input packet
gpu
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020227019998A
Other languages
English (en)
Korean (ko)
Other versions
KR20220113710A (ko
Inventor
토드 마틴
태드 리트윌러
니샨크 파닥
만게쉬 피. 니자슈어
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20220113710A publication Critical patent/KR20220113710A/ko
Application granted granted Critical
Publication of KR102709341B1 publication Critical patent/KR102709341B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00General purpose image data processing
    • G06T1/20Processor architectures; Processor configuration, e.g. pipelining
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/16Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163Interprocessor communication
    • G06F15/173Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
    • G06F15/17337Direct connection machines, e.g. completely connected computers, point to point communication networks
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L47/00Traffic control in data switching networks
    • H04L47/50Queue scheduling
    • H04L47/62Queue scheduling characterised by scheduling criteria
    • H04L47/625Queue scheduling characterised by scheduling criteria for service slots or service orders
    • H04L47/6255Queue scheduling characterised by scheduling criteria for service slots or service orders queue load conditions, e.g. longest queue first
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/90Buffering arrangements
    • H04L49/9057Arrangements for supporting packet reassembly or resequencing
    • GPHYSICS
    • G06COMPUTING OR CALCULATING; COUNTING
    • G06TIMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T2200/00Indexing scheme for image data processing or generation, in general
    • G06T2200/28Indexing scheme for image data processing or generation, in general involving image processing hardware
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L2212/00Encapsulation of packets

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Mathematical Physics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
KR1020227019998A 2019-12-13 2020-12-09 Gpu 패킷 집계 시스템 Active KR102709341B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/713,472 2019-12-13
US16/713,472 US11210757B2 (en) 2019-12-13 2019-12-13 GPU packet aggregation system
PCT/US2020/063923 WO2021119072A1 (en) 2019-12-13 2020-12-09 Gpu packet aggregation system

Publications (2)

Publication Number Publication Date
KR20220113710A KR20220113710A (ko) 2022-08-16
KR102709341B1 true KR102709341B1 (ko) 2024-09-25

Family

ID=76316977

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020227019998A Active KR102709341B1 (ko) 2019-12-13 2020-12-09 Gpu 패킷 집계 시스템

Country Status (6)

Country Link
US (1) US11210757B2 (https=)
EP (1) EP4073639B1 (https=)
JP (1) JP7528217B2 (https=)
KR (1) KR102709341B1 (https=)
CN (1) CN114902181A (https=)
WO (1) WO2021119072A1 (https=)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12106112B2 (en) * 2020-12-03 2024-10-01 Intel Corporation Methods and apparatus to generate graphics processing unit long instruction traces
CN113626369B (zh) * 2021-08-14 2023-05-26 苏州浪潮智能科技有限公司 一种多节点集群环形通信的方法、装置、设备及可读介质

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015502618A (ja) 2011-12-14 2015-01-22 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドAdvanced Micro Devices Incorporated シェーダコアにおけるシェーダリソース割当てのポリシー
US20160379336A1 (en) * 2015-04-01 2016-12-29 Mediatek Inc. Methods of a graphics-processing unit for tile-based rendering of a display area and graphics-processing apparatus

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100628619B1 (ko) * 2000-07-10 2006-09-26 마쯔시다덴기산교 가부시키가이샤 복수의 디코드 장치 및 방법
WO2005053216A2 (en) * 2003-11-25 2005-06-09 Dg2L Technologies Methods and systems for reliable distribution of media over a network
US7209139B1 (en) * 2005-01-07 2007-04-24 Electronic Arts Efficient rendering of similar objects in a three-dimensional graphics engine
US7839876B1 (en) 2006-01-25 2010-11-23 Marvell International Ltd. Packet aggregation
CN101471826B (zh) * 2007-12-27 2012-12-12 华为技术有限公司 命令行接口的测试方法及装置
US8374986B2 (en) 2008-05-15 2013-02-12 Exegy Incorporated Method and system for accelerated stream processing
JP2010055214A (ja) 2008-08-26 2010-03-11 Sanyo Electric Co Ltd データ処理装置
EP2596470A1 (en) * 2010-07-19 2013-05-29 Advanced Micro Devices, Inc. Data processing using on-chip memory in multiple processing units
CN102323917B (zh) * 2011-09-06 2013-05-15 中国人民解放军国防科学技术大学 一种基于共享内存实现多进程共享gpu的方法
US20130162661A1 (en) * 2011-12-21 2013-06-27 Nvidia Corporation System and method for long running compute using buffers as timeslices
US9509616B1 (en) * 2014-11-24 2016-11-29 Amazon Technologies, Inc. Congestion sensitive path-balancing
KR102287402B1 (ko) * 2015-03-23 2021-08-06 삼성전자주식회사 버스 인터페이스 장치, 이를 포함하는 반도체 집적회로 장치 및 상기 장치의 동작 방법
US10320695B2 (en) 2015-05-29 2019-06-11 Advanced Micro Devices, Inc. Message aggregation, combining and compression for efficient data communications in GPU-based clusters
US20170300361A1 (en) * 2016-04-15 2017-10-19 Intel Corporation Employing out of order queues for better gpu utilization
JP7100624B2 (ja) * 2016-08-29 2022-07-13 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッド 優先プリミティブバッチのビニング及びソートを用いたハイブリッドレンダリング
US10572258B2 (en) * 2017-04-01 2020-02-25 Intel Corporation Transitionary pre-emption for virtual reality related contexts
CN110223216B (zh) * 2019-06-11 2023-01-17 西安芯瞳半导体技术有限公司 一种基于并行plb的数据处理方法、装置及计算机存储介质
CN110415161B (zh) * 2019-07-19 2023-06-27 龙芯中科(合肥)技术有限公司 图形处理方法、装置、设备及存储介质

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015502618A (ja) 2011-12-14 2015-01-22 アドバンスト・マイクロ・ディバイシズ・インコーポレイテッドAdvanced Micro Devices Incorporated シェーダコアにおけるシェーダリソース割当てのポリシー
US20160379336A1 (en) * 2015-04-01 2016-12-29 Mediatek Inc. Methods of a graphics-processing unit for tile-based rendering of a display area and graphics-processing apparatus

Also Published As

Publication number Publication date
JP7528217B2 (ja) 2024-08-05
EP4073639A4 (en) 2024-01-10
US20210183004A1 (en) 2021-06-17
CN114902181A (zh) 2022-08-12
WO2021119072A1 (en) 2021-06-17
EP4073639A1 (en) 2022-10-19
JP2023505783A (ja) 2023-02-13
US11210757B2 (en) 2021-12-28
KR20220113710A (ko) 2022-08-16
EP4073639B1 (en) 2026-03-04

Similar Documents

Publication Publication Date Title
US9413683B2 (en) Managing resources in a distributed system using dynamic clusters
US10198377B2 (en) Virtual machine state replication using DMA write records
CN103019962B (zh) 数据缓存处理方法、装置以及系统
US8615759B2 (en) Methods and apparatus for data center management independent of hypervisor platform
CN110609730B (zh) 一种实现虚拟处理器间中断透传的方法及设备
CN103370691A (zh) 管理缓冲器溢出状况
KR102061466B1 (ko) 메모리 관리를 위한 보존 가비지 콜렉팅 및 정수 태깅 기법
KR102709341B1 (ko) Gpu 패킷 집계 시스템
US10216517B2 (en) Clearing specified blocks of main storage
US12050927B2 (en) Techniques for concurrently supporting virtual NUMA and CPU/memory hot-add in a virtual machine
CN105446653A (zh) 一种数据合并方法和设备
CN103093005A (zh) 一种遥信数据处理方法和装置
CN108156208A (zh) 一种应用程序数据的发布方法、装置和系统
CN104104705A (zh) 分布式存储系统的接入方法和设备
CN109753338B (zh) 虚拟gpu使用率的检测方法和装置
CN107391672B (zh) 数据的读写方法及消息化的分布式文件系统
JP7306966B2 (ja) 平均オブジェクト参照に基づいた、コピー・ガベージ・コレクションのためのワーク・スティーリングにおけるスピン・カウントの削減
US20140325508A1 (en) Pausing virtual machines using api signaling
CN108021448B (zh) 一种内核空间的优化方法及装置
CN104331322B (zh) 一种进程迁移方法和装置
WO2018173300A1 (ja) I/o制御方法およびi/o制御システム
WO2022107346A1 (ja) データ処理装置、プログラム、システム、及びデータ処理方法
US20180060118A1 (en) Method and system for processing data
JP2017156824A (ja) 情報処理システム及びプログラム
JP2014182744A (ja) ディスク制御装置およびディスクの減設方法、ストレージシステム、並びにコンピュータ・プログラム

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PA0302 Request for accelerated examination

St.27 status event code: A-1-2-D10-D17-exm-PA0302

St.27 status event code: A-1-2-D10-D16-exm-PA0302

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601