JP2023184327A - Computer - Google Patents

Abstract

To update the configuration of an internal logic circuit of a PLD without causing power interruption of a computer.SOLUTION: A computer 10 includes a PLD30 having a memory 32, and a power supply section 40. The memory 32 stores a first sequence of turning on power of the computer 10 again after turning off the power of the computer 10, and the power supply section 40 supplies power to the computer 10 according to control from the PLD30 based on the first sequence. The PLD30 determines whether or not the power of the computer 10 is turned on when the configuration of an internal logic circuit of the PLD30 is updated, causes the power supply section 40 to execute processing in accordance with the first sequence when the power of the computer 10 is not turned on, and does not cause the power supply section 40 to execute the processing in accordance with the first sequence when the power of the computer 10 is turned on.SELECTED DRAWING: Figure 1

Description

TECHNICAL FIELD This disclosure relates to computers.

Some computers are equipped with a programmable logic device (PLD) in which the PLD controls the power supply of the computer.

Japanese Patent Application Publication No. 2001-290758 Japanese Patent Application Publication No. 2015-142361 Japanese Patent Application Publication No. 2020-109553

In computers where the PLD controls the power supply, if the configuration of the PLD's internal logic circuit is updated while the computer is powered on, the computer will be powered off, so the configuration of the PLD's internal logic circuit must be updated. When this happens, the computer stops working.

Therefore, the present disclosure proposes a technique that can update the configuration of the internal logic circuit of a PLD without powering off the computer.

A computer according to the present disclosure includes a programmable logic device having a memory and a power supply section. The memory stores a first sequence for powering down and then powering the computer back on. The power supply unit supplies power to the computer according to control from the programmable logic device based on the first sequence. The programmable logic device determines whether the computer is powered on when the configuration of the internal logic circuit of the programmable logic device is updated. The programmable logic device causes the power supply unit to execute processing according to the first sequence when the power is not turned on, while supplying the power when the power is turned on. prevent the unit from executing the processing according to the first sequence.

According to the present disclosure, the configuration of the internal logic circuit of a PLD can be updated without powering off the computer.

FIG. 1 is a diagram illustrating an example configuration of a computer according to a first embodiment of the present disclosure. FIG. 2 is a flowchart illustrating an example of a processing procedure in a computer according to the first embodiment of the present disclosure. FIG. 3 is an example of a timing chart in the computer according to the first embodiment of the present disclosure. FIG. 4 is a flowchart illustrating an example of a processing procedure in a computer according to a second embodiment of the present disclosure. FIG. 5 is an example of a timing chart in the computer according to the second embodiment of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described based on the drawings. In the following embodiments, the same configurations and steps that perform the same processing are denoted by the same reference numerals.

[Example 1]
<Computer configuration>
FIG. 1 is a diagram illustrating an example configuration of a computer according to a first embodiment of the present disclosure. In FIG. 1, a computer 10 includes a CPU (Central Processing Unit) 20, a PLD 30, a power supply section 40, a controlled device 50, a pull-up power source with voltages V1 and V2, and pull-up resistors R1 and R2. have The PLD 30 includes a control section 31, a memory 32, and buffers 33 and 34. Examples of PLDs include SPLD (Simple PLD), CPLD (Complex PLD), and FPGA (Field Programmable Gate Array).

A control sequence is stored in the memory 32 in advance. The control sequence includes a sequence (hereinafter sometimes referred to as a "first sequence") of turning off the power of the computer 10 and then turning on the power of the computer 10 again. The control unit 31 outputs a high level power control signal PCS (hereinafter sometimes referred to as "High level PCS") and a low level power control signal PCS (hereinafter referred to as "Low level PCS") based on the first sequence. The power supply unit 40 is controlled by outputting the following: The power supply section 40 supplies power to the computer 10 under control from the control section 31 . When the power control signal PCS input to the power supply unit 40 is at High level PCS, the power supply unit 40 supplies power to the computer 10, so while the computer 10 is powered on, the power supply unit 40 When the input power control signal PCS is at a low level PCS, the power supply unit 40 does not supply power to the computer 10, so the power of the computer 10 is turned off. The first sequence stipulates that the control unit 31 outputs the High level PCS after outputting the Low level PCS, and the control unit 31 outputs the power control signal PCS to the outside of the PLD 30 in accordance with the first sequence. Then, the power of the computer 10 is once turned off and then turned on again.

A power source for the PLD 30 is prepared separately from the power source for the computer 10, and the PLD 30 can operate even when the computer 10 is not powered on.

The controlled device 50 is restarted based on the reset signal RS. In addition to the first sequence, the control sequences stored in the memory 32 further include a sequence (hereinafter sometimes referred to as a "second sequence") for controlling a plurality of reset signals RS. The control unit 31 generates a high level reset signal RS (hereinafter sometimes referred to as "High level RS") and a low level reset signal RS (hereinafter referred to as "Low level RS") based on the second sequence. The control target device 50 is controlled by outputting the following. When the reset signal RS input to the controlled device 50 is at High level RS, the controlled device 50 is not restarted and the activated state of the controlled device 50 is maintained; When the reset signal RS is at a low level RS, the controlled device 50 is restarted. The second sequence stipulates that the control unit 31 outputs the High level RS after outputting the Low level RS, and the control unit 31 outputs the reset signal RS to the outside of the PLD 30 according to the second sequence. , the controlled device 50 is restarted.

Further, the control unit 31 controls the buffers 33 and 34, and sets the buffers 33 and 34 to either a high impedance state or a low impedance state. When the high impedance control signal HCS is output from the control unit 31 to the buffers 33 and 34, the high impedance of the buffers 33 and 34 is enabled, so the buffers 33 and 34 are in a high impedance state, while the control signal HCS is output from the control unit 31 When the high impedance control signal HCS is not output to the buffers 33 and 34, the high impedance of the buffers 33 and 34 is disabled, so the buffers 33 and 34 enter a low impedance state.

When the buffer 33 is in a low impedance state, the control section 31 and the power supply section 40 are electrically connected, so that the power control signal PCS output from the control section 31 is input to the power supply section 40 . On the other hand, when the buffer 33 is in a high impedance state, the power control signal PCS output from the control unit 31 is blocked by the buffer 33, so that the power control signal input to the power supply unit 40 is not transmitted outside the PLD 30. PCS no longer exists.

Therefore, by applying the voltage V1 of the pull-up power supply to the input of the power supply unit 40 via the pull-up resistor R1, the buffer 33 is in a high impedance state and the power supply control signal PCS input to the power supply unit 40 is Even when no longer exists, the input level of the power supply unit 40 is maintained at High level. Therefore, when the buffer 33 is in a high impedance state, the power supply from the power supply unit 40 to the computer 10 is maintained, and the computer 10 remains powered on. When power is not being supplied to the computer 10, the pull-up power supply V1 is not turned on, so the input level of the power supply unit 40 is at Low level.

Furthermore, when the buffer 34 is in a low impedance state, the control section 31 and the controlled device 50 are electrically connected, so that the reset signal RS output from the control section 31 is input to the controlled device 50. On the other hand, when the buffer 34 is in a high impedance state, the reset signal RS output from the control unit 31 is blocked by the buffer 34, so that the reset signal RS input to the controlled device 50 is not output outside the PLD 30. cease to exist.

Therefore, by applying the voltage V2 of the pull-up power supply to the input of the controlled device 50 via the pull-up resistor R2, the control signal RS input to the controlled device 50 while the buffer 34 is in a high impedance state is Even when the controlled device 50 ceases to exist, the input level of the controlled device 50 is maintained at High level. Therefore, when the buffer 34 is in a high impedance state, the controlled device 50 is not restarted, and the controlled device 50 remains activated. When power is not being supplied to the computer 10, the pull-up power supply V2 is not turned on, so the input level of the controlled device 50 is at Low level.

Further, the CPU 20 updates the configuration of the internal logic circuit of the PLD 30 by updating the settings of the control unit 31.

The power supply section 40 sends a signal (hereinafter referred to as a "power state signal") indicating whether or not the power supply section 40 is supplying power to the computer 10, that is, whether or not the computer 10 is powered on. ”) is output to the control unit 31.

The control unit 31 determines whether the computer 10 is powered on based on the power state signal PSS when the configuration of the internal logic circuit of the PLD 30 is updated by the CPU 20.

Then, when the computer 10 is not powered on, the control unit 31 causes the power supply unit 40 to execute processing according to the first sequence, while when the computer 10 is powered on, the The supply unit 40 is not caused to perform processing according to the first sequence. Further, the control unit 31 does not restart the controlled device 50 when the computer 10 is not powered on, but restarts the controlled device 50 when the computer 10 is powered on. .

<Processing procedure on computer>
FIG. 2 is a flowchart illustrating an example of a processing procedure in a computer according to the first embodiment of the present disclosure. The flowchart shown in FIG. 2 is started when the configuration of the internal logic circuit of the PLD 30 is updated by the CPU 20.

In step S100, the control unit 31 outputs the high impedance control signal HCS to the buffers 33 and 34 to enable the high impedance of the buffers 33 and 34. As a result, in step S100, the buffers 33 and 34 enter a high impedance state, so that the power supply control signal PCS output from the control section 31 is cut off by the buffer 33, and the reset signal RS output from the control section 31 is cut off. It is blocked by buffer 34.

Next, in step S105, the control unit 31 determines whether the computer 10 is powered on based on the power state signal PSS. When the computer 10 is powered on (step S105: Yes), the process proceeds to step S110, and when the computer 10 is not powered on (step S105: No), the process proceeds to step S120.

In step S110, the control unit 31 executes the control sequence stored in the memory 32. Here, when the control sequence is executed in step S110, since the buffers 33 and 34 are in a high impedance state, the first sequence is executed within the PLD 30 while the output from the control section 31 to the power supply section 40 is cut off. When the execution is completed, the execution of the second sequence is completed within the PLD 30 with the output from the control unit 31 to the controlled device 50 being cut off. In this way, when the computer 10 is powered on (step S105: Yes), the control unit 31 controls the PLD 30 while the output from the control unit 31 to the power supply unit 40 is cut off (step S100). By completing the execution of the first sequence, the power supply unit 40 is not caused to execute the process according to the first sequence. In addition, when the computer 10 is powered on (step S105: Yes), the control unit 31 controls the control unit 31 in the PLD 30 while the output from the control unit 31 to the controlled device 50 is cut off (step S100). By completing the execution of the second sequence, the controlled device 50 is not restarted.

After the process in step S110 is completed, in step S115, the control unit 31 stops outputting the high impedance control signal HCS to the buffers 33 and 34 to disable the high impedance of the buffers 33 and 34. As a result, in step S115, the buffers 33 and 34 enter a low impedance state, so that the power control signal PCS output from the control section 31 is input to the power supply section 40, and the power control signal PCS is output from the control section 31. The reset signal RS is now input to the controlled device 50. After the process of step S115, the flowchart shown in FIG. 2 ends.

On the other hand, in step S120, the control unit 31 stops outputting the high impedance control signal HCS to the buffers 33 and 34 to disable the high impedance of the buffers 33 and 34.

After the high impedance of the buffers 33 and 34 is disabled in step S120, the control unit 31 executes the control sequence stored in the memory 32 in step S125. After the process of step S125, the flowchart shown in FIG. 2 ends.

<Timing chart in computer>
FIG. 3 is an example of a timing chart in the computer according to the first embodiment of the present disclosure. Hereinafter, a timing chart for when the computer 10 is not powered on (when the power is not turned on) and a timing chart when the computer 10 is powered on (when the power is turned on) will be explained separately.

<When power is not turned on>
When the power is not turned on in FIG. 3, when updating of the configuration of the internal logic circuit of the PLD 30 is started (PLD: start of setting update), the control unit 31 enables high impedance of the buffers 33 and 34 (step S100). .

Next, at time t11, since the computer 10 is not powered on (step S105: No), the control unit 31 disables the high impedance of the buffers 33 and 34 (step S120). While the high impedance of the buffers 33 and 34 is enabled, the power supply control signal PCS and the reset signal RS do not appear outside the PLD 30. Since the pull-up power supplies V1 and V2 are not turned on, the input level of the power supply unit 40 and the input level of the controlled device 50 are at Low level.

Next, at time t12, the control unit 31 starts executing the control sequence while the high impedance of the buffers 33 and 34 is disabled (step S125). While the high impedance of the buffers 33 and 34 is disabled, the power supply control signal PCS and the reset signal RS output from the control unit 31 are not cut off by the buffers 33 and 34 and appear outside the PLD 30, so that the power supply control signal is disabled. The signal PCS is input to the power supply section 40, and the reset signal RS is input to the controlled device 50.

The control unit 31 executing the control sequence inside the PLD 30 outputs the Low level PCS at time t12 and the High level PCS at time t13 according to the first sequence. Further, the control unit 31 executing the control sequence inside the PLD 30 outputs the Low level RS at time t12 and the High level RS at time t14 according to the second sequence.

Then, at time t15, the control unit 31 completes execution of the control sequence while the high impedance of the buffers 33 and 34 is disabled.

<When power is turned on>
When the power is turned on in FIG. 3, when updating of the configuration of the internal logic circuit of the PLD 30 is started (PLD: start of setting update), the control unit 31 enables high impedance of the buffers 33 and 34 (step S100). .

Next, at time t21, since the computer 10 is powered on (step S105: Yes), the control unit 31 starts executing the control sequence while the high impedance of the buffers 33 and 34 is enabled. (Step S110). While the high impedance of the buffers 33 and 34 is enabled, the output from the control unit 31 is blocked by the buffers 33 and 34, so the power control signal PCS and reset signal RS output from the control unit 31 are output from the PLD 30. It does not appear outside of.

Therefore, the low level PCS that the control unit 31 that is executing the control sequence inside the PLD 30 outputs at time t21 according to the first sequence, and the low level PCS that the control unit 31 that is executing the control sequence inside the PLD 30 outputs at time t21 according to the first sequence. The High level PCS output at t22 is not input to the power supply section 40.

In addition, the control unit 31 that is executing the control sequence inside the PLD 30 outputs the low level RS at time t21 according to the second sequence, and the control unit 31 that is executing the control sequence inside the PLD 30 outputs the low level RS at time t21 according to the second sequence. The High level RS output at t23 is not input to the controlled device 50.

Next, at time t24, the control unit 31 completes execution of the control sequence while the high impedance of the buffers 33 and 34 is enabled.

During the period when the high impedance of the buffers 33 and 34 is enabled, the pull-up power supplies V1 and V2 are turned on, so the input level of the power supply unit 40 and the input level of the controlled device 50 are maintained at High level. Ru.

Then, at time t25, the control unit 31 disables the high impedance of the buffers 33 and 34 (step S115).

The first embodiment has been described above.

[Example 2]
Hereinafter, points different from Example 1 will be explained.

<Processing procedure on computer>
FIG. 4 is a flowchart illustrating an example of a processing procedure in a computer according to a second embodiment of the present disclosure. The flowchart shown in FIG. 4 is started when the configuration of the internal logic circuit of the PLD 30 is updated by the CPU 20.

After the process in step S100, the process advances to step S105.

If the computer 10 has been powered on in step S105 (step S105: Yes), the process proceeds to step S200, and if the computer 10 has not been powered on in step S105 (step S105: No), the process The process advances to step S120.

In step S200, the control unit 31 skips execution of the control sequence stored in the memory 32. That is, the control sequence is not executed in step S200. In this way, when the computer 10 is powered on (step S105: Yes), the control unit 31 performs the first operation while the output from the control unit 31 to the power supply unit 40 is cut off (step S100) By skipping the execution of the sequence, the power supply unit 40 is not caused to execute the process according to the first sequence. Further, when the computer 10 is powered on (step S105: Yes), the control unit 31 performs the second sequence while the output from the control unit 31 to the controlled device 50 is cut off (step S100). By skipping execution, the controlled device 50 is not restarted.

After the process in step S200, the process advances to step S115.

<Timing chart in computer>
FIG. 5 is an example of a timing chart in the computer according to the second embodiment of the present disclosure. The timing chart when the power of the computer 10 is not turned on (when the power is not turned on) is the same as that in the first embodiment, so a description thereof will be omitted. A timing chart when the computer 10 is powered on (when the power is already turned on) will be described below.

<When power is turned on>
When the power is turned on in FIG. 5, when updating of the configuration of the internal logic circuit of the PLD 30 is started (PLD: start of setting update), the control unit 31 enables high impedance of the buffers 33 and 34 (step S100). .

Next, at time t31, since the computer 10 is powered on (step S105: Yes), the control unit 31 skips execution of the control sequence while the high impedance of the buffers 33 and 34 is enabled. (Step S200). Further, at time t31, the control unit 31 changes the initial state of Low level PCS to High level PCS, and changes the initial state of Low level RS to High level RS.

During the period when the high impedance of the buffers 33 and 34 is enabled, the pull-up power supplies V1 and V2 are turned on, so the input level of the power supply unit 40 and the input level of the controlled device 50 are maintained at High level. Ru.

Then, at time t32, the control unit 31 disables the high impedance of the buffers 33 and 34 (step S115).

The second embodiment has been described above.

As described above, the computer of the present disclosure (computer 10 of the embodiment) includes a programmable logic device (PLD 30 of the embodiment) having a memory (memory 32 of the embodiment), and a power supply section (power supply section 40 of the embodiment). ). The memory stores a first sequence for powering the computer off and then powering it back on. The power supply unit supplies power to the computer under control from the programmable logic device based on the first sequence. The programmable logic device determines whether the computer is powered on when the configuration of the internal logic circuit of the programmable logic device is updated. The programmable logic device causes the power supply unit to execute processing according to the first sequence when the computer is not powered on, while the programmable logic device causes the power supply unit to execute processing according to the first sequence when the computer is powered on. Do not allow processing according to the first sequence to be executed.

For example, when the computer is powered on, the programmable logic device completes execution of the first sequence within the programmable logic device with the output from the programmable logic device to the power supply section cut off. Do not allow the power supply unit to execute processing according to the first sequence.

For example, when the computer is powered on, the programmable logic device skips the execution of the first sequence while the output from the programmable logic device to the power supply is cut off. Do not allow processing according to the first sequence to be executed.

By doing so, the configuration of the internal logic circuit of the programmable logic device can be updated without powering off the computer.

Further, the computer of the present disclosure includes a device (the controlled device 50 of the embodiment) that restarts based on a reset signal. The memory also stores a second sequence controlling the reset signal. Then, the programmable logic device restarts the device when the computer is not powered on, but does not restart the device when the computer is powered on.

For example, a programmable logic device can be activated by completing execution of a second sequence within the programmable logic device while the output from the programmable logic device to the device is cut off when the computer is powered on. Don't restart.

For example, when the computer is powered on, the programmable logic device skips execution of the second sequence while the output from the programmable logic device to the device is cut off, thereby preventing the device from restarting.

This allows you to restart your device without powering down your computer.

10 computer 20 CPU
30 PLD
31 Control unit 32 Memory 33, 34 Buffer 40 Power supply unit 50 Controlled device V1, V2 Pull-up power supply R1, R2 Pull-up resistor

Claims (6)

a programmable logic device having a memory that stores a first sequence for turning on the power again after turning off the power to the computer;
a power supply unit that supplies power to the computer according to control from the programmable logic device based on the first sequence;
Equipped with
The programmable logic device includes:
determining whether the power is turned on when the configuration of the internal logic circuit of the programmable logic device is updated;
When the power is not turned on, causing the power supply unit to execute processing according to the first sequence,
When the power is turned on, the power supply unit does not execute the process according to the first sequence;
Computer. The programmable logic device may complete execution of the first sequence within the programmable logic device while the output from the programmable logic device to the power supply unit is cut off when the power is turned on. prevents the power supply unit from executing the process according to the first sequence;
A computer according to claim 1. The programmable logic device skips execution of the first sequence in a state where output from the programmable logic device to the power supply unit is cut off when the power is turned on, thereby controlling the power supply unit. does not allow the user to execute the process according to the first sequence;
A computer according to claim 1. further comprising: a device that restarts based on a reset signal;
the memory further stores a second sequence controlling the reset signal;
The programmable logic device includes:
while restarting the device when the power is not turned on;
not restarting the device when the power is on;
A computer according to claim 1. The programmable logic device completes execution of the second sequence within the programmable logic device while the output from the programmable logic device to the device is cut off when the power is turned on. do not restart the device,
A computer according to claim 4. The programmable logic device does not restart the device by skipping execution of the second sequence while the output from the programmable logic device to the device is cut off when the power is turned on. ,
A computer according to claim 4.

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