JP2023167834A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device which can prevent the occurrence of a problem such as an increase in leakage current and a reduction in voltage-withstanding even when the reverse bias is applied for a long period of time to a space between a drain and a source under a high-temperature environment.SOLUTION: A semiconductor device comprises: a first conductive type semiconductor layer 20; an active electrode layer 30 which is formed on one side of the semiconductor layer 20 in an active region; a plurality of voltage-withstanding buried layers 25 which are formed on the semiconductor layer 20 in a voltage-withstanding region surrounding the active region and are made of a second conductive type semiconductor material; and an interlayer insulating layer 40 which is formed on one side of the voltage-withstanding buried layers 25 and in which conductive films 11, 12 extending in the in-plane direction are buried. The conductive films 11, 12 have the first conductive film 11, and the second conductive film 12 provided on a side closer to one side than the first conductive film 11.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device having a breakdown voltage region surrounding an active region.

2. Description of the Related Art Semiconductor devices having a superjunction structure have been known. According to a semiconductor device having a superjunction structure, a plurality of (for example, several dozen) guard rings are provided in the breakdown voltage region surrounding the active region, so that during reverse bias, the depletion layer moves from the active region to the outermost periphery of the breakdown voltage region. It is possible to increase the breakdown voltage of the semiconductor device.

The patent is for a semiconductor device that prevents leakage current from increasing and breakdown voltage from decreasing even when reverse bias is applied for a long time in a high-temperature environment in a semiconductor device having such a superjunction structure. This is proposed in Document 1. In Patent Document 1, a semiconductor layer of a first conductivity type, a plurality of columnar buried layers formed on the surface of the semiconductor layer in the active region and made of a semiconductor material of the second conductivity type, and a surface of the semiconductor layer in the active region are disclosed. an active electrode layer formed thereon; a plurality of annular columnar buried layers formed on the surface of the semiconductor layer in a breakdown voltage region surrounding the active region and made of a semiconductor material of a second conductivity type; A semiconductor device having a superjunction structure, comprising: an insulating layer formed on a surface of a semiconductor layer in a surrounding peripheral region; A semiconductor device has been proposed that further includes a second annular columnar buried layer and an annular conductive layer formed on an insulating layer in a peripheral region.

However, when a reverse bias is applied for a long time in a high-temperature environment, mobile ions in the package resin move through the passivation film and interlayer insulation film, and even move to the top of the superjunction structure, causing the depletion layer to elongate. This may cause problems such as an increase in leakage current and a decrease in breakdown voltage due to the collapse of the electric field strength distribution on the surface.

Japanese Patent Application Publication No. 2013-102087

The present invention provides a semiconductor device that can prevent problems such as an increase in leakage current and a decrease in breakdown voltage even when a reverse bias is applied for a long time in a high-temperature environment.

The semiconductor device according to the present invention includes:
a first conductivity type semiconductor layer;
an active electrode layer formed on one side of the semiconductor layer in an active region;
a plurality of breakdown voltage buried layers formed in the semiconductor layer in a breakdown voltage region surrounding an active region and made of a semiconductor material of a second conductivity type;
an insulating film formed on one side of the withstand voltage buried layer, in which a conductive film extending in the in-plane direction is embedded;
Equipped with
The conductive film may include a first conductive film and a second conductive film provided on one side of the first conductive film.

In the semiconductor device according to the present invention,
The first conductive film has a plurality of first conductive spacing films spaced apart from each other,
The second conductive film may include a plurality of second conductive spacing films spaced apart from each other.

In the semiconductor device according to the present invention,
The second conductive spacing film is provided at a location overlapping with the voltage-resistant buried layer in a plan view,
The first conductive spacing film may be provided between the second conductive spacing films in plan view.

In the semiconductor device according to the present invention,
The second conductive spacing film is provided corresponding to each of the plurality of voltage-resistant buried layers,
The first conductive spacing film may be provided between each of the second conductive spacing films in plan view.

The semiconductor device according to the present invention includes:
comprising a peripheral electrode layer formed on one side of the semiconductor layer in the breakdown voltage region,
In a longitudinal section, the number of voltage-resistant buried layers and the number of second conductive spacing films provided between the active electrode layer and the peripheral electrode layer may be the same.

The semiconductor device according to the present invention includes:
comprising a peripheral electrode layer formed on one side of the semiconductor layer in the breakdown voltage region,
In a plan view, the outer end of the second conductive spacing film located outermost and the peripheral electrode layer may overlap.

In the semiconductor device according to the present invention,
In a plan view, the innermost end of the second conductive spacing film located innermost and the active electrode layer may overlap.

An insulating film formed on one side of a pressure-resistant buried layer as in the present invention, in which a conductive film extending in the in-plane direction is embedded, the first conductive film and the first conductive film being embedded. By using an insulating film with a second conductive film provided on one side of the film, an increase in leakage current and a decrease in breakdown voltage occur even when reverse bias is applied for a long time in a high-temperature environment. This problem can be prevented from occurring.

FIG. 1 is a vertical cross-sectional view of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a vertical cross-sectional view showing in-plane overlap of a voltage-resistant buried layer, a first conductive spacing film, and a second conductive spacing film in the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a vertical cross-sectional view showing in-plane overlap between a peripheral electrode layer and a second conductive spacing film in the semiconductor device according to the first embodiment of the present invention. FIG. 3 is a vertical cross-sectional view showing the in-plane overlap between the active electrode layer and the second conductive spacing film in the semiconductor device according to the first embodiment of the present invention. FIG. 2 is a vertical cross-sectional view schematically showing how mobile ions are trapped by a pseudo capacitor in the semiconductor device according to the first embodiment of the present invention. The graph which showed the surface electric field intensity at the time of the HTRB test when the first conductive film and the second conductive film were not provided. A graph showing the surface electric field strength during an HTRB test when a first conductive film and a second conductive film are provided. FIG. 2 is a schematic plan view showing a first conductive film provided in an annular shape in plan view in the first embodiment of the present invention. FIG. 3 is a schematic plan view showing a second conductive film provided in an annular shape in plan view in the first embodiment of the present invention. FIG. 3 is a vertical cross-sectional view of a semiconductor device according to a modification of the first embodiment of the present invention. FIG. 7 is a longitudinal cross-sectional view of a semiconductor device in a second embodiment of the present invention, in which a second conductive film extends longer in a second direction than a first conductive film. FIG. 7 is a longitudinal cross-sectional view of a semiconductor device in which a first conductive film and a second conductive film have approximately the same length and extend in a second direction in a second embodiment of the present invention. FIG. 7 is a vertical cross-sectional view of a semiconductor device according to a third embodiment of the present invention. FIG. 3 is a vertical cross-sectional view showing an embodiment in which a plurality of conductive spacing films each made of one layer of conductive films are provided in an interlayer insulating layer.

First embodiment <<Configuration>>
In this embodiment, "one side" means the upper side in FIG. 1, and "the other side" means the lower side in FIG. The vertical direction in FIG. 1 is called a "first direction," the horizontal direction is called a "second direction," and the front and back direction of the paper is called a "third direction." The in-plane direction including the second direction and the third direction is referred to as the "in-plane direction." The view from one side in the first direction is called planar view. Note that the second direction in this embodiment means a direction perpendicular to the direction in which a pressure-resistant buried layer 25 made of a guard ring, which will be described later, extends among in-plane directions.

The semiconductor device according to this embodiment may be a Schottky barrier diode having a superjunction structure. However, it is not limited to this, and may be a pn diode, MOSFET, thyristor, IGBT, or the like.

As shown in FIG. 1, the semiconductor device includes a semiconductor layer 20 of a first conductivity type, an active electrode layer 30 formed on one side of the semiconductor layer 20 in an active region, and a semiconductor layer 20 in a breakdown voltage region surrounding the active region. a plurality of voltage-resistant buried layers 25 made of a semiconductor material of a second conductivity type, and an interlayer insulating layer 40 formed on one side of the voltage-resistant buried layer 25, and a conductive layer extending in the in-plane direction. and an interlayer insulating layer 40 in which the films 11 and 12 are embedded. The conductive films 11 and 12 include a first conductive film 11 and a second conductive film 12 provided on one side of the first conductive film 11 (on the front side of the semiconductor device). The conductive films 11 and 12 may be made of polysilicon, for example. The breakdown voltage region may be provided surrounding part or all of the active region. A peripheral region may be provided surrounding part or all of the breakdown voltage region. In this embodiment mode, an n-type is used as the first conductivity type, and a p-type is used as the second conductivity type. However, the present invention is not limited to this. N-type may be used as the conductivity type. Note that the active region refers to the other side (lower side) of the area where the active electrode layer 30 contacts the semiconductor layer 20, and refers to the area where current flows from the back surface to the front surface when in the on state. There is. In the embodiment shown in FIG. 1, the peripheral region means the other side (lower side) of the region where the peripheral electrode layer 60 contacts the semiconductor layer 20.

An n + -type semiconductor substrate 21 having a higher impurity concentration than the semiconductor layer 20 may be provided on the back side (lower side) of the n ^- type semiconductor layer 20 . The n-type semiconductor layer 20 may be formed by epitaxial growth on the n ⁺ -type semiconductor substrate 21.

A plurality of columnar buried layers 125 made of p-type silicon may be provided in the front surface region of the n ^- type semiconductor layer 20 in the active region. The active electrode layer 30 provided on the front surface of the n ^- type semiconductor layer 20 in the active region may be a Schottky barrier metal layer as a source electrode layer. The breakdown voltage buried layer 25 provided in the front surface region of the n ^- type semiconductor layer 20 in the breakdown voltage region surrounding the active region may be a plurality of guard rings (annular buried layers) made of p-type silicon. . A drain electrode layer 90 may be provided on the back surface of the n ⁺ -type semiconductor substrate 21 . The columnar buried layer 125 may have a p-type high concentration ohmic diffusion region (not shown) on the front surface side. The breakdown voltage buried layer 25 may have a p-type high concentration diffusion region (not shown) on the front surface side.

In the front surface region of the n ⁻ type semiconductor layer 20 in the active region, there is a p type body region 161, and an n ⁺ type source region 165 and a p ⁺ type contact formed in the front surface region of the p type body region 161. A region 167 may also be provided. Further, on the front surface of the n ^- type semiconductor layer 20 in the active region, there is a gate insulating layer 172, a gate electrode layer 170 provided on the front surface side of the gate insulating layer 172, and a gate electrode layer 170. An interlayer insulating film 174 may be provided between the source electrode layer and the active electrode layer 30 (see also FIG. 4). Although this embodiment mode is described using a mode in which the active electrode layer 30, which is a source electrode layer, the drain electrode layer 90, and the gate electrode layer 170 are provided, the present invention is not limited to this, and an anode and a cathode are provided. A semiconductor device having the following may be used.

A peripheral electrode layer 60 having an annular shape in plan view may be provided on one side of the interlayer insulating layer 40 in the peripheral region. The peripheral electrode layer 60 may be connected to an n-type high concentration diffusion region (n ⁺⁺ diffusion region) 65 formed in the front surface region of the n ^- type semiconductor layer 20 . The impurity concentration of the n-type high concentration diffusion region 65 is, for example, 1×10 ¹⁹ cm ⁻³ to 5×10 ²⁰ cm ⁻³ .

The n ⁺ -type semiconductor substrate 21 and the n ^- -type semiconductor layer 20 constitute a semiconductor base. The thickness of the n ^- type semiconductor layer 20 is, for example, 6 μm to 70 μm, and the impurity concentration of the n ⁻ type semiconductor layer 20 is, for example, 5×10 ¹³ cm ⁻³ to 5×10 ¹⁶ cm ⁻³ . The impurity concentration of the n ⁺ -type semiconductor substrate 21 is, for example, 1×10 ¹⁹ cm ⁻³ to 5×10 ²⁰ cm ⁻³ .

The columnar buried layer 125 may be made of a p-type semiconductor material (second conductivity type semiconductor material) formed by epitaxial growth inside the first trench 116 formed in the active region of the n ^- type semiconductor layer 20. The number of columnar buried layers 125 can be appropriately set according to the purpose of use and structure. The impurity concentration of the p-type semiconductor material is, for example, 5×10 ¹³ cm ⁻³ to 5×10 ¹⁶ cm ⁻³ .

The depth of the columnar buried layer 125 is, for example, 5 μm to 50 μm, and the width of the columnar buried layer 125 is, for example, 0.5 μm to 5 μm. The columnar buried layers 125 may be formed in parallel with a first interval. The first interval is, for example, 1 μm to 15 μm.

The breakdown voltage buried layer 25 may be made of a p-type semiconductor material (second conductivity type semiconductor material) formed by epitaxial growth inside a second trench formed in the breakdown voltage region of the n ^- type semiconductor layer 20. The number of voltage-resistant buried layers 25 is, for example, 5 to 50, but can be set as appropriate depending on the purpose of use and structure. The impurity concentration of the p-type semiconductor material is, for example, 2×10 ¹⁴ cm ⁻³ to 5×10 ¹⁶ cm ⁻³ .

The depth of the voltage-resistant buried layer 25 is, for example, 5 μm to 50 μm, and the width of the voltage-resistant buried layer 25 is, for example, 0.5 μm to 5 μm. The voltage-resistant buried layers 25 are formed in parallel with each other at second intervals. The second interval is, for example, 1 μm to 15 μm.

The interlayer insulating layer 40 may be made of a silicon oxide film. The active electrode layer 30 may form a Schottky junction with the n ^- type semiconductor layer 20 and may form an ohmic junction with the columnar buried layer 125. The material of the active electrode layer 30 is metal (for example, aluminum), and the thickness of the active electrode layer 30 is, for example, 5 μm. The material of the peripheral electrode layer 60 is metal (for example, aluminum), and the thickness of the peripheral electrode layer 60 is, for example, 5 μm. The drain electrode layer 90 may be formed by depositing a metal (for example, a multilayer metal film such as Ti--Ni--Au) as an electrode material on the back surface of the semiconductor substrate. The thickness of the entire multilayer metal film that is the drain electrode layer 90 is, for example, 0.5 μm. The peripheral electrode layer 60 is electrically connected to the drain electrode layer 90, and the peripheral electrode layer 60 and the drain electrode layer 90 may be at the same potential.

The first conductive film 11 may include a plurality of first conductive spacing films 1 spaced apart from each other in the in-plane direction. Similarly, the second conductive film 12 may include a plurality of second conductive spacing films 2 spaced apart from each other in the in-plane direction.

On the front side of the voltage-resistant buried layer 25, a second conductive spacing film 2 is provided on a straight line from the voltage-resistant buried layer 25 toward the thickness direction of the semiconductor device (on a straight line extending parallel to the first direction). (See “A” in FIG. 2). In this case, the second conductive spacing film 2 is provided at a location overlapping with the voltage-resistant buried layer 25 in plan view. On the back side between the in-plane directions of the second conductive spacing film 2, there is a The first conductive spacing film 1 may be provided on a straight line extending in parallel (see "B" in FIG. 2). In this case, the first conductive spacing film 1 is provided between the second conductive spacing films 2 in plan view (see FIGS. 7A and 7B).

The second conductive spacing film 2 may be provided corresponding to each of the plurality of voltage-resistant buried layers 25. In this case, the second conductive spacing film 2 is placed on a straight line from each of the plurality of pressure-resistant buried layers 25 toward the front surface side in the thickness direction of the semiconductor device (on a straight line extending parallel to the first direction). will be established. One second conductive spacing film 2 is provided on a straight line from each of the plurality of pressure-resistant buried layers 25 toward the front surface side in the thickness direction of the semiconductor device (on a straight line extending parallel to the first direction). In this case, the number of voltage-resistant buried layers 25 and the number of second conductive spacing films 2 are the same. At this time, the second conductive spacing film 2 corresponds to the pressure-resistant buried layer 25 located on the other side (back side, lower side in FIG. 1) of the active electrode layer 30 and completely covered by the active electrode layer 30 in plan view. is not provided, and the number of pressure-resistant buried layers 25 and the number of second conductive spacing films 2 provided between the active electrode layer 30 and the peripheral electrode layer 60 in the in-plane direction are the same. (See Figure 1).

When the voltage-resistant buried layer 25 has an annular shape in a plan view, the second conductive film 12 also has an annular shape in a plan view corresponding to the voltage-resistant buried layer 25 (see FIG. 7B). In this case, the annular first conductive film 11 is provided between the second conductive spacing films 2 in plan view (see FIG. 7A). Although FIG. 7B schematically shows the second conductive film 12, in the second conductive film 12 shown in FIG. 7B, a plurality of second conductive spacing films 2 are arranged at a certain distance apart. (See Figure 1). Similarly, although FIG. 7A schematically shows the first conductive film 11, in the first conductive film 11 shown in FIG. 7A, a plurality of first conductive spacing films 1 are arranged at a certain distance apart. (See Figure 1)

When the voltage-resistant buried layer 25 has a dot shape in a plan view, the second conductive spacing film 2 also has a dot shape in a plan view corresponding to the voltage-resistant buried layer 25. In this case, the first conductive spacing film 1 also has a dot shape in plan view, corresponding to the second conductive spacing film 2. However, in consideration of ease of design, the pressure-resistant buried layer 25 is formed in an annular shape in plan view, and each of the first conductive film 11 and the second conductive film 12 is formed in a planar shape as shown in FIGS. 7A and 7B. It is advantageous to form it from an annular shape in view.

The first conductive spacing film 1 may be provided between each of the second conductive spacing films 2 in plan view. In this case, the first conductive spacing film 1 is provided on a straight line from each of the second conductive spacing films 2 toward the back surface side in the thickness direction of the semiconductor device (on a straight line extending parallel to the first direction). It will be done.

The second conductive spacing film 2 located most outwardly on a straight line from the peripheral electrode layer 60 to the back side of the semiconductor device in the thickness direction of the semiconductor device (on a straight line extending parallel to the first direction). An outer end may be provided (see "C" in Figure 3). In this case, the outer end of the second conductive spacing film 2 located at the outermost position and the peripheral electrode layer 60 overlap in plan view.

The inner side of the second conductive spacing film 2 located innermost on a straight line from the active electrode layer 30 toward the back side of the semiconductor device in the thickness direction of the semiconductor device (on a straight line extending parallel to the first direction) An end may be provided (see "D" in Figure 4). In this case, in plan view, the innermost end of the second conductive spacing film 2 located innermost and the active electrode layer 30 overlap.

The interlayer insulating layer 40 in which the first conductive film 11 and the second conductive film 12 of this embodiment are embedded is formed, for example, as follows.

First, the interlayer insulating layer 40 is formed on the n ^- type semiconductor layer 20 in which the withstand voltage buried layer 25 is formed in the front surface region by approximately 1/3 of the thickness of the interlayer insulating layer 40 to be finally formed. . After that, the first conductive film 11 is formed on the formed interlayer insulating layer 40. At this time, a plurality of first conductive spacing films 1 are formed by forming a conductive film made of, for example, polysilicon and partially removing the conductive film.

Next, the interlayer insulating layer 40 is formed to cover the plurality of first conductive spacing films 1 to approximately ⅔ of the thickness of the interlayer insulating layer 40 to be finally formed. After that, the second conductive film 12 is formed on the formed interlayer insulating layer 40. Also in this case, a plurality of second conductive spacing films 2 are formed by forming a conductive film made of, for example, polysilicon and partially removing the conductive film.

Next, the remaining interlayer insulating layer 40 is formed so as to cover the plurality of second conductive spacing films 2. By doing so, the interlayer insulating layer 40 in which the first conductive film 11 and the second conductive film 12 are embedded is formed.

Although this embodiment mode is described using a mode in which the first conductive film 11 and the second conductive film 12 are provided within the interlayer insulating layer 40, the present invention is not limited to this mode; Three or more layers may be laminated in the thickness direction (first direction), and a third conductive film, a fourth conductive film, ..., an n-th conductive film ("n" is an integer of 3 or more). may be provided.

"effect"
Next, an example of the effect of the present embodiment having the above-described configuration will be described. Note that all the aspects described under "effects" can be employed in the above configuration.

An interlayer insulating layer 40 formed on one side of the withstand voltage buried layer 25, in which the conductive films 11 and 12 extending in the in-plane direction are embedded, the first conductive film 11 and In the case of employing the interlayer insulating layer 40 having the second conductive film 12 provided on one side of the first conductive film 11, when a reverse bias is applied between the drain and the source for a long time in a high temperature environment, Even if this happens, problems such as an increase in leakage current and a decrease in breakdown voltage can be prevented from occurring.

When the first conductive film 11 has a plurality of first conductive spacing films 1 spaced apart from each other, or when the second conductive film 12 has a plurality of second conductive spacing films 2 spaced apart from each other, a low resistance first A pseudo capacitor can be formed by the conductive spacing film 1, the second conductive spacing film 2, and the interlayer insulating layer 40 sandwiched between the first conductive spacing film 1 and the second conductive spacing film 2 (see FIG. 5). ), mobile ions can be captured by a pseudo capacitor. Therefore, problems such as an increase in leakage current and a decrease in breakdown voltage can be more effectively prevented. 6A and 6B are graphs showing the surface electric field strength during the HTRB (High Temperature Reverse Bias) test, where the horizontal axis represents the in-plane distance from the active region, and the vertical axis represents the electric field strength. ing. According to the aspect of this embodiment, as shown in FIG. 6B, the electric field strength as designed can be maintained without being affected by mobile ions. On the other hand, unlike this embodiment, if the first conductive film 11 and the second conductive film 12 are not provided, as shown in FIG. 6A, the electric field strength on the surface decreases due to mobile ions, and The electric field strength increases, making it easier to cause BD (breakdown).

That is, when the first conductive film 11 and the second conductive film 12 are not provided as shown in FIG. 6A, the mobile ions of the package resin tend to move due to high temperature. As a result, mobile ions gather on the surface of the peripheral structure due to the bias between the drain and source, and the gathered mobile ions affect the extension of the depletion layer, disrupting the electric field strength distribution and causing a drop in breakdown voltage. In contrast, according to the present embodiment, even if mobile ions move into the interlayer insulating layer 40 when a reverse bias is continuously applied in a high-temperature environment, the first conductive film 11 and the second conductive film 12 can block mobile ions. In addition, mobile ions that try to pass through the block are captured by the capacitance formed by the first conductive film 11, the second conductive film 12, and the interlayer insulating layer 40 (see FIG. 5), and are captured by the capacitance formed by the first conductive film 11, the second conductive film 12, and the interlayer insulating layer 40 (see FIG. 5). Do not get close to the upper part of the interface of layer 40 (see FIG. 6B). Therefore, it is possible to create a structure that does not affect the extension of the depletion layer in the peripheral structure and does not cause an increase in leakage current or a variation in breakdown voltage.

The inventors have also provided an embodiment in which a plurality of first conductive spacing films 1 are provided at locations overlapping with the pressure-resistant buried layer 25 in a plan view, and a second conductive spacing film 2 is provided between the plurality of first conductive spacing films 1. We conducted an experiment (see FIG. 8), but from the viewpoint of not causing an increase in leakage current or a variation in breakdown voltage, it was found that a plurality of second conductive spaces located on the upper side (on one side) overlapped with the breakdown voltage buried layer 25 in plan view. It has been confirmed that it is preferable to provide the membrane 2 and provide the first conductive spacing membrane 1 located below (on the other side) between the plurality of second conductive spacing membranes 2.

In addition, the inventors also experimented with an embodiment in which a plurality of conductive spacing films 111 made of a single conductive film 110 are provided in the interlayer insulating layer 40 at locations overlapping with the voltage-resistant buried layer 25 in plan view (Fig. 12 ), it was not possible to obtain a sufficient effect of not causing an increase in leakage current or a variation in breakdown voltage.

When the second conductive spacing film 2 is provided at a location overlapping with the pressure-resistant buried layer 25 in a plan view, and the first conductive spacing film 1 is provided between the second conductive spacing films 2 in a plan view, the pressure-resistant buried layer 25 is provided. While positioning the second conductive spacing film 2 on one side of the embedded layer 25, a pseudo capacitor can be formed between the second conductive spacing film 2 and the first conductive spacing film 1, thereby preventing an increase in leakage current. This is advantageous in that it is possible to more effectively prevent the problem of a decrease in breakdown voltage.

When the second conductive spacing film 2 is provided corresponding to each of the plurality of pressure-resistant buried layers 25, and the first conductive spacing film 1 is provided between each of the second conductive spacing films 2 in plan view, A second conductive spacing film 2 is provided corresponding to each of the plurality of pressure-resistant buried layers 25, and between the second conductive spacing film 2 and the first conductive spacing film 1 corresponding to the second conductive spacing film 2. This is advantageous in that it is possible to form a pseudo capacitor using the method, and to prevent an increase in leakage current and a decrease in breakdown voltage caused by each breakdown voltage buried layer 25.

In the longitudinal section, the number of pressure-resistant buried layers 25 provided between the active electrode layer 30 and the peripheral electrode layer 60 is the same as the number of second conductive spacing films 2, and the number of the second conductive spacing films 2 is the same. When the first conductive spacing film 1 is provided in each of the withstand voltage buried layers 25, the second conductive spacing film 2 can be provided in one-to-one correspondence with the withstand voltage buried layers 25, and the leakage current caused by each withstand voltage buried layer 25 can be provided. This is advantageous in that it can more effectively prevent an increase in pressure and a drop in withstand voltage. Note that in order to effectively capture the above-mentioned mobile ions, as in this embodiment, the number of pressure-resistant buried layers 25 provided between the active electrode layer 30 and the peripheral electrode layer 60 and the second conductive distance must be adjusted. The number of films 2 is the same, and the first conductive spacing film 1 is provided between each of the second conductive spacing films 2, as in the second embodiment and the third embodiment described later. It is also preferable compared to other solutions.

In a plan view, when the outer end of the second conductive spacing film 2 located at the outermost position overlaps with the peripheral electrode layer 60 (see FIG. 3), the second conductive spacer film located at the outermost position overlaps with the peripheral electrode layer 60 (see FIG. 3). This is advantageous in that the membrane 2 can be brought into a stable voltage state.

In a plan view, when the inner end of the second conductive spacing film 2 located innermost overlaps the active electrode layer 30 (see FIG. 4), the second conductive spacing film 2 located innermost overlaps with the active electrode layer 30 (see FIG. 4). This is advantageous in that the membrane 2 can be brought into a stable voltage state.

Second Embodiment Next, a second embodiment of the present invention will be described.

In this embodiment, as shown in FIG. 9, one first conductive film 11 (first conductive spacing film 1) extending in the plane may be provided. Similarly, one second conductive film 12 (second conductive spacing film 2) extending within the plane is provided. The other configurations are the same as those in the first embodiment, and all aspects described in the first embodiment can be adopted. The members described in the first embodiment will be described using the same reference numerals.

In the embodiment shown in FIG. 9, the second conductive film 12 extends longer than the first conductive film 11 in the second direction. However, the present invention is not limited to this embodiment, and for example, as shown in FIG. 10, the first conductive film 11 and the second conductive film 12 may extend in the second direction with approximately the same length. Further, the first conductive film 11 may extend longer than the second conductive film 12 in the second direction.

Also in this embodiment, a pseudo capacitor can be formed between the first conductive film 11 and the second conductive film 12, and problems such as an increase in leakage current and a decrease in breakdown voltage can be prevented from occurring. . However, it cannot be denied that there is a risk that the voltage will be concentrated at one location of the first conductive film 11 or the second conductive film 12, and the withstand voltage will drop. Therefore, as shown in the first embodiment, the first conductive film 11 has a plurality of first conductive spacing films 1 spaced from each other, and the second conductive film 12 has a plurality of second conductive films 1 spaced apart from each other. It is more advantageous to adopt an embodiment having the spacing film 2.

Third Embodiment Next, a third embodiment of the present invention will be described.

In this embodiment, as shown in FIG. 11, the second conductive film 12 is provided in a manner that does not correspond one-to-one with the voltage-resistant buried layer 25, and the first conductive film 12 is provided in correspondence with the second conductive film 12. A spacing membrane 1 is provided. The other configurations are the same as those in the first embodiment, and all aspects described in the first embodiment can be adopted. The members described in the first embodiment will be described using the same reference numerals.

Also in this embodiment, a pseudo capacitor can be formed between the first conductive film 11 and the second conductive film 12, and problems such as an increase in leakage current and a decrease in breakdown voltage can be prevented from occurring. . However, as an effect, as shown in the first embodiment, the second conductive spacing films 2 are provided in one-to-one correspondence with the voltage-resistant buried layers 25, and the second conductive spacing films 2 are provided in each space between the second conductive spacing films 2. By adopting the mode in which one conductive spacing film 1 is provided, the second conductive spacing film 2 and the first conductive spacing film 1 can be provided corresponding to each withstand voltage buried layer 25, and leakage current can be reduced. This is advantageous in that it is possible to more effectively prevent problems such as increases and decreases in breakdown voltage. Furthermore, from the viewpoint of reducing the risk of the withstand voltage dropping as a result of voltage concentration as described in the second embodiment, it is more beneficial to adopt the aspect of the first embodiment.

The description of each of the embodiments described above and the disclosure of the drawings are merely examples for explaining the invention described in the claims, and the description of each of the embodiments and the disclosure of the drawings described above are only examples for explaining the invention described in the claims. The invented invention is not limited. Furthermore, the claims originally filed are merely examples, and the claims may be changed as appropriate based on the description, drawings, etc.

1 First conductive spacing film 2 Second conductive spacing film 11 First conductive film 12 Second conductive film 20 Semiconductor layer 25 Voltage-resistant buried layer 30 Active electrode layer 40 Interlayer insulating layer 60 Peripheral electrode layer

Claims (7)

a first conductivity type semiconductor layer;
an active electrode layer formed on one side of the semiconductor layer in an active region;
a plurality of breakdown voltage buried layers formed in the semiconductor layer in a breakdown voltage region surrounding an active region and made of a semiconductor material of a second conductivity type;
an insulating film formed on one side of the withstand voltage buried layer, in which a conductive film extending in the in-plane direction is embedded;
Equipped with
A semiconductor device in which the conductive film includes a first conductive film and a second conductive film provided on one side of the first conductive film. The first conductive film has a plurality of first conductive spacing films spaced apart from each other,
The semiconductor device according to claim 1, wherein the second conductive film has a plurality of second conductive spacing films spaced apart from each other. The second conductive spacing film is provided at a location overlapping with the voltage-resistant buried layer in a plan view,
3. The semiconductor device according to claim 2, wherein the first conductive spacing film is provided between the second conductive spacing films in plan view. The second conductive spacing film is provided corresponding to each of the plurality of voltage-resistant buried layers,
4. The semiconductor device according to claim 3, wherein the first conductive spacing film is provided between each of the second conductive spacing films in plan view. comprising a peripheral electrode layer formed on one side of the semiconductor layer in the breakdown voltage region,
5. The semiconductor device according to claim 4, wherein in a longitudinal section, the number of the breakdown voltage buried layers and the number of the second conductive spacing films provided between the active electrode layer and the peripheral electrode layer are the same. comprising a peripheral electrode layer formed on one side of the semiconductor layer in the breakdown voltage region,
6. The semiconductor device according to claim 2, wherein an outer end of the second conductive spacing film located at the outermost position and the peripheral electrode layer overlap in plan view. 6. The semiconductor device according to claim 2, wherein the innermost end of the second conductive spacing film located innermost and the active electrode layer overlap in plan view.