JP2023163097A - Semiconductor optical element - Google Patents

Abstract

To secure high reliability and reduce a parasitic capacitance.SOLUTION: A semiconductor optical element includes: a semiconductor layer 10 having a protrusion 12 on an upper surface; a multiple quantum well layer 20 extending in a first direction D1 on the protrusion 12; first semiconductor layers 24 in contact with a mesa stripe structure 14 at both sides in a second direction D2; a second semiconductor layer 26 on an upper surface of the semiconductor layer 10; resin layers 34 above the second semiconductor layer 26; third semiconductor layers 28 arranged on the second semiconductor layer 26, each of which is present at a periphery of a corresponding part of the resin layers 34, and having constituent materials different from the second semiconductor layer 26; a first electrode 38 on a lower surface of the semiconductor layer 10; and a second electrode 40 including a mesa electrode 42 arranged at an upper end face of the mesa-stripe structure 14, a lead out electrode 44 extending in the second direction D2 from the mesa electrode 42, and a pad electrode 46 arranged above one of the resin layers 34 and connected to the lead out electrode 44.SELECTED DRAWING: Figure 2

Description

The present invention relates to a semiconductor optical device.

A buried hetero-structure (BH structure) is sometimes applied to an electro-absorption modulator (hereinafter referred to as an EA modulator). The BH structure is a structure in which a mesa stripe structure including an optical functional layer is embedded with a semiconductor layer (buried layer), and achieves high reliability and high-speed response. Furthermore, parasitic capacitance can be reduced by forming a recess in the buried layer and filling the recess with a resin having a low dielectric constant (Patent Documents 1 and 2).

Japanese Patent Application Publication No. 2011-9456 JP2022-64266A

It is difficult to control the depth of the recess in the buried layer during the formation process. If there are variations in the depth of the recesses, the height of the resin base will vary, which will cause the thickness of the resin to vary and the characteristics to change. Patent Document 1 discloses that etching is stopped by an etching stop layer, but since the etching stop layer is also located directly under the mesa stripe structure, it affects electrical characteristics. Cited Document 2 makes no mention of controlling the depth of the recess.

The present invention aims to ensure high reliability and reduce parasitic capacitance.

The semiconductor optical device has a convex portion on an upper surface, and the convex portion extends in a stripe shape in a first direction to form a lower end portion of a mesa stripe structure, and the semiconductor layer has a convex portion on the convex portion of the semiconductor layer. a multi-quantum well layer extending in a first direction and forming another part of the mesa stripe structure; and a pair of first semiconductor layers contacting the mesa stripe structure on both sides of a second direction perpendicular to the first direction. a pair of second semiconductor layers located on the upper surface of the semiconductor layer on both sides of the convex portion in the second direction; a pair of resin layers located above the pair of second semiconductor layers; a pair of third semiconductor layers, each of which is located on a pair of second semiconductor layers, is located around a corresponding one of the pair of resin layers, and is different in constituent material from the pair of second semiconductor layers; a first electrode on the lower surface of the layer, a mesa electrode on the upper end surface of the mesa stripe structure, an extraction electrode extending from the mesa electrode in the second direction, and a first electrode located above one of the pair of resin layers. It has a second electrode including a pad electrode connected to the extraction electrode.

FIG. 1 is a plan view of a semiconductor optical device according to a first embodiment. 2 is a sectional view taken along line II-II of the semiconductor optical device shown in FIG. 1. FIG. 2 is a side view of the semiconductor optical device shown in FIG. 1. FIG. 4 is a sectional view taken along the line IV-IV of the semiconductor optical device shown in FIG. 3. FIG. FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor optical device according to a first embodiment. FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor optical device according to a first embodiment. FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor optical device according to a first embodiment. FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor optical device according to a first embodiment. FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor optical device according to a first embodiment. FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor optical device according to a first embodiment. FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor optical device according to a first embodiment. FIG. 3 is a diagram illustrating a method for manufacturing a semiconductor optical device according to a first embodiment. FIG. 3 is a plan view of a semiconductor optical device according to a second embodiment. 14 is a sectional view taken along the line XIV-XIV of the semiconductor optical device shown in FIG. 13. FIG. FIG. 7 is a plan view of a semiconductor optical device according to a third embodiment. 16 is a sectional view taken along the line XVI-XVI of the semiconductor optical device shown in FIG. 15. FIG. 16 is a sectional view taken along the line XVII-XVII of the semiconductor optical device shown in FIG. 15. FIG.

Hereinafter, embodiments of the present invention will be described specifically and in detail with reference to the drawings. In all the figures, members given the same reference numerals have the same or equivalent functions, and their repeated explanations will be omitted. Note that the size of the figure does not necessarily match the magnification.

[First embodiment]
FIG. 1 is a plan view of a semiconductor optical device according to a first embodiment. FIG. 2 is a sectional view taken along line II-II of the semiconductor optical device shown in FIG. The semiconductor optical device is an electro-absorption modulator (EA modulator), but it may also be a semiconductor laser or a light-receiving device.

[Semiconductor layer]
The semiconductor optical device has a semiconductor layer 10. The semiconductor layer 10 may be a semiconductor substrate (for example, an n-InP substrate), or may be a stacked body in which a buffer layer (for example, an n-InP layer) is provided on the semiconductor substrate. The semiconductor layer 10 has a convex portion 12 on its upper surface. The convex portions 12 extend in a stripe shape in the first direction D1. The convex portion 12 constitutes the lower end portion of the mesa stripe structure 14. The mesa stripe structure 14 extends from the rear end face 16 to the front end face 18 of the semiconductor optical device. The semiconductor layer 10 (particularly the convex portions 12) functions as a lower cladding layer of a first conductivity type (for example, n-type).

[Multiple quantum well layer]
The semiconductor optical device has a multiple quantum well layer 20. The multiple quantum well layer 20 extends in the first direction D1 above the convex portion 12 of the semiconductor layer 10. The multiple quantum well layer 20 constitutes the other part of the mesa stripe structure 14. The upper surface of the semiconductor layer 10 is lower than the lower end of the multiple quantum well layer 20, except for the convex portions 12.

[Top cladding layer]
The semiconductor optical device has an upper cladding layer 22 of a second conductivity type (for example, p-type). The upper cladding layer 22 extends in a stripe shape in the first direction D1 on the multiple quantum well layer 20. The upper cladding layer 22 is a p-InP layer. Another layer (for example, an optical confinement layer) may be arranged between the multiple quantum well layer 20 and the convex portion 12 (lower cladding layer) or between the multiple quantum well layer 20 and the upper cladding layer 22. Although this embodiment will be described assuming that the first conductivity type is n type and the second conductivity type is p type, the reverse may be possible. A contact layer (not shown) is arranged on the upper cladding layer 22.

[First semiconductor layer]
The semiconductor optical device has a pair of first semiconductor layers 24. The pair of first semiconductor layers 24 are made of a semi-insulating semiconductor (eg, Fe--InP). The pair of first semiconductor layers 24 are in contact with the mesa stripe structure 14 (for example, the entirety of both side surfaces) on both sides of the second direction D2 perpendicular to the first direction D1. The pair of first semiconductor layers 24 extend so as to contact the side surfaces of the convex portion 12 and also contact the upper surface of the semiconductor layer 10 (excluding the convex portion 12).

[Second semiconductor layer]
The semiconductor optical device has a pair of second semiconductor layers 26. The pair of second semiconductor layers 26 are made of an intrinsic semiconductor (for example, InGaAs) to which impurities are not intentionally added. The pair of second semiconductor layers 26 are different from the pair of first semiconductor layers 24 in their constituent materials. The pair of second semiconductor layers 26 are located on both sides of the convex portion 12 in the second direction D2, and on the upper surface of the semiconductor layer 10, respectively. A pair of first semiconductor layers 24 extend below the pair of second semiconductor layers 26, respectively. The pair of second semiconductor layers 26 completely cover the upper surface of the semiconductor layer 10 except for the vicinity of the upper end surface of the mesa stripe structure 14 (excluding the convex portion 12). Further, the second semiconductor layer 26 is adjacent (in contact) with the first semiconductor layer 24 adjacent to (in contact with) the mesa stripe structure 14 in the second direction D2.

[Third semiconductor layer]
The semiconductor optical device has a pair of third semiconductor layers 28. The pair of third semiconductor layers 28 are made of a semi-insulating semiconductor (eg, Fe--InP). The pair of third semiconductor layers 28 are made of the same material as the pair of first semiconductor layers 24 . Each of the pair of third semiconductor layers 28 is continuous with a corresponding one of the pair of first semiconductor layers 24. For example, the first semiconductor layer 24 rises along the side surface of the mesa stripe structure 14, and the second semiconductor layer 26 continues from its upper end. Furthermore, a corresponding one of the pair of second semiconductor layers 26 is interposed between the two.

The pair of third semiconductor layers 28 stand up on the pair of second semiconductor layers 26, respectively. The pair of third semiconductor layers 28 are different from the pair of second semiconductor layers 26 in their constituent materials. Each of the pair of third semiconductor layers 28 has a side surface exposed in at least one (for example, both) of the first direction D1 and two directions (see FIG. 4).

[Embedded layer]
The pair of first semiconductor layers 24 , the pair of second semiconductor layers 26 , and the pair of third semiconductor layers 28 constitute a buried layer 30 of the multiple quantum well layer 20 . Buried layers 30 are on both sides of mesa stripe structure 14 . The buried layer 30 is provided except for the upper end surface of the mesa stripe structure 14. The buried layer 30 contacts both side surfaces of the mesa stripe structure 14 on both sides in the second direction D2. The buried layer 30 is higher than the mesa stripe structure 14. The buried layer 30 extends from the rear end surface 16 to the front end surface 18 .

The pair of second semiconductor layers 26 extend horizontally along the upper surface of the semiconductor layer 10 (excluding the convex portions 12), and rise obliquely instead of vertically next to the mesa stripe structure 14. This is because the side surfaces of the first semiconductor layer 24 are inclined. The buried layer 30 has a pair of recesses 32 . Recesses 32 are on both sides of mesa stripe structure 14. The recess 32 is surrounded by the buried layer 30 from all sides.

[Resin layer]
The semiconductor optical device has a pair of resin layers 34. The pair of resin layers 34 are arranged in the pair of recesses 32, respectively. The resin layer 34 is arranged so as to fill the recess 32. The resin layer 34 is made of a material having a lower dielectric constant than the semiconductor constituting the buried layer 30 (eg, benzocyclobutene (BCB) or polyimide).

A semiconductor optical device is obtained by forming a plurality of semiconductor optical devices on a semiconductor wafer and making them into chips. Since it is difficult to cut the resin layer 34 when making chips, it is cleaved at the buried layer 30 (third semiconductor layer 28). Therefore, the resin layer 34 is not exposed on the end face or side surface of the semiconductor optical device.

The pair of resin layers 34 are above the pair of second semiconductor layers 26, respectively. Each of the pair of second semiconductor layers 26 extends between a corresponding one of the pair of first semiconductor layers 24 and a corresponding one of the pair of resin layers 34 . The pair of resin layers 34 are higher than the pair of first semiconductor layers 24 in height from the top surface of the semiconductor layer 10 . The resin layer 34 is higher than the buried layer 30.

FIG. 3 is a side view of the semiconductor optical device shown in FIG. 1, viewed from the rear end face 16 side. FIG. 4 is a cross-sectional view taken along line IV-IV of the semiconductor optical device shown in FIG. Each of the pair of third semiconductor layers 28 is located around a corresponding one of the pair of resin layers 34. Each of the pair of third semiconductor layers 28 surrounds a corresponding one of the pair of resin layers 34 from all circumferential directions including the first direction D1 and the second direction D2.

[Inorganic insulation film]
Each of the pair of resin layers 34 is surrounded by an inorganic insulating film 36 (for example, a silicon oxide film or a silicon nitride film). The inorganic insulating film 36 is interposed between each of the pair of resin layers 34 and a corresponding one of the pair of third semiconductor layers 28 .

The inorganic insulating film 36 is arranged along the inner surface of the recess 32 . The inorganic insulating film 36 is interposed between each of the pair of resin layers 34 and a corresponding one of the pair of first semiconductor layers 24 . The inorganic insulating film 36 is interposed between each of the pair of resin layers 34 and a corresponding one of the pair of second semiconductor layers 26 . The inorganic insulating film 36 is also disposed at the upper end of a portion of the buried layer 30 (a portion around the recess 32) (FIG. 2). The inorganic insulating film 36 is not disposed on the upper end surface of the mesa stripe structure 14.

[First electrode]
The semiconductor optical device has a first electrode 38 on the lower surface (back surface) of the semiconductor layer 10 (FIG. 2). The first electrode 38 covers almost the entire lower surface of the semiconductor layer 10. The first electrode 38 is electrically and physically connected to the semiconductor layer 10 and has the same potential. A semiconductor layer having the same conductivity type as the semiconductor layer 10 may be interposed between the first electrode 38 and the semiconductor layer 10.

[Second electrode]
The semiconductor optical device has a second electrode 40. The second electrode 40 may be constructed entirely of the same material and structure. The second electrode 40 includes a mesa electrode 42 on the top surface of the mesa stripe structure 14 . Mesa electrode 42 is electrically and physically connected to mesa stripe structure 14 . By applying a reverse bias between the mesa electrode 42 and the first electrode 38, the semiconductor optical device functions as a modulator that absorbs light in the multiple quantum well layer 20.

The mesa electrode 42 has a rectangular planar shape. The tip of the mesa electrode 42 in the first direction D1 is located inside the rear end surface 16 and the front end surface 18 (FIG. 1), but may extend to each end surface. Since a large parasitic capacitance hinders high-speed driving, it is preferable that the mesa electrode 42 has a small area in order to reduce the parasitic capacitance. Therefore, even if the mesa electrode 42 extends beyond the upper end surface of the mesa stripe structure 14 and reaches onto the buried layer 30, it is preferably thin enough to rest only on the end adjacent to the mesa stripe structure 14. Here, the mesa electrode 42 does not overlap the resin layer 34.

The second electrode 40 includes an extraction electrode 44 extending from the mesa electrode 42 in the second direction D2. The extraction electrode 44 is thinner than the mesa electrode 42 in width in the first direction D1. A part of the extraction electrode 44 overlaps with the resin layer 34. Here, only the end portion of the resin layer 34 adjacent to the mesa stripe structure 14 overlaps with the extraction electrode 44 . The second electrode 40 includes a pad electrode 46 located above one of the pair of resin layers 34 and connected to the extraction electrode 44 . The pad electrode 46 is wider than the extraction electrode 44 in the first direction D1. The pad electrode 46 is wire-bonded.

[Effect]
Semiconductor optical devices have at least two advantages. First, both sides of the mesa stripe structure 14 are in contact with the semiconductor (buried layer 30). Therefore, compared to a structure in which the side surfaces of the mesa stripe structure 14 are in contact with an inorganic material or resin, deterioration of the semiconductor included in the mesa stripe structure 14 can be prevented and reliability is improved.

Next, since the buried layer 30 is provided with a recess 32 and the resin layer 34 is placed therein, the capacitance component can be reduced and excellent high-speed response can be achieved. Specifically, the resin layer 34 is arranged between a part of the extraction electrode 44 and the pad electrode 46 and the semiconductor layer 10. Therefore, parasitic capacitance caused by these electrodes can be reduced.

For example, assume a structure in which there is no recess 32 and the buried layer 30 is placed under the pad electrode 46. In this case, a parasitic capacitance is generated between the pad electrode 46 and the semiconductor layer 10. The parasitic capacitance depends on the distance between the pad electrode 46 and the semiconductor layer 10, the area of the pad electrode 46, and the dielectric constant of the layer between them. A semiconductor (buried layer 30) is present between the pad electrode 46 and the semiconductor layer 10. Therefore, the magnitude of the parasitic capacitance is determined by the dielectric constant of the buried layer 30.

In this embodiment, since there is a resin layer 34 having a lower dielectric constant than the semiconductor (buried layer 30) between the pad electrode 46 and the semiconductor layer 10, the parasitic capacitance can be reduced. Therefore, excellent high-speed response can be achieved.

Furthermore, since the resin layer 34 is arranged on both sides of the mesa stripe structure 14, it is possible to reduce the capacitance during high frequency driving. When a high frequency voltage is applied to the mesa stripe structure 14, the electric field spreads not only inside the mesa stripe structure 14 but also on both sides thereof. Compared to the case where both sides of the mesa stripe structure 14 are all buried layers 30 (semiconductor layers), the resin layer 34 having a lower dielectric constant is arranged, so that the electric field distribution area on both sides of the mesa stripe structure 14 is The dielectric constant can be lowered. This contributes to faster operation. In order to obtain this effect, the thickness of the buried layer 30 arranged on the side surface of the mesa stripe structure 14 is preferably 10 μm or less, and the band improvement effect is obtained by 10% or more compared to the case without the resin layer 34. Therefore, it is more desirable that the thickness be 5 μm or less.

Placing the pair of resin layers 34 on both sides of the mesa stripe structure 14 not only reduces the parasitic capacitance caused by the pad electrodes 46, but also reduces the capacitance of the electric field distribution region that spreads on both sides of the mesa stripe structure 14. also contributes. As a result, a semiconductor optical device with excellent high-speed response can be provided.

Furthermore, since the buried layer 30 includes the second semiconductor layer 26, the recess 32 can be easily manufactured. As will be explained in detail in the manufacturing method described later, since the second semiconductor layer 26 is made of a different material from the first semiconductor layer 24 and the third semiconductor layer 28, it functions as an etching stop layer when forming the recess 32.

In this embodiment, the second semiconductor layer 26 functioning as an etching stop layer is not disposed below the mesa stripe structure 14. Since no layer having a different band gap is included between the convex portion 12 below the multi-quantum well layer 20 and the semiconductor layer 10, there is no electrical influence.

Light guided around the multiple quantum well layer 20 spreads to the buried layer 30. If the second semiconductor layer 26 is close to the mesa stripe structure 14, it may have an optical influence. Therefore, it is desirable that the second semiconductor layer 26 be located at a distance of 300 nm or more from the side surface of the multiple quantum well layer 20. Further, in order for the second semiconductor layer 26 to function as an etching stop layer while suppressing the influence on optical properties, the thickness of the second semiconductor layer 26 is preferably 5 nm or less.

The thicker the resin layer 34 is, the more parasitic capacitance caused by the pad electrode 46 can be reduced. However, when the resin layer 34 rises from the buried layer 30 around the recess 32, a large step (height difference) occurs between the pad electrode 46 and the mesa electrode 42. As a result, there is a possibility that electrode discontinuity (step breakage) may occur in the extraction electrode 44. Therefore, in order to thicken the resin layer 34 so as not to bulge, it is desirable to make the recess 32 deep. The depth of the recess 32 is determined by the position of the second semiconductor layer 26. As one guideline, it is preferable that the second semiconductor layer 26 be disposed on the upper surface of the semiconductor layer 10 (excluding the convex portions 12) lower than the lower end of the multiple quantum well layer 20.

As described above, semiconductor optical devices can maintain reliability, which is an advantage of a buried structure, while reducing capacitive components without affecting optical or electrical characteristics. Contributes to faster speeds.

[Production method]
5 to 12 are diagrams illustrating a method for manufacturing a semiconductor optical device according to the first embodiment. In this embodiment, the semiconductor layer 10 is prepared in the form of a wafer in order to manufacture a semiconductor optical device with multiple layers.

As shown in FIG. 5, a semiconductor multilayer including a multiple quantum well layer 20 and an upper cladding layer 22 is formed on the semiconductor layer 10. The formation method may be MOCVD (Metal Organic Chemical Vapor Deposition) or another method. Further, an etching mask 48 is formed to cover a region that will become the mesa stripe structure 14.

As shown in FIG. 6, the area not covered by the etching mask 48 is etched to form the mesa stripe structure 14. Here, a portion of the semiconductor layer 10 is also etched to form the convex portion 12.

As shown in FIG. 7, first semiconductor layers 24 are formed on both sides of the mesa stripe structure 14 on the semiconductor layer 10. As shown in FIG. The constituent material of the first semiconductor layer 24 was InP. The formation method may be MOCVD or another method. The first semiconductor layer 24 is formed on the top surface of the semiconductor layer 10 and the side surfaces of the mesa stripe structure 14 . The side surface of the first semiconductor layer 24 rising along the mesa stripe structure 14 is tilted upward so as to approach the mesa stripe structure 14 .

As shown in FIG. 8, a second semiconductor layer 26 is formed on the first semiconductor layer 24. The constituent material of the second semiconductor layer 26 was InGaAs. The formation method may be MOCVD or another method. The second semiconductor layer 26 is formed along the surface shape of the first semiconductor layer 24. Since the second semiconductor layer 26 is very thin compared to the first semiconductor layer 24, it does not reach the top of the mesa stripe structure 14.

As shown in FIG. 9, a third semiconductor layer 28 is formed on the second semiconductor layer 26. The constituent material of the third semiconductor layer 28 was InP. The formation method may be MOCVD or another method. The crystal growth is performed until the third semiconductor layer 28 becomes higher than the mesa stripe structure 14, but may be stopped at the same height as the mesa stripe structure 14.

The first semiconductor layer 24 and the third semiconductor layer 28 are in contact next to the upper end of the mesa stripe structure 14 . Since both are made of the same InP, the interface cannot actually be seen clearly. Therefore, although the interface between the two is not illustrated in FIG. 2, the interface between the two is illustrated in FIG. 9 for explanation.

The second semiconductor layer 26 may be adjacent to the upper end of the mesa stripe structure 14 and completely cover the first semiconductor layer 24 . In that case, the first semiconductor layer 24 and the third semiconductor layer 28 are not in contact with each other, but this does not affect the characteristics of the semiconductor optical device. After that, the etching mask 48 is removed.

As shown in FIG. 10, an etching mask 50 is formed. The etching mask 50 covers the upper end surface of the mesa stripe structure 14 and the third semiconductor layer 28, except for the region that will become the recess 32.

As shown in FIG. 11, etching is performed to remove a portion of the third semiconductor layer 28. The constituent material of the third semiconductor layer 28 is InP. The constituent material of the second semiconductor layer 26 is different from InP, and by using selective etching, etching can be stopped at the surface of the second semiconductor layer 26. A recess 32 is formed by etching. The depth of the recess 32 (the position of the bottom surface) is exactly the surface of the second semiconductor layer 26. The material of the second semiconductor layer 26 may be InGaAs, InGaAsP, or InGaAlAs. After that, the etching mask 50 is removed.

As shown in FIG. 12, an inorganic insulating film 36 is formed over the entire surface including the recesses 32. The inorganic insulating film 36 covers all of the upper end of the buried layer 30, the inner surface of the recess 32, and the upper end surface of the mesa stripe structure 14. Thereafter, a resin layer 34 is formed in the recess 32. The resin layer 34 is formed higher than the inorganic insulating film 36.

The inorganic insulating film 36 is removed from the upper end surface of the mesa stripe structure 14 (through-hole formation), and a second electrode 40 is formed (see FIG. 2). A first electrode 38 is formed on the lower surface (back surface) of the semiconductor layer 10. Thereafter, a semiconductor optical device is obtained through a step of cleaving the semiconductor wafer.

[Second embodiment]
FIG. 13 is a plan view of a semiconductor optical device according to the second embodiment. FIG. 14 is a sectional view taken along the line XIV-XIV of the semiconductor optical device shown in FIG. 13.

An inorganic spacer 252 is interposed between the pad electrode 246 and one of the pair of resin layers 234. The inorganic spacer 252 is made of silicon nitride, for example, and has higher adhesion to the pad electrode 246 than the resin layer 234. The inorganic spacer 252 has the effect of moving the pad electrode 246 away from the first electrode 238 and further reducing the parasitic capacitance caused by the pad electrode 246. The inorganic spacer 252 is larger than the pad electrode 246 in plan view. The inorganic spacer 252 also overlaps a part of the extraction electrode 244.

The end portion of the inorganic spacer 252 may overlap the mesa electrode 242, or may extend above the buried layer 230 adjacent to the mesa stripe structure 214. If parts of the extraction electrode 244 and mesa electrode 242 overlap with the inorganic spacer 252, parasitic capacitance caused by the electrodes in these regions can be reduced. Conversely, the inorganic spacer 252 may be smaller than the pad electrode 246, but the effect of reducing parasitic capacitance caused by the pad electrode 246 will be weaker.

A portion of the mesa electrode 242 is on the pair of resin layers 234. Therefore, the parasitic capacitance caused by the mesa electrode 242 can be reduced. Since the mesa electrode 242 is larger than in the first embodiment, the parasitic capacitance is increased, but the tolerance against positional deviation is high and the productivity is excellent. The thin mesa electrode 242 may be displaced from the upper end surface of the mesa stripe structure 214 due to the alignment accuracy of the photomask during manufacturing.

[Third embodiment]
FIG. 15 is a plan view of a semiconductor optical device according to the third embodiment. FIG. 16 is a cross-sectional view taken along the line XVI-XVI of the semiconductor optical device shown in FIG. 15. FIG. 17 is a sectional view taken along the line XVII-XVII of the semiconductor optical device shown in FIG.

The semiconductor optical device is a modulator integrated semiconductor laser, and includes an EA modulator 354 and a semiconductor laser 356, both of which are integrally integrated.

The semiconductor optical device has a mesa stripe structure 314 spanning both a semiconductor laser 356 and an EA modulator 354. Semiconductor laser 356 includes a portion of mesa stripe structure 314. The semiconductor laser 356 emits continuous light toward the EA modulator 354. A dielectric high reflection film (not shown) is formed on the rear end face 316 of the semiconductor optical device located behind the semiconductor laser 356 (on the opposite side from the EA modulator 354), but a low reflection film may be formed thereon. do not have.

The semiconductor laser 356 may be any of a DFB (Distributed Feedback) laser, an FP (Fabry-Perot) laser, a DBR (Distributed Bragg Reflector) laser, and a DR (Distributed Reflector) laser, and has a 1.3 μm band or a 1.55 μm band. It is designed to oscillate in the band. However, the wavelength band is not limited to this, and other wavelength bands may be used.

The semiconductor laser 356 includes a multiple quantum well layer 320 and a diffraction grating layer 358 provided thereon. An upper cladding layer 322 is provided on the diffraction grating layer 358, and a cladding layer is also interposed between the diffraction gratings. Optical confinement layers (not shown) are provided above and below the multiple quantum well layer 320, respectively, and a contact layer (not shown) is provided above the upper cladding layer 322. Semiconductor laser 356 has a laser electrode 360. By applying a voltage between the laser electrode 360 and the first electrode 338, the semiconductor laser 356 oscillates continuous light.

The semiconductor laser 356 does not have a recess 332 in the buried layer 330. Since direct current is injected into the semiconductor laser 356, parasitic capacitance is not a problem. In fact, from the viewpoint of heat dissipation, it is preferable that the side surfaces of the mesa stripe structure 314 are all made of a buried layer 330 made of semiconductor. In addition, since the second semiconductor layer 326 has a thickness of 5 nm or less, it has almost no effect on the function of the semiconductor laser 356.

EA modulator 354 includes another portion of mesa stripe structure 314. The mesa stripe structure 314 is shifted from the center position of the semiconductor optical device in the second direction D2 in order to downsize the semiconductor optical device. The pad electrode 346 of the EA modulator 354 requires a certain amount of area for wire bonding. One electrode is sufficient for wire bonding, and a wide electrode is not required on the opposite side of the mesa stripe structure 314. Therefore, by making the left region smaller compared to the first embodiment, the semiconductor optical device is miniaturized. Accordingly, the number of elements that can be obtained from one semiconductor wafer can be increased, and costs can be reduced.

Note that the structure of the semiconductor optical device shown in the second embodiment may be applied to the EA modulator 354 of the third embodiment. The other configurations are the same as the semiconductor optical device shown in the first embodiment except that the mesa stripe structure 314 is not located at the center in the second direction D2.

[Overview of embodiment]
(1) A semiconductor layer 10 having a convex portion 12 on its upper surface, the convex portion 12 extending in a stripe shape in the first direction D1 and forming a lower end portion of the mesa stripe structure 14; and the convex portion of the semiconductor layer 10. a multi-quantum well layer 20 extending in the first direction D1 on top of the mesa stripe structure 12 and constituting another part of the mesa stripe structure 14; 14, a pair of second semiconductor layers 26 on the upper surface of the semiconductor layer 10 on both sides of the convex portion 12 in the second direction D2, and a pair of resin layers 34 above the second semiconductor layer 26; A pair of third semiconductor layers 28 different in constituent material from the second semiconductor layer 26, a first electrode 38 on the lower surface of the semiconductor layer 10, a mesa electrode 42 on the upper end surface of the mesa stripe structure 14, a second electrode 40 including an extraction electrode 44 extending from the mesa electrode 42 in the second direction D2; and a pad electrode 46 located above one of the pair of resin layers 34 and connected to the extraction electrode 44; A semiconductor optical device having

In addition to the pair of first semiconductor layers 24, the pair of second semiconductor layers 26, and the pair of third semiconductor layers 28, the pair of resin layers 34 can reduce parasitic capacitance. Further, the pair of third semiconductor layers 28 are different from the pair of second semiconductor layers 26 in their constituent materials. Therefore, it becomes easy to stop the etching of the pair of third semiconductor layers 28 at the pair of second semiconductor layers 26 located therebelow. Thereby, variations in the height of the base of the pair of resin layers 34 can be suppressed, and high reliability can be ensured.

(2) The semiconductor optical device described in (1), wherein the pair of first semiconductor layers 24, the pair of second semiconductor layers 26, and the pair of third semiconductor layers 28 are the multiple quantum well layers. 20 buried layers 30, the buried layer 30 has a pair of recesses 32, and the pair of resin layers 34 are respectively disposed in the pair of recesses 32.

(3) In the semiconductor optical device described in (1) or (2), each of the pair of third semiconductor layers 28 can be viewed from any circumferential direction including the first direction D1 and the second direction. A semiconductor optical device surrounding a corresponding one of the pair of resin layers 34.

(4) In the semiconductor optical device according to any one of (1) to (3), each of the pair of third semiconductor layers 28 has at least one of the first direction D1 and the second direction. A semiconductor optical device having one side surface exposed.

(5) The semiconductor optical device according to any one of (1) to (4), wherein each of the pair of first semiconductor layers 24 extends below the pair of second semiconductor layers 26. and a semiconductor optical device in contact with the upper surface of the semiconductor layer 10.

(6) The semiconductor optical device according to any one of (1) to (5), wherein each of the pair of second semiconductor layers 26 has a corresponding one of the pair of first semiconductor layers 24. and a corresponding one of the pair of resin layers 34.

(7) The semiconductor optical device according to any one of (1) to (6), in which the pair of first semiconductor layers 24 is made of the constituent material of the pair of second semiconductor layers 26. and different semiconductor optical devices.

(8) In the semiconductor optical device according to any one of (1) to (7), the pair of third semiconductor layers 28 are different from the pair of first semiconductor layers 24 in the constituent material. Semiconductor optical devices are the same.

(9) The semiconductor optical device described in (8), wherein each of the pair of third semiconductor layers 28 is continuous with a corresponding one of the pair of first semiconductor layers 24.

(10) The semiconductor optical device according to any one of (1) to (9), in which each of the pair of resin layers 34 and a corresponding one of the pair of second semiconductor layers 26 A semiconductor optical device further comprising an inorganic insulating film 36 interposed therein.

(11) In the semiconductor optical device described in (10), the inorganic insulating film 36 is also provided between each of the pair of resin layers 34 and a corresponding one of the pair of first semiconductor layers 24. Intervening semiconductor optical device.

(12) In the semiconductor optical device described in (10) or (11), the inorganic insulating film 36 is connected to each of the pair of resin layers 34 and a corresponding one of the pair of third semiconductor layers 28. Semiconductor optical devices also exist between them.

(13) The semiconductor optical device according to any one of (1) to (12), in which the pair of first semiconductor layers 24 are made of a semi-insulating semiconductor.

(14) A semiconductor optical device according to any one of (1) to (13), in which the pair of second semiconductor layers 26 are made of an intrinsic semiconductor.

(15) The semiconductor optical device according to any one of (1) to (14), wherein an inorganic spacer 252 is interposed between the pad electrode 246 and the one of the pair of resin layers 234. A semiconductor optical device further comprising.

(16) The semiconductor optical device according to any one of (1) to (15), in which the upper surface of the semiconductor layer 10, except for the convex portion 12, is formed of the multi-quantum well layer 20. Semiconductor optical device lower than the bottom end.

(17) The semiconductor optical device according to any one of (1) to (16), in which a part of the mesa electrode 242 is on the pair of resin layers 234.

(18) In the semiconductor optical device according to any one of (1) to (17), the pair of resin layers 34 are arranged at a height from the top surface of the semiconductor layer 10. A semiconductor optical device higher than the first semiconductor layer 24.

(19) The semiconductor optical device according to any one of (1) to (18), wherein the semiconductor optical device is an electroabsorption modulator.

(20) A semiconductor optical device according to (19), further comprising a semiconductor laser 356, in which the electroabsorption modulator 354 and the semiconductor laser 356 are integrally integrated. A semiconductor optical device.

The present invention is not limited to the embodiments described above, and various modifications are possible. For example, the configuration described in the embodiment can be replaced with a configuration that is substantially the same, has the same effect, or can achieve the same purpose.

10 semiconductor layer, 12 convex portion, 14 mesa stripe structure, 16 rear end face, 18 front end face, 20 multiple quantum well layer, 22 upper cladding layer, 24 first semiconductor layer, 26 second semiconductor layer, 28 third semiconductor layer, 30 buried layer, 32 recess, 34 resin layer, 36 inorganic insulating film, 38 first electrode, 40 second electrode, 42 mesa electrode, 44 extraction electrode, 46 pad electrode, 48 etching mask, 50 etching mask, 214 mesa stripe structure , 230 buried layer, 234 resin layer, 238 first electrode, 242 mesa electrode, 244 extraction electrode, 246 pad electrode, 252 inorganic spacer, 314 mesa stripe structure, 316 rear end surface, 320 multiple quantum well layer, 322 upper cladding layer, 326 second semiconductor layer, 330 buried layer, 332 recess, 338 first electrode, 346 pad electrode, 354 EA modulator, 356 semiconductor laser, 358 diffraction grating layer, 360 laser electrode, D1 first direction, D2 second direction.

Claims (20)

a semiconductor layer having a convex portion on an upper surface, the convex portion extending in a stripe shape in a first direction and forming a lower end portion of a mesa stripe structure;
a multi-quantum well layer extending in the first direction over the convex portion of the semiconductor layer and forming another part of the mesa stripe structure;
a pair of first semiconductor layers each contacting the mesa stripe structure on both sides of a second direction perpendicular to the first direction;
a pair of second semiconductor layers located on the upper surface of the semiconductor layer on both sides of the convex portion in the second direction;
a pair of resin layers above the pair of second semiconductor layers;
a pair of third semiconductor layers located on the pair of second semiconductor layers, each located around a corresponding one of the pair of resin layers, and having a different constituent material from the pair of second semiconductor layers;
a first electrode on the lower surface of the semiconductor layer;
A mesa electrode on the upper end surface of the mesa stripe structure, an extraction electrode extending from the mesa electrode in the second direction, and a pad electrode located above one of the pair of resin layers and connected to the extraction electrode. a second electrode comprising;
A semiconductor optical device having The semiconductor optical device according to claim 1,
The pair of first semiconductor layers, the pair of second semiconductor layers, and the pair of third semiconductor layers constitute a buried layer of the multiple quantum well layer,
The buried layer has a pair of recesses,
In the semiconductor optical device, the pair of resin layers are respectively disposed in the pair of recesses. The semiconductor optical device according to claim 1,
In the semiconductor optical device, each of the pair of third semiconductor layers surrounds the corresponding one of the pair of resin layers from all circumferential directions including the first direction and the second direction. The semiconductor optical device according to claim 1,
Each of the pair of third semiconductor layers has a side surface exposed in at least one of the first direction and the second direction. The semiconductor optical device according to claim 1,
In the semiconductor optical device, each of the pair of first semiconductor layers extends below the pair of second semiconductor layers and is in contact with the upper surface of the semiconductor layer. The semiconductor optical device according to claim 1,
Each of the pair of second semiconductor layers extends between a corresponding one of the pair of first semiconductor layers and a corresponding one of the pair of resin layers. The semiconductor optical device according to claim 1,
In the semiconductor optical device, the pair of first semiconductor layers are different from the pair of second semiconductor layers in the constituent material. The semiconductor optical device according to claim 1,
In the semiconductor optical device, the pair of third semiconductor layers are made of the same constituent material as the pair of first semiconductor layers. The semiconductor optical device according to claim 8,
In the semiconductor optical device, each of the pair of third semiconductor layers is continuous with a corresponding one of the pair of first semiconductor layers. The semiconductor optical device according to claim 1,
The semiconductor optical device further includes an inorganic insulating film interposed between each of the pair of resin layers and a corresponding one of the pair of second semiconductor layers. The semiconductor optical device according to claim 10,
In the semiconductor optical device, the inorganic insulating film is also interposed between each of the pair of resin layers and a corresponding one of the pair of first semiconductor layers. The semiconductor optical device according to claim 10,
In the semiconductor optical device, the inorganic insulating film is also interposed between each of the pair of resin layers and a corresponding one of the pair of third semiconductor layers. The semiconductor optical device according to claim 1,
The pair of first semiconductor layers is a semiconductor optical device made of a semi-insulating semiconductor. The semiconductor optical device according to claim 1,
The pair of second semiconductor layers is a semiconductor optical device made of an intrinsic semiconductor. The semiconductor optical device according to claim 1,
A semiconductor optical device further comprising an inorganic spacer interposed between the pad electrode and the one of the pair of resin layers. The semiconductor optical device according to claim 1,
In the semiconductor optical device, the upper surface of the semiconductor layer, excluding the convex portion, is lower than the lower end of the multiple quantum well layer. The semiconductor optical device according to claim 1,
A semiconductor optical device in which a part of the mesa electrode is located on the pair of resin layers. The semiconductor optical device according to claim 1,
In the semiconductor optical device, the pair of resin layers are higher in height from the upper surface of the semiconductor layer than the pair of first semiconductor layers. The semiconductor optical device according to claim 1,
The semiconductor optical device is an electro-absorption modulator. The semiconductor optical device according to claim 19,
further comprising a semiconductor laser;
A semiconductor optical device that is a modulator-integrated semiconductor laser in which the electro-absorption modulator and the semiconductor laser are integrally integrated.

Images