CN112350145B

CN112350145B - Buried semiconductor optical device and method for manufacturing the same

Info

Publication number: CN112350145B
Application number: CN202010607549.2A
Authority: CN
Inventors: 三泷雅俊
Original assignee: Langmeitong Japan Co ltd
Current assignee: Langmeitong Japan Co ltd
Priority date: 2019-08-06
Filing date: 2020-06-29
Publication date: 2022-12-27
Anticipated expiration: 2040-06-29
Also published as: CN112350145A

Abstract

A buried semiconductor optical device includes a semiconductor substrate having a pair of grooves extending in a first direction. The upper surface of the buried layer has a first region adjacent to the mesa strip structure, overlapping a corresponding one of the pair of grooves, inclined to be raised in the second direction with respect to the mesa strip structure, and on which the passivation film is not formed. The upper surface of the buried layer has a second region that does not overlap with any of the pair of grooves, the second region being flat and higher than the lower end of the first region, and a passivation film is formed on the second region. The upper surface of the buried layer has a connection region between the first region and the second region at the same height as the second region.

Description

Buried semiconductor optical device and method for manufacturing the same

Technical Field

The present invention relates to a buried semiconductor optical device and a method for manufacturing the same.

Background

With the increase in internet and data center traffic, 100Gbps or 400Gbps products are required. This requires that the semiconductor optical device have a high speed capable of operating at 25Gbaud or 56 Gbaud. As a modulator used for optical communication, a buried semiconductor optical device such as an electro-absorption modulator (hereinafter referred to as electro-absorption (EA) modulator) is known.

In the buried EA modulator, an electrode (p-electrode) for applying a voltage to the mesa stripe structure is provided not only directly above the mesa stripe structure but also covering a buried layer. Further, an n-electrode is formed on the back surface of the conductor substrate. A semiconductor region sandwiched between the p-electrode and the n-electrode causes parasitic capacitance. In order to improve the response of the EA modulator at high speed, it is necessary to reduce the parasitic capacitance.

Disclosure of Invention

According to some possible embodiments, a buried semiconductor optical device may include: a semiconductor substrate including a pair of grooves extending in a first direction and including a convex portion extending in a stripe shape in the first direction between the pair of grooves to constitute a lower end of the mesa stripe structure; a quantum well layer extending in a stripe shape in a first direction on the convex portion to constitute a part of the mesa stripe structure; a buried layer disposed on the semiconductor substrate while being adjacent to both sides of the mesa structure in a second direction orthogonal to the first direction to constitute a buried heterostructure; an electrode continuously extending from the upper surface of the mesa strip structure onto the buried layer and contacting the upper surface of the mesa strip structure; and a passivation film interposed between a portion of an upper surface of the buried layer and the electrode, wherein the upper surface of the buried layer includes: a first region adjacent to the mesa strip structure, overlapping a corresponding one of the pair of grooves, inclined to be raised in a second direction with respect to the mesa strip structure, and on which no passivation film is formed; a second region which does not overlap with any of the pair of grooves, is flat, and is higher than a lower end of the first region, and on which a passivation film is formed; and a connection region between the first region and the second region and having the same height as the second region.

According to some possible embodiments, an optical device may include: a semiconductor substrate including a pair of grooves extending in a first direction and including a convex portion extending in a stripe shape in the first direction between the pair of grooves to constitute a lower end of the mesa stripe structure; a quantum well layer extending in a stripe shape in a first direction on the convex portion to constitute a part of the mesa stripe structure; a buried layer disposed on the semiconductor substrate while being adjacent to both sides of the mesa structure in a second direction orthogonal to the first direction to constitute a buried heterostructure; an electrode continuously extending from the upper surface of the mesa strip structure onto the buried layer and contacting the upper surface of the mesa strip structure; and a passivation film interposed between a portion of an upper surface of the buried layer and the electrode, wherein the upper surface of the buried layer includes: a first region adjacent the mesa strip structure and overlapping a respective one of the pair of grooves; a second flat region that does not overlap with any of the pair of grooves; and a connecting region located between the first region and the second flat region.

According to some possible embodiments, a method of manufacturing a buried semiconductor optical device may include: preparing a semiconductor substrate including a pair of grooves extending in a first direction and a convex portion between the pair of grooves, and provided with a mesa stripe structure extending in a stripe shape in the first direction with the convex portion as a lower end portion, wherein the mesa stripe structure includes a quantum well layer extending in a stripe shape on the convex portion, a cladding layer, and a contact layer; forming a buried layer constituting the buried heterostructure by crystal growth to be disposed on the semiconductor substrate while being adjacent to both sides of the mesa structure in a second direction orthogonal to the first direction; forming a passivation film on the second region of the upper surface of the buried layer, and avoiding the first region of the upper surface of the buried layer and the upper surface of the mesa strip structure; and forming an electrode to be in contact with an upper surface of the mesa strip structure and to continuously extend from the upper surface of the mesa strip structure onto the passivation film, wherein a first region is adjacent to the mesa strip structure, overlaps a corresponding one of the pair of grooves, and is inclined to be raised in a second direction with respect to the mesa strip structure, a second region does not overlap any one of the pair of grooves, is flat, and is higher than a lower end of the first region, and the upper surface of the buried layer further includes a connection region between the first region and the second region, which has the same height as the second region.

Drawings

Fig. 1A is a plan view of a buried semiconductor optical device according to a first embodiment.

Fig. 1B is a cross-sectional view taken along line IB-IB of the buried semiconductor optical device shown in fig. 1A.

Fig. 1C is a sectional view taken along an IC-IC of the buried semiconductor optical device shown in fig. 1A.

Fig. 1D is a sectional view taken along line ID-ID of the buried semiconductor optical device shown in fig. 1A.

Fig. 2 is a view showing a process of forming a continuous quantum well layer.

Fig. 3A is a view showing etching of the first continuous quantum well layer.

Fig. 3B is a cross-sectional view taken along line IIIB-IIIB of the structure shown in fig. 3A.

Fig. 4A is a view showing a formation process of a continuous quantum well layer.

FIG. 4B is a cross-sectional view taken along line IVB-IVB of the structure shown in FIG. 4A.

Fig. 5A is a view showing a process of forming a continuous cladding layer.

Fig. 5B is a cross-sectional view taken along line VB-VB of the structure shown in fig. 5A.

Fig. 6A is a view showing an etching mask.

Fig. 6B is a cross-sectional view taken along line VIB-VIB of the structure shown in fig. 6A.

Fig. 6C is a cross-sectional view taken along line VIC-VIC of the structure shown in fig. 6A.

Fig. 7A is a view showing etching.

Fig. 7B is a cross-sectional view taken along line VIIB-VIIB of the structure shown in fig. 7A.

FIG. 7C is a cross-sectional view taken along line VIIC-VIIC of the structure shown in FIG. 7A.

Fig. 8A is a view showing a formation process of a buried layer.

FIG. 8B is a cross-sectional view taken along line VIIIB-VIIIB of the structure shown in FIG. 8A.

Fig. 8C is a cross-sectional view taken along line VIIIC-VIIIC of the structure shown in fig. 8A.

Fig. 9A is a view showing a separation process of the continuous contact layer.

Fig. 9B is a cross-sectional view taken along line IXB-IXB of the structure shown in fig. 9A.

Fig. 10A is a view showing a formation process of a continuous passivation film.

Fig. 10B is a cross-sectional view taken along line XB-XB of the structure shown in fig. 10A.

Figure 10C is a cross-sectional view taken along line XC-XC of the structure shown in figure 10A.

FIG. 10D is a cross-sectional view taken along line XD-XD of the structure shown in FIG. 10A.

Fig. 11A is a view showing etching of a continuous passivation film.

FIG. 11B is a cross-sectional view taken along line XIB-XIB of the structure shown in FIG. 11A.

FIG. 11C is a cross-sectional view taken along line XIC-XIC of the structure shown in FIG. 11A.

FIG. 11D is a cross-sectional view taken along line XID-XID of the structure shown in FIG. 11A.

Fig. 12 is a view showing a process of forming an additional continuous layer in the second embodiment.

Fig. 13A is a view showing a process of patterning an additional continuous layer.

FIG. 13B is a cross-sectional view taken along line XIIIB-XIIIB of the structure shown in FIG. 13A.

FIG. 13C is a cross-sectional view taken along line XIIIC-XIIIC of the structure shown in FIG. 13A.

Fig. 14A is a view showing etching through the mesa mask portion.

Fig. 14B is a cross-sectional view taken along line XIVB-XIVB of the structure shown in fig. 14A.

FIG. 14C is a cross-sectional view taken along line XIVC-XIVC of the structure shown in FIG. 14A.

Fig. 15 is a view illustrating a buried semiconductor optical device according to the related art.

Detailed Description

Hereinafter, some embodiments will be described in detail and with reference to the accompanying drawings. In all the drawings explaining the embodiments, members having the same or the same functions have the same reference numerals, and repeated description thereof will be omitted. The drawings used below are only for explaining examples in the embodiments, and the size of the drawings does not always coincide with the magnification in the examples.

Fig. 1A is a plan view of a buried semiconductor optical device according to a first embodiment. Fig. 1B is a cross-sectional view taken along line IB-IB of the buried semiconductor optical device shown in fig. 1A. Fig. 1C is a sectional view taken along an IC-IC of the buried semiconductor optical device shown in fig. 1A. Fig. 1D is a sectional view taken along line ID-ID of the buried semiconductor optical device shown in fig. 1A.

The semiconductor optical device modulates the emitted continuous light by injecting a driving current into the laser unit 10 through the modulator unit 12 to output signal light. The semiconductor optical device is a modulator-integrated semiconductor optical device (e.g., a modulator-integrated laser) in which a laser unit 10 (e.g., a semiconductor laser) and a modulator unit 12 are integrally integrated. The laser unit 10 is a distributed feedback semiconductor laser (DFB laser). The modulator unit 12 is an electro-absorption modulator (EA modulator). Electro-absorption modulators are widely used due to their small size and low cost, and advantageous characteristics of having low chirp (wave modulation), high extinction ratio (difference between ON level and OFF level of an optical signal), and wide bandwidth. The semiconductor optical device is a DFB laser device integrated with an EA modulator.

The semiconductor optical device has a buried heterostructure (BH structure). The BH structure is a structure having buried layers 16 on both sides of a mesa stripe structure (mesa stripe structure) 14 having an optical waveguide. Since the BH structure has a strong effect of confining light in a lateral direction and has a more circular Far Field Pattern (FFP), the BH structure has an advantage of high coupling efficiency with an optical fiber and also has excellent heat dissipation and is widely used.

The semiconductor optical device has a semiconductor substrate 18 (n-type InP substrate). The semiconductor substrate 18 has a pair of grooves 20 extending in the first direction D1. By forming the pair of grooves 20, no "rabbit ears" are formed, and parasitic capacitance can be reduced. Details will be described in the description of the manufacturing method. The semiconductor substrate 18 has a convex portion 22. The convex portion 22 extends in a bar shape in the first direction D1 between the pair of grooves 20. The raised portion 22 constitutes the lower end portion of the mesa strip structure 14.

As shown in fig. 1D, the mesa tape structure 14 includes a first mesa tape structure 14A for a laser. The first mesa stripe structure 14A includes, in order from the side close to the semiconductor substrate 18 (convex portion 22), a lower light guide layer (InGaAsP layer), a first quantum well layer 24A (active layer), an upper light guide layer (InGaAsP layer), a diffraction grating layer, and a cap layer (p-InP layer).

As shown in fig. 1C, the mesa stripe structure 14 includes a second mesa stripe structure 14B for the modulator. The second mesa stripe structure 14B includes a lower light guide layer (InGaAsP layer), a second quantum well layer 24B (absorption layer), an upper light guide layer (InGaAsP layer), and a cap layer (p-InP layer) in this order from the side close to the semiconductor substrate 18 (convex portion 22).

The semiconductor optical device has a quantum well layer 24. The quantum well layer 24 includes a first quantum well layer 24A for a laser and a second quantum well layer 24B for a modulator. The quantum well layer 24 is made of an intrinsic semiconductor that is not intentionally doped with a p-type or n-type impurity. The quantum well layers 24 form part of the mesa stripe structure 14. The quantum well layers 24 extend in stripe shapes in the first direction D1 on the convex section 22.

The quantum well layer 24 is a Multiple Quantum Well (MQW) layer. When an electric field is applied to the MQW layer, a quantum-confined Stark effect (QCSE) is obtained in which light is shifted toward the long wavelength side at the absorption edge in the MQW layer. The EA modulator modulates light by using QCSE. The MQW layer includes a plurality of strained quantum well layers 24 (InGaAsP) and barrier layers between adjacent quantum well layers 24.

The mesa stripe structure 14 has a cladding layer 26 on the quantum well layers 24. The cladding 26 extends in a stripe shape in the first direction D1. The cladding layer 26 is made of a semiconductor (p-type InP) doped with zinc (Zn), which is a p-type impurity.

The mesa stripe structure 14 includes a contact layer 28. The contact layers 28 are made of p-type InGaAsP layers and p-type InGaAsP, respectively, both of which are doped with p-type impurity (Zn).

The semiconductor optical device has a dummy quantum well layer 30. The dummy quantum well layer 30 is interposed between the buried layer 16 and the semiconductor substrate 18 while avoiding overlapping with the pair of recesses 20. The dummy quantum well layer 30 is made of the same material as the quantum well layer 24, and is uniform in thickness with the quantum well layer 24.

The semiconductor optical device has a dummy cladding 32. Dummy cladding layer 32 is interposed between buried layer 16 and dummy quantum well layer 30. The dummy cladding 32 is made of the same material as the cladding 26 and is smaller in thickness than the cladding 26.

The semiconductor optical device has a buried layer 16. Buried layer 16 is made of a semi-insulating semiconductor material. Buried layer 16 is made of a semiconductor (e.g., inP) doped with iron (Fe) or ruthenium (Ru). Buried layer 16 is disposed on the upper surface of semiconductor substrate 18.

Buried layer 16 constitutes a buried heterostructure. Buried layer 16 is located on semiconductor substrate 18 while being adjacent to both sides of mesa 14 in second direction D2. Buried layer 16 is in direct contact with semiconductor substrate 18 through a pair of recesses 20. Buried layer 16 is in direct contact with dummy cladding 32.

The upper surface of buried layer 16 includes a first region 34. The first region 34 is adjacent to the mesa stripe structure 14. The first region 34 overlaps a respective one of the pair of grooves 20. The first area 34 is inclined so as to rise from the mesa strip structure 14 in the second direction D2. The lower end of the first region 34 is at the same height as the upper surface of the mesa stripe structure 14 (the upper surface of the contact layer 28).

The upper surface of buried layer 16 includes second region 36. The second region 36 does not overlap with any of the pair of grooves 20. The second region 36 overlaps the dummy cladding 32. The second region 36 is flat and higher than the lower end of the first region 34.

The upper surface of buried layer 16 includes a connecting region 38. The connecting region 38 is between the first region 34 and the second region 36. Here, the same height means that the heights in the in-plane distribution of the semiconductor layers by the same wafer process are the same. An area higher than the pair of grooves 20 is formed on the lower layer side (dummy quantum well layer 30 and dummy cladding layer 32) of the second region 36. Therefore, the flat region shown in fig. 15 rises by an amount corresponding to the height H of the apex of the rabbit ear, and a sharp region like the rabbit ear may not be formed.

The semiconductor optical device has a passivation film 40. Buried layer 16 is covered by a passivation film 40. The passivation film 40 has a through hole 42. The upper surface of the mesa strip structure 14 (contact layer 28) is exposed in the via 42, and a portion of the upper surface of the buried layer 16 (first region 34 and connection region 38) is also exposed in the vicinity of the via 42. In the present embodiment, since no rabbit ear is formed, the starting point of the second region 36 can be closer to the mesa stripe structure 14 than in the state of fig. 15. Therefore, the opening width of the through hole 42 can be narrowed.

The passivation film 40 is not formed in the first region 34. The passivation film 40 is not formed in the connection region 38. The passivation film 40 is formed in the second region 36. A passivation film 40 is interposed between a portion of the upper surface of buried layer 16 (second region 36) and electrode 44.

The semiconductor optical device has an electrode 44 (p-electrode). The electrode 44 extends continuously from the upper surface of the mesa strip structure 14 (the top surface of the contact layer 28) to the buried layer 16. The electrode 44 contacts the upper surface of the mesa stripe structure 14 (the top surface of the contact layer 28). The electrode 44 is electrically connected to the contact layer 28 in the via 42. An electrode 44 is disposed on the passivation film 40. The electrodes 44 include a first electrode 44A for the laser and a second electrode 44B for the modulator. In the present embodiment, since no rabbit ear is formed as described above, the opening width of the through hole 42 may be narrowed, and the width of the second electrode 44B may be narrowed accordingly. Furthermore, even if the buried layer 16 is formed thick to form a rabbit ear, the width of the via hole 42 can be reduced, and therefore, the electrode width can be reduced while thickening the buried layer 16 and reducing parasitic capacitance.

The other electrode 46 (n-electrode) is formed on the rear surface of the semiconductor substrate 18. The electrode 46 (n-electrode) faces both the first electrode 44A and the second electrode 44B. The semiconductor optical device has an antireflection film (not shown) on an end face from which light is emitted and a highly reflective film (not shown) on an opposite end face. In the present embodiment, semiconductor substrate 18 is shown as n-type and cladding layer 26 is shown as p-type, but p-type and n-type may be reversed.

Next, a method of manufacturing the buried semiconductor optical device according to the first embodiment will be described.

A semiconductor material (for example, inP) has a characteristic of crystal growth in the (111) plane direction. Thus, as shown in fig. 15, when the height of the mesa stripe structure 514 is exceeded, crystal growth proceeds at an angle of about 55 degrees on both sides thereof. When proceeding to a certain extent, the inclination of the crystal growth is reversed in the direction of the apex, and a protrusion 500 called "rabbit ear" is formed in the buried layer 516. Next to the protrusion 500, the buried layer 516 has a flat region 502.

As a preliminary preparation, a buried semiconductor optical device (dummy element) having a structure that can form "rabbit ears" was prepared, and the height (height H from the flat region 502) and position (horizontal distance D from the mesa strip structure 14 to the apex) of the "rabbit ears" were measured. The dummy component is a component for position confirmation, and may be prepared once at the time of development, and is not necessary at the time of mass production.

Fig. 2 is a view showing a formation process of a continuous quantum well layer. A continuous quantum well layer 124 including a portion to be the quantum well layer 24 is formed on the semiconductor substrate 18 (n-type InP substrate). The continuous quantum well layer 124 includes a first continuous quantum well layer 124A for a laser. The first continuous quantum well layer 124A is included in a continuous multilayer of the laser (not shown).

Specifically, a continuous multilayer for a laser is formed on the semiconductor substrate 18 by a Metal Organic Chemical Vapor Deposition (MOCVD) method. The continuous multilayer for a laser includes, in order from the semiconductor substrate 18 side, a continuous lower light guide layer (InGaAsP layer), a first continuous quantum well layer 124A, a continuous upper light guide layer (InGaAsP layer), a continuous grating layer, and a continuous cap layer (p-InP layer).

The first continuous quantum well layer 124A is formed by using an InGaAsP-based material, but may be formed by using an InGaAlAs-based material.

Fig. 3A is a view illustrating etching of the first continuous quantum well layer. Fig. 3B is a cross-sectional view taken along line IIIB-IIIB of the structure shown in fig. 3A. The laser mask 148 is formed on a continuous multilayer for a laser including the first continuous quantum well layer 124A. A laser mask 148 is formed in the area including the first mesa stripe structure 14A for the laser. The successive multiple layers (first successive quantum well layer 124A) for the laser are etched through the laser mask 148.

Fig. 4A is a view showing a formation process of a continuous quantum well layer. Fig. 4B is a cross-sectional view taken along line IVB-IVB of the structure shown in fig. 4A. The continuous quantum well layer 124 includes a second continuous quantum well layer 124B for the modulator. The second continuous quantum well layer 124B is included in a continuous multilayer of the modulator (not shown).

The successive layers of the modulator are formed by the MOCVD method. The area covered by the laser mask 148 is not multi-layered grown. The continuous multilayer for the modulator includes, in order from the semiconductor substrate 18 side, a continuous lower light guide layer (InGaAsP layer), a second continuous quantum well layer 124B (absorption layer), a continuous upper light guide layer (InGaAsP layer), and a continuous cap layer (p-InP layer). An InGaAlAs-based material may be used for the second continuous quantum well layer 124B.

Then, the laser mask 148 is removed. Although not shown, the continuous cap layer of the laser in the continuous multilayer of the laser is removed and the continuous grating layer is etched to form the diffraction grating.

Fig. 5A is a view showing a formation process of a continuous cladding layer. Fig. 5B is a cross-sectional view taken along line VB-VB of the structure shown in fig. 5A.

On the continuous quantum well layer 124, a continuous cladding layer 126 including a portion to be the cladding layer 26 is formed. A continuous contact layer 128, including what will become part of the contact layer 28, is formed on the continuous cladding layer 126. The continuous cladding layer 126 (p-InP layer) and the continuous contact layer 128 (p-InGaAsP layer and p-InGaAs layer) are formed by crystal growth. The continuous cap layer of the modulator on top of the continuous multilayer of the modulator is substantially integrated with the continuous cladding layer 126.

Fig. 6A is a view showing an etching mask. Fig. 6B is a cross-sectional view taken along line VIB-VIB of the structure shown in fig. 6A. Fig. 6C is a cross-sectional view taken along line VIC-VIC of the structure shown in fig. 6A.

An etch mask 150 having openings corresponding to the pair of grooves 20 is formed on the continuous contact layer 128. The position of the pair of notches 20 is determined by the "rabbit ear" position shown in fig. 15.

Recessed portions 152 corresponding to the pair of grooves 20 are formed in the continuous contact layer 128 and the continuous cladding layer 126 so as not to reach the semiconductor substrate 18 through the etching mask 150. The depth of the recessed portion 152 is equal to the depth of a pair of grooves 20 described later. The depth of a pair of grooves 20 is determined by the height H of the "rabbit ear" obtained from the dummy element shown in fig. 15.

Subsequently, the etching mask 150 is removed so that a portion of the etching mask 150 remains as a mesa mask portion 154 in an area corresponding to the mesa stripe structure 14 (see fig. 7A to 7C).

Fig. 7A is a view showing etching. FIG. 7B is a cross-sectional view taken along line VIIB-VIIB of the structure shown in FIG. 7A. FIG. 7C is a cross-sectional view taken along line VIIC-VIIC of the structure shown in FIG. 7A.

The continuous contact layer 128, the continuous cladding layer 126, the continuous quantum well layer 124, and the semiconductor substrate 18 are etched. The etching is performed with the continuous contact layer 128 covered by the mesa mask portion 154. The etching is performed until a pair of recesses 20 are formed in the semiconductor substrate 18.

A pair of grooves 20 extending in the first direction D1 is formed by etching. The convex portion 22 is formed between the pair of grooves 20. The mesa stripe structure 14 extending in a stripe shape in the first direction D1 is formed with a convex portion 22 as a lower end portion. The mesa stripe structure 14 includes a quantum well layer 24, a cladding layer 26, and a contact layer 28, and the contact layer 28 extends in a stripe shape on the convex portion 22 in the first direction D1.

During the etching process, the lower layer portion of the continuous cladding layer 126 is left as the dummy cladding layer 32 except for the regions corresponding to the pair of grooves 20. Below the dummy cladding 32 is a dummy quantum well layer 30. Here, the height from the bottom of the pair of grooves 20 to the continuous quantum well layer 124 is the same as the height of the dummy element (fig. 15) formed in advance.

Fig. 8A is a view showing a formation process of a buried layer. FIG. 8B is a cross-sectional view taken along line VIIIB-VIIIB of the structure shown in FIG. 8A. Fig. 8C is a cross-sectional view taken along line VIIIC-VIIIC of the structure shown in fig. 8A.

The buried layer 16 constituting the buried heterostructure is formed by crystal growth. Buried layer 16 is formed to overlie semiconductor substrate 18. Buried layer 16 is formed adjacent to both sides of mesa 14 in second direction D2 orthogonal to first direction D1.

Buried layer 16 is formed such that the upper surface includes first region 34. The first region 34 is adjacent to the mesa tape structure 14, overlaps a respective one of the pair of grooves 20, and is inclined higher from the mesa tape structure 14 in the second direction D2. The crystal growth is based on the crystal of the semiconductor substrate 18 under the first region 34.

Buried layer 16 is formed such that the upper surface includes second region 36. The second region 36 does not overlap with any of the pair of grooves 20, is flat, and is higher than the lower end of the first region 34. The crystal growth is based on the crystals of the continuous cladding 126 below the second region 36.

Buried layer 16 is formed such that the upper surface includes a connection region 38. The connecting region 38 is between the first region 34 and the second region 36.

By forming a thick buried layer 16, parasitic capacitance can be reduced. However, due to the formation of the rabbit ears, it may be necessary to position the opening of the through-hole in the flat region 502. As a result, the electrode width becomes wider and the parasitic capacitance increases. However, in the present embodiment, even in the case where the buried layer 16 having the same thickness as the dummy element is formed, the rabbit ear is not formed. This is because the dummy quantum well layer 30, the dummy cladding layer 32, and the like are formed in the region from the vicinity of the apex of the rabbit ear to the outside, the bottom of the outside may be raised from the apex of the rabbit ear, and the second region 36 may be formed from the vicinity of the apex of the rabbit ear. As a result, the start of the flat region can be brought closer to the mesa stripe structure, and the electrode width can be reduced.

Fig. 9A is a view showing a separation process of the continuous contact layer. Fig. 9B is a cross-sectional view taken along line IXB-IXB of the structure shown in fig. 9A.

The mesa mask portion 154 is removed and an insulating mask 156 having an opening or gap is formed between the modulator portion 12 and the laser portion 10. A portion of the continuous contact layer 128 (the portion between the laser portion 10 and the modulator portion 12) is removed through the insulating mask 156. In this way, the continuous contact layer 128 is divided into a contact layer 28A for the laser and a contact layer 28B for the modulator. Thereafter, the insulating mask 156 is removed.

Fig. 10A is a view showing a formation process of a continuous passivation film. Fig. 10B is a cross-sectional view taken along line XB-XB of the structure shown in fig. 10A. Figure 10C is a cross-sectional view taken along line XC-XC of the structure shown in figure 10A. Fig. 10D is a cross-sectional view taken along line XD-XD of the structure shown in fig. 10A. A continuous passivation film 140 is formed over contact layer 28 and buried layer 16.

Fig. 11A is a view showing etching of a continuous passivation film. Fig. 11B is a cross-sectional view taken along line XIB-XIB of the structure shown in fig. 11A. Fig. 11C is a cross-sectional view taken along line XIC-XIC of the structure shown in fig. 11A. FIG. 11D is a cross-sectional view taken along line XID-XID of the structure shown in FIG. 11A.

A via mask 158 is formed on the continuous passivation film 140. The via mask 158 has openings or gaps in the connection regions 38 and the first regions 34 on the upper surface of the buried layers 1 and 6 mesa stripe structures 14 (first mesa stripe structure 14A for the laser and second mesa stripe structure 14B for the modulator).

The continuous passivation film 140 is etched through the via mask 158. The passivation film 40 patterned in this manner remains in the second region 36 on the upper surface of the buried layer 16. The passivation film 40 is formed while avoiding the upper surface of the mesa stripe structure 14. The passivation film 40 is formed while avoiding the connection region 38 and the first region 34 on the upper surface of the buried layer 16. Thereafter, the via mask 158 is removed.

As shown in fig. 1A to 1D, an electrode 44 (p-electrode) is formed. The electrode 44 is formed in contact with the upper surface of the mesa strip structure 14. The electrode 44 is formed to continuously extend from the upper surface of the mesa strip structure 14 onto the passivation film 40. Further, another electrode 46 (n-electrode) is formed on the rear surface of the semiconductor substrate 18.

A method of manufacturing a buried semiconductor optical device according to a second embodiment will be described. The buried semiconductor optical device manufactured according to the present embodiment is the same as the buried semiconductor optical device shown in fig. 1. Prior to the process shown in fig. 5B, the present embodiment is the same as the first embodiment.

Fig. 12 is a view showing a process of forming an additional continuous layer in the second embodiment. An additional continuous layer 260 made of the same material as the continuous cladding layer 126 is formed on the continuous contact layer 128. Fig. 13A is a view showing a process of patterning an additional continuous layer. FIG. 13B is a cross-sectional view taken along line XIIIB-XIIIB of the structure shown in FIG. 13A. FIG. 13C is a cross-sectional view taken along line XIIIC-XIIIC of the structure shown in FIG. 13A.

The additional continuous layer 260 is patterned to avoid the areas corresponding to the mesa stripe structure 14 and the pair of recesses 20. Patterning is performed by etching using the additional mask 262. Etching is performed to leave the continuous contact layer 128. Thereafter, the additional mask 262 is removed.

Fig. 14A is a view showing etching performed through the mesa mask portion. Fig. 14B is a cross-sectional view along line XIVB-XIVB of the structure shown in fig. 14A. FIG. 14C is a cross-sectional view along line XIVC-XIVC of the structure shown in FIG. 14A. The mesa mask portion 154 is formed on the continuous contact layer 128 and in an area corresponding to the mesa stripe structure 14.

Then, the additional continuous layer 260, the continuous contact layer 128, the continuous cladding layer 126, the continuous quantum well layer 124, and the semiconductor substrate 18 are etched until a pair of grooves 20 are formed (see fig. 7A, 7B, and 7C).

The etching is performed with the continuous contact layer 128 covered by the mesa mask portion 154. That is, the mesa stripe structure 14 is not etched. Because a portion of the continuous contact layer 128 (the portion covered by the mesa mask portion 154 but exposed from the additional continuous layer 260) is lower than the additional continuous layer 260, the etch reaches the semiconductor substrate 18 before the lower portion of the additional continuous layer 260. Thus, a pair of grooves 20 is formed in the semiconductor substrate 18. Meanwhile, in the region covered by the additional continuous layer 260, etching is completed so that the lower portion of the continuous cladding layer 126 (the portion to be the dummy cladding layer 32) is left.

Through the above-described process, the structures shown in fig. 7A, 7B, and 7C are obtained. Thereafter, the buried semiconductor optical device can be manufactured by performing the processes shown in fig. 8A and later.

The foregoing disclosure provides illustration and description, but is not intended to be exhaustive or to limit the implementations to the precise form disclosed. Modifications and variations are possible in light of the above disclosure or may be acquired from practice of the implementations.

Even if specific combinations of features are set forth in the claims and/or disclosed in the specification, these combinations are not intended to limit the disclosure of the various embodiments. In fact, many of these features may be combined in ways not specifically recited in the claims and/or disclosed in the specification. Although each dependent claim listed below may directly depend on only one claim, the disclosure of various implementations includes a combination of each dependent claim with every other claim in the claim set.

No element, act, or instruction used herein should be construed as critical or essential unless explicitly described as such. Also, as used herein, the article "a" is intended to include one or more items and may be used interchangeably with "one or more," and further, as used herein, the article "the" is intended to include one or more items related to the article "the" and may be used interchangeably with "one or more," and further, as used herein, the term "group" is intended to include one or more items (e.g., related items, unrelated items, combinations of related and unrelated items, etc.). ) And the phrase "only one" or similar language may be used interchangeably with "one or more" if only one item is intended. In addition, as used herein, the term "having" and the like are intended to be open-ended terms. Further, the phrase "based on" is intended to mean "based, at least in part, on" unless explicitly stated otherwise. Further, as used herein, the term "or" as used in a series is intended to be inclusive and may be used interchangeably with "and/or" unless specifically stated otherwise (e.g., if used in conjunction with "either" or "only one of").

Cross Reference to Related Applications

This application claims priority from japanese patent application No. 2019-144888, filed on 8/6/2019, which is expressly incorporated herein by reference.

Claims

1. A buried semiconductor optical device comprising:

a semiconductor substrate including a pair of grooves extending in a first direction and including a convex portion extending in a stripe shape in the first direction between the pair of grooves to constitute a lower end of the mesa stripe structure;

a quantum well layer extending in a stripe shape in a first direction on the convex portion to constitute a part of the mesa stripe structure;

a buried layer disposed on the semiconductor substrate while being adjacent to both sides of the mesa stripe structure in a second direction orthogonal to the first direction to constitute a buried heterostructure;

an electrode continuously extending from the upper surface of the mesa strip structure onto the buried layer and contacting the upper surface of the mesa strip structure; and

a passivation film interposed between a portion of an upper surface of the buried layer and the electrode,

wherein, the upper surface of buried layer includes:

a first region adjacent to the mesa strip structure, overlapping a corresponding one of the pair of grooves, inclined to be raised in a second direction with respect to the mesa strip structure, and on which no passivation film is formed,

a second region which does not overlap with any of the pair of grooves, which is flat and higher than the lower end of the first region, and on which a passivation film is formed, and

and a connection region between the first region and the second region and having the same height as the second region.

2. A buried semiconductor optical device according to claim 1, wherein the buried layer is made of a semi-insulating semiconductor material.

3. The buried semiconductor optical device of claim 1, wherein a lower end of the first region is at the same height as an upper surface of the mesa stripe structure.

4. The buried semiconductor optical device of claim 1, further comprising:

a dummy quantum well layer interposed between the buried layer and the semiconductor substrate while avoiding overlapping with the pair of grooves, made of the same material as the quantum well layer, and having a thickness equal to the quantum well layer.

5. The buried semiconductor optical device of claim 4, wherein the mesa strip structure comprises:

a cladding layer on the quantum well layer; and

a dummy cladding layer interposed between the buried layer and the dummy quantum well layer, made of the same material as the cladding layer, and having a thickness smaller than the cladding layer.

6. A buried semiconductor optical device according to claim 1, wherein the buried layer is in direct contact with the semiconductor substrate through the pair of recesses.

7. The buried semiconductor optical device of claim 1,

the mesa stripe structure includes a first mesa stripe structure for the laser and a second mesa stripe structure for the modulator,

the quantum well layer includes a first quantum well layer for a laser and a second quantum well layer for a modulator, and

the electrodes include a first electrode for the laser and a second electrode for the modulator.

8. An optical device, comprising:

a buried layer disposed on the semiconductor substrate while being adjacent to both sides of the mesa structure in a second direction orthogonal to the first direction to constitute a buried heterostructure;

wherein, the upper surface of buried layer includes:

a first region adjacent the mesa strip structure and overlapping a respective one of the pair of grooves,

a second flat region that does not overlap with any one of the pair of grooves, an

A connecting region located between the first region and the second flat region.

9. The optical apparatus of claim 8, wherein the buried layer is made of a semi-insulating semiconductor material.

10. The optical device of claim 8, wherein a lower end of the first region is at the same height as an upper surface of the mesa stripe structure.

11. The optical device of claim 8, further comprising:

12. The optical device of claim 11, wherein the mesa stripe structure comprises:

a cladding layer on the quantum well layer; and

13. The optical apparatus of claim 8, wherein the buried layer is in direct contact with the semiconductor substrate through the pair of recesses.

14. The optical device of claim 8,

15. A method of fabricating a buried semiconductor optical device, the method comprising:

preparing a semiconductor substrate including a pair of grooves extending in a first direction and a convex portion between the pair of grooves, and provided with a mesa stripe structure extending in a stripe shape in the first direction, the convex portion serving as a lower end portion, wherein the mesa stripe structure includes a quantum well layer extending in a stripe shape on the convex portion, a cladding layer, and a contact layer;

forming a buried layer constituting the buried heterostructure by crystal growth to be disposed on the semiconductor substrate while being adjacent to both sides of the mesa structure in a second direction orthogonal to the first direction;

forming a passivation film on the second region of the upper surface of the buried layer, and avoiding the first region of the upper surface of the buried layer and the upper surface of the mesa strip structure; and

forming an electrode to contact an upper surface of the mesa strip structure and extend continuously from the upper surface of the mesa strip structure onto the passivation film, wherein.

The first region is adjacent to the mesa strip structure, overlaps a respective one of the pair of recesses, and is inclined to be raised in the second direction relative to the mesa strip structure,

the second region does not overlap with any of the pair of grooves, is flat, and is higher than the lower end of the first region, and

the upper surface of the buried layer further includes a connection region having the same height as the second region between the first region and the second region.

16. The method of claim 15, wherein,

preparing the semiconductor substrate includes:

forming a continuous quantum well layer including a portion to be a quantum well layer on a semiconductor substrate;

forming a continuous cladding layer including a portion to be a cladding layer on the continuous quantum well layer;

forming a continuous contact layer including a portion to be a contact layer on the continuous cladding layer; and

the continuous contact layer, the continuous cladding layer, the continuous quantum well layer, and the semiconductor substrate are etched.

17. The method of claim 16, further comprising:

forming an etching mask having an opening corresponding to the pair of grooves on the continuous contact layer;

forming a concave portion corresponding to the pair of grooves in the continuous contact layer and the continuous cladding layer so as not to reach the semiconductor substrate through the etching mask; and

the etch mask is removed, leaving a portion of the etch mask as a mesa mask portion in the region corresponding to the mesa stripe structure.

18. The method of claim 17, wherein the continuous contact layer, continuous cladding layer, continuous quantum well layer, and semiconductor substrate are etched with the mesa mask portion covering the continuous contact layer until the pair of recesses are formed.

19. The method of claim 16, further comprising:

prior to the etching step, the etching step is carried out,

forming an additional continuous layer of the same material as the continuous cladding layer on the continuous contact layer while avoiding regions corresponding to the mesa stripe structure and the pair of grooves; and

a mesa mask portion is formed on the continuous contact layer in a region corresponding to the mesa stripe structure,

wherein the additional continuous layer, the continuous contact layer, the continuous cladding layer, the continuous quantum well layer, and the semiconductor substrate are etched with the mesa mask partially covering the continuous contact layer until the pair of recesses are formed.

20. The method of claim 16, wherein,

a lower portion of the continuous cladding remains except for regions corresponding to the pair of grooves,

the crystal growth is based on a crystal of the semiconductor substrate under the first region, and

the crystal growth is based on crystals of the continuous cladding layer below the second region.