JP2023147678A - Electro-optic device and electronic apparatus - Google Patents

Abstract

To improve an aperture ratio.SOLUTION: An electro-optic device includes a substrate, a transistor, a capacitive element provided between the substrate and the transistor, a source drain electrode electrically connected to the transistor, a pixel electrode provided corresponding to the transistor, a conductive member that electrically connects the source drain electrode and the pixel electrode, and an insulating member provided between the capacitive element and the conductive member and having a first contact hole. The conductive member, via the first contact hole, is electrically connected to an end of the source drain electrode and is electrically connected to the capacitive element.SELECTED DRAWING: Figure 6

Description

The present disclosure relates to electro-optical devices and electronic equipment.

BACKGROUND ART Electronic devices such as projectors use, for example, electro-optical devices such as liquid crystal display devices that can change optical characteristics for each pixel.

The electro-optical device described in Patent Document 1 includes a substrate, a transistor, a capacitive element provided between the substrate and the transistor, a source electrode electrically connected to the transistor, and a source electrode provided corresponding to the transistor. and a pixel electrode. In Patent Document 1, a capacitive element and a source electrode are electrically connected to each other via a second relay layer provided in the same layer as a gate electrode of a transistor.

JP2020-38248A

In Patent Document 1, it is necessary to provide a plurality of contact holes for electrically connecting the capacitor and the transistor. Therefore, there are problems in that the load on the manufacturing process increases and the aperture ratio decreases.

One embodiment of the electro-optical device of the present disclosure includes a substrate, a transistor, a capacitor provided between the substrate and the transistor, a source/drain electrode electrically connected to the transistor, and a source/drain electrode electrically connected to the transistor. a pixel electrode provided correspondingly, a conductive member electrically connecting the source/drain electrode and the pixel electrode, and an insulator provided between the capacitive element and the conductive member and having a first contact hole. The conductive member is electrically connected to an end of the source/drain electrode and to the capacitive element via the first contact hole.

One aspect of the electronic device of the present disclosure includes the electro-optical device according to the above-described aspect, and a control unit that controls the operation of the electro-optical device.

FIG. 1 is a plan view of an electro-optical device according to a first embodiment. 2 is a sectional view taken along line AA in FIG. 1. FIG. 2 is an equivalent circuit diagram showing the electrical configuration of the element substrate of FIG. 1. FIG. 3 is a plan view showing a part of the element substrate of FIG. 2. FIG. 3 is a cross-sectional view showing a part of the element substrate of FIG. 2. FIG. 3 is a cross-sectional view showing a part of the element substrate of FIG. 2. FIG. 6 is an enlarged sectional view of the first recess shown in FIG. 5. FIG. FIG. 3 is a plan view of a plurality of capacitive elements. FIG. 3 is a plan view of a plurality of transistors in the first embodiment. FIG. 3 is a diagram for explaining the positional relationship in a plan view of a capacitor and a transistor in the first embodiment. FIG. 3 is a plan view of a source-drain electrode and a relay electrode in the same layer as the source-drain electrode. FIG. 3 is a plan view of a data line and a relay electrode in the same layer as the data line. FIG. 2 is a plan view of a constant potential line and a relay electrode in the same layer as the constant potential line. FIG. 7 is a cross-sectional view showing a part of the element substrate in the second embodiment. 1 is a perspective view showing a personal computer that is an example of an electronic device. FIG. 1 is a plan view showing a smartphone, which is an example of an electronic device. FIG. 1 is a schematic diagram showing a projector that is an example of an electronic device.

Hereinafter, preferred embodiments according to the present disclosure will be described with reference to the accompanying drawings. In the drawings, the dimensions and scale of each part are appropriately different from the actual size, and some parts are shown schematically to facilitate understanding. Further, the scope of the present disclosure is not limited to these forms unless there is a statement specifically limiting the present disclosure in the following description.

1. Electro-optical device 1-1. First embodiment 1-1A. Basic Configuration FIG. 1 is a plan view of an electro-optical device 100 according to the first embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. Note that in FIG. 1, illustration of the counter substrate 3 is omitted for convenience of explanation. Further, in the following description, for convenience of explanation, the X-axis, Y-axis, and Z-axis, which are orthogonal to each other, are appropriately used. Further, one direction along the X axis is expressed as an X1 direction, and a direction opposite to the X1 direction is expressed as an X2 direction. Similarly, one direction along the Y axis is expressed as the Y1 direction, and the direction opposite to the Y1 direction is expressed as the Y2 direction. One direction along the Z axis is referred to as the Z1 direction, and the direction opposite to the Z1 direction is referred to as the Z2 direction. Further, hereinafter, viewing in the Z1 direction or the Z2 direction may be referred to as "planar view". Furthermore, in the following description, the X direction is the X1 direction or the X2 direction. The Y direction is the Y1 direction or the Y2 direction. The Z direction is the Z1 direction or the Z2 direction.

The electro-optical device 100 shown in FIGS. 1 and 2 is a transmissive electro-optical device using an active matrix drive method. As shown in FIG. 2, the electro-optical device 100 includes an element substrate 2, a counter substrate 3, a frame-shaped seal member 4, and a liquid crystal layer 5. The element substrate 2, the liquid crystal layer 5, and the counter substrate 3 are arranged in this order in the Z1 direction. In the example shown in FIG. 1, the electro-optical device 100 has a rectangular shape in plan view. Note that the planar shape of the electro-optical device 100 is not limited to the example shown in FIG. 1, and may be circular, for example.

The element substrate 2 is a substrate having a plurality of TFTs (Thin Film Transistors), which will be described later. The element substrate 2 includes a first substrate 21 that is an example of a "substrate," a laminate 22, a plurality of pixel electrodes 25, and a first alignment film 29. Each of the first substrate 21, the laminate 22, the plurality of pixel electrodes 25, and the first alignment film 29 has light-transmitting properties. Although not shown, the element substrate 2 includes a plurality of dummy pixel electrodes arranged in a region surrounding the plurality of pixel electrodes 25 in plan view. In addition, "light transmittance" means transparency to visible light, and preferably means that the transmittance of visible light is 50% or more.

The first substrate 21, the stacked body 22, the plurality of pixel electrodes 25, and the first alignment film 29 are stacked in this order in the Z1 direction. The first substrate 21 is a flat plate that is transparent and insulating. The first substrate 21 is, for example, a glass substrate or a quartz substrate. The laminate 22 includes a plurality of light-transmitting insulating layers and various wirings arranged between the plurality of insulating layers. Details of the first substrate 21 and the laminate 22 will be explained later based on FIGS. 5 to 13. In addition, the pixel electrode 25 has translucency and conductivity. The pixel electrode 25 is used to apply an electric field to the liquid crystal layer 5. The pixel electrode 25 is made of a transparent conductive material such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), and FTO (Fluorine-doped tin oxide). The first alignment film 29 has translucency and insulation properties. The first alignment film 29 aligns liquid crystal molecules contained in the liquid crystal layer 5. The first alignment film 29 is arranged to cover the plurality of pixel electrodes 25 . The material constituting the first alignment film 29 is, for example, polyimide, silicon oxide, or the like.

The counter substrate 3 is a substrate disposed facing the element substrate 2. The counter substrate 3 includes a second substrate 31 having a light-transmitting property, an inorganic insulating layer 32 having a light-transmitting property, a common electrode 33 having a light-transmitting property, and a second alignment film 34 having a light-transmitting property. have Further, although not shown, the counter substrate 3 has a light-shielding section that surrounds the plurality of pixel electrodes 25 in a plan view. Note that "light-shielding property" means light-shielding property against visible light, and preferably means that the transmittance of visible light is less than 50%, more preferably 10% or less.

The second substrate 31, the inorganic insulating layer 32, the common electrode 33, and the second alignment film 34 are stacked in this order in the Z2 direction. The second substrate 31 is a flat plate that is transparent and insulating. The second substrate 31 is, for example, a glass substrate or a quartz substrate. The inorganic insulating layer 32 has translucency and insulating properties, and is made of an inorganic material containing silicon, such as silicon oxide. The common electrode 33 is a counter electrode arranged with the liquid crystal layer 5 in between with respect to the plurality of pixel electrodes 25. The common electrode 33 is used to apply an electric field to the liquid crystal layer 5. The common electrode 33 has translucency and conductivity. The common electrode 33 includes, for example, a transparent conductive material such as ITO, IZO, and FTO. The second alignment film 34 has translucency and insulation properties. The second alignment film 34 aligns liquid crystal molecules included in the liquid crystal layer 5. The material constituting the second alignment film 34 is, for example, polyimide, silicon oxide, or the like.

The seal member 4 is arranged between the element substrate 2 and the counter substrate 3. The seal member 4 is made of, for example, an adhesive containing various curable resins such as epoxy resin. The seal member 4 may include a gap material made of an inorganic material such as glass.

The liquid crystal layer 5 is arranged within a region surrounded by the element substrate 2, the counter substrate 3, and the seal member 4. The optical characteristics of the liquid crystal layer 5 change depending on the electric field. The liquid crystal layer 5 includes liquid crystal molecules having positive or negative dielectric anisotropy. The orientation of the liquid crystal molecules changes depending on the voltage applied to the liquid crystal layer 5.

As shown in FIG. 1, a plurality of scanning line drive circuits 11, a data line drive circuit 12, and a plurality of external terminals 13 are arranged on the element substrate 2. Although not shown, some of the plurality of external terminals 13 are connected to wiring routed from the scanning line drive circuit 11 or the data line drive circuit 12. Further, the plurality of external terminals 13 include terminals to which a common potential is applied. The terminal is electrically connected to the common electrode 33 of the counter substrate 3 via wiring and a conductive material (not shown).

The electro-optical device 100 has a display area A10 that displays an image, and a peripheral area A20 located outside the display area A10 in plan view. A plurality of pixels P arranged in a matrix are provided in the display area A10. A plurality of pixel electrodes 25 are arranged one-to-one for a plurality of pixels P. The above-mentioned common electrode 33 is provided in common for a plurality of pixels P. Furthermore, the peripheral area A20 surrounds the display area A10 in plan view. A scanning line drive circuit 11 and a data line drive circuit 12 are arranged in the peripheral region A20.

In this embodiment, the electro-optical device 100 is of a transmissive type. Specifically, in this embodiment, as shown in FIG. 2, the light LL is incident on the counter substrate 3, and the light LL that has entered the counter substrate 3 is modulated while being emitted from the element substrate 2, thereby creating an image. is displayed. Note that an image may be displayed by modulating the light incident on the element substrate 2 while being emitted from the counter substrate 3.

Further, the electro-optical device 100 is applied to, for example, a display device that performs color display such as a personal computer and a smartphone, which will be described later. When applied to the display device, a color filter is appropriately used for the electro-optical device 100. Further, the electro-optical device 100 is applied to, for example, a projection type projector, which will be described later. In this case, the electro-optical device 100 functions as a light valve. Note that in this case, a color filter is omitted from the electro-optical device 100.

1-1B. Electrical Configuration of Element Substrate 2 FIG. 3 is an equivalent circuit diagram showing the electrical configuration of the element substrate 2 of FIG. 1. As shown in FIG. 3, the element substrate 2 has a plurality of transistors 23, n scanning lines 241, m data lines 242, and n constant potential lines 243. It is provided in the laminate 22 shown in FIG. Each of n and m is an integer of 2 or more. A transistor 23 is arranged corresponding to each intersection between the n scanning lines 241 and the m data lines 242. Each transistor 23 is, for example, a TFT (thin film transistor) that functions as a switching element. Each transistor 23 includes a gate, a source, and a drain.

Each of the n scanning lines 241 extends in the X direction, and the n scanning lines 241 are arranged at equal intervals in the Y direction. Each of the n scanning lines 241 is electrically connected to the gates of the corresponding plurality of transistors 23. The n scanning lines 241 are electrically connected to the scanning line drive circuit 11 shown in FIG. Scanning signals G1, G2, . . . , and Gn are supplied line-sequentially from the scanning line drive circuit 11 to the 1 to n scanning lines 241.

Each of the m data lines 242 shown in FIG. 3 extends in the Y direction, and the m data lines 242 are arranged at equal intervals in the X direction. Each of the m data lines 242 is electrically connected to the sources of the corresponding plurality of transistors 23. The m data lines 242 are electrically connected to the data line drive circuit 12 shown in FIG. Image signals S1, S2, . . . , and Sm are supplied from the data line drive circuit 12 to the 1 to m data lines 242 in parallel.

The n scanning lines 241 and the m data lines 242 shown in FIG. 3 are electrically insulated from each other and arranged in a lattice shape when viewed from above. A region surrounded by two adjacent scanning lines 241 and two adjacent data lines 242 corresponds to a pixel P. Each pixel electrode 25 is electrically connected to the drain of the corresponding transistor 23.

Each of the n constant potential lines 243 extends in the Y direction, and the n constant potential lines 243 are arranged at equal intervals in the X direction. Further, the n constant potential lines 243 are electrically insulated from the m data lines 242 and the n scanning lines 241, and are arranged at intervals from them. A constant potential such as a ground potential is applied to each constant potential line 243. Each of the n constant potential lines 243 is a capacitor line electrically connected to the corresponding capacitor element 26. Each capacitive element 26 is a holding capacitor for holding the potential of the pixel electrode 25, and is arranged to overlap with the transistor 23 in a plan view. Note that the plurality of capacitive elements 26 are electrically connected to the plurality of pixel electrodes 25 on a one-to-one basis. The plurality of capacitive elements 26 are electrically connected to the drains of the plurality of transistors 23 on a one-to-one basis.

When the n scanning lines 241 are sequentially selected by sequentially activating the scanning signals G1, G2, . . . , and Gn, the transistors 23 connected to the selected scanning lines 241 are turned on. Then, image signals S1, S2, . . . , and Sm of sizes corresponding to the gradation to be displayed are transmitted via the m data lines 242 to the pixel electrode 25 of the pixel P corresponding to the selected scanning line 241. applied. As a result, a voltage corresponding to the gradation to be displayed is applied to the liquid crystal capacitor formed between the pixel electrode 25 and the common electrode 33 shown in FIG. 2, and the orientation of the liquid crystal molecules is adjusted according to the applied voltage. Change. Further, the applied voltage is held by the capacitive element 26. Light is modulated by such changes in the orientation of liquid crystal molecules, making it possible to display gradations.

1-1C. Structure of Element Substrate 2 FIG. 4 is a plan view showing a part of the element substrate 2 of FIG. 2. FIG. 4 shows a diagram of the element substrate 2 viewed in the Z2 direction in region B in FIG. As shown in FIG. 4, the plurality of pixel electrodes 25 on the element substrate 2 are spaced apart from each other and arranged in a matrix. In the element substrate 2, a transparent opening A11 is provided for each pixel electrode 25 in a region overlapping the pixel electrode 25 in plan view. Furthermore, a frame-shaped region located between the plurality of openings A11 in plan view is provided on the element substrate 2 as a light-shielding region A12. In the light-shielding region A12, the transistor 23, the capacitive element 26, and various wirings such as the scanning line 241, the data line 242, and the constant potential line 243 shown in FIG. 3 are arranged. Pixel electrode 25 is electrically connected to each of transistor 23 and capacitive element 26 via contact hole CH13.

Each of FIGS. 5 and 6 is a cross-sectional view showing a part of the element substrate 2 of FIG. 2. As shown in FIG. FIG. 5 schematically shows a cross section of region C in FIG. 4 taken along the line C1-C1 along the X direction. FIG. 6 schematically shows a cross section of region C in FIG. 4 taken along the line C2-C2 along the Y direction. Note that the C1-C1 line in FIG. 4 corresponds to the C1-C1 line in FIG. 8, which will be described later, in a plan view, and the C2-C2 line in FIG. 4 corresponds to the C2-C2 line in FIG. 8, which will be described later, in a plan view. corresponds to

As described above, the element substrate 2 includes the first substrate 21, the laminate 22, a plurality of pixel electrodes 25, and the first alignment film 29. Here, as shown in FIGS. 5 and 6, a plurality of capacitive elements 26 are arranged between the first substrate 21 and the laminate 22. Further, inside the stacked body 22, a transistor 23, a scanning line 241, a data line 242, a constant potential line 243, and relay electrodes 271, 272, 273, 274, 275, 276, 277, and 279 are appropriately arranged. Here, the relay electrode 271 is an example of a "source drain electrode." Relay electrode 273 is an example of a "conductive member". Hereinafter, regarding the laminated structure of the element substrate 2, each part of the element substrate 2 will be explained in order based on FIGS. 5 and 6.

The first substrate 21 has a first recess 211, a second recess 212, and a third recess 213, which are examples of "recesses". Each of the first recess 211, the second recess 212, and the third recess 213 is a recess provided in the surface of the first substrate 21 facing the Z1 direction for each transistor 23. These recesses are arranged in the order of the second recess 212, the first recess 211, and the third recess 213 in the X1 direction, and are spaced apart from each other. Here, the first recess 211 extends in the Y direction along the data line 242. On the other hand, each of the second recess 212 and the third recess 213 extends in the X direction along the scanning line 241. In this embodiment, the depths of the first recess 211, the second recess 212, and the third recess 213 in the Z2 direction are equal to each other.

A capacitive element 26 is arranged on the first substrate 21 . Capacitive element 26 includes a first conductive layer 261, a dielectric layer 263, and a second conductive layer 262. The first conductive layer 261, the dielectric layer 263, and the second conductive layer 262 are stacked in this order in the Z1 direction. The first conductive layer 261 contacts the first substrate 21 . Dielectric layer 263 is disposed between first conductive layer 261 and second conductive layer 262 . Note that the first conductive layer 261 and the first substrate 21 may have a light-transmitting layer.

The capacitive element 26 has a shape that follows the shape of the surface of the first substrate 21 facing the Z1 direction. Here, the capacitive element 26 has a portion disposed inside each of the first recess 211 , the second recess 212 , and the third recess 213 . Therefore, the capacitive element 26 has a portion shaped like each of the first recess 211 , the second recess 212 , and the third recess 213 . Since the thickness of each of the first conductive layer 261, dielectric layer 263, and second conductive layer 262 is uniform over the bottom and side surfaces of each recess, a capacitive element 26 with stable characteristics can be obtained.

Such a capacitive element 26 includes a first element section 265, a second element section 266, and a third element section 267. The first element portion 265 is a portion of the capacitive element 26 disposed in the first recess 211. The second element portion 266 is a portion of the capacitive element 26 disposed in the second recess 212. The third element portion 267 is a portion of the capacitive element 26 disposed in the third recess 213.

The material constituting the first conductive layer 261 and the second conductive layer 262 is preferably polysilicon, which has low light-shielding properties and is conductive, but is not limited to this, and metals such as titanium, metal oxides, etc. Alternatively, it may be a metal nitride. The polysilicon contains impurities such as phosphorus (P), for example. For the dielectric layer 263, for example, a silicon nitride film with low light-shielding properties and a high dielectric constant is desirable, but metal oxide films such as aluminum oxide, hafnium oxide, and silicon oxide, metal nitride films such as silicon nitride, or A multilayer film in which these metal oxide films and metal nitride films are laminated may be used.

The thickness of each of the first conductive layer 261 and the second conductive layer 262 is, for example, 0.03 μm or more and 0.2 μm or less. The thickness of the dielectric layer 263 is, for example, 0.01 μm or more and 0.03 μm or less. The thickness of the laminated film consisting of the first conductive layer 261, dielectric layer 263, and second conductive layer 262 is, for example, 0.13 μm or more and 0.26 μm or less. The first conductive layer 261, dielectric layer 263, and second conductive layer 262 can be formed all at once. Further, the thickness of the second conductive layer 262 is preferably greater than the thickness of the first conductive layer 261.

The laminate 22 is arranged on the first substrate 21 so as to cover the capacitive element 26 described above. Laminated body 22 has a plurality of insulating layers 221, 222, 223, 224, 225, 226, 227. These layers are stacked in the Z1 direction in the order of insulating layers 221, 222, 223, 224, 225, 226, and 227. Here, the laminate consisting of the insulating layers 221, 222, 223, and 224 constitutes the insulating member 22a.

The insulating layers 221 to 227 have translucency and insulating properties. The material constituting the insulating layers 221 to 227 is, for example, an inorganic material containing silicon such as silicon oxide or silicon oxynitride. The thickness of each of the insulating layer 221 and the insulating layer 221 is, for example, 0.2 μm or more and 0.6 μm or less. The insulating layer 221 buries the recessed region of the first substrate 21, and the thickness of the embedded region in the Z2 direction is thicker than the other portions.

The insulating layer 221 is arranged on the first substrate 21 so as to cover the capacitive element 26. Here, the insulating layer 221 is arranged so as to fill each recess formed in the capacitive element 26 by the first recess 211 , the second recess 212 , and the third recess 213 . Therefore, the thickness of the insulating layer 221 in the Z direction in the region corresponding to each recess is thicker than the other regions of the insulating layer 221. Depending on the shape of the first recess 211 and the formation conditions of the insulating layer 221, the surface of the insulating layer 221 facing the Z1 direction can have a shape as shown in FIG. 7, which will be described later. It may be flattened by a flattening process such as a method.

A scanning line 241 is arranged between the insulating layer 221 and the insulating layer 222. The scanning line 241 has light shielding properties and conductivity. A semiconductor layer 231 of the transistor 23 is arranged between the insulating layer 222 and the insulating layer 223.

The semiconductor layer 231 has an LDD (Lightly Doped Drain) structure. Specifically, the semiconductor layer 231 has a channel region 231a, a source/drain region 231b, a source region 231c, a lightly doped source/drain region 231d, and a lightly doped source region 231e. Channel region 231a is located between source/drain region 231b and source/drain region 231c. The low concentration source/drain region 231d is located between the channel region 231a and the source/drain region 231b. The low concentration source/drain region 231e is located between the channel region 231a and the source/drain region 231c. The semiconductor layer 231 is made of polysilicon, for example. A region other than the channel region 231a is doped with an impurity that increases conductivity. The impurity concentration in the low concentration source/drain region 231d is lower than the impurity concentration in the source/drain region 231b. The impurity concentration in the low concentration source/drain region 231e is lower than the impurity concentration in the source/drain region 231c. Note that, for example, the low concentration source/drain region 231e may be omitted.

The transistor 23 includes a semiconductor layer 231, a gate electrode 232, and a gate insulating film 233. Gate electrode 232 is arranged between insulating layer 223 and insulating layer 224. Gate insulating film 233 is interposed between gate electrode 232 and channel region 231a of semiconductor layer 231. Here, a region of the insulating layer 223 corresponding to the gate electrode 232 functions as a gate insulating film 233.

The gate insulating film 233 is made of, for example, a silicon oxide film formed by thermal oxidation or chemical vapor deposition (CVD). The gate electrode 232 is formed, for example, by doping polysilicon with an impurity that increases conductivity. Note that the gate electrode 232 may be formed using a conductive material such as a metal, a metal oxide, or a metal compound.

The gate electrode 232 has a portion disposed in each of the contact holes CH1 and CH2 that penetrate the insulating layers 222 and 223, and is connected to the scanning line 241 via the contact holes CH1 and CH2.

In addition to the gate electrode 232, a part of the relay electrode 272 is arranged on the insulating layer 223 as shown in FIG. 5, and a part of the relay electrode 271 is arranged as shown in FIG.

The relay electrode 272 has a portion disposed in a contact hole CH3 that penetrates the insulating layers 221 to 223, and is connected to the second conductive layer 262 of the capacitive element 26 via the contact hole CH3. Relay electrode 271 has a portion disposed in contact hole CH6 penetrating insulating layer 223, and is connected to source/drain region 231b of semiconductor layer 231 via contact hole CH6.

On the insulating layer 224, a part of the relay electrode 275 is arranged as shown in FIG. 5, and a part of the relay electrode 273 and a part of the relay electrode 274 are arranged as shown in FIG.

Relay electrode 275 has a portion disposed in contact hole CH5 penetrating insulating layer 224, and is connected to relay electrode 272 via contact hole CH5. The relay electrode 273 has a portion disposed in a contact hole CH4 that penetrates the insulating member 22a made of the insulating layers 221 to 224, and connects the first conductive layer 261 of the capacitive element 26 and the relay electrode 271 through the contact hole CH4. connected to each. Here, the relay electrode 273 is connected to the end of the relay electrode 271 in the Y2 direction. The end portion includes an end (end surface) of the relay electrode 271 in the Y2 direction and a part of the surface facing the Z1 direction. The relay electrode 274 has a portion disposed in a contact hole CH7 penetrating the insulating layers 223 and 224, and is connected to the source/drain region 231c of the semiconductor layer 231 via the contact hole CH7.

The insulating layer 225 is provided to cover the relay electrodes 273, 274, and 275. As shown in FIGS. 5 and 6, a portion of the relay electrode 276, a portion of the relay electrode 277, and the data line 242 are arranged on the insulating layer 225.

Relay electrode 276 has a portion disposed in contact hole CH8 penetrating insulating layer 225, and is connected to relay electrode 275 via contact hole CH8. Relay electrode 277 has a portion disposed in contact hole CH9 penetrating insulating layer 225, and is connected to relay electrode 273 via contact hole CH9.

As shown in FIG. 6, the data line 242 has a portion disposed in a contact hole CH10 penetrating the insulating layer 225, and is connected to the relay electrode 274 via the contact hole CH10. Thereby, the data line 242 is electrically connected to the source/drain region 231c of the semiconductor layer 231 via the relay electrode 274.

The insulating layer 226 is provided to cover the data line 242 and the relay electrodes 276 and 277. On the insulating layer 226, a part of the constant potential line 243 and a part of the relay electrode 279 are arranged as shown in FIG. 5, and a constant potential line 243 is arranged as shown in FIG.

Constant potential line 243 has a portion disposed in contact hole CH11 penetrating insulating layer 226, and is connected to relay electrode 276 via contact hole CH11. Relay electrode 279 has a portion disposed in contact hole CH12 penetrating insulating layer 226, and is connected to relay electrode 277 via contact hole CH12. Constant potential line 243 is electrically connected to second conductive layer 262 of capacitive element 26 via relay electrodes 276, 275 and relay electrode 272.

The insulating layer 227 is provided to cover the constant potential line 243 and the relay electrode 279. The pixel electrode 25 is arranged on the insulating layer 227.

As shown in FIG. 5, the pixel electrode 25 has a portion disposed in a contact hole CH13 penetrating the insulating layer 227, and is connected to the relay electrode 279 via the contact hole CH13. Thereby, the pixel electrode 25 is electrically connected to the source/drain region 231b of the semiconductor layer 231 via the relay electrodes 279, 277 and the relay electrode 273, and the relay electrode 279, 277, 273 and the relay electrode 271 It is electrically connected to the first conductive layer 261 of the capacitive element 26 via. Further, the first conductive layer 261 of the capacitive element 26 is electrically connected to the source/drain region 231b of the semiconductor layer 231 via relay electrodes 273 and 271.

Examples of materials for forming the scanning line 241, data line 242, and constant potential line 243 include metals such as tungsten (W), titanium (Ti), chromium (Cr), iron (Fe), and aluminum (Al), and titanium. Examples include metal materials such as metal nitrides such as nitride and metal oxides such as tungsten silicide. Further, each of the scanning line 241, the data line 242, and the constant potential line 243 is composed of a single layer or a stack of metal materials. The thickness of the scanning line 241 is, for example, 0.1 or more and 0.4 μm or less. Further, the thickness of each of the data line 242 and the constant potential line 243 is, for example, 0.3 or more and 0.6 μm or less.

Relay electrodes 271, 272, relay electrodes 273, 274, 275, 276, 277, and relay electrode 279 are each made of the same material as gate electrode 232, data line 242, and constant potential line 243.

Although the laminated structure of the element substrate 2 has been described above based on FIGS. 5 and 6, the configurations of various wirings and the like of the element substrate 2 are merely examples, and are not limited to the configurations shown in FIGS. 5 and 6. For example, the scanning line 241 may be provided in a layer above the transistor 23. In this case, a light shielding film having a light shielding property other than the scanning line 241 is arranged between the capacitive element 26 and the transistor 23. The light-shielding film only needs to have light-shielding properties, and may be a wiring or a conductive film insulated from the wiring.

The cross-sectional structure of the first recess 211 and the planar structure of the element substrate 2 will be described in detail below.

FIG. 7 is an enlarged cross-sectional view of the first recess 211 shown in FIG. The first recess 211 includes a bottom surface 2111 and side surfaces 2113. The depth D1 of the first recess 211 is larger than the width W1 of the bottom surface 2111 of the first recess 211. Furthermore, the depth D1 is larger than the width W2 of the opening 2112 of the first recess 211. Note that the depth D1 is the length from the opening 2112 to the bottom surface 2111 in the Z direction. The width W1 is the length of the bottom surface 2111 in the X direction. Further, the width W2 is the length of the opening 2112 in the X direction.

It is preferable that the ratio (D1/W1) between the depth D1 and the width W1 of the first recess 211 is, for example, 1.5 or more. Furthermore, it is preferable that the ratio (D1/W2) between the depth D1 and the width W2 is, for example, 1.4 or more. The specific depth D1 is determined depending on the characteristics of the capacitive element 26, and is not particularly limited, but is, for example, 0.5 μm or more and 2.0 μm or less. The specific width W1 is, for example, 0.2 μm or more and 1.0 μm or less. The specific width W2 is, for example, 0.3 μm or more and 1.5 μm or less.

As shown in FIG. 7, the first element part 265 of the capacitive element 26 has a shape that follows the shape of the first recess 211, and the first element part 265 is provided with a recess caused by the first recess 211. It will be done. The width W3 of the opening 260 of this recess is smaller than the depth D1 of the first recess 211. In the example shown in FIG. 7, the width W3 is smaller than the width W1 of the first recess 211. In the example shown in FIG. However, depending on the inclination angle of the side surface 2113 of the first recess 211 with respect to the bottom surface 2111, the width W3 may be greater than or equal to the width W1. Note that the width W3 is the length of the opening 260 in the X direction. Moreover, each of the above-mentioned widths W1, W2, and W3 may be greater than or equal to the depth D1.

As shown in FIG. 7, the scanning line 241 has a portion 2410 that is recessed toward the first element portion 265 of the capacitive element 26. As shown in FIG. The portion 2410 is provided because a portion of the scanning line 241 is provided on the first recess 211 . Note that the surface of the insulating layer 221 facing the Z1 direction also has a portion recessed toward the first element portion 265.

As shown in FIG. 7, the surface of the insulating layer 222 facing the Z1 direction is a flat surface. By stacking the insulating layer 222, the influence of the first recess 211 is alleviated, so that the surface of the insulating layer 222 in the Z1 direction becomes a flat surface.

FIG. 8 is a plan view of the plurality of capacitive elements 26. FIG. 8 shows the configuration on the first substrate 21 viewed in the Z2 direction, and the configuration on the first substrate 21 is shown by solid lines, and the first recess 211, the second recess 212, and the third recess 213 is indicated by a dashed line.

As described above, the layered film including the first conductive layer 261, the dielectric layer 263, and the second conductive layer 262, and the insulating layer 221 are provided on the surface of the first substrate 21 facing the Z1 direction. As shown in FIG. 8, the first recess 211 has an elongated shape extending in the Y direction in plan view. Each of the second recess 212 and the third recess 213 extends in the X direction. Here, the first recess 211 is located between the second recess 212 and the third recess 213, with an interval from each of the second recess 212 and the third recess 213, in plan view.

The capacitive element 26 has a portion extending in the Y direction, a portion extending in the X direction, and an intersection where these portions intersect. Further, the capacitive element 26 overlaps with the first recess 211, the second recess 212, and the third recess 213 in plan view. Specifically, the capacitive element 26 is provided over a region including the first recess 211, the second recess 212, and the third recess 213 in plan view. A notch 2710 is provided at one end of the capacitive element 26 in the Y2 direction to electrically connect the first conductive layer 261 and the pixel electrode 25, etc., by cutting out the dielectric layer 263 and the second conductive layer 262. It will be done. The notch 2710 and the first recess 211 do not overlap each other in plan view. Further, the end portion of the second conductive layer 262 of the capacitive element 26 in the X1 direction is a portion electrically connected to the constant potential line 243 via the relay electrode 272 etc., and the second recess 212 and It does not overlap any of the third recesses 213.

FIG. 9 is a plan view of the plurality of transistors 23. In FIG. 9, the structure on the insulating layer 223 is shown as seen in the Z2 direction, and the structure on the insulating layer 223 is shown by a solid line, and the structure between the insulating layer 221 and the insulating layer 223 is shown by a broken line. shown.

As described above, on the insulating layer 221, the scanning line 241, the insulating layer 222, the semiconductor layer 231, the insulating layer 223, the gate electrode 232, the relay electrodes 271 and 272, and the insulating layer 224 are provided.

As shown in FIG. 9, the semiconductor layer 231 has a source/drain region 231b, a lightly doped source/drain region 231d, a channel region 231a, a lightly doped source/drain region 231e, and a source/drain region 231c along the Y1 direction in plan view. They are arranged in this order. The width of the semiconductor layer 231 in the X direction is, for example, about 0.3 μm. The semiconductor layer 231 has an elongated shape extending linearly in the Y direction in plan view. Note that the drain electrode forming region of the source/drain region 231b and the source electrode forming region of the source/drain region 231c may be wider than other regions.

The gate electrode 232 overlaps the channel region 231a of the semiconductor layer 231 in plan view. Here, as described above, a part of the gate electrode 232 is arranged in the contact holes CH1 and CH2, and the low concentration source/drain region 231d is located between the contact hole CH1 and the contact hole CH2 in plan view. To position. As a result, the gate electrode 232 blocks light directed toward the low concentration source/drain region 231d in the X1 direction and the X2 direction. Furthermore, the low concentration source/drain region 231d overlaps the scanning line 241 in plan view. As a result, the scanning line 241 blocks light directed toward the low concentration source/drain region 231d in the Z2 direction.

The scanning line 241 extends in the X direction in plan view, and has a width of, for example, 0.5 μm or more and 1 μm or less. Further, the scanning line 241 includes a wide portion that overlaps the semiconductor layer 231 in a plan view, and a protruding portion that extends from the wide portion in the Y1 direction and the Y2 direction. The wide portion and the protrusion are provided over a region that includes the semiconductor layer 231 in plan view. Furthermore, the scanning line 241 is electrically connected to the gate electrode 232 at the wide portion through the contact holes CH1 and CH2.

The relay electrodes 272 are arranged at intervals in the X1 direction with respect to the gate electrode 232 in plan view. A portion of the relay electrode 272 overlaps the scanning line 241 in plan view. The relay electrode 271 is arranged at a distance from the gate electrode 232 in the Y2 direction in plan view.

Relay electrode 271 extends in the Y direction and is connected to relay electrode 273. Here, as described above, a part of the relay electrode 273 is arranged in the contact hole CH4, and the contact hole CH4 is connected to Y2 with respect to the low concentration source drain region 231d and the source drain region 231b of the semiconductor layer 231. Located in the direction. As a result, the relay electrode 273 blocks light directed towards the low concentration source/drain region 231d and the source/drain region 231b in the Y1 direction and a direction slightly inclined therefrom.

FIG. 10 is a diagram for explaining the positional relationship between the capacitive element 26 and the transistor 23 in a plan view. FIG. 10 shows a diagram of the first recess 211, the first element section 265, the scanning line 241, the semiconductor layer 231, and the gate electrode 232 as viewed in the Z2 direction.

The first recess 211 is arranged along the longitudinal direction of the semiconductor layer 231 in plan view, and overlaps the semiconductor layer 231. Therefore, the first element portion 265 of the capacitive element 26 is arranged along the semiconductor layer 231 and overlaps the semiconductor layer 231 in plan view. Further, the portion 2410 of the scanning line 241 overlaps the first recess 211, the first element portion 265, and the low concentration source/drain region 231d in plan view.

In the example shown in FIG. 10, the width W1 of the bottom surface 2111 of the first recess 211 is equal to or less than the width W0 of the source/drain region 231c of the semiconductor layer 231. The width W0 is the length of the source/drain region 231c in the X direction. Furthermore, the width W0 of the source/drain region 231c and the width of the source/drain region 231b are equal to each other. Further, the width W0 of the source/drain region 231c is larger than the width W3 of the opening 260 of the first element section 265 shown in FIG. 7 described above. Note that the width W1 may exceed the width W0. Further, in the example shown in FIG. 10, the width W1 of the bottom surface 2111 of the first recess 211 is smaller than the width of the channel region 231a, but is not limited thereto, and may be greater than or equal to the width of the channel region 231a. Further, the width W0 may be less than or equal to the width W3.

FIG. 11 is a plan view of relay electrodes 273, 274, and 275. In FIG. 11, the structure on the insulating layer 224 is shown as seen in the Z2 direction, and the structure on the insulating layer 224 is shown by a solid line, and the semiconductor layer 231 is shown by a broken line.

As described above, relay electrodes 273, 274, and 275 are provided on the insulating layer 224. The relay electrode 273 overlaps a part of the semiconductor layer 231 in a plan view. Further, the relay electrode 274 overlaps a part of the semiconductor layer 231 in a plan view, and is arranged at a distance from the relay electrode 273 in the Y1 direction. Further, the relay electrode 275 is arranged at a distance from the relay electrode 273 in the X1 direction in a plan view.

Here, as shown in FIG. 11, the relay electrode 273 has a wide portion 246 extending in the Y direction in plan view. The wide portion 246 overlaps the source/drain region 231b and the low concentration source/drain region 231d of the semiconductor layer 231 in plan view. As a result, the wide portion 246 blocks light directed toward the source/drain region 231b and the low concentration source/drain region 231d in the Z2 direction. Further, as described above, a part of the relay electrode 271 is arranged in the contact hole CH6, and the contact hole CH6 is located in the Y2 direction with respect to the low concentration source/drain region 231d and the source/drain region 231b. As a result, the relay electrode 271 blocks light directed toward the source/drain region 231b and the low concentration source/drain region 231d in the Y1 direction.

FIG. 12 is a plan view of the data line 242 and the relay electrodes 276 and 277. FIG. 12 shows a diagram of the structure on the insulating layer 225 viewed in the Z2 direction.

As described above, the data line 242 and the relay electrodes 276 and 277 are provided on the insulating layer 225. As shown in FIG. 12, the relay electrodes 276 are arranged at intervals in the X1 direction with respect to the corresponding data lines 242 in plan view. The relay electrodes 277 are arranged at intervals in the X2 direction with respect to the corresponding data lines 242 in plan view. The data line 242 extends in the Y direction and overlaps the semiconductor layer 231 in plan view. The width of the data line 242 is, for example, 0.5 μm or more and 1 μm or less.

FIG. 13 is a plan view of the constant potential line 243 and the relay electrode 279. FIG. 13 shows a diagram of the structure on the insulating layer 226 viewed in the Z2 direction.

As described above, the constant potential line 243 and the relay electrode 279 are arranged on the insulating layer 226. As shown in FIG. 13, a portion of the constant potential line 243 protrudes in the X1 direction from the corresponding constant potential line 243 in plan view. The relay electrode 279 is arranged at a position in the X2 direction with respect to the corresponding constant potential line 243 in plan view. The constant potential line 243 extends in the Y direction, and overlaps each of the data line 242 and the semiconductor layer 231 in plan view. The width of the constant potential line 243 is, for example, 0.5 μm or more and 1 μm or less.

As described above, the electro-optical device 100 includes the first substrate 21, which is an example of a "substrate," the transistor 23, the capacitor 26, the relay electrode 271, which is an example of a "source-drain electrode," and the pixel electrode 25. , a relay electrode 273 which is an example of a "conductive member", and an insulating member 22a. Capacitive element 26 is provided between first substrate 21 and transistor 23. Relay electrode 271 is electrically connected to transistor 23. The pixel electrode 25 is provided corresponding to the transistor 23. Relay electrode 273 electrically connects relay electrode 271 and pixel electrode 25 . The insulating member 22a is provided between the capacitive element 26 and the relay electrode 273, and has a contact hole CH4 that is an example of a "first contact hole." The relay electrode 273 is electrically connected to the end of the relay electrode 271 and to the capacitive element 26 via the contact hole CH4.

In the electro-optical device 100 described above, the relay electrode 273 is connected to the end surface of the relay electrode 271 via the contact hole CH4 and is also connected to the capacitive element 26. There is no need to provide a contact hole separately from the contact hole for connecting the relay electrode 273 and the capacitive element 26. Therefore, the aperture ratio can be improved.

Further, as described above, the contact hole CH4 does not overlap the transistor 23 in plan view. Therefore, even if the transistor 23 is provided between the layer where the relay electrode 273 is provided and the layer where the capacitive element is provided, the relay electrode 273 and the capacitive element 26 can be connected through the contact hole CH4. Further, the contact hole CH4 can be placed on the side of the transistor 23. As a result, a part of the relay electrode 273 in the contact hole CH4 can be used as a light shield for the transistor 23.

Further, as described above, the transistor 23 includes the gate electrode 232, and the relay electrode 271 is provided in the same layer as the gate electrode 232. Therefore, the relay electrode 271 and the gate electrode 232 can be formed at once in the same film forming process.

Further, as described above, the electro-optical device 100 further includes the data line 242. The data line 242 is electrically connected to the transistor 23 and extends along the X direction, which is an example of the "first direction." Furthermore, the insulating member 22a has a contact hole CH6, which is an example of a "second contact hole." Contact hole CH6 is a contact hole for electrically connecting transistor 23 and relay electrode 271. Contact hole CH4 and contact hole CH6 are arranged along the X direction at positions overlapping data line 242 in plan view. Therefore, the aperture ratio can be increased compared to a configuration in which the contact hole CH4 and the contact hole CH6 are arranged in a direction intersecting the X direction in plan view.

Further, as described above, the transistor 23 includes the semiconductor layer 231, and the semiconductor layer 231 extends along the X direction and overlaps the data line 242 in plan view. Therefore, the data line 242 can be used as a light shield for the semiconductor layer 231.

Further, as described above, the first substrate 21 has the first recess 211, which is an example of a "recess". The first recess 211 extends along the X direction and overlaps the data line 242 in plan view. Then, the capacitive element 26 is provided along the first recess 211. Therefore, it is possible to reduce the size of the capacitive element 26 in a plan view while ensuring the necessary capacity for the capacitive element 26. As a result, the aperture ratio can be increased.

Further, as described above, the electro-optical device 100 further includes the scanning line 241, which is an example of a "light shielding member". The scanning line 241 is provided between the transistor 23 and the capacitive element 26. The contact hole CH6 does not overlap the scanning line 241 in plan view. Therefore, the aperture ratio can be increased compared to a configuration in which the contact hole CH6 overlaps the scanning line 241 in plan view.

1-2. Second Embodiment A second embodiment of the present invention will be described below. In the embodiments illustrated below, for elements whose operations and functions are similar to those in the first embodiment, the reference numerals used in the description of the first embodiment will be used, and detailed descriptions of each will be omitted as appropriate.

FIG. 14 is a sectional view showing a part of the element substrate 2A in the second embodiment. The element substrate 2A is configured similarly to the first embodiment described above, except that the relay electrode 271 is omitted and the transistor 23A is provided instead of the transistor 23.

The transistor 23A is configured similarly to the transistor 23 of the first embodiment except that the semiconductor layer 231 is replaced by a semiconductor layer 231A. The semiconductor layer 231A is configured in the same manner as the semiconductor layer 231 of the first embodiment, except that an extension portion 231f extending the drain region 23b to the contact hole CH4 is added. The extension portion 231f is an example of a "source/drain electrode."

In this embodiment, the contact hole CH4 passes through the extension portion 231f. Relay electrode 273 is connected to the side surface of extension portion 231f via contact hole CH4.

The second embodiment described above can also increase the aperture ratio. In this embodiment, as described above, the relay electrode 273 constitutes a source/drain electrode. Therefore, the number of film formation steps can be reduced compared to a configuration in which source and drain electrodes are provided separately.

2. Modifications The embodiments illustrated above can be modified in various ways. Specific modifications that can be applied to the above-described embodiments are illustrated below. Two or more aspects arbitrarily selected from the examples below may be combined as appropriate to the extent that they do not contradict each other.

In each of the embodiments described above, the electro-optical device 100 of an active matrix type is illustrated, but the drive method of the electro-optical device 100 is not limited to this, and may be, for example, a passive matrix type.

The driving method of the "electro-optical device" is not limited to the vertical electric field method, but may be a transverse electric field method. Note that an example of the transverse electric field method is an IPS (In Plane Switching) mode. Furthermore, examples of the vertical electric field method include TN (Twisted Nematic) mode, VA (Vertical Alignment) mode, PVA mode, and OCB (Optically Compensated Bend) mode.

3. Electronic Device The electro-optical device 100 can be used in various electronic devices.

FIG. 17 is a perspective view showing a personal computer 2000, which is an example of an electronic device. The personal computer 2000 includes an electro-optical device 100 that displays various images, a main body section 2010 in which a power switch 2001 and a keyboard 2002 are installed, and a control section 2003. The control unit 2003 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

FIG. 18 is a plan view showing a smartphone 3000, which is an example of an electronic device. The smartphone 3000 includes an operation button 3001, an electro-optical device 100 that displays various images, and a control unit 3002. The screen content displayed on the electro-optical device 100 is changed in accordance with the operation of the operation button 3001. The control unit 3002 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

FIG. 19 is a schematic diagram showing a projector that is an example of an electronic device. The projection display device 4000 is, for example, a three-panel projector. The electro-optical device 1r is an electro-optical device 100 corresponding to a red display color, the electro-optical device 1g is an electro-optical device 100 corresponding to a green display color, and the electro-optical device 1b is an electro-optical device 100 corresponding to a blue display color. This is an electro-optical device 100 corresponding to. That is, the projection display device 4000 includes three electro-optical devices 1r, 1g, and 1b corresponding to red, green, and blue display colors, respectively. The control unit 4005 includes, for example, a processor and a memory, and controls the operation of the electro-optical device 100.

The illumination optical system 4001 supplies the red component r of the light emitted from the illumination device 4002, which is a light source, to the electro-optical device 1r, the green component g to the electro-optical device 1g, and the blue component b to the electro-optical device 1b. supply to. Each of the electro-optical devices 1r, 1g, and 1b functions as a light modulator such as a light valve that modulates each monochromatic light supplied from the illumination optical system 4001 according to a displayed image. A projection optical system 4003 combines the light emitted from each electro-optical device 1r, 1g, and 1b and projects the combined light onto a projection surface 4004.

The above electronic device includes the electro-optical device 100 described above and a control section 2003, 3002, or 4005. By including the electro-optical device 100 described above, the display quality of the personal computer 2000, smartphone 3000, or projection display device 4000 can be improved.

Note that electronic devices to which the electro-optical device of the present disclosure is applied are not limited to the exemplified devices, and include, for example, PDAs (Personal Digital Assistants), digital still cameras, televisions, video cameras, car navigation devices, and in-vehicle devices. Examples include displays, electronic notebooks, electronic paper, calculators, word processors, workstations, videophones, and POS (Point of Sale) terminals. Furthermore, examples of electronic devices to which the present disclosure is applied include printers, scanners, copiers, video players, devices equipped with touch panels, and the like.

Although the present disclosure has been described above based on the preferred embodiments, the present disclosure is not limited to the above-described embodiments. Further, the configuration of each part of the present disclosure can be replaced with any configuration that exhibits the same function as in the above-described embodiment, or any configuration can be added.

Further, in the above description, a liquid crystal display device was described as an example of the electro-optical device of the present disclosure, but the electro-optical device of the present disclosure is not limited to this. For example, the electro-optical device of the present disclosure can be applied to an image sensor, etc.

1b... Electro-optical device, 1g... Electro-optical device, 1r... Electro-optical device, 2... Element substrate, 2A... Element substrate, 3... Counter substrate, 4... Seal member, 5... Liquid crystal layer, 11... Scanning line drive circuit, 12... Data line drive circuit, 13... External terminal, 21... First substrate (substrate), 22... Laminated body, 22a... Insulating member, 23... Transistor, 23A... Transistor, 23b... Drain region, 25... Pixel electrode, 26 ... Capacitive element, 29... First alignment film, 31... Second substrate, 32... Inorganic insulating layer, 33... Common electrode, 34... Second alignment film, 100... Electro-optical device, 211... First recess (recess), 212... Second recess, 213... Third recess, 221... Insulating layer, 222... Insulating layer, 223... Insulating layer, 224... Insulating layer, 225... Insulating layer, 226... Insulating layer, 227... Insulating layer, 231... Semiconductor Layer, 231A...Semiconductor layer, 231a...Channel region, 231b...Drain region, 231c...Source region, 231d...Low concentration drain region, 231e...Low concentration source region, 231f...Extension portion, 232...Gate electrode, 233...Gate insulation Film, 241... Scanning line (light shielding member), 242... Data line, 243... Constant potential line, 246... Wide portion, 260... Opening, 261... First conductive layer, 262... Second conductive layer, 263... Dielectric layer , 265... First element part, 266... Second element part, 267... Third element part, 271... Relay electrode (source drain electrode), 272... Relay electrode, 273... Relay electrode (conductive member), 274... Relay electrode , 275... Relay electrode, 276... Relay electrode, 277... Relay electrode, 279... Relay electrode, 2000... Personal computer, 2001... Power switch, 2002... Keyboard, 2003... Control unit, 2010... Main unit, 2111... Bottom surface, 2112 ... opening, 2113 ... side, 2410 ... portion, 2710 ... notch, 3000 ... smartphone, 3001 ... operation button, 3002 ... control section, 4000 ... projection type display device, 4001 ... illumination optical system, 4002 ... illumination device, 4003 ...projection optical system, 4004...projection surface, 4005...control unit, A10...display area, A11...opening, A12...shading area, A20...peripheral area, B...area, C...area, CH1...contact hole, CH2... Contact hole, CH3... contact hole, CH4... contact hole (first contact hole), CH5... contact hole, CH6... contact hole (second contact hole), CH7... contact hole, CH8... contact hole, CH9... contact hole, CH10...contact hole, CH11...contact hole, CH12...contact hole, CH13...contact hole, D1...depth, G1...scanning signal, G2...scanning signal, LL...light, P...pixel, S1...image signal, S2... Image signal, W0...width, W1...width, W2...width, W3...width, b...blue component, g...green component, r...red component.

Claims (8)

A substrate and
transistor and
a capacitive element provided between the substrate and the transistor;
a source drain electrode electrically connected to the transistor;
a pixel electrode provided corresponding to the transistor;
a conductive member that electrically connects the source drain electrode and the pixel electrode;
an insulating member provided between the capacitive element and the conductive member and having a first contact hole,
The conductive member is electrically connected to an end of the source/drain electrode and to the capacitive element via the first contact hole.
An electro-optical device characterized by: The first contact hole does not overlap the transistor in plan view;
The electro-optical device according to claim 1. The source drain electrode is provided in the same layer as the gate electrode of the transistor,
The electro-optical device according to claim 1 or 2. a data line electrically connected to the transistor and extending along the first direction;
The insulating member has a second contact hole for electrically connecting the transistor and the source/drain electrode,
The first contact hole and the second contact hole are arranged along the first direction at a position overlapping the data line in a plan view.
The electro-optical device according to claim 1 . The semiconductor layer of the transistor extends along the first direction and overlaps the data line in plan view.
The electro-optical device according to claim 4. The substrate has a recess that extends along the first direction and overlaps the data line in plan view,
The capacitive element is provided along the recess,
The electro-optical device according to claim 4 or 5. comprising a light shielding member provided between the transistor and the capacitor,
the second contact hole does not overlap the light shielding member in plan view;
The electro-optical device according to claim 4 . The electro-optical device according to any one of claims 1 to 7,
An electronic device comprising: a control section that controls the operation of the electro-optical device.

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