JP2023136776A - Ceramic electronic component and manufacturing method thereof - Google Patents

Abstract

To provide a ceramic electronic component and a manufacturing method thereof that can improve bonding between an internal electrode layer and an external electrode.SOLUTION: A ceramic electronic component includes a plurality of dielectric layers containing ceramic as a main component, a laminated chip in which a plurality of internal electrode layers containing Ni as a main component are alternately stacked, that has a substantially rectangular parallelepiped shape, and in which the plurality of internal electrode layers are alternately exposed on two opposing end surfaces of the substantially rectangular parallelepiped shape, and an external electrode that is provided on the two end surfaces, and contains Ni as a main component. The plurality of internal electrode layers include an additive metal element other than Ni and a co-material. The concentration of the additive metal element is higher in the internal electrode layer than in the external electrode.SELECTED DRAWING: Figure 1

Description

The present invention relates to a ceramic electronic component and a method for manufacturing the same.

In addition to the increasing functionality and performance of mobile terminals such as mobile phones and other electronic devices, as well as the increasing capacity of batteries, ceramic electronic components such as multilayer ceramic capacitors, which are one of their component parts, are increasing. However, demands for smaller size and larger capacity continue to increase.

JP2014-082435A JP2013-229555A JP 2018-195799 Publication Japanese Patent Application Publication No. 2014-093516 Japanese Patent Application Publication No. 2014-170911 Japanese Patent Application Publication No. 2013-055314 Japanese Patent Application Publication No. 2002-343669

In order to increase the capacity of ceramic electronic components, measures are being taken such as studying the material composition to increase the dielectric constant of the dielectric material used and making the dielectric layer thinner. It is also an effective means to increase the number of laminated layers by making the internal electrode layers thinner. However, if the internal electrode layer is made thinner, there is a risk that the internal electrode layer will become oversintered and the continuity rate will decrease due to the difference in the densification temperature range between the dielectric layer and the internal electrode layer during the firing process. be. In this case, there is a possibility that the bonding between the internal electrode layer and the external electrode may deteriorate, making it impossible to obtain desired characteristics.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a ceramic electronic component that can improve the bonding properties between an internal electrode layer and an external electrode, and a method for manufacturing the same.

A ceramic electronic component according to the present invention has a substantially rectangular parallelepiped shape in which a plurality of dielectric layers containing ceramic as a main component and a plurality of internal electrode layers containing Ni as a main component are alternately laminated, and the substantially rectangular parallelepiped A laminated chip formed such that the plurality of internal electrode layers are alternately exposed on two opposing end faces, and an external electrode mainly composed of Ni and provided on the two end faces, The internal electrode layer is characterized in that it contains an additive metal element other than Ni and a co-material, and the concentration of the additive metal element is higher in the internal electrode layer than in the external electrode.

In the ceramic electronic component, the additive metal elements include Au, Sn, Cr, Fe, Y, In, As, Co, Cu, Ir, Mg, Os, Pd, Pt, Re, Rh, Ru, Se, Te, It may be one or more selected from Zn and Ge.

In the above ceramic electronic component, the concentration of the additive metal element in the plurality of internal electrode layers may be 0.01 at% or more and 5.0 at% or less based on Ni.

In the above ceramic electronic component, the ratio of the concentration of the added metal element in the external electrode to which the internal electrode layer is connected to the concentration of the added metal element in the internal electrode layer is 0.1 or more and 0.5 or less. It may be.

In the ceramic electronic component, for the plurality of internal electrode layers, the horizontal axis represents the diameter of each of the common materials, and the vertical axis represents the volume distribution (%) such that the total volume of each of the common materials is 100%. ) and connect the 20% value and 80% value of the obtained graph to perform a linear approximation, the slope m may be 3.8 or more and 5.0 or less.

In the above ceramic electronic component, the concentration of the added metal element is within the end margin region where internal electrode layers exposed on the same end face of the multilayer chip face each other without intervening the internal electrode layers exposed on different end faces. The internal electrode layer may be higher than the external electrode.

In the ceramic electronic component, the dielectric layer may have a thickness of 0.8 μm or less.

In the ceramic electronic component, the internal electrode layer may have a thickness of 0.8 μm or less.

In the above ceramic electronic component, the external electrode may contain the additive metal element.

In the above ceramic electronic component, the external electrode may include a common material.

A method for manufacturing a ceramic electronic component according to the present invention is to alternately laminate dielectric green sheets containing ceramic powder and internal electrode patterns containing Ni as a main component metal and co-materials and additive metal elements to form a substantially rectangular parallelepiped. forming a ceramic laminate, exposing the laminated internal electrode patterns alternately on two opposing end faces of the ceramic laminate, disposing a metal paste containing Ni as a main component metal on the two end faces, The ceramic laminate is fired so that the internal electrode layer obtained from the internal electrode pattern has a higher concentration of the metal element than the external electrode obtained from the metal paste.

According to the present invention, it is possible to provide a ceramic electronic component that can maintain bonding between an internal electrode layer and an external electrode, and a method for manufacturing the same.

FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. 2 is a sectional view taken along line BB in FIG. 1. FIG. It is a figure showing the continuity rate of an internal electrode layer. It is a figure which illustrates the volume distribution of a common material. FIG. 3 is a diagram illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. (a) and (b) are diagrams illustrating a lamination process. (a) is a traced SEM photograph of a cross section in the lamination direction of Example 1, and (b) is a traced diagram of a SEM photograph of a cross section in the lamination direction of a comparative example. It is a graph calculated from the diameter and volume distribution of common materials for Example 1 and Comparative Example.

Hereinafter, embodiments will be described with reference to the drawings.

FIG. 1 is a partially cross-sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. FIG. 3 is a sectional view taken along line BB in FIG. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a multilayer chip 10 having a substantially rectangular parallelepiped shape, and external electrodes 20a and 20b provided on two opposing end surfaces of the multilayer chip 10. . Note that, of the four surfaces of the stacked chip 10 other than the two end surfaces, two surfaces other than the upper surface and the lower surface in the stacking direction are referred to as side surfaces. The external electrodes 20a and 20b extend on the top surface, bottom surface, and two side surfaces of the stacked chip 10 in the stacking direction. However, the external electrodes 20a and 20b are spaced apart from each other.

The multilayer chip 10 has a structure in which dielectric layers 11 containing a ceramic material functioning as a dielectric and internal electrode layers 12 mainly composed of metal are stacked alternately. In other words, the stacked chip 10 includes a plurality of internal electrode layers 12 facing each other and a dielectric layer 11 sandwiched between the plurality of internal electrode layers 12. The edges of each internal electrode layer 12 are exposed alternately at the end surface where the external electrode 20a of the stacked chip 10 is provided and the end surface where the external electrode 20b is provided. Thereby, each internal electrode layer 12 is alternately electrically connected to the external electrodes 20a and 20b. As a result, multilayer ceramic capacitor 100 has a structure in which a plurality of dielectric layers 11 are stacked with internal electrode layers 12 in between. Further, in the laminate of the dielectric layer 11 and the internal electrode layer 12, the internal electrode layer 12 is disposed as the outermost layer in the stacking direction, and the top and bottom surfaces of the laminate are covered with a cover layer 13. The cover layer 13 has a ceramic material as its main component. For example, the cover layer 13 may have the same composition as the dielectric layer 11 or may have a different composition.

The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm long, 0.125 mm wide, and 0.125 mm high, or 0.4 mm long, 0.2 mm wide, 0.2 mm high, or long. 0.6mm, width 0.3mm, height 0.3mm, or length 0.6mm, width 0.3mm, height 0.110mm, or length 1.0mm, width 0.5mm, height The length is 0.5 mm, or the length is 1.0 mm, the width is 0.5 mm, and the height is 0.1 mm; or the length is 3.2 mm, the width is 1.6 mm, and the height is 1.6 mm; The size is 4.5 mm, the width is 3.2 mm, and the height is 2.5 mm, but the size is not limited to these.

The dielectric layer 11 has, for example, a ceramic material having a perovskite structure represented by the general formula _ABO3 as a main phase. Note that the perovskite structure includes ABO _3-α that deviates from the stoichiometric composition. For example, the ceramic materials include BaTiO ₃ (barium titanate), CaZrO ₃ (calcium zirconate), CaTiO ₃ (calcium titanate), SrTiO ₃ (strontium titanate), MgTiO ₃ (magnesium titanate), and perovskite structures. Select and use at least one of Ba _1-x-y Ca _x Sry _{Ti 1-z} Zr _z O ₃ (0≦x≦1, 0≦y≦1, 0≦z≦1) to form. be able to. Ba _1-x-y Ca _{x Sry} Ti _1-z Zr _z O ₃ is barium strontium titanate, barium calcium titanate, barium zirconate, barium zirconate titanate, calcium zirconate titanate, and zirconate titanate. Barium calcium, etc.

An additive may be added to the dielectric layer 11. As additives to the dielectric layer 11, molybdenum (Mo), niobium (Nb), tantalum (Ta), tungsten (W), magnesium (Mg), manganese (Mn), vanadium (V), chromium (Cr), Rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm) and ytterbium ( Yb)), or an oxide containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K) or silicon (Si), or Examples include glasses containing Co, Ni, Li, B, Na, K or Si.

The internal electrode layer 12 has Ni as a main component. In addition to Ni, which is the main component, the internal electrode layer 12 contains an additional metal element in a smaller molar ratio than the main component. The additive metal element is not particularly limited as long as it is other than Ni, but examples include gold (Au), tin (Sn), Cr, iron (Fe), yttrium (Y), indium (In), and arsenic ( As), Co, copper (Cu), iridium (Ir), Mg, osmium (Os), palladium (Pd), platinum (Pt), rhenium (Re), rhodium (Rh), ruthenium (Ru), selenium (Se) ), tellurium (Te), zinc (Zn), and germanium (Ge). When there are two or more types of added metal elements, the total molar ratio is smaller than the molar ratio of Ni. Further, the internal electrode layer 12 includes a co-material of ceramic particles. The common material is not particularly limited, but the same material as the main component ceramic of the dielectric layer 11 can be used. For example, as co-materials, BaTiO ₃ (barium titanate), CaZrO ₃ (calcium zirconate), CaTiO ₃ (calcium titanate), SrTiO ₃ (strontium titanate), MgTiO ₃ (magnesium titanate), forming a perovskite structure Select and use at least one of Ba _1-x-y Ca _x Sr _y Ti _1-z Zr _z O ₃ (0≦x≦1, 0≦y≦1, 0≦z≦1), etc. I can do it. Ba _1-x-y Ca _{x Sry} Ti _1-z Zr _z O ₃ is barium strontium titanate, barium calcium titanate, barium zirconate, barium zirconate titanate, calcium zirconate titanate, and zirconate titanate. Barium calcium or the like can be used.

The external electrodes 20a and 20b contain Ni as a main component. In addition to Ni, which is the main component, the external electrodes 20a and 20b may contain the same additive metal element as the internal electrode layer 12 at a smaller molar ratio than the main component. Further, the external electrodes 20a and 20b may contain a co-material of ceramic particles. Furthermore, one or more plating layers may be formed on the surface of the external electrodes 20a, 20b on the side opposite to the stacked chip 10.

As illustrated in FIG. 2, the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region in which capacitance occurs in the multilayer ceramic capacitor 100. . Therefore, the region where the electric capacitance occurs is referred to as a capacitance region 14. That is, the capacitive region 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.

The region where the internal electrode layers 12 connected to the external electrode 20a face each other without interposing the internal electrode layer 12 connected to the external electrode 20b is referred to as an end margin 15. Further, the end margin 15 is also a region where the internal electrode layers 12 connected to the external electrode 20b face each other without interposing the internal electrode layer 12 connected to the external electrode 20a. That is, the end margin 15 is a region where internal electrode layers 12 connected to the same external electrode face each other without interposing the internal electrode layers 12 connected to a different external electrode. The end margin 15 is an area where no capacitance occurs.

As illustrated in FIG. 3, in the stacked chip 10, the area from the two side surfaces of the stacked chip 10 to the internal electrode layer 12 is referred to as a side margin 16. That is, the side margin 16 is a region provided so as to cover the ends of the plurality of stacked internal electrode layers 12 extending toward the two side surfaces in the stacked structure. The side margin 16 is also a region that does not generate capacitance.

The thickness of the internal electrode layer 12 per layer is, for example, 0.2 μm or more and 0.8 μm or less, 0.3 μm or more and 0.8 μm or less, 0.6 μm or more and 0.8 μm or less, 0.8 μm or more and 1.5 μm or less, It is 1.5 μm or more and 4.0 μm or less. The thickness of the internal electrode layer 12 per layer is determined by the average thickness of 10 locations from an image taken with a microscope such as a scanning transmission electron microscope after exposing the cross section of the multilayer ceramic capacitor 100 shown in FIG. 2 by mechanical polishing, for example. It can be measured by calculating the value.

The thickness of the dielectric layer 11 per layer is, for example, 0.2 μm or more and 0.4 μm or less, or 0.4 μm or more and 0.5 μm or less, or 0.4 μm or more and 1.0 μm or less, or It is 1.0 μm or more and 10 μm or less. The thickness of the dielectric layer 11 per layer is determined by the average value of the thickness of 10 points from an image taken with a microscope such as a scanning transmission electron microscope after exposing the cross section of a multilayer ceramic capacitor as shown in FIG. 2 by mechanical polishing. It can be measured by asking for .

In order to reduce the size and increase the capacity of the multilayer ceramic capacitor 100, it is possible to increase the capacitance per unit volume by making the dielectric layer 11 and the internal electrode layer 12 thinner. However, since the sintering temperature of the dielectric layer 11 is higher than that of the internal electrode layer 12, if the internal electrode layer 12 is made thinner, the internal There is a possibility that the continuity rate of the electrode layer 12 may decrease. In particular, the continuity rate of the internal electrode layer 12 may decrease near the external electrodes 20a, 20b. For example, the continuity rate of the internal electrode layer 12 at the end margin 15 may be reduced. When the continuity rate of the internal electrode layer 12 decreases, the bondability between the internal electrode layer 12 and the external electrodes 20a and 20b decreases, resulting in poor conductivity, and there is a possibility that desired characteristics may not be obtained.

FIG. 4 is a diagram showing the continuity rate of the internal electrode layer 12. As illustrated in FIG. 4, in an observation area of length L0 in a certain internal electrode layer 12, the lengths L1, L2, ..., Ln of the metal portions are measured and summed, and the ratio of the metal portion is calculated. ΣLn/L0 can be defined as the continuity rate of the layer.

The multilayer ceramic capacitor 100 according to this embodiment has a configuration that improves the bonding between the internal electrode layer 12 and the external electrodes 20a and 20b.

First, since the internal electrode layer 12 contains the common material, sintering of the internal electrode layer 12 is delayed. In addition, the amount of the co-material remaining in the internal electrode layer 12 can be increased by including a different kind of additive metal element in addition to Ni, which is the main component. This is considered to be because the added metal element segregates around the co-material particles. By using a fine and highly dispersed co-material, the amount of co-material remaining in the internal electrode layer 12 can be particularly increased. Since the co-material added for the purpose of delaying sintering does not diffuse into the dielectric layer 11 during the sintering process and remains in large amounts in the internal electrode layer 12, a sufficient sintering delay effect can be obtained, and the internal electrode layer 12 Continuation rate improves. Furthermore, in the multilayer ceramic capacitor 100 according to the present embodiment, the concentration of the added metal element is higher in the internal electrode layer 12 than in the external electrodes 20a and 20b. With this configuration, the added metal element diffuses from the internal electrode layer 12 toward the external electrodes 20a, 20b, and a flow of the added metal element occurs, thereby improving the bonding property between the internal electrode layer 12 and the external electrodes 20a, 20b. . As a result, a decrease in capacity due to poor connection can be suppressed, and desired capacity and characteristics can be achieved.

It is preferable that there is a difference in the concentration of the added metal element near the external electrode, so in each end margin 15, the concentration of the added metal element is higher in the inner electrode layer 12 connected to the external electrode than in the external electrode. It is preferable that .

When Au, Sn, Cr, Fe, Y, In, As, Co, Cu, Ir, Mg, Os, Pd, Pt, Re, Rh, Ru, Se, Te, Zn, Ge are used as additive metal elements, These additional metal elements are likely to segregate around the material particles, and the amount of co-material remaining in the internal electrode layer 12 can be increased.

In the internal electrode layer 12, if the amount of the added metal element is small, there is a possibility that a sufficient amount of the co-material cannot remain in the internal electrode layer 12. Therefore, it is preferable to set a lower limit to the concentration of the added metal element in the internal electrode layer 12. For example, in the internal electrode layer 12, the concentration of the added metal element relative to Ni is preferably 0.01 at% or more, more preferably 0.1 at% or more, and 1.0 at% or more. is even more preferable. Note that the concentration of the added metal element is the atomic ratio of the added metal element when Ni is assumed to be 100 at%.

On the other hand, if the amount of the added metal element is large in the internal electrode layer 12, the added metal element will diffuse into the dielectric layer 11, worsening the additive design of the dielectric layer 11, and causing the capacitance and characteristic values to deviate from the designed values. There is a risk. Therefore, it is preferable to set an upper limit on the concentration of the added metal element in the internal electrode layer 12. For example, in the internal electrode layer 12, the concentration of the added metal element relative to Ni is preferably 5.0 at% or less, more preferably 3.0 at% or less, and 1.5 at% or less. is even more preferable.

From the viewpoint of setting upper and lower limits on the concentration of the added metal element in the internal electrode layer 12, upper and lower limits are set on the ratio of the concentration of the added metal element in the external electrode to which the internal electrode layer is connected to the concentration of the added metal element in the internal electrode layer 12. It is preferable to provide For example, the ratio is preferably 0.3 or more and 0.5 or less, more preferably 0.2 or more and 0.4 or less, and preferably 0.1 or more and 0.2 or less. More preferred.

If the amount of the co-material remaining in the internal electrode layer 12 is small, there is a possibility that a sufficient sintering retardation effect cannot be obtained. Therefore, in the internal electrode layer 12, it is preferable to set a lower limit on the amount of the common material. For example, in the internal electrode layer 12, the amount of the co-material is preferably 5.0 wt% or more, more preferably 10 wt% or more, and even more preferably 15 wt% or more. Note that the amount of the additive is the weight ratio of the additive based on the assumption that Ni is 100 wt%.

On the other hand, if the amount of co-material remaining in the internal electrode layer 12 is large, the electrical properties may deteriorate due to a decrease in the continuity rate of the internal electrode layer 12 and diffusion into the dielectric layer 11 during the sintering process. Therefore, it is preferable to set an upper limit on the amount of the common material in the internal electrode layer 12. For example, in the internal electrode layer 12, the amount of the common material is preferably 20 wt% or less, more preferably 15 wt% or less, and even more preferably 10 wt% or less.

Note that the volume distribution of the common material can also be used as an index for the amount of the common material remaining in the internal electrode layer 12. For example, as illustrated in FIG. 5, the sum of the diameters of the plurality of common materials dispersed and remaining in the internal electrode layer 12 and the volume of each common material calculated from each diameter is 100%. Calculate volume distribution. The horizontal axis indicates the diameter of each common material. The vertical axis indicates volume distribution (%). In this distribution graph, the smaller the slope m of the straight line obtained by linear approximation, the more common materials with larger diameters remain. For example, the slope m is preferably 3.8 or more and 5.0 or less, more preferably 3.9 or more and 4.9 or less, and even more preferably 4.5 or more and 4.8 or less. Note that the diameter of each common material can be obtained, for example, by measuring the maximum length of each particle in an SEM (scanning electron microscope) photograph of a central cross section. The cubic volume when the measured diameter is taken as one side of the cube can be calculated as the volume of the particle. Regarding linear approximation, a straight line can be obtained by using the 20% value and 80% value of the volume distribution and calculating by connecting two data points.

Next, a method for manufacturing the multilayer ceramic capacitor 100 will be described. FIG. 6 is a diagram illustrating a flow of a method for manufacturing the multilayer ceramic capacitor 100.

(Raw material powder production process)
First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site element and the B-site element contained in the dielectric layer 11 are usually contained in the dielectric layer 11 in the form of a sintered body of ABO ₃ particles. For example, BaTiO ₃ is a tetragonal compound having a perovskite structure and exhibits a high dielectric constant. This BaTiO ₃ can generally be obtained by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate to synthesize barium titanate. Various methods are conventionally known for synthesizing the main component ceramic of the dielectric layer 11, such as a solid phase method, a sol-gel method, a hydrothermal method, and the like. In this embodiment, any of these can be adopted.

A predetermined additive compound is added to the obtained ceramic powder depending on the purpose. Additive compounds include molybdenum (Mo), niobium (Nb), tantalum (Ta), tungsten (W), magnesium (Mg), manganese (Mn), vanadium (V), chromium (Cr), rare earth elements (yttrium ( Oxidation of samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm) and ytterbium (Yb)) or oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K) or silicon (Si), or Co, Ni, Li , B, Na, K or Si. Among these, SiO ₂ mainly functions as a sintering aid.

For example, a ceramic material is prepared by wet-mixing a compound containing an additive compound with a ceramic raw material powder, drying and pulverizing the mixture. For example, the average particle size of the ceramic raw material powder is preferably 50 to 200 nm from the viewpoint of making the dielectric layer thinner. For example, the ceramic material obtained as described above may be pulverized to adjust the particle size, if necessary, or may be combined with a classification process to adjust the particle size. Through the above steps, a dielectric material is obtained.

(Lamination process)
Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained dielectric material and wet-mixed. Using the obtained slurry, a dielectric green sheet 52 having a thickness of, for example, 0.8 μm or less is coated on the base material 51 by, for example, a die coater method or a doctor blade method, and then dried. The base material 51 is, for example, a PET (polyethylene terephthalate) film.

Next, as illustrated in FIG. 7A, an internal electrode pattern 53 is formed on the dielectric green sheet 52. In FIG. 7A, as an example, four layers of internal electrode patterns 53 are formed on a dielectric green sheet 52 at predetermined intervals. The dielectric green sheet 52 on which the internal electrode pattern 53 is formed is a laminated unit. The internal electrode pattern 53 is a paste material containing Ni powder as the main component metal, powder as a common material, powder as an additive metal element, and the like.

Next, while peeling the dielectric green sheet 52 from the base material 51, a predetermined number of lamination units (for example, 100 to 500 layers) are laminated as illustrated in FIG. 7(b).

Next, a predetermined number (for example, 2 to 10 layers) of cover sheets 54 are stacked on top and bottom of the laminate obtained by stacking the laminate units, and the cover sheets 54 are bonded by thermocompression to a predetermined chip size (for example, 1.0 mm×0. .5mm). In the example of FIG. 7(b), the cut is made along the dotted line. The cover sheet 54 may have the same components as the dielectric green sheet 52, or may have different additive compounds. A metal paste, which will become external electrodes, is applied to both end faces of each of the obtained ceramic laminates by a dipping method or the like and dried. The metal paste contains Ni powder, which is the main component metal, and may also contain powder of a co-material, powder of an additive metal element, and the like. When the metal paste contains an additive metal element, the concentration of the additive metal element with respect to Ni is made smaller than the concentration of the additive metal element (concentration with respect to Ni) in the internal electrode pattern.

(Firing process)
Next, the obtained ceramic laminate was subjected to binder removal treatment in an N ₂ atmosphere at 250 to 500°C, and then treated at 1100 to 1300°C for 10 minutes in a reducing atmosphere with an oxygen partial pressure of 10 ^-5 to 10 ^-8 atm. Bake for ~2 hours. In this way, a multilayer ceramic capacitor 100 is obtained. Note that by increasing the temperature increase rate in the firing process, the metal material is sintered before the common material is discharged from the metal material, so that the common material tends to remain in the internal electrode layer 12. Therefore, the average temperature increase rate from room temperature to the maximum temperature in the firing step is preferably 30° C./min or more, more preferably 45° C./min or more. Note that if the average temperature increase rate is too high, organic components remaining in the ceramic laminate (those that could not be removed by debinding alone) will not be sufficiently discharged, resulting in problems such as cracks occurring during the firing process. may occur. Therefore, the average temperature increase rate is preferably 80° C./min or less, more preferably 65° C./min or less.

(Re-oxidation treatment process)
Thereafter, reoxidation treatment may be performed at 600° C. to 1000° C. in an N ₂ gas atmosphere.

(Plating process)
Thereafter, the surfaces of the external electrodes 20a and 20b may be coated with a metal such as Cu, Ni, or Sn by plating.

According to the manufacturing method according to the present embodiment, since the internal electrode pattern 53 includes the common material, the sintering of the metal component included in the internal electrode pattern 53 is delayed. Further, by including the additive metal element in addition to Ni, which is the main component, the internal electrode pattern 53 can increase the amount of co-material remaining in the internal electrode layer 12 after firing. Since the co-material added for the purpose of delaying sintering does not diffuse into the dielectric layer 11 during the sintering process and remains in large amounts in the internal electrode layer 12, a sufficient sintering delay effect can be obtained, and the internal electrode layer 12 Continuation rate improves. Furthermore, since the concentration of the added metal element relative to Ni is higher in the internal electrode pattern 53 than in the metal paste for forming the external electrode, the added metal element is concentrated from the internal electrode layer 12 toward the external electrodes 20a and 20b. Since the additive metal element diffuses and flows, the bonding properties between the internal electrode layer 12 and the external electrodes 20a and 20b are improved. As a result, it is possible to suppress a decrease in capacity due to poor connection and achieve desired capacity and characteristics.

Note that in each of the above embodiments, a multilayer ceramic capacitor has been described as an example of a ceramic electronic component, but the present invention is not limited thereto. For example, other electronic components such as varistors and thermistors may be used.

Hereinafter, a multilayer ceramic capacitor according to an embodiment was manufactured and its characteristics were investigated.

(Example 1)
A laminated unit was obtained by coating a dielectric green sheet containing barium titanate as a dielectric material and printing an internal electrode pattern containing Ni powder, a co-material, and an additive metal element. 200 layer laminate units were laminated, crimped and cut. The binder was removed, and a metal paste for external electrodes containing Ni powder and a co-material was applied to the two end faces and fired in a reducing atmosphere. BaTiO ₃ was used as a co-material for the internal electrode pattern and the metal paste. Au was used as an additional metal element for the internal electrode pattern. The amount of Au added in the internal electrode pattern was 1.0 at%, assuming that Ni was 100 at%.

The thickness of the dielectric layer after firing was 0.6 μm, and the thickness of the internal electrode layer was 0.7 μm. After firing, the ratio (concentration of added metal element in the external electrode before forming the plating layer)/(concentration of added metal element in the internal electrode layer) at the end margin was 0.52. The end margin is a portion of the end margin 15 illustrated in FIG. The added metal element was detected by EDS (energy dispersive X-ray analysis), and the ratio was (detected amount of added metal element in the external electrode)/(detected amount of added metal element in the internal electrode layer). . The EDS analysis in this case is a point analysis, and the detected amount is the detected amount at a predetermined irradiation point. The slope m of the graph calculated from the diameter and volume distribution of the common material was 4.64.

(Example 2)
In Example 2, Sn was used as the additive metal element. The amount of Sn added in the internal electrode pattern was 1.0 at%, assuming that Ni was 100 at%. Other conditions were the same as in Example 1.

The thickness of the dielectric layer after firing was 0.6 μm, and the thickness of the internal electrode layer was 0.7 μm. After firing, the ratio (concentration of added metal element in the external electrode before forming the plating layer)/(concentration of added metal element in the internal electrode layer) at the end margin was 0.28. The slope m of the graph calculated from the diameter and volume distribution of the common material was 3.90.

(Example 3)
In Example 3, Cr was used as the additive metal element. The amount of Cr added in the internal electrode pattern was 1.0 at%, assuming that Ni was 100 at%. Other conditions were the same as in Example 1.

The thickness of the dielectric layer after firing was 0.6 μm, and the thickness of the internal electrode layer was 0.7 μm. After firing, the ratio (concentration of added metal element in the external electrode before forming the plating layer)/(concentration of added metal element in the internal electrode layer) at the end margin was 0.51. The slope m of the graph calculated from the diameter and volume distribution of the common material was 4.56.

(Example 4)
In Example 4, Fe was used as the additive metal element. The amount of Fe added in the internal electrode pattern was 1.0 at%, assuming that Ni was 100 at%. Other conditions were the same as in Example 1.

The thickness of the dielectric layer after firing was 0.6 μm, and the thickness of the internal electrode layer was 0.7 μm. After firing, the ratio (concentration of added metal element in the external electrode before forming the plating layer)/(concentration of added metal element in the internal electrode layer) at the end margin was 0.43. The slope m of the graph calculated from the diameter and volume distribution of the common material was 3.80.

(Example 5)
In Example 5, Y was used as the additive metal element. The amount of Y added in the internal electrode pattern was 1.0 at%, assuming that Ni was 100 at%. Other conditions were the same as in Example 1.

The thickness of the dielectric layer after firing was 0.6 μm, and the thickness of the internal electrode layer was 0.7 μm. After firing, the ratio (concentration of added metal element in the external electrode before forming the plating layer)/(concentration of added metal element in the internal electrode layer) at the end margin was 0.44. The slope m of the graph calculated from the diameter and volume distribution of the common material was 3.95.

(Example 6)
In Example 6, In was used as the additive metal element. The amount of In added in the internal electrode pattern was 1.0 at%, assuming that Ni was 100 at%. Other conditions were the same as in Example 1.

The thickness of the dielectric layer after firing was 0.6 μm, and the thickness of the internal electrode layer was 0.7 μm. After firing, the ratio (concentration of added metal element in the external electrode before forming the plating layer)/(concentration of added metal element in the internal electrode layer) at the end margin was 0.43. The slope m of the graph calculated from the diameter and volume distribution of the common material was 3.85.

(Example 7)
In Example 7, Au and Sn were used as additive metal elements. The amounts of Au and Sn added in the internal electrode pattern were 0.5 at% and 1.0 at%, respectively, assuming that Ni was 100 at%. Other conditions were the same as in Example 1.

The thickness of the dielectric layer after firing was 0.6 μm, and the thickness of the internal electrode layer was 0.7 μm. After firing, the ratio (concentration of added metal element in the external electrode before forming the plating layer)/(concentration of added metal element in the internal electrode layer) at the end margin was 0.53. The slope m of the graph calculated from the diameter and volume distribution of the common material was 4.77.

(Example 8)
In Example 8, Au and Cr were used as additive metal elements. The amounts of Au and Cr added in the internal electrode pattern were 0.5 at% and 1.0 at%, respectively, assuming that Ni was 100 at%. Other conditions were the same as in Example 1.

The thickness of the dielectric layer after firing was 0.6 μm, and the thickness of the internal electrode layer was 0.7 μm. After firing, the ratio (concentration of added metal element in the external electrode before forming the plating layer)/(concentration of added metal element in the internal electrode layer) at the end margin was 0.52. The slope m of the graph calculated from the diameter and volume distribution of the common material was 4.66.

(Example 9)
In Example 9, Au, Sn, and Cr were used as additive metal elements. The amounts of Au, Sn, and Cr added in the internal electrode pattern were 0.5 at%, 0.5 at%, and 1.0 at%, respectively, assuming that Ni was 100 at%. Other conditions were the same as in Example 1.

The thickness of the dielectric layer after firing was 0.6 μm, and the thickness of the internal electrode layer was 0.7 μm. After firing, the ratio (concentration of added metal element in the external electrode before forming the plating layer)/(concentration of added metal element in the internal electrode layer) at the end margin was 0.54. The slope m of the graph calculated from the diameter and volume distribution of the common material was 4.79.

(Comparative example)
In the comparative example, no additional metal element was added to the internal electrode pattern. Other conditions were the same as in Example 1.

The thickness of the dielectric layer after firing was 0.6 μm, and the thickness of the internal electrode layer was 0.7 μm. The slope m of the graph calculated from the diameter and volume distribution of the common material was 6.39.

FIG. 8A is a traced SEM photograph of a cross section in the stacking direction of Example 1. FIG. 8(b) is a traced SEM photograph of a cross section in the stacking direction of the comparative example. When compared with FIG. 8(b), it can be seen that a large amount of the common material 17 remains in the internal electrode layer 12 in FIG. 8(a).

FIG. 9 is a graph calculated from the diameter and volume distribution of common materials in internal electric competition for Example 1 and Comparative Example. As shown in FIG. 9, it can be seen that the slope m is smaller in Example 1 than in the comparative example. Therefore, it can be seen that more common materials remain in Example 1 than in Comparative Example. This is considered to be because the additional metal element was added to the internal electrode pattern. In addition, 500 common materials were counted in the comparative example, and 500 common materials were counted in Example 1.

(Continuous rate)
The continuity rate of the internal electrode layer was measured for Examples 1 to 9 and Comparative Example. The continuity rate was determined by burying a fired multilayer ceramic capacitor in resin and polishing it to the center to expose the cross section. The cross section was observed with a SEM, about 10 images were taken, and the continuity rate was measured from the taken images. The continuity rate of Examples 1 to 9 was higher than that of the comparative example. This is considered to be because a large amount of the common material remained in the internal electrode layer, which sufficiently delayed the shrinkage of the internal electrode layer.

(zygosity)
For Examples 1 to 9 and Comparative Examples, the bondability between the internal electrode layer and the external electrode was examined. The state of connection between the internal electrode layer and the external electrode was confirmed from a polished cross-sectional image in comparison with a multilayer ceramic capacitor made of Ni alone to which no additive elements were added. For example, in the case of a 200-layer multilayer ceramic capacitor, if it is confirmed that the bonding condition has improved by 15% or more compared to a monolithic Ni monolithic ceramic capacitor, the bonding performance is judged to be very good, ``◎'', and 10%. If the bonding state improved by % or more, the bondability was determined to be good. If it was less than 10%, and if it was equivalent to Ni alone, the bondability was determined to be poor. In the comparative example, bondability was determined to be poor. This is considered to be because no additional metal element was added. Note that the bonded state expressed here indicates a state in which the internal electrode and the external electrode are connected on the polished cross-sectional image. In contrast, in Examples 1 to 9, the bondability was judged to be very good or good. This is considered to be because the added metal element was diffused by making the added metal element concentration in the internal electrode layer higher than the added metal element concentration in the external electrode.

(capacity)
Capacity was measured for each of Examples 1 to 9 and Comparative Example. The capacitance was measured using an LCR meter under the conditions of 0.5 V and 1 kHz, and the average value of 100 samples was calculated. If the average capacitance value is improved by 10% or more compared to a monolithic ceramic capacitor made of Ni alone without any additive elements, the capacitance is judged to be very good. If the average capacity improved by less than 5%, the capacity was determined to be good. If the average capacity improved by less than 5%, the capacity was determined to be poor. In the comparative example, the capacity was determined to be poor. In contrast, in Examples 1 to 9, the capacity was determined to be very good or good. This is considered to be because the continuity rate of the internal electrode layer was higher than that of the comparative example, and the bondability between the internal electrode layer and the external electrode was also good.

(reliability)
Reliability was investigated for each of Examples 1 to 9 and Comparative Example. Reliability was determined by conducting a HALT test at 6V-125°C. Regarding the HALT lifespan, the average value of 100 samples was calculated. If the average lifespan is more than double that of a single-layer ceramic capacitor made of Ni without any additive elements, the reliability is judged to be very good (◎), and the average lifespan is 1. If it was .5 times or more, the reliability was determined to be good (〇), and if it was equal to or less than 1.5 times, the reliability was determined to be poor (-). In the comparative example, reliability was determined to be poor. In contrast, in Examples 1 to 9, the reliability was determined to be very good or good. This is considered to be because the bonding between the internal electrode layer and the external electrode was also better than in the comparative example.

Although the embodiments of the present invention have been described in detail above, the present invention is not limited to these specific embodiments, and various modifications and variations can be made within the scope of the gist of the present invention as described in the claims. Changes are possible.

10 Laminated chip 11 Dielectric layer 12 Internal electrode layer 13 Cover layer 14 Capacitance region 15 End margin 16 Side margin 17 Common material 20a, 20b External electrode 51 Base material 52 Dielectric green sheet 53 Internal electrode pattern 100 Multilayer ceramic capacitor

Claims (11)

A plurality of dielectric layers containing ceramic as a main component and a plurality of internal electrode layers containing Ni as a main component are alternately laminated and have a substantially rectangular parallelepiped shape, and the plurality of internal electrode layers are formed on two opposing end surfaces of the substantially rectangular parallelepiped shape. a laminated chip formed such that internal electrode layers of are alternately exposed;
external electrodes provided on the two end faces and containing Ni as a main component,
The plurality of internal electrode layers include an additive metal element other than Ni and a common material,
A ceramic electronic component, wherein the concentration of the additive metal element is higher in the internal electrode layer than in the external electrode. The additive metal element is selected from Au, Sn, Cr, Fe, Y, In, As, Co, Cu, Ir, Mg, Os, Pd, Pt, Re, Rh, Ru, Se, Te, Zn, and Ge. The ceramic electronic component according to claim 1, characterized in that the ceramic electronic component is one or more types. The ceramic electronic component according to claim 1 or 2, wherein the concentration of the additive metal element in the plurality of internal electrode layers is 0.01 at% or more and 5.0 at% or less based on Ni. . The ratio of the concentration of the added metal element in the external electrode to which the internal electrode layer is connected to the concentration of the added metal element in the internal electrode layer is 0.1 or more and 0.5 or less. The ceramic electronic component according to any one of claims 1 to 3. For the plurality of internal electrode layers, the diameter of each of the common materials is plotted on the horizontal axis, and the volume distribution (%) is plotted on the vertical axis so that the total volume of each of the common materials is 100%. According to any one of claims 1 to 4, the slope m when a straight line is approximated by connecting the 20% value and the 80% value of the graph is 3.8 or more and 5.0 or less. Ceramic electronic components listed. In an end margin region where internal electrode layers exposed on the same end face of the laminated chip face each other without intervening internal electrode layers exposed on different end faces, the concentration of the added metal element is higher than that of the external electrode. The ceramic electronic component according to any one of claims 1 to 5, characterized in that the electrode layer is taller. 7. The ceramic electronic component according to claim 1, wherein the dielectric layer has a thickness of 0.8 μm or less. The ceramic electronic component according to any one of claims 1 to 7, wherein the internal electrode layer has a thickness of 0.8 μm or less. The ceramic electronic component according to any one of claims 1 to 8, wherein the external electrode contains the additive metal element. The ceramic electronic component according to any one of claims 1 to 9, wherein the external electrode includes a common material. A substantially rectangular parallelepiped-shaped ceramic laminate is formed by alternately laminating dielectric green sheets containing ceramic powder and internal electrode patterns containing Ni as a main component metal and co-materials and additive metal elements, and the ceramic laminate is Alternately exposing the stacked internal electrode patterns on two opposing end surfaces of the
A metal paste containing Ni as a main component metal is placed on the two end faces,
The ceramic laminate is fired so that the internal electrode layer obtained from the internal electrode pattern has a higher concentration of the added metal element than the external electrode obtained from the metal paste. Method of manufacturing ceramic electronic components.

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