JP2023116188A - Image formation apparatus - Google Patents

Abstract

To more easily control a variable magnification in the sub-scanning direction.SOLUTION: An image formation apparatus comprises: first generation means which generates a clock signal in a fixed cycle; second generation means which generates a line synchronous signal indicating writing timing of each line corresponding to the resolution of an image in the rotation direction of a photoreceptor; and control means. The control means causes the second generation means to generate the line synchronous signal such that the cycle of the line synchronous signal becomes the integral multiplication of the cycle of the clock signal according to the variable magnification of the image formed on the photoreceptor.SELECTED DRAWING: Figure 12

Description

The present invention relates to an image forming apparatus.

2. Description of the Related Art Conventionally, there has been known an electrophotographic printer that forms a latent image on a photosensitive drum by exposing a photosensitive drum using an exposure head that uses a light source such as an LED (light emitting diode) or an organic EL (electroluminescence). there is Such a printer can enlarge or reduce the formed image in the sub-scanning direction by adjusting the exposure timing in the sub-scanning direction. In Japanese Patent Application Laid-Open No. 2004-100003, by changing the generation cycle of a line synchronization signal indicating exposure timing in the sub-scanning direction, image enlargement and reduction (so-called zooming) in the sub-scanning direction are realized.

Japanese Patent No. 4531491

By the way, in the conventional method, the possible values of the scaling factor depend on the cycle of the clock signal. This is because the generation period of the line synchronization signal is synchronized with the period of the clock signal. Therefore, in the conventional method, it was necessary to increase the frequency of the clock signal in order to finely adjust the scaling factor. However, increasing the frequency of the clock signal increases the cost of the signal transmission line and requires a complicated circuit. SUMMARY OF THE INVENTION In view of the above problems, an object of the present invention is to control the variable magnification in the sub-scanning direction with a more inexpensive configuration.

The present invention, for example,
a photosensitive member that is rotationally driven;
An exposure head comprising: a plurality of light-emitting elements arranged at different positions in a direction intersecting the rotation direction of the photoreceptor and exposing the surface of the photoreceptor; and a drive circuit driving the plurality of light-emitting elements. and,
a first generating means for generating a clock signal at a constant cycle;
output means for outputting image data to the drive circuit in synchronization with the clock signal;
a second generating means for generating a line synchronization signal indicating timing of writing each line corresponding to image resolution in the rotation direction of the photoreceptor;
and a control means for controlling the second generation means,
The control means generates the line synchronization signal in the second generation means so that the period of the line synchronization signal is an integral multiple of the period of the clock signal according to the scaling factor of the image formed on the photoreceptor. It is characterized by

According to the present invention, it is possible to control the variable magnification in the sub-scanning direction with a less expensive configuration.

Diagram for explaining an image forming apparatus Diagram for explaining arrangement of photoreceptor drums and exposure heads Diagram explaining a printed circuit board Diagram for explaining the light-emitting element array Diagram for explaining arrangement of light-emitting elements Block diagram showing image controller and printed circuit board Block diagram showing the digital part Diagram explaining the timing part Diagram for explaining the lighting control unit Block diagram showing the analog section Diagram explaining the drive circuit Diagram for explaining variable magnification processing in the sub-scanning direction Flowchart showing the control method

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. In addition, the following embodiments do not limit the invention according to the scope of claims. Although multiple features are described in the embodiments, not all of these multiple features are essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant description is omitted.

<Image forming apparatus>
FIG. 1 shows an image forming apparatus 1 which is an electrophotographic copier. However, the image forming apparatus 1 may be realized as a monochrome printer, a full-color printer, a facsimile communication device, and a multi-function machine.

The scanner unit 100 is a document reading device that illuminates a document placed on a document table, optically reads the document image, converts the reading result into an electric signal, and creates image data. The printer engine 103 forms a toner image on the sheet P. FIG. A printer engine 103 rotates the photosensitive drum 102 . The charger 107 charges the surface of the photoreceptor drum 102 so that the surface of the photoreceptor drum 102 has a uniform potential. The exposure head 106 exposes the surface of the photoreceptor drum 102 with light corresponding to image data to form an electrostatic latent image on the surface of the photoreceptor drum 102 . The developing device 108 adheres toner to the electrostatic latent image formed on the photosensitive drum 102 to form a toner image. Further rotation of the photoreceptor drum 102 brings the toner image to the transfer nip. At the transfer nip, the sheet P is conveyed while being nipped between the photosensitive drum 102 and the transfer belt 111 . Thereby, the toner image is transferred from the photosensitive drum 102 to the sheet P. FIG.

The printer engine 103 has four image forming units 101C, 101M, 101Y, and 101K corresponding to toner colors CMYK (cyan, magenta, yellow, and black). The four image forming units 101C, 101M, 101Y, and 101K transfer toner images of different colors onto the sheet P, thereby forming a full-color image on the sheet P. FIG.

The feeding unit 105 is designated in advance among the feeding devices 109a and 109b provided in the main body of the image forming apparatus 1, the feeding device 109c provided outside the main body, and the manual feed type feeding device 109d. The sheet P is fed from the feeding device. The fed sheet P is conveyed to registration rollers 110 . The registration roller 110 conveys the sheet P so that the timing at which the toner image arrives at the transfer nip coincides with the timing at which the sheet P arrives. The transfer belt 111 conveys the sheet P onto which the toner image has been transferred to the fixing device 104 .

The fixing device 104 fixes the toner image onto the sheet P by applying pressure and heat to the toner image and the sheet P. FIG. A paper discharge roller 112 discharges the sheet P to the outside of the image forming apparatus 1 .

<Exposure head>
FIG. 2A is a perspective view of the exposure head 106 that exposes the photosensitive drum 102. FIG. FIG. 2B is a schematic cross-sectional view of the photosensitive drum 102 and the exposure head 106. FIG. The exposure head 106 has a light emitting element group 201 , a printed circuit board 202 , a rod lens array 203 and a housing 204 . Light emitted from the light emitting element group 201 mounted on the printed circuit board 202 is condensed by the rod lens array 203 and irradiated onto the surface of the photosensitive drum 102 . The printed circuit board 202 and rod lens array 203 are fixed to the housing 204 .

The exposure head 106 is individually assembled and adjusted. The adjustment work includes spot size adjustment (focus adjustment) at the condensing position and light amount adjustment. In focus adjustment, the mounting position of the rod lens array 203 is adjusted so that the distance between the rod lens array 203 and the light emitting element group 201 is a predetermined value. In the light amount adjustment, the plurality of light emitting elements included in the light emitting element group 201 are sequentially caused to emit light one by one, and each light emitting element is adjusted so that the light amount condensed through the rod lens array 203 becomes a predetermined light amount. A drive current is adjusted.

<Structure of Light Emitting Element Group>
FIG. 3A shows a non-mounting surface 301 of the printed circuit board 202. FIG. Although no light emitting element is mounted on the non-mounting surface 301, other electronic components such as a connector 305 are mounted. The connector 305 is connected to a cable (power supply line and signal line) that conveys various signals such as a clock signal to the printed circuit board 202 .

As shown in FIG. 3B, the light emitting element group 201 is mounted on the mounting surface 302 of the printed board 202 . The mounting surface 302 is the surface opposite to the non-mounting surface 301 . The light emitting element group 201 has m light emitting element arrays 300-1 to 300-m arranged in a zigzag pattern. The light emitting element arrays 300-1 to 300-m may be collectively referred to as the light emitting element array 300. FIG.

As shown in FIG. 3C, a plurality of light emitting elements 350 are arranged along the longitudinal direction of the light emitting element array 300 in each of the light emitting element arrays 300-1 to 300-m.

As shown in FIG. 3B, the light emitting element array 300 is arranged in two columns. A light emitting element array 300-1, a light emitting element array 300-3, . . . , a light emitting element array 300-m-1 are provided in the first row. A light emitting element array 300-2, a light emitting element array 300-4, . . . , a light emitting element array 300-m are provided in the second row.

As shown in FIG. 3C, the distance between two adjacent light emitting elements 350 in a certain light emitting element array 300 is L. As shown in FIG. A distance L is a longitudinal distance of the light emitting element array 300 . At 1200 dpi resolution, L=about 21.16 μm. This is a distance corresponding to one pixel at 1200 dpi. The distance between the right end light emitting element 350 of the i-th light emitting element array 300-i and the left end light emitting element 350 of the i+1-th light emitting element array 300-i+1 is also L. i is any integer from 1 to m−1. As shown in FIG. 3C, in the lateral direction of the light emitting element array 300, the distance S between the right end light emitting element 350 of the light emitting element array 300-i and the left end light emitting element 350 of the light emitting element array 300-i+1 is about 105 μm. This corresponds to a distance of 5 pixels at 1200 dpi. Note that the distances L and S are only examples.

<Structure of Light Emitting Element Array>
FIG. 4 is a plan view of the light emitting element array 300. FIG. The X direction indicates the longitudinal direction of the photoreceptor drum 102 . The Y direction indicates the direction of rotation of the photosensitive drum 102 . The light emitting element array 300 has a light emitting substrate 402 , a light emitting section 404 including a plurality of light emitting elements 350 mounted on the light emitting substrate 402 , and WB pads 408 mounted on the light emitting substrate 402 . WB is an abbreviation for wire bonding. The light emitting substrate 402 incorporates a circuit section 406 for controlling the light emitting section 404 . Circuit portion 406 includes both analog drive circuitry (analog portion) and digital control circuitry (digital portion). Power supply to the circuit section 406 and signal input/output to/from the light emitting element array 300 are performed through the WB pad 408 .

<Light emitting part>
FIG. 5 shows a light-emitting element array that constitutes the light-emitting section 404 . The light emitting section 404 has n light emitting elements 350 arranged in a line. The plurality of light emitting elements 350 are arranged at a predetermined pitch (distance L=21.16 μm) in the X direction.

In FIG. 5, W1 is the length of the light emitting element 350 in the X direction. d1 is the distance between two adjacent light emitting elements 350 in the X direction. W2 is the length of the light emitting element 350 in the Y direction. The length W2 is determined in consideration of the scanning speed and resolution in the Y direction. As an example, the lengths W1 and W2 are 20.9 μm, and the adjacent distance d1 is 0.26 μm.

<Control block>
FIG. 6 shows a block diagram of image controller 600 and printed circuit board 202 . In this embodiment, for the sake of simplicity, the circuit configuration and processing for the K single color of YMCK will be described. Similar processing and circuit configuration are adopted for YMC as well.

The image controller 600 is a control circuit that generates a group of signals for controlling the printed circuit board 202 and transmits them to the printed circuit board 202 . Such signal groups include clock signal clk, image data data_1 to data_m, line synchronization signal lsync_x, and communication signal com. The clock signal clk is a signal generated by the clock unit 608 and serving as a reference for operations in various circuits. Image data data_1 to data_m are image data supplied to the light emitting element arrays 300-1 to 300-m, respectively. The line synchronization signal lsync_x represents the image writing timing in the sub-scanning direction. A communication signal com is a communication signal transmitted or received between the CPU 603 and the printed circuit board 202 . The clock signal clk is transmitted from the clock unit 608 to the printed circuit board 202 and the like via the clock signal line 605 . The line synchronization signal lsync_x is transmitted from the synchronization section 604 to the printed circuit board 202 or the like via the synchronization signal line 606 . The image data data_1 to data_m are transmitted to the light emitting element arrays 300-1 to 300-m via image signal lines 607-1 to 607-m, respectively. A communication signal com is transmitted from the CPU 603 to the information storage unit 610 and the light emitting element arrays 300-1 to 300-m via the communication signal line 609. FIG.

The image data unit 601 applies image processing to image data received from a computer external to the scanner unit 100 or the image forming apparatus 1 and outputs the image data to the conversion unit 602 . Image processing includes, for example, dithering processing at the resolution instructed by CPU 603 . For example, the dithering process is performed with a resolution of 2400 dpi in the sub-scanning direction and a resolution of 1200 dpi in the main scanning direction. Also, the image data data_1 to data_m are binary data, where 1 indicates lighting and 0 indicates lighting off.

A clock unit 608 is an oscillation circuit that generates a clock signal clk with a constant cycle. The clock signal clk is supplied to the CPU 603 , synchronization section 604 , conversion section 602 and printed circuit board 202 . The CPU 603 executes the following processing according to the control program stored in the ROM area of the memory 650 . Note that the memory 650 also includes a RAM area for holding variables and the like.

The CPU 603 determines the generation cycle of the line synchronization signal lsync_x. The generation cycle is calculated based on, for example, the rotation speed of the photoreceptor drum 102 (speed information of movement of the surface of the photoreceptor drum 102 in the rotation direction) and the variable magnification of the image in the sub-scanning direction. The CPU 603 sets the generation cycle of the line synchronization signal lsync_x in the synchronization section 604 . Also, the CPU 603 receives the line synchronization signal lsync_x from the synchronization unit 604 and recognizes the timing when generation of the line synchronization signal lsync_x is completed.

The conversion unit 602 divides one line of image data output from the image data unit 601 to generate image data data_1 to data_m. The conversion unit 602 transmits the image data data_1 to data_m to the printed circuit board 202 in synchronization with the line synchronization signal lsync_x and the clock signal clk.

The synchronization unit 604 generates the line synchronization signal lsync_x at the generation cycle instructed by the CPU 603 . The line synchronization signal lsync_x is supplied to the printed circuit board 202 , conversion section 602 and CPU 603 .

In the printed circuit board 202, the light emitting element array 300-i operates by being supplied with the line synchronization signal lsync_x, clock signal clk, image data data_i, and communication signal com. The information storage unit 610 is a storage circuit that stores head information. The head information includes the amount of light emitted from each of the light emitting element arrays 300-1 to 300-m and the position information indicating the mounting position. The CPU 603 accesses the information storage unit 610 via the communication signal line 609 to read head information and write setting information. Note that the information storage unit 610 may store the setting value of the driving current adjusted in the assembly process of the exposure head 106 .

As shown in FIG. 6, the clock signal line 605, the communication signal line 609, and the synchronization signal line 606 are connected to all the light emitting element arrays 300. FIG. The image signal lines 607 and the light-emitting element arrays 300 are connected one-to-one. That is, one image signal line 607 is connected to one light emitting element array 300 .

<Structure of circuit section>
FIG. 7 is a block diagram of the circuit section 406 in the i-th light emitting element array 300-i (i is an integer from 1 to m). Circuit portion 406 has a digital portion 700 and an analog portion 750 . In synchronization with the clock signal clk, the digital unit 700 generates a lighting signal for causing the light emitting element 350 to emit light based on a setting value preset by the communication signal com, the line synchronization signal lsync_x, and the image data data. Digital section 700 outputs a lighting signal to analog section 750 via lighting signal line 708 .

The communication IF 701 controls writing and reading of set values to and from the register 702 based on the communication signal com from the CPU 603 . A register 702 holds setting values necessary for the operation of the light emitting element 350 . The set value includes a value indicating the drive current set in the analog section 750 .

The timing section 704 generates a timing signal based on the line synchronization signal lsync_x, and supplies the timing signal to the lighting control section 705-1 via the signal line 707-1. The lighting control unit 705-1 takes in the image data data from the image signal line 607 according to the timing signal. The number n of lighting control units 705 and the number n of light emitting elements 350 are the same. That is, one lighting control section 705 is provided for one light emitting element 350 . The lighting control unit 705-j outputs a lighting signal to the analog unit 750 via the lighting signal line 708-j (j is an integer from 1 to n). The lighting control unit 705-j generates a timing signal for the lighting control unit 705-j+1 based on the input timing signal, and sends the timing signal to the lighting control unit 705-j+1 through the signal line 707-j+1. supply. In this way, the lighting control section 705-1 is directly supplied with the timing signal from the timing section 704, but the lighting control sections 705-2 to 705-n receive the timing signal from the preceding stage lighting control sections 705-1 to 705-n, respectively. -1 is supplied with a timing signal.

The analog section 750 drives the light emitting elements 350-1 to 350-n based on the pulse-like lighting signal generated by the digital section 700. FIG.

<Details of the timing section>
FIG. 8A is a circuit diagram of the timing section 704. FIG. Here, the line synchronization signal lsync_x is assumed to be a negative logic signal, but may be a positive logic signal. we[1] is a timing signal. A timing unit 704 is a logic circuit that outputs a timing signal we[0] only when the line synchronization signal lsync_x changes from Low to High.

The delay circuit 801 , to which the synchronization signal line 606 and the clock signal line 605 are connected, delays the line synchronization signal lsync_x transmitted by the synchronization signal line 606 by one cycle and outputs it to the logic gate 802 . Delay circuit 801 is realized by, for example, a flip-flop circuit.

A logic gate 802 performs a logical product (AND) operation of the line synchronization signal lsync_x and a signal obtained by inverting the output signal of the delay circuit 801 by an inverting element 803 to generate a timing signal we[0]. Timing signal we[0] is output to signal line 707-1.

FIG. 8B is a timing chart of the timing unit 704. FIG. The timing signal we[0] becomes High at the timing when the line synchronization signal lsync_x changes from Low to High. The timing signal we[0] continues to be High for a period of time corresponding to one cycle of the clock signal clk, and then returns to Low.

<Details of lighting controller>
FIG. 9A is a circuit diagram of the j-th lighting control unit 705-j in the i-th light emitting element array 300-i (j is an integer from 1 to n). The delay circuit 901 is connected to the signal line 707 - j and the clock signal line 605 . The delay circuit 901 delays the timing signal we[j] transmitted by the signal line 707-j by one cycle to generate the timing signal we[j+1] for the lighting control unit 705-j+1 in the subsequent stage. output on line 707-j+1. The delay circuit 901 may be a circuit capable of delaying an input signal by a time corresponding to one cycle of the clock signal clk. For example, a flip-flop circuit can be used as the delay circuit 901 .

The latch circuit 902 is connected to the signal line 707-j and the image signal line 607-i. The latch circuit 902 takes in the image data data_i during the period when the timing signal we[j] is High, and outputs it as the lighting signal el[j] to the lighting signal line 708-j. In this embodiment, the latch circuit 902 is employed as a circuit for capturing the image data data_i, but this is merely an example. Any circuit that can hold the image data data_i from when the timing signal we[j] becomes High until the next timing signal we[j] becomes High may be used. For example, instead of latch circuit 902, a flip-flop circuit may be employed.

FIG. 9B is a timing chart of the delay circuit 901. FIG. The timing signal we[j+1] is generated by delaying the timing signal we[j] by one cycle of the clock signal clk.

FIG. 9C is a timing chart of the latch circuit 902. FIG. The image data data_i (“000” in this example) is taken in while the timing signal we[j] is High, and the lighting signal el[j] is generated.

<Details of the analog section>
FIG. 10 is a block diagram of the analog section 750. As shown in FIG. Two light-emitting elements 350-1, 350-n and two drive circuits 1001-1, 1001-n are shown for simplicity of explanation. Actually, there are n light emitting elements 350-1 to 350-n and n driving circuits 1001-1 to 1001-n. Here, for generalization, the j-th light emitting element 350-j and the j-th driving circuit 1001-j will be described (j is an integer from 1 to n).

A drive circuit 1001-j is a circuit that drives the i-th light emitting element 350-j. A lighting signal el[j] is supplied to the driving circuit 1001-j through a lighting signal line 708-j.

The DAC 1002 converts the drive current data set in the register 702 into an analog voltage and supplies the analog voltage to the drive circuits 1001-1 to 1001-n via the signal line 1003. FIG. DAC is an abbreviation for digital-to-analog converter. Here, the drive current data indicates set values of drive currents supplied to the light emitting elements 350-1 to 350-n.

The selection circuit 1007 generates a select signal for selecting the driving circuit 1001 based on data set in the register 702 . The selection circuit 1007 supplies select signals to the drive circuits 1001-1 to 1001-n via the signal lines 1004-1 to 1004-n. The select signal is such that only the signal connected to one drive circuit 1001 selected from among the n drive circuits 1001-1 to 1001-n becomes High. When the drive circuit 1001-1 is selected, only the signal line 1004-1 is controlled to high level. The signal lines 1004-2 (not shown) to 1001-n are controlled to low level. Each of the drive circuits 1001-1 to 1001-n is set with an analog voltage through the signal line 1003 at the timing selected by the selection circuit 1007 (the timing at which the select signal becomes High). The CPU 603 sequentially selects the driving circuits 1001-1 to 1001-n one by one via the register 702, and sets the analog voltage corresponding to the selected driving circuit 1001. FIG. This makes it possible to use a single DAC 1002 to set individual analog voltages to the n drive circuits 1001-1 to 1001-n. In this way, the drive circuits 1001-1 to 1001-n receive analog voltages for determining drive currents and lighting signals, respectively, and cause the corresponding light emitting elements 350-1 to 350-n to emit light.

<Details of drive circuit>
FIG. 11 is a circuit diagram of the jth drive circuit 1001-j (j is an integer from 1 to n). All of the drive circuits 1001-1 to 1001-n have the same circuit configuration.

MOSFET Q1 supplies a drive current to light emitting element 350-j according to the gate voltage applied to its gate. When the gate voltage is at the Low level, the drive current is reduced and the light emitting element 350-j is extinguished. A lighting signal line 708-j is connected to the gate of the MOSFET Q2. The MOSFET Q2 turns on when the lighting signal el[j] is High, and transfers the voltage charged in the capacitor C1 to the MOSFET Q1. A signal line 1004-j is connected to the gate of MOSFET Q3. MOSFET Q3 turns on and off according to a select signal from selection circuit 1007 . That is, the MOSFET Q3 turns on when the select signal is High, applies the analog voltage output from the DAC 1002 to the capacitor C1, and charges the capacitor C1. In this embodiment, DAC 1002 sets an analog voltage on capacitor C1 prior to image formation. During imaging, MOSFET Q3 is turned off and capacitor C1 maintains the voltage level continuously. As a result, the MOSFET Q1 supplies or stops supplying the driving current corresponding to the set analog voltage to the light emitting element 350-1 according to the lighting signal.

If the input capacitance of the light emitting element 350-j is too large, the response speed for switching the light emitting element 350-j from on to off will be slow. Therefore, MOSFET Q4 and inverter 1101 may be added to improve the response speed. A signal obtained by inverting the logic of the lighting signal el[j] by the inverter 1101 is input to the gate of the MOSFET Q4. When the lighting signal el[j] is at Low level, the gate of MOSFET Q4 goes High. Therefore, the MOSFET Q4 is turned on, and it becomes possible to forcibly discharge the charge charged in the input capacitance of the light emitting element 350-j.

<Variable Magnification Processing in Sub-Scanning Direction (Generation Cycle of Line Synchronization Signal)>
FIG. 12 is a diagram for explaining variable magnification processing in the sub-scanning direction. FIG. 12 shows the relationship between the period lsync_period of the line synchronization signal lsync_x of each line from L1 to L11 and the variable accum.

As an example, the cycle of the line synchronization signal lsync_x without scaling is 1058 cycles in units of the clock signal clk. This means that one line synchronization signal lsync_x is output when 1058 clock signals clk are input.

As an example, it is assumed that the length in the sub-scanning direction is scaled (reduced) to 98%. In this case, the ideal generation period lsync_period of the line synchronization signal lsync_x is calculated from the following equation.

1058×(98/100)=1036.84 (1)
The line synchronization signal lsync_x is generated in synchronization with the clock signal clk. Therefore, if the fractional part of the clock signal clk, which is less than one cycle, is rounded off, an error will occur in the magnification.

Therefore, as shown in FIG. 12, the CPU 603 determines the period lsync_period of the line synchronization signal lsync_x for each line. According to the formula (1), the period lsync_period is calculated as 1036.84, but the period lsync_period must be an integer. Therefore, the period lsync_period for the L1th line is determined to be 1036 cycles. Note that the initial value of the variable accum is 0.0.

Similarly, the period lsync_period for the L2th line is also determined to be 1036 cycles. Here, since the fractional part frac of the period lsync_period for the L1-th line is 0.84, the CPU 603 cumulatively adds the fractional part frac to the variable accum. Therefore, the variable accum is less than 1 because the variable accum for the L2th line is 0.84. Therefore, the period lsync_period for the L2th line is not adjusted.

The variable accum for the L3th line is 1.68 obtained by accumulating the fractional part frac of the L1th line and the fractional part frac of the L2th line. That is, the variable accum for the L3th line exceeds one. Therefore, the CPU 603 adds 1 to the period lsync_period. As a result, the period lsync_period of the L3th line is 1037. Here, since 1 is added to the period lsync_period, the variable accum becomes 0.68 (1.68−1=0.68).

Thereafter, similarly, the period lsync_period and the variable accum are calculated. That is, when the variable accum becomes 1 or more, 1 is added to the period lsync_period and 1 is subtracted from the variable accum.

As shown in FIG. 12, each of the L3th to L7th lines has a period lsync_period that is longer by one cycle. In the L8th line, the variable accum is not greater than 1, so the period lsync_period remains 1036. After that, each line from L9th to L11th has a period lsync_period that is lengthened by one cycle.

Here, the average value of the period lsync_perio for the L1-th line to the L11-th line is obtained from the following equation.

(1036 x 3 + 1037 x 8)/11 = 1036.727 (2)
That is, the error in the scaling factor of this embodiment is smaller than the error in the case of rounding off the decimal part. The actual number of lines is much larger than 11 lines. Therefore, the error of the actual scaling factor is further reduced. In this way, by reflecting the fractional part frac of the period lsync_period, which is less than one period of the clock signal clk, in the average period of a plurality of lines, the accuracy of the scaling process in the sub-scanning direction is improved.

<Flowchart>
FIG. 13 shows the control method executed by the CPU 603 . In S1301, the CPU 603 calculates a reference generation cycle Lb. For example, the CPU 603 may calculate the reference generation cycle Lb using the following equation similar to (1).

Lb=ROUND ((l÷s)×(1÷t)) (3)
where the function ROUND(X) is a mathematical function that rounds X to one decimal place and rounds to an integer. l is the distance between two adjacent lines in the sub-scanning direction. s is the speed (peripheral speed) at which the surface of the photosensitive drum 102 moves in the rotational direction. t is the period of the clock signal clk. For example, assume that s=200 mm/sec and the resolution in the sub-scanning direction is 2400 dpi (that is, distance l is about 10.58 μm). Further assume that the clock period t is 0.05 μsec (=20 MHz). In this case, Lb=1058 is calculated.

In S1302, the CPU 603 calculates the variable magnification generation period Lm (period lsync_period) and the fractional part frac based on the reference generation period Lb and the sub-scanning magnification magnification mag. For example, the CPU 603 may calculate the scaling generation period Lm using the following equation. However, the sub-scanning scaling factor mag is a percentage.
Lm=INT (Lb×(mag÷100)) (4)
where INT(X) is a mathematical function representing the largest integer not greater than X. For example, when Lb=1058 and mag=98%, Lm=1036 is calculated. Further, the CPU 603 calculates the fractional part frac, which is the adjustment value of the scaling factor for each line, using the following equation. The fractional part frac may be calculated according to the following equation.

frac = (Lb x (mag/100)) - Lm (5)
For example, when Lb=1058, mag=98%, and Lm=1036, frac=0.84 is calculated.

In S1303, the CPU 603 initializes the accumulated value (variable accum) of the fractional part frac. Here, 0 is substituted for the variable accum.

In S1304, the CPU 603 determines whether or not the variable accum is 1 or more. If the variable accum is not 1 or more, the CPU 603 advances the process to S1311. In S1311, the CPU 603 maintains the period lsync_period. That is, Lm is substituted for the period lsync_period. After that, the CPU 603 advances the process from S1311 to S1307. On the other hand, if the variable accum is 1 or more, the CPU 603 advances the process from S1304 to S1305.

In S1305, the CPU 603 adjusts the period lsync_period. For example, the CPU 603 adds 1 to the period lsync_period (lsync_period=Lm+1).

In S1306, the CPU 603 adjusts the accumulated value (variable accum) based on the result of adjusting the period lsync_period. For example, subtract 1 from the variable accum.

In S1307, the CPU 603 instructs the synchronization unit 604 to specify the period lsync_period. In S1308, the CPU 603 determines whether the synchronization unit 604 has generated the line synchronization signal lsync_x. In this embodiment, the line synchronization signal lsync_x itself generated by the synchronization section 604 is used as a trigger. After confirming that the line synchronization signal lsync_x has been generated, the CPU 603 advances the process to S1309.

In S1309, the CPU 603 determines whether the current line is the last line. If the current line is the last line, the CPU 603 ends the control method. If the current line is not the last line, the CPU 603 advances the process to S1310.

In S1310, the CPU 603 updates the accumulated value (variable accum). For example, CPU 603 adds the fractional part frac to the variable accum. After that, the CPU 603 advances the process to S1304.

Thus, the period lsync_period of the line synchronization signal lsync_x is adjusted line by line according to the scaling factor mag. This adjustment is performed so that the period lsync_period is always an integer multiple of the clock period. Furthermore, the fractional part frac that is less than the clock period is cumulatively added, and when the cumulative result is equal to or greater than the clock period (that is, the variable accum is equal to or greater than 1), 1 is added to the period lsync_period. This makes it possible to finely control the scaling factor without finely adjusting the cycle of the clock signal clk itself.

<Technical Concept Derived from Examples>
[Viewpoint 1]
As shown in FIG. 1, the photoreceptor drum 102 is an example of a rotationally driven photoreceptor (image carrier). The light-emitting elements 350-1 to 350-n are an example of a plurality of light-emitting elements that are arranged at mutually different positions in a direction that intersects the rotation direction of the photoreceptor and that expose the surface of the photoreceptor. Drive circuits 1001-1 to 1001-n are examples of drive circuits that drive a plurality of light emitting elements. The clock unit 608 functions as first generation means for generating a clock signal at regular intervals. The conversion unit 602 functions as output means for outputting image data to the driving circuit in synchronization with the clock signal. The synchronization unit 604 functions as second generation means for generating a line synchronization signal (eg, lsync_x) indicating the write timing of each line corresponding to the image resolution in the rotation direction of the photoreceptor. The CPU 603 functions as control means for controlling the second generation means. As shown in FIG. 12, the CPU 603 secondly generates the cycle of the line synchronizing signal so that it becomes an integral multiple (eg, 1036, 1037) of the cycle of the clock signal according to the scaling factor of the image formed on the photoreceptor. cause the means to generate a line synchronization signal; This eliminates the need for a complicated clock oscillator that can vary the cycle of the clock signal. In addition, since the cycle of the clock signal is maintained constant, a plurality of circuits that operate based on the clock signal operate stably. Alternatively, there is no need to separately prepare a clock oscillator for the CPU 603 and a clock oscillator for the synchronization section 604 . That is, the number of clock oscillators is reduced. Also, expensive signal lines for transmitting high-frequency clock signals are not required. Therefore, it is possible to more easily control the variable magnification in the sub-scanning direction.

[Viewpoint 2]
The CPU 603 may distribute the scaling factor error caused by setting the cycle of the line synchronization signal to an integral multiple of the cycle of the clock signal among a plurality of lines forming the image. This makes it possible not only to easily control the variable magnification in the sub-scanning direction, but also to accurately control the variable magnification in the sub-scanning direction.

[Viewpoint 3]
As described with reference to FIG. 12, the CPU 603 reflects the error of the scaling factor to the average cycle of the line synchronization signals for forming the image, thereby adjusting the error of the scaling factor between the lines. may be distributed in This makes it possible to accurately control the variable magnification in the sub-scanning direction.

[Viewpoints 4 and 5]
As shown in FIG. 12, the CPU 603 may accumulate the scaling factor error for each line to calculate an accumulated value, and distribute the scaling factor error among a plurality of lines based on the accumulated value. For example, when the accumulated value reaches a value corresponding to one cycle of the clock signal, the CPU 603 adds 1 to the cycle of the line synchronization signal obtained as an integral multiple of the cycle of the clock signal, thereby reducing the error of the scaling factor to multiple values. may be distributed between the lines of

[Viewpoints 6 and 7]
As shown in FIG. 13, the CPU 603 may adjust the cumulative value when adding 1 to the period of the line synchronization signal obtained as an integral multiple of the period of the clock signal. For example, the CPU 603 may adjust the cumulative value by subtracting a value corresponding to one cycle of the clock signal from the cumulative value.

[Viewpoint 8]
The CPU 603 may calculate the period of the line synchronizing signal from the interval between a plurality of lines according to the resolution of the image and the peripheral speed of the photosensitive member. Further, the CPU 603 may divide the period of the line synchronization signal by the period of the clock signal to calculate an integer part and a decimal part, and calculate an accumulated value using the decimal part as an error of the scaling factor.

[Viewpoint 9]
The CPU 603 sequentially accumulates the fractional part from the line on the leading end side of the image toward the line on the trailing end side. In this case, the CPU 603 adds 1 to the integer part obtained by dividing by the period of the clock signal when the cumulative value of the decimal part becomes 1 or more. As a result, it is possible to distribute the scaling factor error among a plurality of lines while maintaining the cycle of the line synchronization signal at an integral multiple of the cycle of the clock signal.

The invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the claims are appended to make public the scope of the invention.

102: photoreceptor drum, 106: exposure head, 608: clock section, 602: conversion section, 603: CPU

Claims (9)

a photosensitive member that is rotationally driven;
An exposure head comprising: a plurality of light-emitting elements arranged at different positions in a direction intersecting the rotation direction of the photoreceptor and exposing the surface of the photoreceptor; and a drive circuit driving the plurality of light-emitting elements. and,
a first generating means for generating a clock signal at a constant cycle;
output means for outputting image data to the drive circuit in synchronization with the clock signal;
a second generating means for generating a line synchronization signal indicating timing of writing each line corresponding to image resolution in the rotation direction of the photoreceptor;
and a control means for controlling the second generation means,
The control means generates the line synchronization signal in the second generation means so that the period of the line synchronization signal is an integral multiple of the period of the clock signal according to the scaling factor of the image formed on the photoreceptor. An image forming apparatus characterized by: The control means disperses an error in the scaling factor caused by setting the period of the line synchronization signal to an integral multiple of the period of the clock signal, among a plurality of lines forming the image. Item 1. The image forming apparatus according to item 1. The controller disperses the error of the scaling factor among the plurality of lines by reflecting the error of the scaling factor on an average period of a plurality of line synchronization signals for forming the image. 3. The image forming apparatus according to claim 2, wherein: The control means accumulates the error of the scaling factor for each line to calculate an accumulated value, and distributes the error of the scaling factor among the plurality of lines based on the accumulated value. 4. The image forming apparatus according to claim 2 or 3. When the cumulative value reaches a value corresponding to one cycle of the clock signal, the control means adds 1 to the cycle of the line synchronizing signal obtained as an integer multiple of the cycle of the clock signal, so that the variable 5. The image forming apparatus according to claim 4, wherein the error in magnification is dispersed among the plurality of lines. 6. The image formation according to claim 5, wherein said control means adjusts said accumulated value when adding 1 to the period of said line synchronizing signal obtained as an integer multiple of the period of said clock signal. Device. 7. The image forming apparatus according to claim 6, wherein said control means adjusts said cumulative value by subtracting a value corresponding to one cycle of said clock signal from said cumulative value. The control means calculates the period of the line synchronization signal from the intervals between the plurality of lines corresponding to the resolution of the image and the peripheral speed of the photoreceptor, and converts the period of the line synchronization signal into the clock signal. 8. An integer part and a decimal part are calculated by dividing by the period of , and the cumulative value is calculated by using the decimal part as the error of the scaling factor. image forming device. The control means accumulates the decimal part in order from the leading line of the image to the trailing line, and when the accumulated value of the decimal part becomes 1 or more, By adding 1 to the integer part obtained by division, while maintaining the period of the line synchronization signal at an integer multiple of the period of the clock signal, the error of the scaling factor is distributed among the plurality of lines. 9. The image forming apparatus according to claim 8, wherein the image forming apparatus