JP2022108501A - Exposure head and image formation apparatus - Google Patents

Abstract

To reduce such a risk that shortage of a light amount occurs even in a case where light emitting timing of a light-emitting thyristor is quickly switched.SOLUTION: The drive of a light-emitting thyristor by a precharge control part 1002 is started before shifting to a continuous period being the next on-state and before starting the drive of the light-emitting thyristor by a drive current control part 1001 in a period being the next on-state after a drive period of the light-emitting thyristor by the drive current control part 1001 is terminated in a period in which the light-emitting thyristor is in the on-state. Concretely, the drive of the light-emitting thyristor is started at timing T1 before switching of the ON state of a transfer thyristor.SELECTED DRAWING: Figure 9

Description

The present invention relates to an exposure head and an image forming apparatus equipped with the exposure head.

2. Description of the Related Art In a printer, which is an electrophotographic image forming apparatus, a method of forming a latent image by exposing a photosensitive drum using an exposure head using a light emitting element such as an LED is generally known. The exposure head includes a light emitting element array arranged in the longitudinal direction of the photosensitive drum, and a rod lens array for forming an image of the light from the light emitting element array on the photosensitive drum. As a configuration of the light-emitting element, a configuration having a surface-emitting shape in which the direction of light irradiation from the light-emitting surface is the same as that of the rod lens array is known. The length of the light emitting element array is determined according to the width of the image area on the photosensitive drum, and the element spacing is determined according to the resolution of the printer.

For example, in the case of a 1200 dpi printer, the pixel spacing is approximately 21.16 μm, so the element spacing is also 21.16 μm. In the case of a printer capable of printing A3 size (approximately 300 mm wide) with this element spacing, 14173 light emitting elements are arranged. Mounting a large number of light emitting elements on a printed circuit board increases the mounting cost. Therefore, conventionally, a method has been used in which a plurality of light emitting element arrays are formed on one semiconductor chip to reduce the number of elements mounted on a printed circuit board. For example, when 500 light emitting elements are formed on one semiconductor chip, by mounting 28 semiconductor chips on a printed circuit board, it is possible to form an image with an image area width of 296 mm. By forming a plurality of light emitting elements on one semiconductor chip in this manner, the mounting cost can be reduced. A printer using such an exposure head uses fewer parts than a laser scanning printer that deflects and scans a laser beam with a polygon motor, so it is easy to reduce the size and cost of the device. be.

Patent Document 1 describes a self-scanning light-emitting element array having a shift portion. In this array, by providing a shift section (hereinafter referred to as a transfer circuit) in the semiconductor chip, the number of connection signals between the chip and the printed circuit board can be reduced, and the mounting cost of wire bonding for connecting signals is reduced. can be reduced.

JP 2019-214153 A

In the self-scanning light-emitting element array having the above-described transfer circuit, the transfer clock signal that is input switches the transfer thyristors corresponding to the light-emitting thyristors (light-emitting elements) between ON and OFF states. Here, in order to perform the switching operation of the transfer thyristor, it is necessary to turn off the light-emitting thyristor connected to the gate of the transfer thyristor. Therefore, it is difficult to turn on the light-emitting thyristor during the switching operation of the transfer thyristor (hereinafter referred to as a transfer period).

On the other hand, the self-scanning light-emitting element array has the characteristic that the terminal capacitance of the light-emitting thyristor is relatively large. For example, when 200 light-emitting thyristors each having an anode terminal parasitic capacitance of 1.0 PF are connected in an array, the total anode terminal parasitic capacitance is 200 PF. That is, in order to start light emission, the parasitic capacitance of 200 PF must be charged to a predetermined threshold value or higher, and depending on the drive capability of the drive circuit, it takes time to start light emission. If it takes a long time for the light emission to rise, a sufficient amount of light cannot be obtained during the rising period. Therefore, in an image forming apparatus that requires a high-speed image forming operation, it is difficult to secure the light emission time, that is, the amount of light required for image formation.

SUMMARY OF THE INVENTION It is an object of the present invention to reduce the risk of insufficient light intensity even when the light emission timing of a light emitting thyristor is switched at high speed.

In order to achieve the above object, the present invention provides a plurality of transfer thyristors whose on-states are sequentially shifted based on an input clock signal, and a plurality of light-emitting thyristors which emit light to expose a photoreceptor, wherein the plurality of and a self-scanning light-emitting element array in which the light-emitting light-emitting thyristor is selected based on the state of the transfer thyristor, wherein the light-emitting thyristor is connected to a gate terminal of each of the transfer thyristors. a first driving means for driving the light-emitting thyristor with a voltage higher than a threshold voltage based on a first driving signal; and driving the light-emitting thyristor with a voltage equal to or lower than the threshold voltage based on a second driving signal. Control for controlling the timing of driving the light-emitting thyristor by a second driving means, and the first driving means based on the first driving signal and the second driving means based on the second driving signal, respectively after the driving period of the light-emitting thyristor by the first driving means in the period in which the light-emitting thyristor is in the ON state ends, and before shifting to the next continuous period in which the light-emitting thyristor is in the ON state; and a control means for causing the second driving means to start driving the light emitting thyristors before the first driving means starts driving the light emitting thyristors in the next ON state period. Characterized by

Advantageous Effects of Invention According to the present invention, it is possible to reduce the possibility that the amount of light will be insufficient even when the light emission timing of the light emitting thyristor is controlled to be switched at high speed.

1 is a schematic cross-sectional view showing the overall configuration of an image forming apparatus; FIG. 2A and 2B are diagrams for explaining a positional relationship between an exposure head and a photosensitive drum, and a diagram for explaining a configuration of the exposure head; FIG. It is a figure which shows a printed circuit board and a light emitting element array chip. 3 is a block diagram of an image controller section and an exposure head; FIG. 4 is a block diagram of a chip data converter; FIG. It is a figure which shows the internal circuit of a light emitting element drive part. It is an equivalent circuit obtained by extracting a part of the light emitting element array. FIG. 4 is a diagram showing the distribution of gate potentials of a common gate; 4 is a timing chart showing waveforms of driving signals and the like; It is a figure which shows the internal circuit of a light emitting element drive part. 4 is a timing chart showing waveforms of driving signals and the like;

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
[Configuration of Image Forming Apparatus]
FIG. 1 is a schematic cross-sectional view showing the overall configuration of an image forming apparatus to which an exposure head according to the first embodiment of the invention is applied.

This image forming apparatus is, for example, an electrophotographic multifunction peripheral (MFP) having a scanner function and a printer function. has a printer control unit that controls the The scanner unit 100 illuminates a document placed on a document table to optically read the document image, converts the read image into an electrical signal, and generates image data.

The image forming unit 103 includes an endless transfer belt 111 and four image forming stations. The transfer belt 111 rotates counterclockwise in FIG. The four image forming stations are arranged along the transfer belt 111 in the order of cyan (C), magenta (M), yellow (Y), and black (K). The four imaging stations have the same configuration. Each image forming station includes a photosensitive drum 102, which is a photosensitive member that rotates clockwise in FIG. The exposure heads 106a, 106b, 106c, and 106d, which are exposure units, correspond to black (K), yellow (Y), magenta (M), and cyan (C) of the image forming station, respectively. Since the operations in each image forming station are common, the operations of the exposure head 106a and the components corresponding thereto will be described below as a representative.

In the image forming unit 103 , the photosensitive drum 102 is rotationally driven, and the charger 107 charges the photosensitive drum 102 . The exposure head 106a condenses light emitted from the chip surface of an arranged self-scanning light emitting element (Self-Scanning LED: SLED) array (hereinafter referred to as a light emitting element array) onto the photosensitive drum 102 by means of a rod lens array. to form an electrostatic latent image. A developing device 108 develops the electrostatic latent image formed on the photosensitive drum 102 with toner. Then, the developed toner image is transferred onto the recording paper on the transfer belt 111 . A series of such electrophotographic processes are performed at each image forming station. During image formation, the magenta (M), yellow (Y), and black (K) image forming stations are sequentially formed after a predetermined time has passed since the image forming station for cyan (C) started forming images. , the image forming operation is executed.

The paper feed/conveyance unit 105 includes internal paper feed units 109a and 109b, an external paper feed unit 109c as a large-capacity paper feed unit, and a manual paper feed unit 109d as paper feed units for feeding recording paper. ing. At the time of image formation, recording paper is fed from a paper feeding unit that has been instructed in advance, and the fed recording paper is conveyed to registration rollers 110 . The registration roller 110 conveys the recording paper to the transfer belt 111 at the timing when the toner image formed in the image forming unit 103 is transferred to the recording paper. A toner image formed on the photosensitive drum 102 of each image forming station is sequentially transferred onto the recording paper conveyed by the transfer belt 111 . The recording paper onto which the unfixed toner image has been transferred is conveyed to fixing section 104 . The fixing unit 104 incorporates a heat source such as a halogen heater, and heats and presses the toner image on the recording paper with two rollers to fix the toner image on the recording paper. The recording paper on which the toner image is fixed by the fixing unit 104 is discharged to the outside of the image forming apparatus by the discharge roller 112 .

An optical sensor 113 is arranged at a position facing the transfer belt 111 . The optical sensor 113 detects the position of the test chart printed on the transfer belt 111 in order to derive the amount of color misregistration between stations. The amount of color shift derived here is notified to the image controller unit 415 (FIG. 4), and the image position of each color is corrected. With this control, a full-color toner image without color shift is transferred onto the paper.

The printer control unit communicates with an MFP (multi-function printer) control unit that controls the entire image forming apparatus, and executes control according to instructions from the control unit. At the same time, the printer control unit manages the states of the scanner, image forming, fixing, and paper feed/conveyance units, and issues instructions so that the entire unit can operate smoothly in harmony.

[Configuration of Exposure Head]
Next, the exposure head 106a that exposes the photosensitive drum 102 will be described with reference to FIG. FIG. 2A is a perspective view showing the positional relationship between the exposure head 106a and the photosensitive drum 102. FIG. FIG. 2B is a diagram for explaining the internal configuration of the exposure head 106a and how the light flux from the exposure head 106a is focused on the photosensitive drum 102 by the rod lens array 203. As shown in FIG. As shown in FIG. 2A, the exposure head 106a is attached to the image forming apparatus by a mounting member (not shown) at a position facing the photosensitive drum 102 (FIG. 1).

As shown in FIG. 2B, the exposure head 106a has a printed circuit board 202, a light emitting element array element group 201 mounted on the printed circuit board 202, a rod lens array 203, and a housing 204. A rod lens array 203 and a printed circuit board 202 are attached to the housing 204 . A rod lens array 203 converges the light flux from the light emitting element array element group 201 onto the photosensitive drum 102 . At the factory where the exposure head 106a is manufactured, assembly and adjustment work is performed for the exposure head 106a alone, and focus adjustment and light amount adjustment of each spot are performed. Here, it is assembled so that the distance between the photosensitive drum 102 and the rod lens array 203 and the distance between the rod lens array 203 and the light emitting element array element group 201 are predetermined intervals. As a result, light from the light emitting element array element group 201 forms an image on the photosensitive drum 102 . Therefore, when adjusting the focus at the factory, the mounting position of the rod lens array 203 is adjusted so that the distance between the rod lens array 203 and the light emitting element array element group 201 is a predetermined value.

Further, when adjusting the amount of light in the factory, the peak amount of light is measured when each light emitting element of the light emitting element array element group 201 is sequentially DC-lit. Then, the DC current setting data for the driving current of each light emitting element is determined so that the light condensed through the rod lens array 203 has a predetermined target light intensity. Next, light emission rise adjustment data is determined from the integrated amount of light when the light emitting element is pulse-lighted. For example, by setting the pulse cycle to the same lighting cycle as that during image formation, measuring the integrated light quantity when light is emitted under the condition that the pulse duty is 50%, and calculating the difference from the light quantity of 50% during DC lighting. , the amount of light reduced due to the rise delay can be calculated.

By adjusting the correction amount of a precharge control unit 1002 (described later in FIG. 6) that corrects the rise time at the start of light emission for the light amount reduction due to the rise delay, the adjustment data when the light amount is adjusted to the desired level is obtained. , are determined as rising adjustment data. Further, the rising time of light emission has individual variations due to characteristic differences between light emitting elements (chips) in the light emitting element array element group 201 and characteristic differences of driving circuits. Therefore, the adjustment data is determined for each light emitting element. The DC current setting data and the rising adjustment data are stored in the memory 420 (FIG. 4), which is a storage unit built into the exposure head 106a.

In the image forming apparatus, the rise adjustment data is read from the memory 420 during image formation and set in the light emitting element driving section 414 (see FIGS. 4 and 6) in the exposure head 106a. The light emitting element driving section 414 will be described in detail later.

[Configuration of Light Emitting Element Array Element Group]
3A and 3B are diagrams showing a printed circuit board 202 on which light emitting element array element groups 201 are arranged. FIG. 3A is a schematic diagram showing the configuration of the surface (second surface) of the printed circuit board 202 opposite to the surface (first surface) on which the light emitting element array element group 201 is mounted. FIG. 3B is a schematic diagram showing the configuration of the surface of the printed circuit board 202 on which the light emitting element array element group 201 is mounted.

The light emitting element array element group 201 has a structure in which 29 light emitting element array chips 1 to 29 are arranged in two rows in a zigzag pattern along the longitudinal direction of the printed circuit board 202 . In FIG. 3A, the vertical direction indicates the sub-scanning direction (rotational direction of the photosensitive drum 102), and the horizontal direction indicates the main scanning direction. Inside each light-emitting element array chip, light-emitting elements having a total of 516 light-emitting points are arranged at a predetermined resolution pitch in the longitudinal direction of the light-emitting element array chip. In this example, the pitch of each light emitting element of the light emitting element array chip is approximately 21.16 μm (≈2.54 cm/1200 dots), which is the pitch of the first resolution of 1200 dpi. As a result, the end-to-end spacing between the 516 light emitting points in one light emitting element array chip is approximately 10.9 mm (≈21.16 μm×516). As described above, the light emitting element array element group 201 is composed of 29 light emitting element array chips. Therefore, the number of light emitting elements that can be exposed in the light emitting element array element group 201 is 14,964 elements (=516 elements×29 chips), and the image width in the main scanning direction is approximately 316 mm (≈approximately 10.9 mm×29 chips). Corresponding image formation becomes possible.

FIG. 3(c) is a diagram showing the boundary between the light emitting element array chips in the longitudinal direction of the printed circuit board 202. As shown in FIG. As shown in FIG. 3(c), wire bonding pads to which control signals are input are arranged at the ends of the light emitting element array chip. is driven. Also, the light emitting element array chip has a plurality of light emitting elements. Even at the boundary between the light-emitting element array chips, the pitch of the light-emitting elements in the longitudinal direction (the distance between the center points of the two light-emitting elements) is approximately 21.16 μm, which is the pitch of the resolution of 1200 dpi. . Further, the distance S between the light emitting points of the light emitting element array chips in the first row and the light emitting element array chips in the second row is about 84 μm (distance of integral multiples of each resolution of 4 pixels at 1200 dpi and 8 pixels at 2400 dpi). It has become.

Further, as shown in FIG. 3(a), drive units 303a and 303b and a connector 305 are mounted on the surface of the printed circuit board 202 opposite to the surface on which the light emitting element array element group 201 is mounted. . Driving units 303a and 303b arranged on both sides of the connector 305 are driver ICs for driving the light emitting element array chips 1 to 15 and the light emitting element array chips 16 to 29, respectively. The drive units 303a and 303b are connected to the connector 305 via control signal lines 304a and 304b, respectively. The connector 305 is connected to a signal line, power supply voltage, and ground for controlling the drive units 303a and 303b from an image controller unit 415 (see FIG. 4), which will be described later. The connector 305 is connected to the drive units 303a and 303b. . Further, from the drive units 303a and 303b, wiring for driving the light emitting element array element group 201 passes through the inner layer of the printed circuit board 202, and each wiring is connected to the light emitting element array chips 1 to 15 and the light emitting element array chips 16 to 29. It is connected to the.

[Control block]
FIG. 4 is a block diagram of the image controller section 415 and the exposure head 106a. In FIG. 4, the light emitting element array chips 1 to 15 and the driving section 303a will be described as a representative, but the configuration and operation are the same for the light emitting element array chips 16 to 29 and the driving section 303b. In order to simplify the explanation, the single-color processing will be described, but it is assumed that the same processing as the single-color processing is performed in parallel for four colors.

The image controller section 415 has a connector 416 for transmitting signals for controlling the exposure head 106a. This signal includes image data, a Line synchronizing signal, and a control signal from the CPU 400 . Image data, Line synchronization signals, and control signals are transmitted from the connector 416 via cables 417, 418, and 419 connected to the connector 305 of the exposure head 106a, and each signal is input to the connector 305 of the exposure head 106a. be.

In the image controller unit 415, the CPU 400 performs image data processing and print timing processing. The image controller unit 415 has functional blocks of an image data generation unit 401 , a full data shift unit 402 , a chip data conversion unit 403 , a chip data shift unit 404 , a data transmission unit 405 and a synchronization signal generation unit 406 .

The image data generating unit 401 dithers input image data received from the scanner unit 100 or an external device connected to the image forming apparatus at a resolution designated by the CPU 400 to generate an image for print output. Generate data. The CPU 400 determines image shift amounts in the main scanning direction (longitudinal direction of the exposure head 106) and the sub-scanning direction (paper transport direction) from the amount of color misregistration detected by the optical sensor 113. Specifies the amount of shift. Based on the shift amount instructed by the CPU 400, the full-surface data shift unit 402 shifts the image data input from the image data generation unit 401 to the entire image area within the page.

The synchronization signal generation unit 406 generates a periodic signal for one line in the rotation direction of the photosensitive drum 102 (hereinafter referred to as a line synchronization signal) in synchronization with the rotation speed of the photosensitive drum 102 . The CPU 400 sets the period in which the surface of the photosensitive drum 102 moves in the rotational direction by the pixel size based on the instructed resolution with respect to the rotation speed of the photosensitive drum 102 determined in advance as one line period, and generates the synchronizing signal generator. Indicate at 406 the time interval of the signal period. The speed in the sub-scanning direction is calculated by the CPU 400 using real-time detection results when a function of detecting the printing speed (for example, an encoder installed on the rotary shaft of the photosensitive drum) is provided. If the printer does not have a function to detect the printing speed, the CPU 400 calculates the speed in the sub-scanning direction using the set value (fixed value) of the printing speed that is set for speed control of the photosensitive drum.

FIG. 5 is a block diagram of the chip data conversion section 403. As shown in FIG. The chip data conversion unit 403 reads line data from the entire surface data shift unit 402 line by line in the sub-scanning direction of the photosensitive drum 102 in synchronization with the line synchronization signal. After storing the data in the line memory 500, the chip data conversion unit 403 stores the data in the memories 501 to 529 corresponding to the light emitting element array chips 1 to 29, respectively.

A READ control unit 531 shown in FIG. 5 instructs the line memory 500 to read data according to the count value of the counter 530 . The WR control unit 532 divides and writes the data for one line read from the line memory 500 into the memories 501 to 529 according to the count value of the counter 530 . By this operation, one line of data is stored in the memories 501 to 529 corresponding to the light emitting element array chips 1 to 29, respectively. It is assumed that 10 lines of image data are stored in order to cope with the data shift in the sub-scanning direction on a chip-by-chip basis by the subsequent chip data shifter 404 .

The chip data shift unit 404 shifts the image in the sub-scanning direction by controlling the data read timing from the memories 501 to 529 based on the image shift information in the sub-scanning direction for each light emitting element array chip instructed in advance by the CPU 400. make a shift. As described above, the memories 501 to 529 store 10 lines of image data, and by advancing the data read timing, the image data can be shifted in the paper leading edge direction. For example, by advancing the readout timing by one period of the Line synchronization signal, the image data is shifted by one line.

In this embodiment, image data shift is performed for each light emitting element array chip based on position correction information for each light emitting element array chip instructed by the CPU 400 . The position correction information instructed by the CPU 400 is calculated by adding the interval (eight pixels) in the sub-scanning direction due to the zigzag arrangement (two rows) and the pre-measured mounting position deviation of each light emitting element array chip. be. Here, the mounting position deviation refers to a position deviation from the design nominal position that occurs due to variations in mounting on the printed circuit board 202 . By measuring the mounting position of each light emitting element array chip in the inspection process of the exposure head 106 and holding the position correction information for each chip in the memory 420 based on the measured value, the position correction information can be calculated. . The data transmission unit 405 transmits the image data after the series of image data processing described above to the exposure head 106a.

Next, processing in the drive unit 303a will be described. The driving unit 303 a has functional blocks of a data receiving unit 407 , a filtering unit 408 , an LUT 410 , a PWM signal generating unit 411 , a timing control unit 412 , a control signal generating unit 413 , a memory 420 and a light emitting element driving unit 414 .

The CPU 400 communicates with each section of the driving section 303a via the connector 305 and the communication line 421. FIG. The data receiving section 407 receives the signal transmitted from the data transmitting section 405 . Here, the data receiving unit 407 and the data transmitting unit 405 transmit and receive image data on a line-by-line basis in synchronization with the line synchronization signal. As described above, the chip data conversion unit 403 arranges data for each of the 29 light emitting element array chips, and subsequent processing blocks process each image data in parallel. The driving unit 303a is assumed to have a circuit capable of receiving image data corresponding to the light emitting element array chips 1 to 15 and processing in parallel for each light emitting element array chip.

The PWM signal generation unit 411 generates a pulse width signal (hereinafter referred to as a PWM signal) corresponding to the light emission time during which the light emitting element array chip emits light within one pixel section according to the data value for each pixel input from the data reception unit 407. to generate The timing of outputting the PWM signal is controlled by the timing control section 412 . The timing control unit 412 generates a synchronizing signal corresponding to the pixel interval of each pixel from the Line synchronizing signal generated by the synchronizing signal generating unit 406 , and outputs the signal to the PWM signal generating unit 411 and the control signal generating unit via the signal line 422 . 413 , send to light emitting element drive unit 414 . This makes it possible to control the PWM signal generating section 411, the control signal generating section 413, and the light emitting element driving section 414 in synchronization. The PWM signal generator 411 transmits the PWM signal to the light emitting element driver 414 through the signal line 423 .

Each light-emitting element array chip is configured to independently drive four light-emitting elements at the same time. The light emitting element driving section 414 supplies 4 lines of driving signals (total 15 chips×4=60 lines) for each light emitting element array chip. The drive signals supplied to each light emitting element array chip are assumed to be lighting signals ΦW1 to ΦW4 (see FIG. 7). On the other hand, the operation of a transfer thyristor (see FIG. 7), which will be described later, sequentially drives the light emitting element array chips. The control signal generation unit 413 generates control signals Φs, Φ1, and Φ2 (see FIGS. 7 and 9) for transferring the transfer thyristors for each pixel from the synchronization signals corresponding to the pixel intervals generated by the timing control unit 412. Generate.

FIG. 6 is an equivalent circuit diagram corresponding to one ch (channel) in the light emitting element driving section 414. As shown in FIG. Each signal is input to this circuit from the communication line 421, the signal line 423, and the signal line 422 described above. The output terminal OUT is connected to one of the lighting signal lines (ΦW1 to ΦW4) of the light emitting elements (light emitting thyristors L4n−3 to L4n+4, etc.) of the light emitting element array element group 201 (see FIG. 7). The CPU 400 can control the light emission amount of the light emitting element by controlling the output current (hereinafter referred to as drive current Iout).

The light emitting element driving section 414 is roughly divided into four blocks: a drive signal generation section 1009 , a drive current generation section 1000 , a drive current control section 1001 and a precharge control section 1002 . The drive current control unit 1001 supplies the light emitting element with the drive current Iout after the light emitting element transitions to the ON state. A precharge control unit 1002 as a second driving unit starts driving the light emitting element before the drive current control unit 1001 as a first driving unit starts driving the light emitting element. Specifically, the precharge control unit 1002 supplies the light emitting element with the drive current Iout during the light emission rising period (this is called a precharge operation). Details will be described below.

The CPU 400 reads the DC current setting data and the rise adjustment data from the memory 420 and sets these data in the register in the drive signal generation section 1009 . The drive signal generator 1009 incorporates a DAC (DA converter) and outputs an analog voltage Vin based on set data. An analog voltage Vin generated based on the DC current setting data is input to the drive current generator 1000 via the signal line 1012 . An analog Vcharge voltage (threshold voltage) generated by the DAC in the drive signal generator 1009 based on the rise adjustment data is input to the precharge controller 1002 via the signal line 1011 as a Vcharge signal.

The PWM signal output from the PWM signal generation unit 411 is stepped up to a voltage (5 V) capable of driving the circuit of the drive current control unit 1001 by the drive signal generation unit 1009, and is passed through the signal line 1013 as a P_dirve signal to generate the drive current. It is input to the control unit 1001 . The drive signal generator 1009 generates a P_precharge signal for controlling the operation timing of the precharge controller 1002 from the synchronization signal for each pixel output from the timing controller 412 . The generated P_precharge signal is input to precharge control section 1002 via signal line 1010 .

Here, the P_drive signal is a signal that instructs the timing to turn on the output current from the drive current control section 1001 . The P_precharge signal is a signal that turns on the output current from the precharge control section 1002 . The P_discharge signal transmitted via the signal line 1014 is a signal that becomes Hi under the exclusive condition of the P_drive signal and the P_precharge signal. Under the condition that the P_discharge signal is Hi, the switch 1003 between the output terminals OUT and GND is turned on, and an OFF operation is performed to extinguish the light emitting element.

Drive current generator 1000 generates current I1=Vin/R1 determined by resistor R1 according to input voltage Vin. Drive current generator 1000 generates current I2 from current I1 via first current mirror circuit 1005 . Drive current generator 1000 and drive current controller 1001 constitute a second current mirror circuit 1006 . The second current mirror circuit 1006 supplies the current I2 to the drive current controller 1001 as the current I3. The drive current control section 1001 further has a third current mirror circuit 1007 to generate the drive current Iout from the current I3.

As described above, the current I1 generated by the drive current generator 1000 is multiplied by the ratios corresponding to the respective mirror ratios by the first, second and third current mirror circuits, and is driven from the drive current controller 1001. It is output as current Iout.

In the precharge control section 1002, a switch 1004 and a control section 1008 for controlling the switch 1004 are arranged between the output terminal OUT and the power supply. Switch 1004 is controlled by the P_precharge signal through controller 1008 . During the period when the P_precharge signal is Low, the gate potential of the switch 1004 is at the GND level and is OFF. During the period when the P_precharge signal is High, the gate potential of the switch 1004 becomes the Vcharge voltage and the precharge operation is enabled.

FIG. 7 is an equivalent circuit extracted from a part of the light emitting element array. The light-emitting elements of the light-emitting element array in this embodiment are light-emitting thyristors whose light-emitting portions are composed of thyristors.

In FIG. 7, Ra and Rg are an anode resistance and a gate resistance, respectively, Tn etc. are transfer thyristors, Dn etc. are transfer diodes, and Ln etc. are light emitting thyristors. Gn and the like represent the common gate (gate terminal) of the corresponding transfer thyristor Tn and the light-emitting thyristor Ln connected to the transfer thyristor Tn. Here, n is an integer of 2 or more. Lines labeled with Φ1 are transfer lines for odd-numbered transfer thyristors, and lines labeled with Φ2 are transfer lines for even-numbered transfer thyristors. Lines labeled ΦW1 to ΦW4 are lighting signal lines for the light-emitting thyristors. VGK is the gate line and the line labeled Φs is the start pulse line. As shown in FIG. 7, four light-emitting thyristors L4n-3 to L4n are connected to one transfer thyristor Tn, and the four light-emitting thyristors L4n-3 to L4n can be lit at the same time. It has become.

Next, operation of the circuit shown in FIG. 7 will be described. In the circuit diagram of FIG. 7, 5V is applied to the gate line VGK, and the voltages input to the Φ1 transfer line, Φ2 transfer line, and ΦW1 to ΦW4 lighting signal lines are also 5V. When the transfer thyristor Tn is in the ON state (ON state), the potential of the common gate Gn of the transfer thyristor Tn and the light-emitting thyristor Ln connected to the transfer thyristor Tn is lowered to about 0.2V. Since the common gate Gn of the light emitting thyristor Ln and the common gate Gn+1 of the light emitting thyristor Ln+1 are connected by the coupling diode Dn, a potential difference substantially equal to the diffusion potential of the coupling diode Dn is generated between them. In this example, the diffusion potential of the coupling diode Dn is approximately 1.5V. Therefore, the potential of the common gate Gn+1 of the light-emitting thyristor Ln+1 is 1.7V (=0.2V+1.5V) obtained by adding the diffusion potential of 1.5V to the potential of the common gate Gn of the light-emitting thyristor Ln of 0.2V. .

Similarly, the potential of the common gate Gn+2 of the light-emitting thyristor Ln+2 is 3.2 V (=1.7 V+1.5 V), and the potential of the common gate Gn+3 (not shown) of the light-emitting thyristor Ln+3 (not shown) is 4.7 V (= 3.2V+1.5V). However, the potential after the common gate Gn+4 (not shown) of the light-emitting thyristor Ln+4 is 5V because the voltage of the gate line VGK is 5V and cannot reach a higher voltage. As for the potential of the common gate Gn-1 before the common gate Gn of the light-emitting thyristor Ln (to the left of the common gate Gn in FIG. 7), the potential of the gate line Gn-1 is in the reverse biased state. The voltage of VGK is applied as it is and becomes 5V.

FIG. 8(a) is a diagram showing the distribution of the gate potential of the common gate Gn of each light-emitting thyristor Ln when the transfer thyristor Tn is in the ON state. Common gates Gn−1, Gn, Gn+1, . . . refer to the common gates of the light emitting thyristors in FIG. The vertical axis of FIG. 8(a) indicates the gate potential.

The voltage required to turn on each transfer thyristor (hereinafter referred to as threshold voltage) is approximately the same as the sum of the gate potential of the common gate of each light emitting thyristor and the diffusion potential (1.5 V). be. For example, when the transfer thyristor is ON, the transfer thyristor Tn+2 has the lowest common gate potential among the transfer thyristors connected to the Φ2 transfer line of the same transfer thyristor Tn. The potential of the common gate Gn+2 of the light-emitting thyristor Ln+2 connected to the transfer thyristor Tn+2 is 3.2 V (=1.7 V+1.5 V) as described above. Therefore, the threshold voltage of the transfer thyristor Tn+2 is 4.7V (=3.2V+1.5V). However, since the transfer thyristor Tn is ON, the potential of the Φ2 transfer line is drawn to about 1.5 V (diffusion potential), and 1.5 V is lower than the threshold voltage of the transfer thyristor Tn+2. Thyristor Tn+2 cannot be turned ON. Since the threshold voltages of the other transfer thyristors connected to the same transfer line Φ2 are higher than the threshold voltage of the transfer thyristor Tn+2, they cannot be similarly turned on, and only the transfer thyristor Tn is turned on. can keep.

Regarding the transfer thyristors connected to the Φ1 transfer line, the threshold voltage of the transfer thyristor Tn+1, which has the lowest threshold voltage, is 3.2V (=1.7V+1.5V). Then, the transfer thyristor Tn+3 (not shown in FIG. 7) having the next lowest threshold voltage is 6.2V (=4.7V+1.5V). In this state, when 5V is input to the transfer line Φ1, only the transfer thyristor Tn+1 can transition to the ON state. In this state, the transfer thyristor Tn and the transfer thyristor Tn+1 are simultaneously turned ON. Therefore, in FIG. 7, the gate potentials of the transfer thyristors Tn+2, Tn+3, etc. provided on the right side of the transfer thyristor Tn+1 are lowered by the diffusion potential (1.5 V). However, since the voltage of the gate line VGK is 5V and the voltage of the common gate of the light-emitting thyristors is limited by the voltage of the gate line VGK, the gate potential on the right side of the transfer thyristor Tn+5 is 5V. FIG. 8(b) shows the gate voltage distribution of each of the common gates Gn−1 to Gn+4 at this time, and the vertical axis represents the gate potential.

In this state, when the potential of the transfer line Φ2 is lowered to 0V, the transfer thyristor Tn is turned off, and the potential of the common gate Gn of the transfer thyristor Tn rises to the VGK potential. The transfer thyristor Tn+1 remains ON. FIG. 8(c) is a diagram showing the gate voltage distribution at this time, and the vertical axis indicates the gate potential. Thus, the transfer of the ON state from the transfer thyristor Tn to the transfer thyristor Tn+1 is completed.

Next, the light emitting operation of the light emitting thyristor will be described. The gates of the four light emitting thyristors L4n-3 to L4n are commonly connected to the common gate Gn of the transfer thyristor Tn. Therefore, when only the transfer thyristor Tn is ON, the gate potential of the light-emitting thyristors L4n-3 to L4n is 0.2 V, which is the same as the common gate Gn. Therefore, since the threshold value of each light-emitting thyristor is 1.7V (=0.2V+1.5V), if a voltage of 1.7V or higher is input from the ΦW1 to ΦW4 lighting signal lines of the light-emitting thyristors, the light-emitting The thyristors L4n-3 to L4n can be lit. Therefore, when the transfer thyristor Tn is ON, the four light emitting thyristors L4n−3 to L4n are selected by inputting the lighting signal, which is the driving signal, to the ΦW1 to ΦW4 lighting signal lines. It is possible to emit light

At this time, the potential of the common gate Gn+1 of the transfer thyristor Tn+1 adjacent to the transfer thyristor Tn is 1.7 V, and the threshold voltage of the light-emitting thyristors L4n+1 to 4n+4 gate-connected to the common gate Gn+1 is 3.2 V (= 1.7V+1.5V). Since the lighting signal input from the ΦW1 to ΦW4 lighting signal lines is 5V, it seems that the light emitting thyristors L4n+1 to L4n+4 are also lit in the same lighting pattern as the light emitting thyristors L4n−3 to 4n. However, the light-emitting thyristors L4n-3 to L4n have lower threshold voltages. Therefore, when the lighting signal is input from the ΦW1 to ΦW4 lighting signal lines, the light-emitting thyristors L4n−3 to L4n are turned on earlier than the light-emitting thyristors L4n+1 to L4n+4.

Once the light emitting thyristors L4n-3 to L4n are turned on, the connected ΦW1 to ΦW4 lighting signal lines are pulled down to approximately 1.5 V (diffusion potential). Therefore, the potential of the ΦW1 to ΦW4 lighting signal lines becomes lower than the threshold voltage of the light emitting thyristors L4n+1 to L4n+4, so that the light emitting thyristors L4n+1 to L4n+4 cannot be turned ON. Thus, by connecting a plurality of light-emitting thyristors to one transfer thyristor, it is possible to light the plurality of light-emitting thyristors simultaneously.

Here, as in the operation described above, in order to control the gate potential of the transfer thyristor, the corresponding light-emitting thyristor needs to be in the OFF state (OFF state) at the timing when the next transfer thyristor in the selection order turns ON. . This is because, when the light-emitting thyristor is turned on, even if it is attempted to switch the gate potential under the control of the transfer thyristor, the gate voltage is pulled to 0.2 V, so the control of the gate potential by the transfer thyristor becomes ineffective. be.

In this embodiment, as will be described in detail later, the timing of applying voltage to the certain light-emitting thyristor is devised in order to shorten the rising time of the certain light-emitting thyristor. That is, the CPU 400 applies a voltage to the certain light-emitting thyristor in a state in which the light-emitting thyristor immediately before in the selection order is OFF and the transfer thyristor corresponding to the light-emitting thyristor immediately before is ON. Start charging operation. At this time, the CPU 400 applies a voltage to the certain light-emitting thyristor at a level at which the terminal voltage of the certain light-emitting thyristor becomes 1.7 V or less. Such an operation makes it possible to shorten the rise time of light emission of the light-emitting thyristor without affecting the transfer operation of the transfer thyristor.

FIG. 9 is a timing chart showing waveforms of driving signals and the like of the circuit shown in FIG. FIG. 9 shows signal waveforms in the gate line VGK, the start pulse line Φs, the transfer lines Φ1 and Φ2 of the odd-numbered and even-numbered transfer thyristors, the P_drive line, the P_precharge line, and the lighting signal line ΦW1 in order from the top. Moreover, the horizontal axis of FIG. 9 indicates time.

5V is always supplied to the gate line VGK. A control signal Φ1, which is a clock signal for odd-numbered transfer thyristors, and a control signal Φ2, which is a clock signal for even-numbered transfer thyristors, are applied at the same period Tc. The start pulse line Φs is supplied with 5V, but is dropped to 0V in order to create a potential difference across the gate lines shortly before the transfer line Φ1 first reaches 5V. As a result, the gate of the first transfer thyristor is pulled from 5V to 1.7V, the threshold becomes 3.2V, and it becomes a state in which it can be turned on by the control signal Φ1. 5 V is applied to the transfer line Φ1, and after a short delay after the first transfer thyristor Tn−1 transitions to the ON state, 5 V is supplied to the start pulse line Φs, and thereafter 5 V is supplied to the start pulse line Φs. continue.

The transfer line Φ1 and the transfer line Φ2 have a time Tov during which their ON states (here, 5 V) overlap, and are configured to have a substantially complementary relationship. The lighting signal ΦW1 for the light-emitting thyristor is transmitted with a cycle that is half the cycle Tc of the control signals Φ1 and Φ2. The length of each of the periods a to e is the same as half the period of the period Tc, and the boundary of each period is the timing at which one of the control signals Φ1 and Φ2 switches from ON to OFF. The lighting signals ΦW2 to ΦW4 are also controlled at the same timing as the lighting signal ΦW1. The output of the drive current control unit 1001 is turned on at the timing when the P_drive signal is Hi. In other words, the timing at which the drive current control unit 1001 starts driving the light-emitting thyristor is the moment when the P_drive signal changes from Low to Hi in FIG. Ideally, the waveform of the signal is a square wave as shown in FIG. 9, but when actually measured, the rising portion of the waveform may be slightly dull. Therefore, the moment when the voltage exceeds about 80% of the maximum value (5 V in this embodiment) can be considered as the timing when the drive current control unit 1001 starts driving the light emitting thyristor. On the other hand, the timing at which the driving period of the light-emitting thyristor by the drive current control unit 1001 ends is the moment when the P_drive signal changes from Hi to Low in FIG. Ideally, the waveform of the signal is a square wave as shown in FIG. 9, but when the waveform is actually measured, the trailing edge of the waveform may be slightly dull. Therefore, the timing when the driving period of the light-emitting thyristor by the drive current control unit 1001 ends may be the moment when the voltage drops below about 20% of the maximum value (5 V in this embodiment).

Also, the output of the precharge control unit 1002 is turned on at the timing when the P_precharge signal is Hi. In other words, the timing at which the precharge control unit 1002 starts driving the light-emitting thyristor is the moment when the P_precharge signal changes from Low to Hi in FIG. Ideally, the waveform of the signal is a square wave as shown in FIG. 9, but when the waveform is actually measured, the rising portion of the waveform may be slightly dull. Therefore, the timing at which the precharge control unit 1002 starts driving the light-emitting thyristor may be considered to be the moment when the voltage exceeds about 80% of the maximum value (5 V in this embodiment). On the other hand, the timing when the driving period of the light-emitting thyristor by the precharge control unit 1002 ends is the moment when the P_precharge signal changes from Hi to Low in FIG. Ideally, the waveform of the signal is a square wave as shown in FIG. 9, but when the waveform is actually measured, the trailing edge of the waveform may be slightly dull. Therefore, the moment when the voltage drops below about 20% of the maximum value (5 V in this embodiment) can be considered as the timing when the precharge control unit 1002 ends the driving period of the light-emitting thyristor.

In this self-scanning light emitting element array, the ON states of the plurality of transfer thyristors are sequentially shifted according to control signals Φ1 and Φ2, which are input signals. A light emitting thyristor (light emitting element) that emits light is selected according to the ON state of the transfer thyristor. The order of selection of the transfer thyristors is Tn−1→Tn→Tn+1→Tn+2 . . . The light-emitting thyristors emit light in the order of . . . L4n−3 to L4n+4→L4n+1 to L4n+4 .

At timing T1, the light emitting operation in period a has already ended, and the ΦW1 lighting signal line is in the OFF state. A transfer operation is performed by the transfer line Φ1 transitioning to Low after timing T1. That is, the ON state of the transfer thyristor is switched at the timing Ty at which the transfer line Φ1 transitions to Low. In other words, the transfer thyristor corresponding to the previous light-emitting thyristor in the selection order switches from the ON state to the OFF state, and the transfer of the ON state to the next transfer thyristor is completed.

The timing Tx is the time when the light-emitting thyristor (which turns on during the period a) immediately before the light-emitting thyristor turned on during the period b finishes driving (completes light emission). The timing Tx is also the time when the transfer line Φ2 is turned ON. Therefore, the period from the timing Tx to the timing Ty is a "transfer period" during which the switching operation of the transfer thyristor to be turned ON is performed. The time at which the transfer line Φ2 is turned ON may be after the time at which the driving of the previous light-emitting thyristor ends. In such a case, the period from the time when the transfer line Φ2 is turned ON to the timing Ty is the transfer period.

At timing T1 between timings Tx and Ty, the P_precharge signal becomes Hi, the precharge control unit 1002 is turned ON, and a voltage is applied to the light-emitting thyristor so that the preset Vcharge voltage (1.7 V or less) is reached. be. Here, by maintaining the Vcharge voltage at 1.7 V or less, it becomes possible to operate the transfer operation normally. At timing T2 after the end of the transfer, the P_precharge signal goes Low to end the precharge operation, and the P_drive signal goes High to turn on the output of the drive current control unit 1001 . At timing T3, the P_drive signal is turned OFF, and the light emitting operation in period b ends. Since the precharge operation is turned off during the period from T2 to T3, application of excess current due to the precharge operation during the light emission period is avoided.

With such an operation, a voltage is applied in advance within a range in which the light-emitting thyristor is not turned on during the transfer period, thereby shortening the rise time during the light-emitting period (T2 to T3) without causing a transfer operation failure. can be done. Therefore, it is possible to secure a sufficient light emission time width of the exposure head 106a. Here, the CPU 400 controls so that the output level of the precharge control section 1002 converges to the Vcharge voltage over time. That is, the CPU 400 causes the precharge control section 1002 to operate so that the voltage of the output terminal OUT converges to the preset Vcharge voltage after a predetermined application time (predetermined time) has elapsed. Therefore, a stable precharge operation is possible without strictly controlling the time width of the P_precharge signal.

According to the present embodiment, CPU 400 as a control means causes precharge control section 1002 to start driving the light emitting thyristor at the following timing. First, after the driving period of the light-emitting thyristor by the drive current control unit 1001 in the period in which the light-emitting thyristor is in the ON state ends, it is before shifting to the next consecutive ON-state period. Moreover, it is before the driving of the light emitting thyristor by the drive current control unit 1001 is started in the next ON state period. That is, the precharge control unit 1002 starts driving the light-emitting thyristor during the period from timing Tx to T2. As a result, even when the light emission timing of the light emitting thyristor is controlled to be switched at high speed, it is possible to reduce the possibility that the amount of light will be insufficient. In particular, the precharge control unit 1002 starts driving the light-emitting thyristor (light-emitting element) at the timing (timing T1 before the timing Ty) before the ON state of the transfer thyristor is switched. Specifically, the CPU 400 causes the precharge control unit 1002 to start driving the light-emitting thyristor during the period from Tx to Ty. The period from Tx to Ty is a period from the end of driving the preceding light-emitting thyristor by the drive current control unit 1001 until the transfer thyristor corresponding to the preceding light-emitting thyristor is switched from the ON state to the OFF state. be. As a result, the light-emitting thyristor can emit light at high speed without causing a transfer operation failure of the transfer thyristor.

Further, the output level of the precharge control section 1002 converges to the preset Vcharge voltage after a predetermined application time (predetermined time) has elapsed. After the CPU 400 starts driving the light-emitting thyristors (precharge operation), at least until the ON state of the transfer thyristors is switched (Tx to Ty), the terminal voltage of the light-emitting thyristors is Vcharge voltage or less (threshold voltage or less). Control so that Here, the Vcharge voltage is the voltage necessary for the light emitting thyristor to emit light. In other words, if the terminal voltage of the light-emitting thyristor is equal to or lower than the Vcharge voltage, the light-emitting thyristor is in a non-light-emitting state. However, the term "non-light-emitting" as used herein does not mean only the state in which light is not emitted at all in a strict sense. After the photosensitive drum is exposed, the toner image is developed with toner and output as an image on paper. If the image cannot be recognized by the human eye, even if the light-emitting thyristor emits a small amount of light. are also defined as being "non-luminescent". Therefore, there is no need to strictly control the time width of the P_precharge signal, and a stable precharge operation can be performed within a range in which the light-emitting thyristor does not emit light.

Further, after the ON state of the transfer thyristor is switched (timing T2 after timing Ty), driving of the light-emitting thyristor by the drive current control unit 1001 is started. This makes it possible to control the light amount of the light-emitting thyristor with high accuracy. From the viewpoint of controlling the light intensity of the light-emitting thyristors with high accuracy, the timing of stopping the driving of the light-emitting thyristors by the precharge control unit 1002 is not limited to the timing when the drive current control unit 1001 starts driving the light-emitting thyristors. That is, the drive of the light-emitting thyristor by the precharge control unit 1002 may be stopped at the same time as or after the driving of the light-emitting thyristor by the drive current control unit 1001 is started.

It should be noted that the Vcharge voltage was determined as a value common to all the light emitting thyristors based on rising adjustment data stored in the memory 420 in advance. However, rise adjustment data for adjusting the light emission rise time of each light emitting thyristor may be stored in the memory 420 for each light emitting thyristor. Then, CPU 400 may control the output level of precharge control section 1002 for each light emitting thyristor based on this adjustment data. That is, CPU 400 may determine the Vcharge voltage for each light-emitting thyristor based on the adjustment data. As a result, even if there are individual variations in the light-emitting thyristors, it is possible to control the rise times of the light-emitting thyristors to be uniform.

In some cases, the amount of light emitted from the exposure head 106a is changed significantly in order to adjust the density of image formation. Therefore, CPU 400 may control the output level of precharge control section 1002 according to the output level of drive current control section 1001 . As a result, for example, by adjusting the amount of voltage applied during the precharge operation according to the amount of light required by the exposure head 106a so that the rise times are uniform, it is possible to form a uniform image.

(Second embodiment)
FIG. 10 is a diagram showing an internal circuit of the light emitting element driving section 414 according to the second embodiment of the invention. FIG. 11 is a timing chart showing waveforms of driving signals and the like of the circuit shown in FIG. In the following, differences from the first embodiment are mainly described. In this embodiment as well, the rise time of light emission is shortened by applying a voltage to the light-emitting thyristor during the transfer operation of the transfer thyristor.

As shown in FIG. 10, a P_precharge signal that becomes 5 V in the Hi state is applied to the gate of the switch 1004, and a precharge operation is performed by applying a current from VDD (5 V) to the output terminal OUT. Signal line 1011 is obsolete. In the first embodiment, the voltage of the output terminal OUT converges to the preset Vcharge voltage after the predetermined application time has elapsed. On the other hand, in this embodiment, the voltage of the output terminal OUT is determined according to the High time of the P_precharge signal.

As shown in FIG. 11, the terminal voltage (lighting signal ΦW1) of the light-emitting thyristor rises during the period during which the precharge operation is performed (while the P_precharge signal is Hi). The CPU 400 adjusts the high time of P_precharge to control the terminal voltage of the light-emitting thyristor during the transfer period to a voltage (1.7 V or less) at which the light-emitting thyristor does not turn on.

A precharge operation is started at timing T1, and the output current of drive current control section 1001 is applied at timing T2. In the present embodiment, the drive current control section 1001 and the precharge control section 1002 are controlled to temporarily output at the timing after the timing T2. In other words, the CPU 400 causes the P_drive signal and the P_precharge signal to overlap each other so that they are in the Hi state at the same time for a certain period of time. A period from timing T2 to Tz is an overlap period. During this overlap period, the drive current control section 1001 and the precharge control section 1002 drive the light emitting thyristors at the same time, thereby increasing the drive capability and enabling the light emitting thyristors to start emitting light more rapidly.

According to the present embodiment, the precharge control unit 1002 starts driving the light-emitting thyristors at the timing T1 before the ON state of the transfer thyristors is switched. Therefore, even when the light emission timing of the light emitting thyristor is controlled to switch at a high speed, the same effect as in the first embodiment can be obtained in terms of reducing the risk of insufficient light quantity. In addition, the same effect as in the first embodiment can be obtained in terms of enabling the light-emitting thyristor to emit light at high speed without causing transfer operation failure of the transfer thyristor.

Further, the CPU 400 controls the driving time from the start of driving the light-emitting thyristor by the precharge control unit 1002 at least until the ON state of the transfer thyristor is switched. At that time, the CPU 400 controls the driving time so that the terminal voltage of the light-emitting thyristor becomes equal to or lower than the Vcharge voltage (threshold voltage) necessary for the light-emitting thyristor to emit light. As a result, a stable precharge operation can be performed within a range in which the light-emitting thyristor does not emit light.

In addition, compared to the first embodiment, the drive signal generation unit 1009 does not need to have a DAC for setting the applied voltage (Vcharge) during precharging, so the same effect can be obtained with a simpler circuit. becomes possible.

Rising adjustment data for adjusting the light emission rising time of each light emitting thyristor is stored in the memory 420 for each light emitting thyristor, and the CPU 400 controls the driving time for each light emitting thyristor based on this adjustment data. You may As a result, even if there are individual variations in the light-emitting thyristors, it is possible to control the rise times of the light-emitting thyristors to be uniform.

In each of the above-described embodiments, when a voltage is applied to the light-emitting thyristor during the transfer period, the voltage at which the light-emitting thyristor does not turn on is 1.7 V or less. Well, not limited to 1.7V.

In each of the above-described embodiments, by connecting four light-emitting thyristors to one transfer thyristor, the four light-emitting thyristors could be lit simultaneously. However, the number of simultaneous lighting is not limited to four, and simultaneous lighting is not essential.

Although the present invention has been described in detail based on its preferred embodiments, the present invention is not limited to these specific embodiments, and various forms without departing from the gist of the present invention can be applied to the present invention. included. Some of the above embodiments may be combined as appropriate.

400 CPUs
1001 drive current controller 1002 precharge controller Tn transfer thyristor Ln light emitting thyristor Φ1, Φ2 control signal

Claims (12)

a plurality of transfer thyristors whose on-states are sequentially shifted based on an input clock signal; and a plurality of light-emitting thyristors that emit light to expose a photoreceptor and are connected to respective gate terminals of the plurality of transfer thyristors. and a self-scanning light-emitting element array in which a light-emitting light-emitting thyristor is selected based on the state of the transfer thyristor,
first driving means for driving the light-emitting thyristor with a voltage higher than a threshold voltage based on a first driving signal;
a second driving means for driving the light-emitting thyristor with a voltage equal to or lower than the threshold voltage based on a second driving signal;
Control means for controlling timings for driving the light-emitting thyristors by the first drive means based on the first drive signal and the second drive means based on the second drive signal, wherein the light emission After the driving period of the light-emitting thyristor by the first driving means in the period in which the thyristor is in the ON state ends, and before shifting to the next successive ON state period, and in the next ON state. and a control means for causing the second driving means to start driving the light emitting thyristors before the first driving means starts driving the light emitting thyristors in the period. 2. The exposure head according to claim 1, wherein the control means controls to start driving the light-emitting thyristor by the second driving means at a timing before the ON state of the transfer thyristor is switched. . The control means controls the transfer thyristor corresponding to the light-emitting thyristor immediately before the light-emitting thyristor in the selection order to turn off after the driving of the light-emitting thyristor immediately before the light-emitting thyristor in the selection order is completed by the first driving means. 3. The exposure head according to claim 1, wherein the second driving means controls to start driving the light-emitting thyristor until the state is changed. The threshold voltage is a voltage required for light emission of the light-emitting thyristor,
The control means controls the terminal voltage of the light-emitting thyristor to be equal to or lower than the threshold voltage at least until the ON state of the transfer thyristor is switched after the second driving means starts driving the light-emitting thyristor. 4. The exposure head according to any one of claims 1 to 3, wherein said second drive means is controlled so as to 5. An exposure head according to claim 4, wherein said control means controls the output level of said second driving means to converge to said threshold voltage over time. The control means controls the driving time from the start of driving the light emitting thyristor by the second driving means at least until the ON state of the transfer thyristor is switched, so that the terminal voltage of the light emitting thyristor changes to the 5. The exposure head according to claim 4, wherein control is performed so that the voltage is equal to or lower than the threshold voltage. 7. The apparatus according to any one of claims 1 to 6, wherein the control means causes the first driving means to start driving the light-emitting thyristor after the ON state of the transfer thyristor is switched. exposure head. 3. The control means stops the driving of the light-emitting thyristor by the second driving means at the same time as or after the driving of the light-emitting thyristor by the first driving means is started. 8. The exposure head according to any one of 7. a storage unit that stores adjustment data for adjusting the light emission rise time of each of the light emitting thyristors;
5. The controller according to any one of claims 1 to 4, wherein the controller determines the output level of the second driver for each light-emitting thyristor based on the adjustment data stored in the storage unit. The exposure head described in . 2. An exposure head according to claim 1, wherein said control means adjusts the output level of said second driving means according to the output level of said first driving means. a storage unit that stores adjustment data for adjusting the light emission rise time of each of the light emitting thyristors;
7. An exposure head according to claim 6, wherein said control means controls said driving time for each said light emitting thyristor based on said adjustment data stored in said storage section. an exposure head according to any one of claims 1 to 11;
and the photoreceptor.

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