JPH11334144A - Driving control apparatus and image-forming apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To make a signal generation circuit compact and low in cost. SOLUTION: A plurality of recording array heads 600-603 are loaded to an image-forming apparatus. When an image is formed by each head 600-603 and is output overlapping to one output paper, control signals ϕS, ϕ1, ϕ2, ϕI excluding image data are generated from a single signal generation circuit 503, and a part or all of the control signals are gated by delay output enable signals 502Y, 502M, 502C, 502K for each head at gate circuits 521Y, 521M, 521C, 521K.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a drive control device and an image forming apparatus.

[0002]

2. Description of the Related Art Conventionally, as a recording light emitting element, for example, a self-scanning LED array (hereinafter, referred to as SLED) has been used.
There is.

This self-scanning LED array is disclosed in
238962, JP-A-2-2008067, JP-A-2-212170, JP-A-3-20457, JP-A-3-194978, JP-A-4-5872, JP-A-4-58
-23367, JP-A-4-296579, JP-A-5
No.-84971, Japan Hard Copy, 91 (A-1
7) Proposal of light-emitting element array for optical printer with integrated drive circuit, IEICE ('90 .3.5) Self-scanning light-emitting element (SLED) using PNPN thyristor structure
And has attracted attention as a recording light-emitting element.

Here, the configuration of the SLED array head will be described.

FIG. 8 shows a schematic configuration of an SLED array head.

Reference numeral 211 denotes an SLED semiconductor chip.
Reference numeral 212 denotes a base substrate on which the SLED semiconductor chip 211 is mounted, and is configured by a printed wiring board made of a glass epoxy material, a ceramic material, or the like. A connector 213 receives an external control signal and power. 214
Is a lighting control circuit (driver IC) that receives a control signal from the outside and generates a drive signal for the SLED semiconductor chip 211.

A bonding wire 215 connects the output signals (φ1, φ2, φS, φI) from the driver IC 214 and the negative power supply input (GND in this example) to the SLED semiconductor chip 211, respectively.
Reference numeral 216 denotes a positive (+) side power supply pattern (+5 V in this example) drawn on the base substrate 212. 217 denotes a positive power supply pattern 216 drawn on the base substrate 212 and S
It is a silver paste for providing electrical conductivity between the back electrode of the LED semiconductor chip 211 and bonding and fixing.

Next, a color image forming apparatus equipped with a recording array head such as the SLED array head will be described.

As a color image forming apparatus, yellow,
An image is formed on the photosensitive drum for each color of magenta, cyan, and black on the photosensitive drum for each color, and is superimposed on one sheet of paper.
2. Description of the Related Art Recently, image forming apparatuses that perform transfer, fixing, and output have been put to practical use.

FIG. 9 schematically shows the entire configuration of the color image forming apparatus.

First, the configuration of the color reader will be described.

Reference numeral 301 denotes a platen glass (platen). Reference numeral 302 denotes a document feeder (a mirror pressure plate or a white pressure plate may be mounted instead of the document feeder 302). Reference numerals 303 and 304 denote light sources of a halogen lamp or a fluorescent lamp for illuminating the original. 30
Reference numerals 5 and 306 denote reflectors for condensing the light from the light sources 303 and 304 onto the document. 307 to 309 are mirrors. Reference numeral 310 denotes a CCD1 which reflects reflected light or projected light from a document.
It is a lens that condenses light on 01. A carriage 314 accommodates the halogen lamps 303 and 304, the reflectors 305 and 306, and the mirror 307. 315 is a carriage that houses the mirrors 308 and 309.

Reference numeral 101 denotes a CCD. 311 is CC
This is a substrate on which D101 is mounted. Reference numeral 312 denotes a printer processing unit. Reference numeral 313 denotes an interface (I / F) unit with another IPU or the like.

The entire surface of the document is scanned by mechanically moving the carriage 314 at a speed V and the carriage 315 at a speed V / 2 in a direction orthogonal to the electrical scanning (main scanning) direction of the CCD 101. (Sub scanning).

Next, the configuration of the printer unit will be described.

Reference numeral 317 denotes a yellow (Y) image forming unit;
8 is a magenta (M) image forming unit, 319 is cyan (C)
An image forming unit 320 is a black (K) image forming unit. Since the configurations of these image forming units are the same, here,
The Y image forming unit 317 will be described in detail, and description of other image forming units will be omitted.

In the Y image forming section 317, reference numeral 342 denotes a photosensitive drum, which is an LED array head 600 as a recording array head (note that the LED array heads 601 and 6).
02, 603 have the same configuration), a latent image is formed on the surface thereof. Reference numeral 321 denotes a primary charger, which charges the surface of the photosensitive drum 342 to a predetermined potential to prepare for forming a latent image. Reference numeral 322 denotes a developing device, and the photosensitive drum 3
The latent image on 42 is developed to form a toner image. The developing device 322 (325, 328, 331) has a sleeve 355 for applying a developing bias to develop.
358 are included. 323 is a transfer charger,
Electric discharge is performed from the back of the transfer material transport belt 333 to transfer the toner image on the photosensitive drum 342 to the transfer material transport belt 333.
Transfer to the upper recording paper. Note that, in this example, a configuration having good transfer efficiency is assumed (for example, by optimizing the physical characteristics of the toner), and thus no cleaner is provided. However, there is no problem even if the cleaner is mounted.

Next, a procedure for transferring a toner image onto a transfer material such as recording paper will be described.

Transfer materials such as recording paper stored in the cassettes 340 and 341 are supplied onto the transfer material transport belt 333 by sheet feed rollers 336 and 337 one by one by pickup rollers 339 and 338. The supplied recording paper is charged by the adsorption charger 360. Reference numeral 348 denotes a transfer material transport belt roller that drives the transfer material transport belt 333 and charges the recording paper or the like in pairs with the attraction charger 360 to attract the recording paper or the like to the transfer material transport belt 333. . The transfer material transport belt roller 348 may be a drive roller for driving the transfer material transport belt 333, and a drive roller for driving the transfer material transport belt 333 may be disposed on the opposite side. Good.

A paper edge sensor 361 detects the edge of a recording sheet or the like on the transfer material conveying belt 333. In addition,
The detection signal of the paper edge sensor 361 is sent from the printer unit to the color reader unit, and is used as a sub-scanning direction synchronization signal when a video signal is sent from the color reader unit to the printer unit.

Thereafter, the recording paper and the like are transferred to the transfer material transport belt 3.
The toner image is formed on the surface of the recording sheet in the order of Y, M, C, and K in the image forming units 317 to 320. The transfer material such as recording paper that has passed through the K image forming unit 320 is separated from the transfer material transport belt 333 after the charge is removed by the charge removing charger 349 in order to facilitate separation from the transfer material transport belt 333. Reference numeral 350 denotes a peeling charger, which prevents image disturbance due to peeling discharge when a recording sheet or the like is separated from the transfer material transport belt 333. The separated recording paper and the like are charged with pre-fixing chargers 351 and 352 in order to compensate for the toner adsorption force and prevent image disturbance.
After the toner image is thermally fixed by the fixing unit 334, the sheet is discharged to a sheet discharge tray 335.

Next, the LED array heads 600 and 60
1, 602, 603 will be described.

When an SLED array head having an SLED chip is used as the LED array head, each LE
As described above, the light emitting position is set to 1 in the D array head.
The start clock φS for returning to the bit position, the transfer clocks φ1 and φ2 for switching the light emitting position one bit at a time, and the lighting timing which is the lighting timing when the light emitting thyristor actually emits light at the selected light emitting position. Four light emission control signals such as a timing signal φI are required.

The light emission control signals φS, φ1, φ2, φ
The circuit for generating I will be described with reference to FIGS.

FIG. 6 shows a printer processing unit 312 and LEDs
The electrical connection relationship with the array heads 600, 601, 602, and 603 is shown (hereinafter, LED array head 600
Will be described as a representative).

500Y, 500M, 500C, 500K
Is an image enable signal sent from the main controller 400 of the printer processing unit 312 in the image forming apparatus. Starting from the recording paper passage timing detected by the paper leading edge signal detection means 347, a sub-scanning synchronization signal for notifying the timing at which the LED array head 600 should start writing when forming an image at a predetermined position on the recording paper. .

501Y, 501M, 501C, 501K
In order to correct the variation in the position of the light emitting point array of the LED array head 600 in the sub-scanning direction with respect to the image enable signals 500Y, 500M, 500C, and 500K sent from the main controller 400, only the timing specified separately is used. This is a delay circuit that generates a delay.

FIG. 7 shows delay circuits 501Y, 501M, 5
The delay operation of 01C and 501K is shown. Here, the delay amounts 520Y, 520M, 520C, and 520K are set in advance. These delay amounts 520Y, 520M, 520
C, 520K output delayed image enable signals 502Y, 502M, 502C, 502K delayed.

In FIG. 6, 503Y, 503M, 50
3C, 503K are delayed image enable signals 502Y,
The light emission control signals φS, φ1, φ2, φI described above start from the input timings of 502M, 502C, 502K.
(504, 505, 506, 507).

Signal generation circuits 503Y, 503M, 503
C and 503K are delayed image enable signals 502Y and 5
02M, 502C, and 502K, the main controller 400 receives the image data request clock 51
5Y, 515M, 515C, and 515K are output. In synchronization with this clock, the image data 509Y, 509M,
509C and 509K are LED array heads 600 and 60
1, 602 and 603.

In the LED head array in this example, since one head uses 56 SLED chips (the light emitting point in one chip is 128 bits), originally, the image data corresponding to each chip position is stored. 56 signals serialized from 1 bit to 128 bits must be input in parallel.

However, the LED array heads 600, 60
The addition of 56 data input lines to 1,602 and 603 causes an increase in the number of connection cables, and poses problems in terms of cable handling and cost. Therefore, in this example, a system is assumed in which a total of 56 bits of data is transferred by transmitting and receiving data eight times using seven parallel signals within a 1-bit lighting timing.

In the LED array head 600, 51
Reference numeral 0 denotes a data conversion unit that distributes the parallel data to each of the 56 chips.

Reference numeral 511 denotes the image data distributed to each chip by the data converter 510 and the light emission control signal OI.
OR only the chip whose image is on (ON) with S
This is a gate circuit unit for supplying the φI L signal to the LED chip.

In this example, when the image data 509Y is at a high level (H), the φI terminal of the SLED chip sticks to H and does not emit light. When the image data 509Y is at a low level (L), the φI signal from the signal generation circuit 503Y passes through as it is, and during that L period, SLE
The φI terminal of the D chip falls to L and emits light.

Reference numeral 512 denotes a buffer section for distributing the light emission control signals φS, φ1, and φ2 from the signal generation circuit 503Y to 56 chips. As for the φI signal, the φI signal is generated independently for each chip by the gate circuit portion 511, and thus, in this example, the configuration does not include the internal buffer.

Reference numeral 513 is an SLED chip.

The LED array head 601 (magenta), the LED array head 602 (cyan), and the LED array head 603 (black) have the same configuration as the LED array head 600.

[0039]

A plurality of LED array heads 600, 601, 602, 603 as described above.
When the LED array head is used, variations in the light emitting point sequence of each LED array head in the sub-scanning direction are caused by various positional accuracy variations such as a chip mounting position in the LED array head itself and each head positioning member when incorporated in the image forming apparatus. There are many causes, such as variations and variations in the positional accuracy of the image forming apparatus, and variations and variations in the relative position between the LED head array and the image forming main body during the mounting operation and during transportation of the apparatus.

If the writing position of the LED head array varies or fluctuates in the sub-scanning direction due to these factors, the images of the four colors are superimposed with their amounts shifted. In this state, it goes without saying that a good output image cannot be obtained.

Therefore, by various methods, the positional deviation amount in the sub-scanning direction of the light emitting point sequence of the LED head array recognized in advance, ie, the delay amounts 520Y, 520M, 520C,
520K are connected to delay circuits 501Y and 501Y as shown in FIG.
01M, 501C, and 501K are set in advance. As a result, the image enable signal (sub-scanning direction synchronization signal) 500Y, 500M, 500C, 500K from the main body is delayed by a predetermined timing, and the delayed image enable signal 502
By outputting Y, 502M, 502C, and 502K, correction of positional deviation and the like is performed.

As described above, in the conventional configuration, the light emission control signals φS, φ1, φ2, and φI are independently generated for the four LED array heads 600, 601, 602, and 603. The timing of the image enable signals 500Y, 500M, 500C, and 500K of each color can be independently corrected.

However, the light emission control signals φS, φ1,
Signal generation circuits 503Y and 503 for generating φ2 and φI
Since M, 503C, and 503K are provided independently for each color, the configuration of the combination sequential circuit which is a circuit part thereof requires exactly four sets of identical circuits, resulting in an increase in cost.

Accordingly, it is an object of the present invention to provide a small and inexpensive drive control device and an image forming apparatus which can reduce the circuit configuration for generating a light emission control signal.

[0045]

According to the present invention, a plurality of recording heads, one signal generating means for generating a plurality of control signals input to the plurality of recording heads in common, and the plurality of recording heads are provided. Signal output means for outputting an enable signal corresponding to each of the heads, and the enable signal and at least one or more control signals of the plurality of control signals are input, and the control signal causes the control signal to be An output control means for controlling an output timing output to each of the recording heads constitutes a drive control device.

Further, according to the present invention, a plurality of recording heads, one signal generating means for generating a plurality of control signals commonly input to the plurality of recording heads, and a plurality of recording heads are provided. Signal output means for outputting a corresponding enable signal, and the enable signal and at least one control signal of the plurality of control signals are inputted, and the control signal is applied to each of the recording heads by the enable signal. A drive control device having output control means for controlling an output timing outputted to the drive control device; and a recording means for recording an image on a recording medium by each recording head in the drive control device, thereby forming an image. A forming apparatus is configured.

Here, the recording medium is a photoreceptor,
An image can be formed by an electrophotographic method.

The recording head may include a plurality of recording elements whose driving is controlled by the control signal.

In the recording head, a plurality of recording elements driven and controlled by the control signal are formed on a semiconductor chip, and a plurality of the semiconductor chips are arranged on a substrate to constitute a recording element array head. it can.

The pre-recording element can be a light-emitting element or a light-emitting thyristor.

By further including a transfer thyristor corresponding to each of the light-emitting thyristors, a self-scanning array element for controlling light emission / non-light emission can be constituted.

The control signal comprises a two-phase pulse signal, and can sequentially turn on the light emitting thyristor and the transfer thyristor.

[0053]

Embodiments of the present invention will be described below in detail with reference to the drawings.

(Outline) First, an outline of the present invention will be described.

According to the present invention, there is provided a recording array head (LED light emitting element or the like) constituted by arranging a plurality of semiconductor chips on which a plurality of recording elements (LED light emitting element or the like) are arranged on a substrate. In the case where the plurality of recording array heads are mounted on an image forming apparatus, images are formed by the respective heads, and the plurality of formed images are superimposed on one output sheet and output, Recording control signals (emission control signals φS, φ1, φ2, φI
) Is generated from a single signal generation circuit (combination sequential circuit), and a part or all of these recording control signals are gated by a gate circuit by a delay output enable signal for each head, so that the output timing is reduced. The corrected recording control signal is output.

(Specific Example) Hereinafter, a specific example according to the present invention will be described with reference to FIGS. In this example, a recording array head similar to that of FIG.
It is assumed that the apparatus is configured using the same color image forming apparatus as that of FIG. Therefore, the description of the basic configuration and operation of the recording array head and the color image forming apparatus is omitted, and the same portions are denoted by the same reference numerals.

FIG. 1 shows a printer processing unit 312 and LED array heads 600 and 60 as recording array heads.
1 shows an electrical connection configuration with the first, second, and third components.

In the printer processing unit 312, 503
Is a single signal generation circuit (composed of a combination sequential circuit) for generating the light emission control signals φS, φ1, φ2, φI. This signal generation circuit 503 is provided with an image enable signal 500 output from the main controller 400.
The light emission control signals φS, φ1, φ2, φI are always generated regardless of Y, 500M, 500C, 500K.

521Y, 521M, 521C, 521K
Is a window circuit for outputting the light emission control signals φS, φ1, φ2, φI at a predetermined timing.

Hereinafter, the operation of this circuit will be described.

Image enable signals 500Y, 500M, 500C, 500K from main controller 400
Are delay circuits 501Y, 501M, 501C, 501K
The predetermined delay amounts 520Y, 52 set in advance
The signals are delayed by 0M, 520C, and 520K, and output as delayed image enable signals 502Y, 502M, 502C, and 502K.

The delayed image enable signals 502Y,
502M, 502C, 502K and a signal generation circuit 503
Are input to the window circuits 521Y, 521M, 521C, and 521K, respectively.

Window circuits 521Y, 521M, 52
1C and 521K are the delayed image enable signals 502Y,
Starting from the first rise of the light emission control signal φS after the 502M, 502C, and 502K are enabled (H), the delayed image enable signals 502Y, 502M, 502C,
The emission control signals (window signals) φS, φ1, φ2, and φI are passed through until 502K is disabled (L).

The image enable signals 500Y and 50Y
0M, 500C, and 500K are delay circuits 501Y, 501M, 501C, and 501K based on the actual image length in the sub-scanning direction.
Is set to a length greater than the set maximum value of
It is assumed that the settings are separately set so that the final line image data is always output regardless of 20Y, 520M, 520C, and 520K.

Next, a comparative example between the present example and the conventional example will be described with reference to FIGS.

FIG. 2 shows the output timing according to this embodiment.

The signal generation circuit 503 operates irrespective of the delayed image enable signals 502Y, 502M, 502C and 502K.
After the rise of Y, 502M, 502C and 502K (p
The emission control signal φS is passed through from the rise of the first emission control signal φS at the point ()). Further, with respect to the light emission control signals φ1, φ2, φI, an internal synchronization window signal 550 indicating a through state of the light emission control signal φS is used.
Through starts at the same timing.

FIG. 3 shows the output timing according to the conventional example (see FIG. 6).

Here, an image enable signal 500,
Delayed image enable signals 502Y, 502M, 502
C, 502K and a signal waveform of the light emission control signal φS.

The high level (H) of the light emission control signal φS is
The bit light emission timing of the head light emitting element (see light emitting element 1 in FIG. 4) of the chip in each head is shown. In the case of this conventional example, the delayed image enable signals 502Y, 502
Since the signal generation circuits 503Y, 503M, 503C, 503K are activated immediately after receiving the signals M, 502C, 502K, the delayed image enable signals 502Y, 502M,
The emission control signal φS rises and is output at the same time as the rise of 502C and 502K.

Therefore, in the case of this method, the setting resolution for registration in the sub-scanning direction is the writing position correction in units of one cycle of the light emission control signal φS, that is, in units of one line of sub-scanning. However, in a system in which one pixel is composed of two sub-scanning lines, alignment can be performed in units of 1/2 pixel.

In addition to the SLED type LED described in this embodiment, an image forming apparatus which divides a light emitting column into a plurality of areas and sequentially scans light emitting points in a main scanning direction in each area to form an image. In the case of (1), an image step occurs in principle at the joint of the scanning areas due to the movement of the writing position in the sub-scanning direction within the scanning time. Therefore, in order to minimize the influence of the image step, one pixel may be formed in the sub-scanning direction by a plurality of lines. In that case, registration correction can be performed with a value obtained by dividing one pixel by the number of constituent lines.

With the above-described configuration, the light emission control signals φS, φ1, φ2, φI have four LED array heads 6
00, 601, 602, and 603 are shared, whereby the configuration of the signal generation circuit can be reduced to 1/4 of the conventional configuration.

Next, the LED array heads 600 and 60
One example of the operations 1,602 and 603 will be described with reference to FIGS.

Here, the LED array heads 600, 6
The operations of 01, 602 and 603 are the same as those of S
This will be described using an LED array head as an example. However, the operation is not limited to the SLED array head.

FIG. 5 shows the light emission control signals φS, φ1, φ2, φI for controlling the SLED and their timings, and is an example in which all the elements are turned on. The hatched area of the image data φD indicates a state where the light emitting thyristors 1 to 5 are turned on.

As shown in FIG. 4, the SLED includes a light emitting thyristor 1 to 5 arranged in an array and a light emitting thyristor 11 to 15 arranged in an array. The gate of each thyristor is connected, and the first thyristor is connected to the signal input of φS. The gate of the second thyristor is connected to the cathode of the diode 41 connected to the terminal of φS, and the third is connected to the cathode of the next diode 42.

Transfer and light emission will be described with reference to the timing chart of FIG.

The start of the transfer is started by changing φS from 0 V to 5 V. When φS becomes 5 V, Va = 5 V, Vb = 3.7 V (the forward voltage drop of the diode is assumed to be 1.3 V), Vc = 2.4 V, V
d = 1.1V, and thereafter becomes 0V, so that the transfer thyristor 1
The gate signals of 1, 12 are 0V, 5V,
It changes to 3.7V.

By changing φ1 from 5 V to 0 V in this state, the potential of the transfer thyristor 11 becomes 5 V for the anode, 0 V for the cathode, and 3.7 V for the gate, and the thyristor is turned on.
1 turns on.

In this state, even if φS is changed to 0 V, Va is 5 V because the thyristor 11 is on (the reason is that a pulse is applied to φS via a resistor. When the thyristor turns on, The potential between the anode and the gate is almost equal.) Therefore, even if φS is set to 0 V, the ON condition of the first thyristor is maintained, and the first shift operation is completed.

In this state, when the φI signal for the light emitting thyristor is changed from 5 V to 0 V, the condition becomes the same as that when the transfer thyristor 11 is turned on. Therefore, the light emitting thyristor 1 is turned on and the first LED is turned on. become. 1st L
When the ED returns φI to 5 V, the potential difference between the anode and the cathode of the light emitting thyristor 1 disappears, so that the minimum holding current of the thyristor cannot flow, so that the light emitting thyristor 1 is turned off.

Next, the transfer conditions from the transfer thyristor 11 to the transfer thyristor 12 will be described.

Even if the light-emitting thyristor 1 is turned off, φ1 is 0
Since the transfer thyristor 11 remains on at V, the gate voltage Va of the transfer thyristor 11 becomes 5 V, and Vb = 3.7 V.

In this state, by changing φ2 from 5 V to 0 V, the potential of the transfer thyristor 12 becomes 5 V for the anode, 0 V for the cathode, and 3.7 V for the gate, and the transfer thyristor 12 is turned on. After the transfer thyristor 12 is turned on, φ1 is changed from 0 V to 5 V, whereby the transfer thyristor 11 is turned off in the same manner as the light emitting thyristor 1 is turned off. In this way, the on state shifts from the transfer thyristor 11 to the transfer thyristor 12. And by changing φI from 5V to 0V,
The light emitting thyristor 2 is turned on to emit light.

The reason that only the light emitting thyristor whose transfer thyristor is on can emit light is that when the transfer thyristor is not on, the gate voltage is 0 V except for the thyristor adjacent to the thyristor which is on. Therefore, the thyristor is not turned on. As for the adjacent thyristor, since the light emitting thyristor is turned on, the potential of φI becomes 3.4 V (a forward voltage drop of the light emitting thyristor), so that the adjacent thyristor has no potential difference between the gate and the cathode. , Do not turn on.

As described above, by setting φI to 0 V, the light-emitting thyristor is turned on to emit light. However, in an actual printing operation, it is natural whether or not to actually emit light at that timing. Must be controlled in accordance with the image data.

The image data φD in FIG. 5 is a signal indicating this. The logical sum of φI and the image signal is externally taken at the φI terminal of the SLED, and the φLED terminal of the SLED is actually connected only when the image data is 0V. When the image data is 5V, the φI terminal of the SLED remains at 5V and does not emit light.

[0089]

As described above, according to the present invention,
When a plurality of recording array heads are mounted on an image forming apparatus, each head forms an image, and the plurality of formed images are superimposed on one output sheet and output, excluding image data. Signals are generated from a single signal generation circuit, and a part or all of the recording control signals are gated by a gate circuit by a delay output enable signal for each head, so that the control signal generation circuit is downsized. And cost reduction can be achieved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a system configuration including a recording array head according to an embodiment of the present invention.

FIG. 2 is a timing chart showing window processing of the present invention.

FIG. 3 is a timing chart showing the conventional window processing shown in comparison with FIG. 2;

FIG. 4 is a circuit diagram showing an operation example of the SLED array head.

FIG. 5 is a timing chart showing operations of various control signals.

FIG. 6 is a block diagram showing a conventional system configuration.

FIG. 7 is a timing chart showing conventional window processing.

FIG. 8 is a perspective view showing a configuration of an SLED array head.

FIG. 9 is a cross-sectional view illustrating a configuration example of an image forming apparatus equipped with a recording array head.

[Explanation of symbols]

 1-5 Light emitting thyristor (recording element) 11-15 Transfer thyristor 211 Semiconductor chip 503 Signal generation circuit 521Y-521K Window circuit 600-603 Recording array head φS, φ1, φ2, φI Control signal

Claims (15)

[Claims] A plurality of recording heads; a signal generating unit for generating a plurality of control signals commonly input to the plurality of recording heads; and an enable signal corresponding to each of the plurality of recording heads. A signal output unit that outputs the control signal, and the control signal is output to each of the printheads by the enable signal. A drive control device for controlling output timing to be performed. 2. The drive control device according to claim 1, wherein the print head has a plurality of print elements driven and controlled by the control signal. 3. A print element array head comprising a plurality of print elements formed on a semiconductor chip, the plurality of print elements being driven and controlled by the control signal, and a plurality of the semiconductor chips arranged on a substrate. The drive control device according to claim 1, wherein: 4. The drive control device according to claim 2, wherein the recording element is a light emitting element. 5. The drive control device according to claim 2, wherein the recording element is a light-emitting thyristor. 6. The drive control according to claim 5, further comprising a transfer thyristor corresponding to each of said light-emitting thyristors to constitute a self-scanning array element for controlling light emission / non-light emission. apparatus. 7. The drive control device according to claim 6, wherein the control signal comprises a two-phase pulse signal, and the light emitting thyristor and the transfer thyristor are sequentially turned on. 8. A method for generating a plurality of print heads and a plurality of control signals commonly input to the plurality of print heads.
Signal generation means, signal output means for outputting an enable signal corresponding to each of the plurality of recording heads, and at least one control signal of the enable signal and the plurality of control signals are inputted. A drive control device having output control means for controlling an output timing at which the control signal is output to each of the printheads according to the enable signal; and a print medium provided by each printhead in the drive control device. And a recording means for recording an image on the image forming apparatus. 9. The image forming apparatus according to claim 8, wherein the recording medium is a photoconductor, and forms an image by an electrophotographic method. 10. The image forming apparatus according to claim 8, wherein the recording head has a plurality of recording elements driven and controlled by the control signal. 11. A print element array head comprising a plurality of print elements formed on a semiconductor chip, the plurality of print elements driven and controlled by the control signal, and a plurality of the semiconductor chips arranged on a substrate. 9. The method according to claim 8, wherein
Or the image forming apparatus according to 9. 12. The image forming apparatus according to claim 10, wherein the recording element is a light emitting element. 13. The image forming apparatus according to claim 10, wherein the recording element is a light emitting thyristor. 14. A light emitting / emitting device according to claim 1, further comprising a transfer thyristor corresponding to each of said light emitting thyristors.
14. The image forming apparatus according to claim 13, comprising a self-scanning type array element for controlling non-light emission. 15. The image forming apparatus according to claim 14, wherein the control signal comprises a two-phase pulse signal, and the light emitting thyristor and the transfer thyristor are sequentially turned on.