JP2023025382A - image forming device - Google Patents

Abstract

To reduce switching noise caused by multiple exposure.SOLUTION: An image forming device comprises: an exposure device that has a chip in which a first light-emitting element row and a second light-emitting element row which are formed of a plurality of light-emitting elements are arranged in sequence and performs, by the second light-emitting element row, multiple exposure at a portion exposed by the first light-emitting element row; and a controller that transmits a signal for controlling the exposure device. The exposure device sets a first pulse signal for making the first light-emitting element row emit light on the basis of a first delay time from an input timing of a line synchronization signal to a first start timing of starting a light emission and a first pulse width from the first start timing to a first finish timing of finishing the light emission; and sets a second pulse signal for making the second light-emitting element row emit light on the basis of a second delay time which is different from the first delay time from the input timing of the line synchronization signal to a second start timing of starting a light emission and a second pulse width that is different from the first pulse width from the second start timing to a second finish timing of finishing the light emission.SELECTED DRAWING: Figure 17

Description

The present invention relates to an image forming apparatus equipped with an exposure device that exposes a photoreceptor.

2. Description of the Related Art In an electrophotographic image forming apparatus such as a printer, a method of forming a latent image by exposing a photosensitive drum using an exposure device using an LED, an organic EL, or the like is generally known. The exposure device is composed of a light-emitting element row arranged in the rotation axis direction (longitudinal direction) of the photosensitive drum and a rod lens array that forms an image of the light from the light-emitting element row on the photosensitive drum. The LEDs and organic ELs are known to have a surface emitting shape in which the direction of light emitted from the light emitting surface is the same as that of the rod lens array.

Here, the length of the light emitting element array in the longitudinal direction is determined according to the width of the image area on the photosensitive drum, and the interval between the light emitting elements is determined according to the resolution of the printer. For example, in the case of a 1200 dpi printer, the interval between pixels is 21.16 μm (three digits after the decimal point are omitted), so the interval between light emitting elements is also 21.16 μm. A printer using such an exposure device uses fewer parts than a laser scanning printer that deflects and scans a laser beam with a polygon motor, so it is easy to reduce the size and cost of the device. .

As such an exposure device, an exposure head using a TFT circuit and an organic EL on a transparent glass substrate has been proposed (Patent Document 1). In addition, an exposure head formed using an LED/driving IC composite chip in which an integrated circuit thin film and a light emitting layer thin film are attached on a substrate, and an exposure formed using a compound semiconductor chip in which a self-scanning light emitting element is formed. A head has been proposed (Patent Document 2, Patent Document 3).

JP 2015-112856 A Japanese Patent Application Laid-Open No. 2009-296003 JP 2017-183436 A

Organic ELs have a lower emission intensity than lasers and LEDs. Therefore, a plurality of light emitting element arrays formed by arranging a plurality of light emitting elements in the longitudinal direction of the photosensitive drum are also arranged in a direction perpendicular to the longitudinal direction of the photosensitive drum so that the plurality of light emitting element arrays can emit light at the same position on the photosensitive drum. The necessary amount of light is secured by multiple exposure of the .

In such a printer that performs multiple exposure, a large number of light emitting elements arranged in the longitudinal direction of the photosensitive drum and in the direction perpendicular to the longitudinal direction are simultaneously lit in accordance with the line synchronization signal. Then, since the signals for turning on the plurality of light emitting elements change all at once, there is a problem that the number of signals that change at the same time increases, resulting in increased switching noise.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to reduce switching noise associated with multiple exposure.

A representative configuration of the present invention for achieving the above object is a photoreceptor and a first light emitting element formed of a plurality of light emitting elements arranged along a first direction that is the rotation axis direction of the photoreceptor. a chip in which a row and a second light emitting element row formed of a plurality of light emitting elements arranged along the first direction are arranged in order in a second direction perpendicular to the first direction; an exposure device that performs multiple exposure with the second light emitting element array on the exposure position exposed by the first light emitting element array on the photosensitive member; and a signal for controlling the exposure apparatus is transmitted to the exposure apparatus. a controller, wherein the exposure apparatus controls a first delay time from an input timing of a line synchronization signal to a first start timing for starting light emission, and a line synchronization signal following the line synchronization signal from the first start timing; setting a first pulse signal for causing the first light emitting element array to emit light based on a first pulse width up to a first end timing that ends the light emission by the input timing of the line synchronization signal, and from the input timing of the line synchronization signal a second delay time different from the first delay time up to a second start timing for starting light emission, and ending the light emission from the second start timing to the input timing of the line synchronization signal next to the line synchronization signal. setting a second pulse signal for causing the second light emitting element array to emit light based on a second pulse width different from the first pulse width up to a second end timing, and emitting light from each light emitting element array according to the setting; is characterized by starting and ending the

According to the present invention, switching noise associated with multiple exposure can be reduced.

Schematic cross-sectional view showing the overall configuration of an image forming apparatus (a) and (b) are diagrams showing the positional relationship between the exposure head and the photosensitive drum. (a) (b) (c) Explanatory drawing of printed circuit board Explanatory diagram of the configuration of the light-emitting element array chip Explanatory diagram of the configuration of the light emitting unit (a) and (b) diagrams for explaining the arrangement of light-emitting elements Block diagram of image controller and printed circuit board Circuit block diagram in the light-emitting element array chip Circuit diagram of image data storage unit Timing chart representing the operation of the image data storage unit Timing chart representing the operation of the image data storage unit Block diagram of pulse signal generator Explanatory diagram of the lighting control unit Block diagram of lighting controller Block diagram of the analog section Explanatory diagram of the drive circuit (a) (b) Explanatory diagram of pulse signal Illustration of Line Delay Time, Pulse Width, and Light Intensity Coefficient

Preferred embodiments of the present invention will be exemplarily described in detail below with reference to the drawings. However, the dimensions, materials, shapes, relative arrangements, etc. of the components described in the following embodiments should be appropriately changed according to the configuration of the device to which the present invention is applied and various conditions. They are not intended to limit the scope of the invention only to them.

(Overall Configuration of Image Forming Apparatus)
An electrophotographic image forming apparatus according to this embodiment will be briefly described. FIG. 1 shows the configuration of the entire image forming apparatus. The image forming apparatus includes a scanner section 100, an image forming section 103, a fixing section 104, a paper feeding/conveying section 105, and a printer control section (not shown) for controlling these.

The scanner unit 100 illuminates a document placed on a document table, optically reads the document image, converts the image into an electrical signal, and creates image data. In the image forming unit 103 , a photosensitive drum 102 as an image carrier (photosensitive member) is rotationally driven, and the photosensitive drum 102 is charged by a charger 107 . An exposure head 106 as an exposure device emits light according to the image data, and collects the light emitted from the chip surface of the arranged light emitting element group on the photosensitive drum 102 to form an electrostatic latent image. A developing device 108 develops the electrostatic latent image formed on the photosensitive drum 102 with toner. The developed toner image is transferred onto the paper conveyed on the transfer belt 111 . The image forming section has four image forming units for performing the series of electrophotographic processes (charging, exposure, development, and transfer), each of which has cyan (C), magenta (M), yellow (Y), and black (K). A full-color image is formed by arranging them in this order. The quadruple image forming units sequentially perform magenta, yellow, and black image forming operations after a predetermined time has elapsed since the cyan image forming unit started image forming.

The paper feed/conveyance unit 105 feeds paper as a recording medium from one of the paper feed units 109a and 109b, the external paper feed unit 109c, and the manual paper feed unit 109d. The folded paper is conveyed to registration rollers 110 . The registration roller 110 conveys the paper onto the transfer belt 111 at the timing when the toner image formed by the image forming unit 103 is transferred onto the paper. An optical sensor 113 is arranged at a position facing the transfer belt 111, and detects the position of the test chart printed on the transfer belt 111 in order to derive the amount of color misregistration between the image forming units. The amount of color misregistration derived here is notified to the image controller unit 700 (see FIG. 7), and the image position of each color is corrected. With this control, a full-color toner image without color shift is transferred onto the paper. The fixing unit 104 is composed of a combination of rollers and incorporates a heat source such as a halogen heater. The sheet on which the image is fixed is discharged to the outside of the image forming apparatus by the discharge roller 112 .

A printer control unit (not shown) communicates with the MFP control unit that controls the entire MFP, executes control according to instructions from the MFP control unit, and monitors the states of the above-described scanner, image forming, fixing, and paper feed/conveyance units. while managing the entire system to maintain harmony and operate smoothly. Note that MFP is an abbreviation for multi-function printer, and the entire MFP refers to the entire image forming apparatus. Here, as an image forming apparatus, a multi-function printer having functions of printer, copy, image reading, and facsimile is exemplified, but the image forming apparatus is not limited to this.

(Configuration of exposure head)
The exposure head 106 as an exposure device that exposes the photosensitive drum 102 will be described with reference to FIG. 2A and 2B show how the exposure head 106 is arranged with respect to the photosensitive drum 102 and how the light emitted from the light emitting element group 201 is focused on the photosensitive drum 102 by the rod lens array 203. FIG. .

The exposure head 106 and the photosensitive drum 102 are attached to the image forming apparatus by attachment members (not shown). The exposure head 106 is composed of a light emitting element group 201, a printed circuit board 202 on which the light emitting element group 201 is mounted, a rod lens array 203, and a housing 204 in which the rod lens array 203 and printed circuit board 202 are mounted. The exposure head 106 is assembled and adjusted in the factory by itself, and focus adjustment and light amount adjustment are performed to adjust the spot at the condensing position to a predetermined size. Here, the distance between the photosensitive drum 102 and the rod lens array 203 and the distance between the rod lens array 203 and the light emitting element group 201 are arranged to be predetermined intervals, so that the light emitted from the light emitting element group 201 is The incident light is imaged on the photosensitive drum 102 . Therefore, when adjusting the focus, the mounting position of the rod lens array 203 is adjusted so that the distance between the rod lens array 203 and the light emitting element group 201 becomes a desired value. Further, when adjusting the amount of light, the light emitting elements are individually caused to emit light sequentially, and the driving current of each light emitting element is adjusted so that the light condensed through the rod lens array 203 has a predetermined light amount. .

(Substrate configuration)
FIG. 3 shows a printed circuit board 202 on which light emitting element groups 201 are arranged. 3A shows the surface opposite to the surface on which the light emitting element group 201 is mounted (hereinafter referred to as the light emitting element non-mounting surface), and FIG. 3B shows the surface on which the light emitting element group 201 is mounted ( hereinafter referred to as a light emitting element mounting surface). The printed board 202 is a board on which components can be mounted on both the non-mounting surface shown in FIG. 3(a) and the mounting surface shown in FIG. 3(b).

As shown in FIG. 3B, a light emitting element group 201 made up of a plurality of light emitting elements is mounted on the light emitting element mounting surface of the printed circuit board 202 . The light emitting element group 201 consists of 20 light emitting element array chips 400-1 to 400-20 arranged in a zigzag pattern. Each light-emitting element array chip has 748 light-emitting elements in the longitudinal direction, which is the first direction of the chip, and 6 rows in the transverse direction, which is the second direction orthogonal to the first direction, at a predetermined resolution pitch. are arranged in In this embodiment, the pitch of the light emitting elements adjacent to each other in the longitudinal direction and the width direction of the chip is a resolution pitch of 1200 dpi (approximately 21.16 μm). The distance from end to end is approximately 15.8 mm. By arranging 20 chips in the light emitting element group 201, the number of light emitting elements that can be exposed in the longitudinal direction of the photosensitive drum 102 is 14960 elements, and image formation corresponding to an image width of about 316 mm is possible. The light emitting element array chips 400-1 to 400-20 are arranged in two rows in a zigzag pattern, and each row is arranged along the longitudinal direction of the printed circuit board 202. FIG. FIG. 3(c) shows the boundary between chips of the light-emitting element array chip 400. As shown in FIG. Even at the boundary between chips, the pitch of the light emitting elements in the longitudinal direction is the pitch of resolution of 1200 dpi (approximately 21.16 μm). The two rows of chips are arranged such that the interval (S in the figure) between the light emitting points is about 105 μm (corresponding to 5 pixels at 1200 dpi).

The interval (L in the figure) between the light emitting points in the longitudinal direction of the exposure head 106 is approximately 21.16 μm (one pixel at 1200 dpi). In the present invention, it is not necessary to limit the intervals S and L between the light emitting element array chips to the values described above.

As shown in FIG. 3A, a connector 305 for connecting a control signal for controlling the light emitting element array chip from the image controller section 700 (see FIG. 7) and a power supply line is provided on the surface of the printed circuit board 202 on which the light emitting elements are not mounted. are placed. Each light emitting element array chip 400 is driven through the connector 305 .

(Structure of light-emitting element array chip)
FIG. 4 shows an outline of the planar configuration of the light emitting element array chip 400. As shown in FIG. Note that the arrow X direction in the drawing is the rotation axis direction (longitudinal direction) of the photosensitive drum 102 and is the first direction of the chip. The arrow Y direction is the rotation direction of the photosensitive drum 102 and is the second direction orthogonal to the first direction of the chip. A light-emitting element array chip 400 has a light-emitting portion 404 including a plurality of light-emitting elements and wire bonding pads (WB pads) 408 formed on a light-emitting substrate 402 . A circuit section 406 for controlling the light emitting section 404 is incorporated in the light emitting substrate 402 . The circuit section 406 has a configuration including both an analog drive circuit and a digital control circuit. Power supply to the circuit section 406 and input/output of signals from outside the light emitting element array chip 400 are performed through the wire bonding pads 408 .

(Structure of light-emitting part)
The light emitting portion 404 will be described with reference to FIG. Note that the arrow Z direction in the drawing is perpendicular to the arrow X direction and the arrow Y direction and is the direction in which the light from the light emitting unit 404 is emitted. FIG. 5 is a schematic view of one light emitting element and its surroundings, which is part of the AA cross section in FIG. A plurality of lower electrodes 504 , light emitting layers 506 and upper electrodes 508 are formed on a light emitting substrate 402 . The bottom electrode 504 is an independent electrode and the top electrode 508 is a common electrode. As shown in FIG. 5, a plurality of lower electrodes 504 are formed with a width W in the direction of arrow X in the figure and with a predetermined interval d between adjacent lower electrodes 504 in the direction of arrow X. As shown in FIG. A light emitting layer 506 is formed between the lower electrode 504 and the upper electrode 508 . Note that the light-emitting layer 506 may be formed continuously, or may be divided into approximately the same size as the lower electrode 504 . The light emitting element 602 forms one element by a portion surrounded by one of the independent lower electrodes 504, the light emitting layer 506, and the upper electrode 508. FIG. A desired electrode is selected from a plurality of lower electrodes 504, and the light-emitting layer 506 at a location corresponding to the selected lower electrode 504 emits light by energizing the light-emitting layer 506 through the selected lower electrode 504 and upper electrode 508. and is emitted as emitted light 510 through the upper electrode 508 . As the lower electrode 504, a metal having a high reflectance with respect to the emission wavelength of the light emitting layer 506 is preferable, and Ag is used in this embodiment. Alternatively, Al or an alloy thereof can be used. Also, the upper electrode 508 is preferably transparent to the emission wavelength of the light emitting layer 506, and indium tin oxide (ITO) is used in this embodiment. Although an organic EL film is used as the light-emitting layer 506 in this embodiment, an inorganic EL layer or the like may be used instead of the organic EL layer.

(Arrangement of light-emitting parts)
The arrangement of the light emitting units 404 will be described with reference to FIGS. 6(a) and 6(b). FIG. 6A is a diagram showing the arrangement of the light emitting elements in the light emitting section 404. FIG. As shown in FIG. 6A, the light emitting section 404 is configured by arranging a plurality of light emitting elements 602 in a row. A plurality of light emitting elements 602 are arranged in rows in the arrow X direction in the figure at predetermined intervals (for example, 21.16 μm pitch at 1200 dpi) in the arrow X direction, and are also arranged in the arrow Y direction in a plurality of light emitting devices. An element row (604-1 to 604-m in FIG. 6(a)) is formed.

In other words, the light-emitting portion 404 has a light-emitting element array 604 formed from a plurality of light-emitting elements 602 arranged along the arrow X direction, which is the first direction, in the second direction perpendicular to the first direction. They are arranged in order in the arrow Y direction. Specifically, in the light emitting section 404 , n light emitting elements 602 are arranged in a row in the direction of the arrow X at predetermined intervals to form a row of light emitting elements 604 . In addition, the light emitting unit 404 includes m light emitting element rows 604 (first light emitting element row 604-1, second light emitting element row 604-2, . . . mth light emitting element row 604-m) formed in this way. They are arranged in order in the arrow Y direction.

In the figure, W1 is the width of the light emitting element 602 in the direction of the arrow X, and d1 is the distance between adjacent light emitting elements 602 in the direction of the arrow X. FIG. When the light emitting layer 506 is sufficiently thin, the size of the light emitting element 602 is substantially the same as that of the lower electrode 504, and W1 can be regarded as W in FIG. 5 and d1 as d in FIG. The width W2 of the light-emitting element 602 in the arrow Y direction, the interval d2, and the number m of the light-emitting element arrays 604 may be determined in consideration of the scanning speed in the arrow Y direction, the required amount of light, and the resolution. In this embodiment, the width W1 is 20.9 μm, the interval d1 is 0.26 μm, and they are arranged at a pitch of 21.16 μm. Also, the width W2 is 20.9 μm, which is the same as the width W1, and the width d2 is 0.26 μm, which is the same as the width d1, and they are arranged at a pitch of 21.16 μm. Also, the number of columns m is assumed to be six.

FIG. 6B is a schematic cross-sectional view of the light emitting element array 604-1. As shown in FIG. 6B, the lower electrodes 504 are arranged in the direction of the arrow X with a width of W1 and a spacing of d1. Each light-emitting element 602 is composed of a portion where each lower electrode 504 faces an upper electrode 508 and a light-emitting layer 506 therebetween. As an example of the configuration of individual light emitting elements, a light emitting element 602-13 is indicated by a portion surrounded by a dotted line in FIG. 6(b).

When the light emitting elements arranged in the arrow Y direction in FIG. 6A are turned on at the same time, they expose different positions in the rotation direction of the photosensitive drum 102 at intervals of W2+d2 on the photosensitive drum 102 . By shifting the lighting timing of each light-emitting element according to the rotation speed of the photosensitive drum 102, it is possible to expose the photosensitive drum 102 at substantially the same position. The state of exposing the light emitting elements arranged in the direction of the arrow Y at substantially the same position is called multiple exposure. For example, the exposure position (substantially the same position) exposed by the first light emitting element array 604-1 shown in FIG. 6A is multiple-exposed by the second light emitting element array 604-2.

(control block)
FIG. 7 shows a block diagram of the image controller section 700 and the printed circuit board 202. As shown in FIG. In this embodiment, the processing for a single color will be described for the sake of simplification, but the same processing will be performed simultaneously for four colors in parallel.

(Image controller part)
The image controller unit 700 is provided on the device side (here, the image forming device) different from the printed circuit board 202 . The image controller unit 700 transmits signals for controlling the printed circuit board 202 to the printed circuit board 202 . The signals include a chip select signal representing the effective range of image data, a clock signal, image data, a signal representing line-by-line separation of image data (hereinafter referred to as a line synchronization signal), and a communication signal with the CPU 703 . Each of the above signals is transmitted to the light emitting element array chip 400 in the printed circuit board 202 via a chip select signal line cs_x 705, a clock signal line clk 706, an image data signal line data 707, a line synchronization signal line lsync_x 708, and a communication signal line 709. . The image controller unit 700 performs processing for image data and processing for print timing. The image controller section 700 has an image data generation section 701 , a chip data conversion section 702 , a CPU 703 and a synchronization signal generation section 704 .

The image data generating unit 701 dithers image data received from the scanner unit 100 or from the outside of the image forming apparatus at a resolution designated by the CPU 703 to generate image data for print output. In this embodiment, it is assumed that the dithering process is performed at a resolution of 1200 dpi. The image data has a width of 3 bits and represents eight gradations of density values 0 to 7, with 7 representing the maximum density.

A synchronization signal generator 704 generates a line synchronization signal. The CPU 703 sets the period in which the surface of the photosensitive drum 102 moves in the rotation direction by 1200 dpi pixel size (approximately 21.16 μm) as one line period with respect to the rotational speed of the photosensitive drum 102 determined in advance. indicates the time interval of the signal period. For example, in the case of printing at a speed of 200 mm/s in the paper transport direction, the time interval is specified with the one-line cycle set to 105.8 μs (two decimal places are omitted). The speed in the paper transport direction is calculated by the CPU 703 using a set value (fixed value) of the printing speed set in a speed control unit (not shown) of the photosensitive drum.

The chip data conversion unit 702 divides one line of image data for each light-emitting element array chip in synchronization with the line synchronization signal generated by the synchronization signal generation unit 704, and sends it to the printed circuit board 202 together with the clock signal and the chip select signal. .

(Printed board)
Next, the configuration of the printed circuit board 202 will be described. The printed circuit board 202 has a plurality of light emitting element array chips 400 and a head information storage section 710 .

A head information storage unit 710 is a storage device that stores head information such as the amount of light emitted from each light emitting element array chip 400 and mounting position information, and is connected to the CPU 703 via a communication signal line 709 . A clock signal line 706 , an image data signal line 707 , a line synchronization signal line 708 and a communication signal line 709 are all connected to the light emitting element array chip 400 . The chip select signal line 705 is connected to the input of the light emitting element array chip 400-1. Further, the chip select signal line 705 connects the output of the light emitting element array chip 400-1 to the input of the light emitting element array chip 400-2 via the signal line 711-1. Further, the chip select signal line 705 connects the output of the light emitting element array chip 400-2 to the input of the light emitting element array chip 400-3 via the signal line 711-2. Thus, the chip select signal line 705 is cascade-connected. Each light-emitting element array chip 400 causes the light-emitting elements to emit light based on set values set by input chip select signals, clock signals, line synchronization signals, image data signals, and communication signals. It also generates a chip select signal for the next chip.

(digital circuit block inside the chip)
FIG. 8 shows a circuit block diagram in the light emitting element array chip 400. As shown in FIG. A circuit section 406 in the light emitting element array chip 400 consists of a digital section 800 and an analog section 807 . The digital section 800 has the function of generating a pulse signal for causing the light emitting element to emit light in synchronization with the clock signal 706, sending the pulse signal to the analog section 807, and generating a chip select signal for the next chip from the input chip select signal. have the function to Here, in synchronization with the clock signal 706, the digital unit 800 controls the light emitting element to emit light based on the set value preset by the communication signal 709, the chip select signal 705, the image data signal 707, and the line synchronization signal 708. Generate a pulse signal.

A communication IF unit 801 controls writing and reading of setting values to and from a register unit 802 based on a communication signal 709 from the CPU 703 .

A register unit 802 stores setting values necessary for operation. The setting values include pulse width information (pulse width setting value b) and line delay information (line delay setting value a) of the pulse signal generated by the pulse signal generation unit 805, and driving current setting information set by the analog unit 807. (light intensity coefficient).

The chip select signal generator 803 delays the input chip select signal and generates a chip select signal for the next chip.

The image data storage unit 804 holds the image data while the inputted chip select signal is valid, and outputs the image data to the lighting control unit 806 in synchronization with the line synchronization signal. Details will be described later.

A pulse signal generation unit 805 generates a pulse signal necessary for lighting the light emitting element in the corresponding light emitting element array based on the pulse width information and line delay information of the pulse signal set in the register unit 802, and turns on the pulse signal. Output to the control unit 806 . Details will be described later.

Based on the image data from the image data storage unit 804, the lighting control unit 806 controls whether to output the pulse signal from the pulse signal generation unit 805 to the analog unit 807 for each light emitting element. Details will be described later.

Based on the pulse signal generated by the digital section 800, the analog section 807 generates a signal necessary for driving the light emitting element. Details will be described later.

Next, the operation of the image data storage unit 804 will be described. FIG. 9 is a circuit diagram of the image data storage unit 804. As shown in FIG.

In this embodiment, the chip select signal cs_x and the line synchronization signal lsync_x are negative logic signals, but they may be positive logic signals. Also, the clock signal is clk, and the image data signal is data. The clock gate circuit 910 outputs the AND of the inverted signal of the chip select signal cs_x and the clock signal clk, and outputs the clock signal s_clk to the flip-flop circuit 911 only when cs_x is valid. The flip-flop circuit 911 is based on the image data signal data input to the image data storage unit 804, and has the same number of light emitting elements as the number of light emitting elements provided in the longitudinal direction of the light emitting element array chip (748 in this embodiment). are connected in series. The flip-flop circuit 911 operates with the clock signal s_clk sent from the clock gate circuit 910 .

The flip-flop circuit will be described below. Flip-flop circuits 912-000, 913-000, 914-000, 915-000, 916-000 and 917-000 will be described as representatives. Other flip-flop circuits 912-001 to 912-747, 913-001 to 913-747, 914-001 to 914-747, 915-001 to 915-747, 916-001 to 916-747, 917-001 to 917 The same is true for -747.

The flip-flop circuit 912-000 receives the output (dly_data_000) of the flip-flop circuit 911-000 and operates with the line synchronization signal lsync_x. The output (buf_data_0_000) of the flip-flop circuit 912-000 is input to the lighting control section 806 and the flip-flop circuit 913-000. The flip-flop circuit 913-000 receives the output (buf_data_0_000) of the flip-flop circuit 912-000 and operates with the line synchronization signal lsync_x. The output (buf_data_1_000) of the flip-flop circuit 913-000 is input to the flip-flop circuit 914-000 and the lighting control section 806. FIG. The flip-flop circuit 914-000 receives the output (buf_data_1_000) of the flip-flop circuit 913-000 and operates with the line synchronization signal lsync_x. The output (buf_data_2_000) of the flip-flop circuit 914-000 is input to the flip-flop circuit 915-000 and the lighting control section 806. FIG. The flip-flop circuit 915-000 receives the output (buf_data_2_000) of the flip-flop circuit 914-000 and operates with the line synchronization signal lsync_x. The output (buf_data — 3 — 000) of flip-flop circuit 915 is input to flip-flop circuit 916-000 and lighting control section 806. FIG. The flip-flop circuit 916-000 receives the output (buf_data_3_000) of the flip-flop circuit 915-000 and operates with the line synchronization signal lsync_x. The output (buf_data_4_000) of the flip-flop circuit 916-000 is input to the flip-flop circuit 917-000 and the lighting control section 806. FIG. The flip-flop circuit 917-000 receives the output (buf_data_4_000) of the flip-flop circuit 916-000 and operates with the line synchronization signal lsync_x. The output (buf_data_5_000) of the flip-flop circuit 917-000 is input to the lighting control section 806. FIG.

FIG. 10 is a timing chart showing the motion of the photosensitive drum in the image data storage unit 804 in the longitudinal direction. Signal names in the figure are shown in FIG. During the period from time T0 when cs_x=0 is caught at the rise of clk to time T1, the image data shifts in order of data→dly_data_000→dly_data_001→ . . . For cs_x=0, it is assumed that 748 clock signals are input, which is the same number as the number of light emitting elements in the longitudinal direction of the photosensitive drum. By doing so, image data for one line is held in dly_data_000 to dly_data_747. Since cs_x=1 after time T1, the shift operation is not performed and is held. When lsync_x=0 is caught at the rising edge of clk at time T2, one line of image data is simultaneously shifted such as dly_data_000→buf_data_0_000, dly_data_001→buf_data_0_001, . . . .

FIG. 11 is a timing chart showing the operation of the photosensitive drum in the image data storage unit 804 in the rotation direction. In FIG. 11, the output buf_data_0_000 of the flip-flop circuit 912-000, the output buf_data_1_000 of the flip-flop circuit 913-000, the output buf_data_2_000 of the flip-flop circuit 914-000, and the output buf_data_3_000 of the flip-flop circuit 915-000 shown in FIG. , the output buf_data_4_000 of the flip-flop circuit 916-000, and the output buf_data_5_000 of the flip-flop circuit 917-000 will be described.図９に示す他のフリップフロップ回路の出力ｂｕｆ＿ｄａｔａ＿０＿００１～ｂｕｆ＿ｄａｔａ＿０＿７４７、ｂｕｆ＿ｄａｔａ＿１＿００１～ｂｕｆ＿ｄａｔａ＿１＿７４７、ｂｕｆ＿ｄａｔａ＿２＿００１～ｂｕｆ＿ｄａｔａ＿２＿７４７、ｂｕｆ＿ｄａｔａ＿３＿００１～ｂｕｆ＿ｄａｔａ＿３＿７４７、ｂｕｆ＿ｄａｔａ＿４＿００１～ｂｕｆ＿ｄａｔａ＿４＿７４７、ｂｕｆ＿ｄａｔａ＿５＿００１～ｂｕｆ＿ｄａｔａ＿５＿７４７の全てにおいて同様である。

As shown, each time lsync_x rises from 0 to 1, it shifts dly_data_000→buf_data_0_000, buf_data_0_000→buf_data_1_000, and so on. Therefore, the value B000 of dly_data_000 at time T0 is output to the lighting control unit 806 as buf_data_0_000 at time T1, buf_data_1_000 at time T2, buf_data_2_000 at time T3, and so on. Multiple exposure is realized by connecting buf_data_0_000, buf_data_1_000, buf_data_2_000, buf_data_3_000, buf_data_4_000, and buf_data_5_000 in order from the light emitting element that is exposed first on the photosensitive drum.

Next, the pulse signal generator 805 will be described. FIG. 12 shows a block diagram of the pulse signal generator 805. As shown in FIG.

The pulse signal generation section 805 is composed of a counter section 1000 and an output determination section 1002 for each light emitting element array. The counter unit 1000 counts the clock signal 706 and resets the count each time the line synchronization signal 708 is input. A count signal (cnt) 1001, which is the output of the counter section, is input to all the output determination sections 1002_0 to 1002_5.

Pulse width setting signal lines 1003_0 to 1003_5 are inputs from the register unit 802, and transmit pulse width setting values b0 to b5 set in clock cycle units for each of the six light emitting element columns. The pulse width setting signal line 1003_0 is connected to the output determining section 1002-00. The pulse width setting signal line 1003_1 is connected to the output determining section 1002-01. The pulse width setting signal line 1003_2 is connected to the output determining section 1002-02. The pulse width setting signal line 1003_3 is connected to the output determining section 1002-03. The pulse width setting signal line 1003_4 is connected to the output determining section 1002-04. The pulse width setting signal line 1003_5 is connected to the output determining section 1002-05.

The line delay setting signal lines 1004_0 to 1004_5 are inputs from the register unit 802, and transmit the delay setting values a0 to a5 from the line synchronization signal counted in clock cycle units for each of the six light emitting element columns. The line delay setting signal line 1004_0 is connected to the output determination section 1002-00. The line delay setting signal line 1004_1 is connected to the output determination section 1002-01. The line delay setting signal line 1004_2 is connected to the output determination section 1002-02. The line delay setting signal line 1004_3 is connected to the output determining section 1002-03. The line delay setting signal line 1004_4 is connected to the output determination section 1002-04. The line delay setting signal line 1004_5 is connected to the output determination section 1002-05.

The output determination unit 1002 generates a pulse signal according to the count signal 1001 , the pulse width setting value b transmitted by the pulse width setting signal line 1003 and the line delay setting value a transmitted by the line delay setting signal line 1004 .

In other words, the pulse signal generator 805 determines the delay time (delay set value a) from the input timing of the line synchronization signal to the start timing of light emission, and the pulse width from the start timing to the end timing of light emission. A pulse signal (pwm) for causing the light emitting element array to emit light is generated based on (pulse width set value b).

As will be described later, the pulse signal generator 805 generates a first delay time (delay set value a) from the input timing of the line synchronization signal to the first start timing for starting light emission, and the line synchronization signal from the first start timing. A first pulse for causing the first light emitting element array to emit light based on the first pulse width (pulse width setting value b) until the first end timing for ending the light emission by the input timing of the line synchronization signal next to Generate a signal. Further, the pulse signal generation unit 805 generates a second delay time (delay set value a) different from the first delay time from the input timing of the line synchronization signal to the second start timing for starting light emission, and the second start timing and a second pulse width (pulse width set value b) different from the first pulse width from the input timing of the line synchronizing signal next to the line synchronizing signal to the second end timing for terminating the light emission. A second pulse signal is generated for causing the second light emitting element array to emit light.

Next, the operation of output determining section 1002 will be described. Below, the output determination unit 1002-0 will be described as a representative. As for the output determining section 1002-0, the connected pulse width setting signal line is 1003-0, the line delay setting signal line is 1004-0, and the output is pwm0. Other output determination units 1002-1, 1002-2, 1002-3, 1002-4 and 1002-5 are connected to pulse width setting signal lines 1003-1, 1003-2, 1003-3 and 1003- 4, 1003-5. The line delay setting signal lines are 1004-1, 1004-2, 1004-3, 1004-4 and 1004-5, and the outputs are pwm1, pwm2, pwm3, pwm4 and pwm5. Also, the operation is the same as that of the output determination unit 1002-0.

FIG. 17(a) is a timing chart showing the operation of the output determining section 1002-0.

The count signal cnt is reset at the input timing (time t0) of the line synchronization signal lsync_x, and the count signal cnt starts incrementing at the cycle of the clock signal clk. When the count signal cnt is less than a0, it outputs Low, and when it is equal to or greater than a0 (time t1), it outputs High. High output is maintained during b0, and becomes Low after a0+b0 (time t2). The count signal cnt is reset at the input timing (time t3) of the next line synchronization signal lsync_x, and the same operation is repeated thereafter. By doing so, a pulse width modulated signal pwm_0 is generated.

In FIG. 17A, the delay time is from the input timing (time t0) of the line synchronization signal lsync_x to the timing (time t1) at which the count signal cnt becomes a0. Also, from the timing (time t1) when the count signal cnt becomes a0 to the timing (time t2) when the count signal cnt becomes a0+b0 (time t2) by the input timing (time t3) of the next line synchronization signal lsync_x, the pulse width. In other words, from the timing (time t1) when the count signal cnt becomes a0 to the input timing (time t3) of the next line synchronization signal lsync_x, the count signal cnt is the pulse width during b0. A pulse signal generator 805 generates a pulse signal corresponding to the delay time and the pulse width for each light emitting element array.

FIG. 17B is a timing chart showing an example of six pulse signals generated by the pulse signal generator 805. FIG.

The pulse signal generator 805 generates a pulse signal corresponding to the delay time and the pulse width for each light emitting element array, as described above. In other words, the pulse signal generator 805 sets the delay time and the pulse width for each light emitting element array. Here, the light-emitting element array refers to each light-emitting element array of a plurality of light-emitting element arrays arranged in order in the drum rotation direction within one light-emitting element array chip. In FIG. 17B, one light-emitting element array chip has m=6 light-emitting element rows (first, second, third, fourth, fifth, and sixth light-emitting element rows) in the drum rotation direction. are arranged in order.

As shown in FIG. 17B, the pulse signal generator 805 generates six pulse signals (pwm0, pwm1, pwm2, pwm3, pwm4, pwm5) for each of the six light emitting element columns. Note that t1 indicates the start timing of the transition from Low to High of each pulse signal pwm, and t2 indicates the end timing of the transition from High to Low. t0 indicates the input timing of the line synchronizing signal, and t3 indicates the input timing of the next line synchronizing signal.

The pulse signal generator 805 generates a first delay time (delay setting value a0) from the input timing t0 of the line synchronization signal to the first start timing t10 at which light emission is started, and the next line synchronization signal from the first start timing. A first pulse signal pwm0 for causing the first light emitting element array to emit light is generated based on the first pulse width (pulse width setting value b0) up to the first end timing t20 that ends the light emission by the input timing t3. .

The pulse signal generator 805 generates a second delay time (delay set value a1) different from the first delay time (delay set value a0) from the input timing t0 of the line synchronization signal to the second start timing t11 at which light emission is started. and a second pulse width different from the first pulse width (pulse width set value b) from the second start timing to the second end timing t21 at which the light emission is finished by the input timing t3 of the next line synchronization signal. A second pulse signal pwm1 for causing the second light emitting element array to emit light is generated based on (pulse width set value b1).

Here, the setting values for setting the pulse signal for each light emitting element array are the delay setting value a0 for the first delay time of the first light emitting element array, the pulse width setting value b0 for the first pulse width, and the pulse width setting value b0 for the first light emitting element array. When the second delay time is a delay set value a1 and the second pulse width is a pulse width set value b1, a0<a1, b0>b1 and a0+b0≠a1+b1 are satisfied.

The third pulse signal pwm2 for the third light emitting element array, the fourth pulse signal pwm3 for the fourth light emitting element array, and the sixth pulse signal pwm5 for the sixth light emitting element array are also the first pulse signal pwm0 for the first light emitting element array and the third pulse signal pwm5 for the sixth light emitting element array. It is generated in the same manner as the relationship with the second pulse signal pwm1 of the two light emitting element arrays.

That is, the line delay set value a, which is the delay time of each light emitting element array, satisfies a0<a1<a2<a3<a4<a5. Also, the pulse width set value b, which is the pulse width, satisfies b5<b4<b3<b2<b1<b0. By setting in this way, the start timing t1 of transition from Low to High of each pulse signal pwm does not overlap, and the end timing t2 of transition from High to Low does not overlap even during multiple exposure. Therefore, there is no timing at which pulse signals of a plurality of light emitting element arrays arranged in the drum rotation direction in one light emitting element array chip change all at once, and switching noise can be reduced.

In order to shift pulse signals that change simultaneously, line delay set values a0 to a5 and pulse width set values b0 to b5 satisfy a0≠a1≠a2≠a3≠a4≠a5. At the same time, a0+b0≠a1+b1≠a2+b2≠a3+b3≠a4+b4≠a5+b5.

In addition, it is necessary to set a light quantity coefficient, which will be described later, at the same time. As described above, in pulse signals whose timings do not overlap, in order to keep the integrated light amount of each light emitting element array uniform, it is necessary to set the driving current for each light emitting element array to a corresponding driving current. The drive current for each light emitting element array is set by the analog section 807 based on the setting information (light quantity coefficient) stored in the register section. This will be discussed later.

In FIG. 17B, pwm5 is a pulse signal based on image data five lines before. pwm4 is a pulse signal based on image data four lines before. pwm3 is a pulse signal based on image data three lines before. pwm2 is a pulse signal based on image data two lines before. pwm1 is a pulse signal based on the image data one line before.

Next, the lighting control unit 806 will be described.

The lighting control unit 806 outputs the pulse signal for each light emitting element row generated by the pulse signal generating unit 805 to the analog unit 807 for each light emitting element in accordance with the image data input from the image data storage unit 804. control whether or not At this time, in order to perform the above-described gradation expression, it is determined how many light emitting elements are assigned to each bit of the image data. FIG. 13 shows an allocation table in this embodiment. The decimal column shows the image data value in decimal notation, and the binary column shows the binary notation for each bit. N in the row of the light emitting elements 602-1N to 602-6N represents a plurality of light emitting elements 1 to 748 arranged in the longitudinal direction of the photosensitive drum, ON means lighting and OFF means turning off. As shown in the figure, bit 0 of the image data has light emitting element 602-1N, bit 1 has two light emitting elements 602-2N and 602-3N, and bit 2 has three light emitting elements 602-4N, 602-5N and 602-6N. are assigned and controlled respectively.

FIG. 14 is a block diagram of the lighting control section 806 that implements the allocation of FIG. [N] in the figure represents bitN of the signal.

The output pulse signals la_pwm_0_000 to la_pwm_0_747 correspond to the light emitting elements 602-11 to 602-1748. The output pulse signals la_pwm_1_000 to la_pwm_1_747 correspond to the light emitting elements 602-21 to 602-2748. The output pulse signals la_pwm_2_000 to la_pwm_2_747 correspond to the light emitting elements 602-31 to 602-3748. The output pulse signals la_pwm_3_000 to la_pwm_3_747 correspond to the light emitting elements 602-41 to 602-4748. The output pulse signals la_pwm_4_000 to la_pwm_4_747 correspond to the light emitting elements 602-51 to 602-5748. The output pulse signals la_pwm_5_000 to la_pwm_5_747 correspond to the light emitting elements 602-61 to 602-6748.

The lighting control unit 806 is provided with AND gates 1100 corresponding to the number of light emitting elements. In this embodiment, both the image signals buf_data_0_000 to buf_data_5_747 from the image data storage unit 804 and the pulse signals pwm0 to pwm5 from the pulse signal generation unit 805 are positive logic, and the output pulse signals la_pwm_0_000 to la_pwm_5_747 to the analog unit 807 are positive logic. is 1, the AND gate is used, but if either input or output is negative logic, a logic gate corresponding to it may be used.

The AND gates 1100-0-N commonly receive the pulse signal pwm0 generated by the pulse signal generation unit 805 on one side and bit 0 of buf_data_0_N on the other side, and output the logical product of both as la_pwm_0_N.

AND gates 1100-1-N commonly receive the pulse signal pwm1 generated by the pulse signal generator 805 on one side and bit 1 of buf_data_1_N on the other side, and output the logical product of both as la_pwm_1_N.

An AND gate 1100-2-N receives the pulse signal pwm2 generated by the pulse signal generator 805 in common on one side and bit 1 of buf_data_2_N on the other side, and outputs the logical product of both as la_pwm_2_N.

The AND gate 1100-3-N receives the pulse signal pwm3 generated by the pulse signal generator 805 in common on one side and bit 2 of buf_data_3_N on the other side, and outputs the logical product of both as la_pwm_3_N.

The AND gate 1100-4-N receives the pulse signal pwm4 generated by the pulse signal generator 805 in common on one side and bit 2 of buf_data_4_N on the other side, and outputs the logical product of both as la_pwm_4_N.

The AND gate 1100-5-N receives the pulse signal pwm5 generated by the pulse signal generator 805 in common on one side and bit 2 of buf_data_5_N on the other side, and outputs the logical product of both as la_pwm_5_N.

As described above, whether or not to output the pulse signal generated for each light emitting element array to the analog unit 807 is controlled by the bit value of the image data signal.

Next, the analog section 807 will be described. FIG. 15 shows a block diagram of the analog section 807. As shown in FIG. The analog section 807 is composed of a DAC (digital-analog converter) 1200 for each light emitting element array, an element group driving section 1201 and a driving section selecting section 1203 for each light emitting element array. An analog section (driving section) 807 drives the light-emitting element array with a predetermined integrated light amount using a pulse signal and a drive current.

The lighting control unit 806 generates a pulse signal la_pwm_0_N for controlling the ON timing of the light emitting elements, and inputs it to the element group driving unit 1201-0 via the signal line 1207_0_N. A DAC 1200_0 (digital-to-analog converter) transmits an analog voltage for determining a drive current through a signal line 1205_0 based on the data set in the register section 802 via a signal line 1202_0 to an element group driving section. 1201_0. The driving section selection section 1203 receives a driving section select signal for selecting a driving section from the register section 802 via the signal line 1204 and outputs it to the element group driving section 1201_0 via the signal line 1206_0.

The analog voltage of the element group driving section 1201 is set by similarly setting the above-described operations to the DACs 1202_1 to 1202_5 and the element group driving sections 1201_1 to 1201_5. In this manner, the element group driving units 1201_0 to 1201_5 are supplied with analog voltages and pulse signals for determining the driving current. -2747, 602-31 to 602-3747, 602-41 to 602-4747, 602-51 to 602-5747, 602-61 to 602-6747) are independently controlled in drive current and emission time.

FIG. 16 shows the circuit of the element group driving section 1201_0. It is assumed that driving units (for example, 1201_1) for other light emitting elements are also driven by the same circuit. The MOSFET 1302 supplies a drive current to the light emitting element 602-11 in accordance with the gate voltage value, and controls the current so that the drive current is turned off (extinguished) when the gate voltage is at Low level. A signal line 1207_0_0 for transmitting a pulse signal from the lighting control unit 806 is connected to the gate of the MOSFET 1304 , and the voltage charged in the capacitor 1306 when the pulse signal is Hi is transferred to the MOSFET 1302 . The gate of the MOSFET 1307 is connected to a signal line 1206_0 that transmits the drive section select signal sent from the drive section selection section 1203 . The MOSFET 1307 turns on when the received driver select signal is Hi, and charges the capacitor 1306 with the analog voltage (transmitted from the signal line 1205_0) output from the DAC 1200_0. In this embodiment, the DAC 1200_0 sets an analog voltage to the capacitor 1306 before image formation, and the voltage level is maintained by turning off the MOSFET 1307 during image formation. By the above operation, the MOSFET 1302 supplies the driving current to the light emitting element 602-11 according to the set analog voltage and the pulse signal. If the input capacitance of the light emitting element 602-11 is large and the response speed when turned off is slow, the MOSFET 1303 can increase the turn-off speed. A signal obtained by logically inverting a pulse signal by an inverter 1305 is input to the gate of the MOSFET 1303 . When the pulse signal is Low, the gate of the MOSFET 1303 becomes Hi, forcibly discharging the charge stored in the input capacitance of the light emitting element 602-11.

By switching the switching timing for each element group (for each light emitting element column) as described above, the number of signals that change simultaneously is reduced. Specifically, the analog section 807 reduces the number of signals that change simultaneously by switching the switching timing for each light emitting element array according to the pulse signal shown in FIG. 17(b). Thereby, switching noise can be reduced.

Furthermore, the analog unit 807 adjusts the integrated light amount of each element group (light-emitting element array) with an individual DAC for each element group. That is, the analog unit 807 drives each light emitting element array with a drive current that keeps the integrated light amount of each light emitting element array uniform in the pulse signal (see FIG. 17B) in which switching timings do not overlap. A drive current for driving each light-emitting element array is set based on setting information (light amount coefficient) input to the analog section 807 , and ON/OFF is controlled by the analog section 807 . Therefore, the analog unit 807 controls the pulse signal (light emission time) and the drive current to drive the light emitting element array composed of a plurality of light emitting elements with a uniform integrated light amount in the pulse signal whose switching timing does not overlap. As a result, it is possible to suppress deterioration of image quality caused by changes in the amount of integrated light, and to reduce switching noise.

Here, the pulse signal (delay time, pulse width) and drive current (light amount coefficient) controlled by the analog section 807 will be described.

FIG. 18 shows an example of the pulse width set value b, line delay set value a, and light amount coefficient set value of each light emitting element array 604 . In this embodiment, the required integral light amount of each light emitting element array is set to 1.015 μW, and the PWM resolution is set to 256. FIG. It is also assumed that the number of light emitting element arrays arranged in order in the rotation direction of the drum in one light emitting element array chip is six.

At this time, if the pulse width setting value b0, which is the first pulse width, of the first light emitting element array 604-1 is set to 128, the PWMDuty is set to 128/256=0.5. Therefore, the light quantity coefficient at the pulse width set value b0 is 1.015/0.5=2.031. The light emitting element array 604-1 is driven with a drive current based on the light intensity coefficient of 2.031 at the pulse width setting value b0, so that the required integrated light intensity at the pulse width setting value b0=128 is 1. 0.015 μW can be obtained. The light quantity coefficient at the pulse width set value b0 is the first light quantity coefficient for obtaining the required integrated light quantity when the first light emitting element array 604-1 emits light with the first pulse width. Also, the line delay set value a0 in the pulse width set value b0 is set to 5 as an arbitrary value.

Similarly, for the second light emitting element array 604-2, the pulse width setting value b1, which is the second pulse width different from the first pulse width, must satisfy b0>b1, so is set to 118. FIG. When the pulse width set value b1 is set to 118, the PWMduty is set to 118/256=0.461. Therefore, the light amount coefficient at the pulse width setting value b1 is 1.015/0.461=2.203. The light emitting element array 604-2 is driven with a driving current based on the light intensity coefficient of 2.203 at the pulse width setting value b1, so that the required integrated light intensity of 1.015 μW can be obtained. The light amount coefficient at the pulse width setting value b1 is set to obtain the same required integral light amount as the first light emitting element array when the second light emitting element array 604-2 emits light with a second pulse width different from the first pulse width. is the second light quantity coefficient of . Also, since the line delay setting a1 in the pulse width setting value b1 must be different from a0+b0=133, a1=10 is set as an example. Thus, each set value of the first light emitting element array and each set value of the second light emitting element array can satisfy a0<a1, b0>b1, a0≠a1, and a0+b0≠a1+b1.

For the other light emitting element arrays 604-3 to 604-5, similarly to the first light emitting element array 604-1 and the second light emitting element array 604-2, each set value is set, and the required integrated light amount is obtained. Each light quantity coefficient for obtaining a certain 1.015 μW is set.

Each light amount coefficient set for each light emitting element array is stored in the register unit 802 as a setting value necessary for operation, like other setting values (line delay setting value, pulse width setting value).

Note that, in this embodiment, as described above, based on the communication signal 709 from the CPU 703, the write and read of the setting value to the register unit 802 are controlled. That is, the image controller unit 700 including the CPU 703 transmits the setting value, which is setting information, as a signal for controlling the exposure head, and stores the setting value in the register unit 802 . However, it is not limited to this. For example, the set values may be stored in a register section on the exposure head side, or in a storage section other than the register section on the exposure head side.

Then, as described above, the pulse signal generator 805 generates the pulse signal shown in FIG. 17B for each light emitting element array.

After the analog unit 807, which is the driving unit, starts light emission of the first light emitting element array 604-1 at the first start timing t10 after the first delay time (=a0) has passed, the first delay time (= At a second start timing t11 after a second delay time (=a1) later than a0), the second light emitting element array 604-2 starts emitting light. Further, the analog unit 807 terminates the light emission of the second light emitting element array 604-2 at the second end timing t21 when the second pulse width (=b1) has passed, and thereafter, the second pulse width (=b1) is wider than the second pulse width (=b1). At the first end timing t20 after one pulse width (=b0) has passed, the light emission of the first light emitting element array 604-1 is ended. Here, only the first light emitting element row 604-1 and the second light emitting element row 604-2 have been illustrated and explained, but the other light emitting element rows 604-3 to 604-5 are similarly shown in FIG. Light emission is started and ended according to the pulse signal shown in b).

Furthermore, the analog section 807, which is a driving section, drives the first light emitting element array 604-1 with the required integrated light amount according to the drive current corresponding to the first pulse width (=b0) and the first light amount coefficient. Further, the analog section 807 drives the second light emitting element array 604-2 in the same manner as the first light emitting element array 604-1 according to the second pulse width (=b1) and the second light quantity coefficient. It is driven with the required integral light amount.

In other words, the analog section 807 drives the first light emitting element array 604-1 with a predetermined integrated light amount by the first pulse signal pwm0 shown in FIG. 17(b) and the drive current. Further, the analog section 807 operates the second light emitting element array 604-2 by the second pulse signal pwm1 shown in FIG. Driven by the amount of light.

As a result, it is possible to keep the integrated light amount of each light emitting element array uniform while preventing the switching timing of each light emitting element array from overlapping. Therefore, in an exposure head that performs multiple exposure using light emitting element arrays, degradation of image quality can be suppressed and switching noise can be reduced.

REFERENCE SIGNS LIST 102: photosensitive drum 106: exposure head 201: light emitting element group 202: printed circuit board 400: light emitting element array chip 602: light emitting element 604: light emitting element array 700: image controller unit 703: CPU
704 ... Synchronization signal generation unit 802 ... Register unit 805 ... Pulse signal generation unit 806 ... Lighting control unit 807 ... Analog unit

Claims (7)

a photoreceptor;
A first light-emitting element row formed of a plurality of light-emitting elements arranged along a first direction that is the rotation axis direction of the photoreceptor, and a plurality of light-emitting elements arranged along the first direction. and a second light emitting element array arranged in order in a second direction orthogonal to the first direction, and the exposure position of the photosensitive member exposed by the first light emitting element array is the second light emitting element array. an exposure device for multiple exposure with a light emitting element array;
a controller that transmits a signal for controlling the exposure device to the exposure device;
with
The exposure device is
a first delay time from the input timing of the line synchronizing signal to the first start timing of starting light emission; setting a first pulse signal for causing the first light emitting element array to emit light based on the first pulse width up to the 1 end timing;
a second delay time different from the first delay time from the input timing of the line synchronizing signal to the second start timing for starting light emission; and the input timing of the line synchronizing signal subsequent to the line synchronizing signal from the second start timing. setting a second pulse signal for causing the second light emitting element array to emit light based on a second pulse width different from the first pulse width up to a second end timing for ending the light emission by;
Starting and ending light emission of each light emitting element row according to the setting;
An image forming apparatus characterized by: The setting value for each light emitting element array is a0<a1, b0>b1, where a0 is the first delay time, b0 is the first pulse width, b1 is the second delay time, and b1 is the second pulse width. satisfies a0+b0≠a1+b1,
2. The image forming apparatus according to claim 1, wherein: The exposure apparatus starts light emission of the first light emitting element array at a first start timing after the first delay time has passed, and then has a second start timing after the second delay time later than the first delay time has passed. After the light emission of the second light emitting element array is started at the second end timing when the second pulse width has passed, the first terminating light emission of the first light emitting element array at a first end timing after the pulse width has elapsed;
3. The image forming apparatus according to claim 1, wherein: The exposure device is
The first light emitting element array is driven with a predetermined integrated light amount by the first pulse signal and driving current, and the second light emitting element array is driven by the second pulse signal and driving current in the same manner as the first light emitting element array. driving with the predetermined integrated light amount of
4. The image forming apparatus according to claim 1, wherein: The exposure device drives the first light emitting element array according to a drive current corresponding to the first pulse width and a first light quantity coefficient for obtaining the predetermined integrated light quantity when light is emitted with the first pulse width. according to a drive current corresponding to the second pulse width and a second light quantity coefficient for obtaining the predetermined integrated light quantity similar to that of the first light emitting element array when light is emitted with the second pulse width driving the second row of light emitting elements;
5. The image forming apparatus according to claim 4, wherein: The exposure device stores the first delay time, the second delay time, the first pulse width, the second pulse width, the first light quantity coefficient, and the second light quantity coefficient. having a register part,
6. The image forming apparatus according to claim 5, wherein: The exposure device is
A pulse signal for causing the light emitting element array to emit light is generated based on the delay time from the input timing of the line synchronization signal to the start timing of light emission and the pulse width from the start timing to the end timing of light emission. a pulse signal generator for
a driving unit that drives the light emitting element array with a predetermined integrated light amount by the pulse signal and the driving current;
has
The pulse signal generation unit includes a first delay time from the input timing of the line synchronizing signal to the first start timing for starting light emission, and from the first start timing to the input timing of the line synchronizing signal next to the line synchronizing signal. a first pulse signal for causing the first light emitting element array to emit light based on a first pulse width up to a first end timing for ending the light emission, and light emission is started from the input timing of the line synchronization signal. a second delay time different from the first delay time up to a second start timing; and a second end timing ending the light emission from the second start timing to the input timing of the line synchronization signal next to the line synchronization signal. generating a second pulse signal for causing the second light emitting element array to emit light based on a second pulse width different from the first pulse width up to
The driving section drives the first light emitting element array with a predetermined integrated light amount by the first pulse signal and the driving current, and drives the second light emitting element array by the second pulse signal and the driving current. Driving with the predetermined integrated light amount similar to the light emitting element array,
7. The image forming apparatus according to claim 1, wherein:

Images