JP2023105439A - Information processing apparatus, image forming apparatus, control method for information processing apparatus, and control program for information processing apparatus - Google Patents

Abstract

To prevent wrong data from being written in a memory while power is cut off.SOLUTION: An information processing apparatus has: a capacitor that stores electric charges supplied from a power source; a first controller that operates by power supply voltage received via the capacitor; a memory that is accessed by the first controller; and a second controller that, when the supply from the power source is stopped for a predetermined time, inhibits a writing operation in the memory performed by the first controller.SELECTED DRAWING: Figure 3

Description

The present invention relates to an information processing device, an image forming device, a control method for an information processing device, and a control program for an information processing device.

In an image forming apparatus, when the zero-crossing point of the AC voltage is not detected for a predetermined time due to a power failure or unplugged power supply, a technique is disclosed for preventing the loss of the latest data by writing data to a nonvolatile memory (see, for example, Patent Document 1).

However, when data is written to the memory while the power supply is cut off and the power supply voltage drops, there is a risk that erroneous data will be written to the memory.

SUMMARY OF THE INVENTION In view of the above problems, it is an object of the present invention to prevent erroneous data from being written to a memory when power is cut off.

In order to solve the above technical problem, an information processing apparatus according to one aspect of the present invention includes: a capacitor that accumulates electric charge supplied from a power source; a first controller that operates with a power supply voltage received via the capacitor; and a second controller that prohibits the write operation of the memory by the first controller when the power supply is stopped for a predetermined time.

Wrong data can be prevented from being written to the memory when the power is cut off.

1 is an overall configuration diagram of an image forming apparatus according to a first embodiment of the present invention; FIG. 2 is a block diagram showing the hardware outline of the main part of the image forming apparatus of FIG. 1; FIG. 3 is a circuit block diagram showing an example of a controller control board in FIG. 2; FIG. 4 is a flow chart showing an example of the operation of the controller control board of FIG. 3; FIG. 4 is a sequence diagram showing an example of the operation of the controller control board of FIG. 3; FIG. FIG. 7 is a circuit block diagram showing an example of a controller control board in the image forming apparatus according to the second embodiment of the invention; FIG. 7 is a sequence diagram showing an example of the operation of the controller control board of FIG. 6;

Embodiments will be described below with reference to the drawings. In the following, symbols indicating signals are also used as symbols indicating signal values, signal lines or signal terminals. Symbols indicating voltages are also used as symbols indicating voltage lines or voltage terminals to which the voltage is supplied.

FIG. 1 is an overall configuration diagram of an image forming apparatus according to the first embodiment of the present invention. The image forming apparatus 1 shown in FIG. 1 is, for example, a digital multifunction peripheral (MFP: Multi-Function Printer) having a copy function, a print function, a scanner function, a facsimile function, and the like. The image forming apparatus 1 can switch between operation modes that realize a copy function, a print function, a scanner function, and a facsimile function by using an application switching key or the like of an operation unit (not shown). The image forming apparatus 1 is in the copy mode when the copy function is selected, in the print mode when the print function is selected, in the scanner mode when the scanner function is selected, and in the facsimile mode when the facsimile function is selected. Note that the image forming apparatus 1 may be a copier having only a copying function, a printer having only a printing function, or a facsimile machine having only a facsimile function.

Further, the internal state of the image forming apparatus 1 is switched to an operating mode (operating state), a standby mode (standby state), an energy saving mode (low power state), or the like, depending on the state of the internal circuit. . In the following, energy saving mode is also referred to as energy saving mode.

For example, the active mode includes a copy mode or a print mode for printing image or text data or the like on a paper medium or the like. The print mode includes an operation of printing received data on a paper medium or the like in the facsimile mode. Also, the operating mode includes transmission/reception operations in a scanner mode for scanning a document or the like or a facsimile mode. The state of the internal circuit is switched by the operation of the operation unit by the user or the control within the image forming apparatus 1 .

For example, the image forming apparatus 1 has an automatic document feeder (ADF), an image reader 3 , a writing unit 4 , a printer unit 5 , a power supply 20 and a control device 21 . The printer unit 5 has a photosensitive drum 6, a developing device 7, a conveying belt 8, a fixing device 9, and a storage space in which a paper feed tray 10 is stored. The printer unit 5 creates a toner image to be transferred onto a paper medium or the like based on image information. The printer unit 5 is an example of an image forming section that forms an image. As an example of the flow of image formation in the image forming apparatus 1, a case where the operation mode is set to the copy mode will be briefly described below.

In the copy mode, a plurality of originals to be copied are set on the automatic document feeder 2 . When a start button on an operation unit (not shown) is pressed, the automatic document feeder 2 feeds the documents one by one to the image reading device 3 . The image reading device 3 reads image information of each document sequentially sent from the automatic document feeder 2 . Image information read by the image reading device 3 is processed by, for example, an image processing unit mounted on the control device 21 .

The writing unit 4 converts the image information processed by the image processing section into optical information. The photosensitive drum 6 is uniformly charged by a charger (not shown) and then exposed to laser light containing optical information converted by the writing unit 4 . An electrostatic latent image is formed on the photosensitive drum 6 by the exposure. The developing device 7 develops the electrostatic latent image on the photoreceptor drum 6 to form a toner image on the photoreceptor drum 6 . A conveying belt 8 transfers the toner image onto a paper medium or the like. The fixing device 9 fixes the toner image onto a paper medium or the like. Then, the transfer paper on which the image of the original is copied is discharged from the discharge section.

For example, the standby mode described above is the state in the copy mode until the start button is pressed, and the operating mode is the state from the time the start button is pressed until the paper medium or the like is ejected. load is in operation. After the operating mode ends, the state of the image forming apparatus 1 returns to the standby mode, and when the standby mode continues for a predetermined time, the energy saving mode is entered. When the operation unit is operated during the energy saving mode, the state of the image forming apparatus 1 returns to the standby mode.

The power supply device 20 converts an AC voltage supplied from an AC power supply 30 such as a commercial power supply into a plurality of types of DC voltages (for example, a first DC voltage and a second DC voltage). The power supply device 20 supplies the converted first DC voltage to various loads such as the printer unit 5 of the image forming apparatus 1 . For example, loads include various motors, a charger for charging the photosensitive drum 6, a developing roller of the developing device 7, and the like. The power supply device 20 supplies the converted second DC voltage to the control device 21 .

The second DC voltage supplied to the control device 21 is used as an operating power source for a CPU (Central Processing Unit) mounted on the control device 21, a memory, and the like. The control device 21 controls the overall operation of the image forming apparatus 1 by causing a controller such as a built-in CPU to execute a control program. Thus, the image forming apparatus 1 operates by receiving power from the commercial power supply. The control device 21 is an example of an information processing device that executes a control method such as image formation by executing a control program.

FIG. 2 is a block diagram showing an example of a hardware configuration of main parts of the image forming apparatus 1 of FIG. The image forming apparatus 1 has an AC (Alternating Current)/DC (Direct Current) converter 40 , a printer 50 , a scanner 60 , a facsimile machine 70 , an operation section 80 , an engine control board 100 and a controller control board 200 .

The AC/DC converter 40 supplies the engine control board 100 with a second DC voltage converted from the AC voltage supplied from the AC power supply 30 . AC/DC converter 40 corresponds to power supply device 20 in FIG. The second DC voltage supplied to engine control board 100 is supplied via engine control board 100 to control units of printer 50 , scanner 60 , facsimile 70 and operation unit 80 , and controller control board 200 .

For example, printer 50 corresponds to writing unit 4 and printer unit 5 of FIG. A scanner 60 corresponds to the image reading device 3 . For example, the facsimile machine 70, the engine control board 100 and the controller control board 200 correspond to the control device 21 in FIG.

FIG. 3 is a circuit block diagram showing an example of the controller control board 200 of FIG. The controller control board 200 has a microcomputer (microcomputer) 210, a main CPU 220, a power control switch 230, a memory 240, power-on reset circuits 250, 260, a switch DCSW, an AND circuit AND, and capacitors C1, C2.

The AC/DC converter 40 is connected to the image forming apparatus 1 via an AC cable or the like, and outputs a zero-cross signal voltage indicating that power is being supplied while receiving power from the AC power supply 30 . do. The zero-cross signal ZCRS is a signal whose logical value is inverted when the AC voltage received from the AC power supply 30 crosses 0 V, and is, for example, a pulse signal having the same period as the AC voltage. Thus, the AC/DC converter 40 functions as a power detector that detects the supply of power.

The microcomputer 210 operates by receiving the power supply voltage VCCA (second DC voltage). The microcomputer 210 has a function of controlling the power of the image forming apparatus 1 . For example, the microcomputer 210 performs control to supply the power supply voltage VCCA supplied to the controller control board 200 to the power supply line VCCB.

Further, the microcomputer 210 can determine whether or not the AC power supply 30 is connected to the image forming apparatus 1 by monitoring the zero cross signal ZCRS output from the AC/DC converter 40 . Then, the microcomputer 210 can control the write protect function of the memory 240 according to the zero cross signal ZCRS. The control program executed by the microcomputer 210 may be stored in the memory 240 or may be stored in the built-in memory. Microcomputer 210 is an example of a second controller.

The main CPU 220 operates by receiving a power supply voltage VCCB (second DC voltage). The main CPU 220 has a function of controlling operations such as a printer operation and a scanner operation of the image forming apparatus 1 . For example, the main CPU 220 accesses the memory 240 to execute a control program for operating the image forming apparatus 1 , and reads and writes data and various parameters used for operation in the memory 240 . Main CPU 220 is an example of a first controller.

The power control switch 230 controls connection between the power line VCCA and the power line VCCB according to a control signal from the microcomputer 210 . For example, the power control switch 230 connects the power line VCCA to the power line VCCB when the image forming apparatus 1 is set to a normal mode in which operations such as a printer operation and a scanner operation are performed. Further, for example, the power control switch 230 cuts off the connection between the power line VCCA and the power line VCCB when the image forming apparatus 1 is set to the energy saving mode.

The memory 240 is, for example, an electrically rewritable nonvolatile memory such as a flash memory or MRAM (Magnetoresistive Random Access Memory), and operates by receiving a power supply voltage VCCB. The memory 240 performs a read operation or a write operation according to a clock signal CLK from the main CPU 220 and memory access signals (address signal, access control signal, etc.) not shown. The memory 240 writes the data input signal DI received from the main CPU 220 together with the memory access signal into the memory cell during the write operation. The memory 240 outputs the data read from the memory cell to the main CPU 220 as a data output signal DO during a read operation.

The memory 240 prohibits the write operation while the write protect terminal /WP receives the write protect signal /WPc output from the main CPU 220 or the write protect signal /WPm output from the microcomputer 210 . The write protect signals /WPc, /WPm, /WP are signals of negative logic, low level indicates a write inhibit state, and high level indicates a write enable state. The memory 240 prohibits the write operation when the write protect signal /WP is at low level, and permits the write operation when the write protect signal /WP is at high level.

The write protect signals /WPc and /WPm are supplied to the write protect terminal /WP via an AND circuit AND (OR circuit of negative logic). An AND circuit AND receives the write protect signal /WPc at one input, the write protect signal /WPm at the other input, and outputs the write protect signal /WP to a write protect terminal /WP.

Thereby, not only the main CPU 220 but also the microcomputer 210 can control the write protection of the memory 240 . In other words, even when the main CPU 220 is executing a program for write access to the memory 240 when the power is turned off, the microcomputer 210 can mask the high-level write protect signal /WPc output by the main CPU 220 . The AND circuit AND is an example of a mask circuit that masks the high-level write protect signal /WPc output by the main CPU 220 .

Two input terminals and one output terminal of the AND circuit AND are pulled down. As a result, when any one of the write protect signal lines /WPm, /WPc, /WP is in a floating state, write access to the memory 240 can be prohibited, and erroneous writing of data to the memory 240 can be prevented. can.

In addition, the transition time for the write protect signal lines /WPm, /WPc, /WP to change from the high level to the low level can be shortened compared to the case of not pulling down. As a result, when the write protect signal /WPm from the microcomputer 210 or the write protect signal /WPc from the main CPU 220 changes to low level, write access to the memory 240 can be quickly prohibited.

If the memory 240 is a volatile memory such as a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory), data stored in the memory 240 will disappear when the power is turned off. On the other hand, the memory 240, such as flash memory, continues to store data even after the power is turned off. For this reason, if there is a risk of incorrect data writing, it is necessary to prohibit write access to the memory 240 to prevent malfunction after the image forming apparatus 1 is restarted.

The power-on reset 250 supplies a high-level reset signal /RSTm to the microcomputer 210 to set the microcomputer 210 to an operable state while receiving the power supply voltage VCCA at the power supply terminal. The power-on reset circuit 250 sets the reset signal /RSTm to a low level and sets the microcomputer 210 to a reset state when the power supply voltage VCCA becomes lower than the threshold voltage VT2 shown in FIG. Power-on reset circuit 250 is an example of a second power-on reset circuit.

The power-on reset circuit 260 supplies a high-level reset signal /RSTc to the main CPU 220 to set the main CPU 220 to an operable state while receiving the power supply voltage VCCB at the power supply terminal. When the power supply voltage VCCB becomes lower than the threshold voltage VT1 shown in FIG. 5, the power-on reset circuit 260 sets the reset signal /RSTc to low level and sets the main CPU 220 to the reset state. Power-on reset circuit 260 is an example of a first power-on reset circuit.

For example, threshold voltage VT1 is higher than threshold voltage VT2. Therefore, when the power supply voltages VCCA and VCCB drop, the reset signal /RSTc changes to low level earlier than the reset signal /RSTm. The threshold voltage VT1 is an example of a first voltage, and the threshold voltage VT2 is an example of a second voltage.

The switch DCSW is a push-down switch operated by, for example, a service person who maintains or repairs the image forming apparatus 1 . When the switch DCSW is pressed, the charges accumulated in the capacitors C1 and C2 are discharged to the ground line VSS via the power supply voltage terminal VCCA of the microcomputer 210 and the switch DCSW. This prevents the microcomputer 210 and the main CPU 220 from continuing to operate until the charges accumulated in the capacitors C1 and C2 are discharged after the power is cut off.

For example, when performing maintenance or repair of the image forming apparatus 1 , the service person pulls out the controller control board 200 from the image forming apparatus 1 after depressing the switch DCSW after turning off the power. As a result, the time until the charges accumulated in the capacitors C1 and C2 are discharged can be shortened, and workability can be improved. Also, by pressing the switch DCSW, the electric charges can be reliably discharged from the capacitors C1 and C2. Therefore, by pulling out the controller control board 200 from the image forming apparatus 1 while electric charges remain in the capacitors C1 and C2, it is possible to prevent the electronic components mounted on the controller control board from being destroyed.

Capacitor C1 has a function of smoothing power supply voltage VCCA and a function of accumulating charges supplied from AC/DC converter 40 . Capacitor C2 has a function of smoothing power supply voltage VCCB and a function of accumulating charges supplied from power control switch 230 .

FIG. 4 is a flow chart showing an example of the operation of the controller control board 200 of FIG. 4 shows an example of a control method executed by the image forming apparatus 1, and shows an example of a control program executed by the image forming apparatus 1. FIG. Further, FIG. 4 shows an example of a control method executed by an information processing apparatus mounted on the image forming apparatus 1, and shows an example of a control program executed by the information processing apparatus mounted on the image forming apparatus 1. FIG. Note that the control program may be stored in a recording medium detachably attached to the image forming apparatus 1, and transferred from the recording medium to the memory 240, the built-in memory of the microcomputer 210, or the like.

First, in step S10, when the AC cable of image forming apparatus 1 is connected to AC power supply 30, AC/DC converter 40 starts generating power supply voltage VCCA. As a result, electric charge is accumulated in capacitor C1, and power supply voltage VCCA is supplied to microcomputer 210 and power-on reset circuit 250. FIG.

Next, in step S12, the power-on reset circuit 250 sets the reset signal /RSTm from low level to high level (reset release state) in response to the rise of the power supply voltage VCCA, and activates the microcomputer 210. FIG.

Next, in step S14, the activated microcomputer 210 turns on the power control switch 230 to connect the power line VCCA to the power line VCCB. As a result, electric charge is accumulated in the capacitor C2.

Next, in step S16, the microcomputer 210 changes the write protect signal /WEm from low level to high level (H). As a result, the input level of the write protect terminal /WP of the memory 240 is also changed from low level to high level (H), and write access to the memory 240 by the main CPU 220 is permitted. After the write protect signal /WPm is set to high level, the main CPU 220 sets the write protect signal /WPc to low level, thereby changing the input level of the write protect terminal /WP to low level. Thereby, write access to the memory 240 can be prohibited.

At step S18, the microcomputer 210 polls the logic level of the zero cross signal ZCRS. Next, in step S20, the microcomputer 210 determines whether or not the period during which the logic level of the zero-cross signal ZCRS does not change is longer than or equal to time T1 (predetermined time). If the logic level of zero-cross signal ZCRS changes before time T1 elapses, microcomputer 210 returns the process to step S18 and continues polling zero-cross signal ZCRS. Microcomputer 210 shifts the process to step S22 when the period in which the logic level of zero-cross signal ZCRS does not change passes time T1 or longer.

Although not particularly limited, the time T1 may be, for example, 50 ms (milliseconds). As a result, the microcomputer 210 can detect interruption of the AC power supply 30 , while excluding momentary power failure of the AC power supply 30 that does not affect the operation of the image forming apparatus 1 from detection. Here, the momentary power failure time that does not affect the operation of the image forming apparatus 1 is determined depending on the amount of charge that can be accumulated in the capacitors C1 and C2, and the time T1 is set based on the determined time. For example, the interruption of the AC power supply 30 occurs due to the wrong extraction of the AC cable, power failure, or the like.

In step S22, the microcomputer 210 changes the write protect signal /WEm from high level to low level. As a result, the input level of the write protect terminal /WP of the memory 240 is also changed from high level to low level, and write access to the memory 240 by the main CPU 220 is prohibited.

Therefore, write access to the memory 240 is prohibited even if the main CPU 220 can access the memory 240 before the charges accumulated in the capacitors C1 and C2 are discharged after the AC power supply 30 is cut off. As a result, it is possible to prevent data destruction in which write access is stopped midway and incorrect data is written to the memory 240 . Further, after the image forming apparatus 1 is restarted, it is possible to prevent the image forming apparatus 1 from malfunctioning due to the memory 240 holding erroneous data.

Next, in step S24, after the microcomputer 210 prohibits write access to the memory 240, the discharge of the capacitors C1 and C2 is completed, and the operations of the microcomputer 210 and the main CPU 220 are stopped.

5 is a sequence diagram showing an example of the operation of the controller control board in FIG. 3. FIG. In FIG. 5, the symbol ON indicates the power supply state or the zero-cross signal ZCRS generation state, and the symbol OFF indicates the power supply stop state or the zero-cross signal ZCRS generation stop state.

First, when the AC cable is connected to the AC power supply 30, the AC/DC converter 40 periodically outputs the pulse-like zero-cross signal ZCRS to generate the power supply voltage VCCA (FIGS. 5A and 5B). ). Capacitor C1 receives power supply voltage VCCA and accumulates electric charges.

The power-on reset circuit 250 changes the reset signal /RSTm to high level when the power supply voltage VCCA becomes equal to or higher than the threshold voltage VT2 (FIG. 5(c)). As a result, the microcomputer 210 starts operating, sets the write protect signal /WPm to high level, and the memory 240 becomes write accessible (FIG. 5(d)).

In addition, when the microcomputer 210 turns on the power control switch 230, the power line VCCA is connected to the power line VCCB, and the power voltage VCCB rises (FIG. 5(e)). Capacitor C2 receives power supply voltage VCCB and accumulates charges.

The power-on reset circuit 260 changes the reset signal /RSTc to high level when the power supply voltage VCCB becomes equal to or higher than the threshold voltage VT1 (FIG. 5(f)). As a result, the main CPU 220 starts operating and starts accessing the memory 240 (not shown).

The microcomputer 210 continues to poll the zero-cross signal ZCRS while receiving the power supply voltage VCCA and operating (FIG. 5(g)). When the microcomputer 210 does not detect the transition edge of the zero-cross signal ZCRS for the time T1 or longer, it detects the occurrence of a power failure such as interruption of the AC power supply 30, and changes the write protect signal /WPm to low level (FIG. 5(h), (i)).

Since the low-level write protect signal /WPm is supplied to the write protect terminal /WP of the memory 240 via the AND circuit AND, the main CPU 220 is in a state in which write access to the memory 240 is disabled. Therefore, it is possible to prevent erroneous writing of data to the memory 240 by the main CPU 220 when the power is shut off (FIG. 5(j)). As a result, it is possible to prevent the image forming apparatus 1 from malfunctioning after being restarted.

Note that the main CPU 220 can perform read access to the memory 240 while the write protect signal /WPm is at low level. The clock CLK in the figure indicates that the main CPU 220 makes read access to the memory 240, and the data output signal DO in the figure indicates that it is output from the memory 240 in response to the read access (FIG. 5 ( k), (l)).

When AC/DC converter 40 stops generating power supply voltage VCCA by shutting off AC power supply 30, the charges accumulated in capacitors C1 and C2 are gradually discharged. The power-on reset circuit 250 changes the reset signal /RSTm to low level when the power supply voltage VCCA becomes lower than the threshold voltage VT2 (FIG. 5(m)). As a result, the microcomputer 210 enters a reset state and stops operating.

The power-on reset circuit 260 changes the reset signal /RSTc to low level when the power supply voltage VCCB becomes lower than the threshold voltage VT1 (FIG. 5(n)). As a result, the main CPU 220 enters a reset state and stops operating (FIG. 5(o)). Even if the main CPU 220 stops operating during read access by the main CPU 220, the data stored in the memory 240 is retained without being lost. The power supply voltages VCCA and VCCB gradually decrease until the discharge of the capacitors C1 and C2 is completed (FIGS. 5(p) and (q)).

Since the threshold voltage VT1 is set higher than the threshold voltage VT2, the reset signal /RSTc transitions to low level earlier than the reset signal /RSTm. Thereby, the main CPU 220 can be stopped before the microcomputer 210 that controls the power supply is stopped. Therefore, even when the write protect signal /WPm temporarily becomes high level when the microcomputer 210 is stopped, it is possible to prevent the main CPU 220 from performing write access to the memory 240 . Since erroneous writing of data can be prevented, malfunction after the image forming apparatus 1 is restarted can be prevented.

As described above, in this embodiment, the microcomputer 210 sets the write protect signal /WP to a low level to prohibit write access to the memory 240 when detecting a power failure such as interruption of the AC power supply 30 . As a result, it is possible to prevent erroneous writing of data to the memory 240 by the main CPU 220 when the power is turned off, and it is possible to prevent malfunction after the image forming apparatus 1 is restarted.

The main CPU 220 can be stopped before the microcomputer 210 stops by causing the reset signal /RSTc to transition to a low level earlier than the reset signal /RSTm when the power is cut off. As a result, even when the write protect signal /WPm temporarily becomes high level when the microcomputer 210 is stopped, erroneous writing of data to the memory 240 by the main CPU 220 can be prevented, and malfunction of the image forming apparatus 1 can be prevented. can be done.

For example, if the memory 240 is a non-volatile memory, it will continue to store data even after power is turned off. In this embodiment, since the microcomputer 210 prohibits write access to the memory 240 when the power is cut off, it is possible to prevent erroneous data from being written to the memory 240 when the power is cut off. As a result, it is possible to prevent malfunction after the image forming apparatus 1 is restarted due to the memory 240 continuing to store erroneous data.

The microcomputer 210 sets the write protect signal /WPm to low level when the power is cut off, and forcibly outputs it to the memory 240 as the low level write protect signal /WP through the AND circuit AND. As a result, even when the main CPU 220 is executing a program for write access to the memory 240 when the power is turned off, the output of the high-level write protect signal /WPc output by the main CPU 220 to the memory 240 can be masked. . As a result, erroneous writing of data to the memory 240 when power is cut off can be prevented.

FIG. 6 is a circuit block diagram showing an example of a controller control board in the image forming apparatus according to the second embodiment of the invention. Elements similar to those in FIGS. 1 to 3 are denoted by the same reference numerals, and detailed description thereof is omitted. A controller control board 200A of this embodiment is configured by adding a battery BAT and diodes D1 and D2 to the controller control board 200 of FIG.

For example, the controller control board 200A may function as an image processing section of the image forming apparatus 1 by being mounted on the control device 21 of FIG. The outline of the hardware of the image forming apparatus 1 on which the controller control board 200A is mounted is the same as that of FIG.

A power supply terminal VCCA of microcomputer 210 and a power supply terminal (not shown) of power-on reset circuit 250 are connected to power supply line VCCA through diode D2 and to battery BAT through diode D2. The microcomputer 210 operates with the power supply voltage VCCA or the voltage supplied from the battery BAT. Diode D1 prevents capacitor C1 from being charged by the voltage output from battery BAT.

While battery BAT is outputting voltage, power-on reset circuit 250 outputs a high-level reset signal /RSTm. Therefore, power-on reset circuit 250 sets reset signal /RSTm to low level or high level according to power supply voltage VCCA generated by AC/DC converter 40 only when battery BAT is exhausted.

In this embodiment, the microcomputer 210 can operate with power from the battery BAT even when the power supply is abnormally cut off. Therefore, even if the power supply voltage VCCA generated by the AC/DC converter 40 drops due to an abnormal shutdown of the power supply, it is possible to prevent a voltage lower than the guaranteed input voltage of the microcomputer 210 from being supplied to the power supply terminal VCCA of the microcomputer 210. can. Therefore, the microcomputer 210 can operate normally even when the power is cut off, and can change the write protect signal /WPm to low level when no transition edge of the zero cross signal ZCRS is detected for the time T1 or longer.

FIG. 7 is a sequence diagram showing an example of the operation of the controller control board 200A of FIG. A detailed description of the same operations as in FIG. 5 will be omitted. The operation flow of the controller control board 200A is the same as in FIG.

The waveforms of AC power supply 30, zero cross signal ZCRS, power supply voltage VCCA output from AC/DC converter 40, clock signal CLK of memory 240, and data output signal DO of memory 240 are the same as in FIG. The waveforms of power supply voltage VCCB and reset signal /RSTc are the same as in FIG. 5 except that the rise timing is earlier than in FIG. The waveform of the write protect signal /WPm is the same as in FIG. 5 except that it is set to high level when the AC cable is connected.

The dashed-dotted lines shown for the power supply terminal VCCA, reset signal /RSTm and write protect signal /WPm of the microcomputer 210 show waveforms when the battery BAT is exhausted, which are similar to the waveforms in FIG.

In this embodiment, the power supply terminal VCCA of the microcomputer 210 receives the power supply voltage supplied from the battery BAT regardless of whether or not the AC power supply 30 is supplied. 7(a)). Similarly, the power-on reset circuit 250 receives the power supply voltage supplied from the battery BAT regardless of whether or not the AC power supply 30 is supplied, so that the reset signal /RSTm is fixed at a high level (FIG. 7(b)). .

Since the reset signal /RSTm is fixed at a high level, the microcomputer 210 keeps the power control switch 230 on all the time. The power line VCCB is always connected to the power line VCCA. Therefore, the power supply voltage VCCB rises together with the power supply voltage VCCA output from the AC/DC converter 40 (FIG. 7(c)).

The power-on reset circuit 260 changes the reset signal /RSTc to high level when the power supply voltage VCCB becomes equal to or higher than the threshold voltage VT1 (FIG. 7(d)). As a result, the main CPU 220 starts operating and starts accessing the memory 240 .

As in FIG. 5, if the microcomputer 210 does not detect a transition edge of the zero-cross signal ZCRS for the time T1 or longer, it changes the write protect signal /WPm to low level (FIGS. 7(e) and (f)).

When AC/DC converter 40 stops generating power supply voltage VCCA by shutting off AC power supply 30, the charges accumulated in capacitors C1 and C2 are gradually discharged. The power supply terminal VCCA of the microcomputer 210 receives the power supply voltage supplied from the battery BAT regardless of whether or not the AC power supply 30 is supplied, so that it is maintained at a constant voltage (FIG. 7(g)). Similarly, the power-on reset circuit 250 receives the power supply voltage supplied from the battery BAT regardless of whether or not the AC power supply 30 is supplied, so that the reset signal /RSTm is fixed at a high level (FIG. 7(h)). . The operation of power-on reset circuit 260 (waveform of reset signal /RSTc) is the same as in FIG.

As described above, also in this embodiment, the same effects as those of the above-described embodiment can be obtained. For example, by prohibiting write access to the memory 240 by the microcomputer 210 when a power failure occurs such as interruption of the AC power supply 30, erroneous writing of data to the memory 240 at the time of power interruption can be prevented. Malfunction after restarting the device 1 can be prevented.

Furthermore, in this embodiment, the microcomputer 210 can operate with power from the battery BAT even when the power supply is abnormally cut off, so it can operate normally even when the power supply is cut off, and can monitor the zero-cross signal ZCRS. Then, when the microcomputer 210 does not detect the transition edge of the zero-cross signal ZCRS for the time T1 or longer, it can change the write protect signal /WPm to low level to reliably prohibit write access to the memory 240 .

Although the present invention has been described above based on each embodiment, the present invention is not limited to the requirements shown in the above embodiments. These points can be changed without impairing the gist of the present invention, and can be determined appropriately according to the application form.

REFERENCE SIGNS LIST 1 image forming device 2 automatic document feeder 3 image reading device 4 writing unit 5 printer unit 6 photoreceptor drum 7 developing device 8 conveying belt 9 fixing device 10 paper feed tray 20 power supply device 21 control device 30 AC power supply 40 AC/DC converter 50 Printer 60 Scanner 70 Facsimile 80 Operation Unit 100 Engine Control Board 200, 200A Controller Control Board 210 Microcomputer 220 Main CPU
230 Power control switch 240 Memory 250, 260 Power-on reset circuit AND AND circuit BAT Battery C1, C2 Capacitor CLK Clock signal D1, D2 Diode DCSW Switch DI Data input signal DO Data output signal /RSTc, /RSTm Reset signal VCCA, VCCB Power supply Voltage /WPc, /WPm Write protect signal ZCRS Zero cross signal

JP-A-10-185965

Claims (8)

a capacitor that accumulates electric charge supplied from a power supply;
a first controller operated by a power supply voltage received through the capacitor;
a memory accessed by the first controller;
a second controller that prohibits the write operation of the memory by the first controller when the power supply is stopped for a predetermined time;
An information processing device comprising: a first power-on reset circuit that resets the first controller when the power supply voltage is lower than a first voltage;
a second power-on reset circuit for resetting the second controller when the power supply voltage is lower than a second voltage lower than the first voltage;
2. The information processing apparatus according to claim 1, wherein when the power supply voltage drops due to the interruption of the power supply, the second controller is reset after resetting the first controller. a battery connected to a power terminal of the second controller;
The second controller operates with the power supply voltage supplied from the capacitor or the power supply voltage supplied from the battery, and when the power supply is stopped for a predetermined time, the write operation of the memory by the first controller is performed. 3. The information processing apparatus according to claim 1, wherein the information processing apparatus is prohibited. The information processing apparatus according to any one of claims 1 to 3, wherein the memory is an electrically rewritable nonvolatile memory. a mask circuit for masking a write enable state by a write protect signal output to the memory by the first controller according to the write protect signal output by the second controller when the power supply is stopped for a predetermined time; The information processing apparatus according to any one of claims 1 to 4, characterized by: an image forming unit that forms an image;
a capacitor that accumulates electric charge supplied from a power supply;
a first controller operated by a power supply voltage received through the capacitor;
a memory accessed by the first controller;
a second controller that prohibits the write operation of the memory by the first controller when the power supply is stopped for a predetermined time;
An image forming apparatus comprising: A control method for an information processing apparatus having a capacitor for accumulating charges supplied from a power supply, a first controller operated by a power supply voltage received via the capacitor, and a memory accessed by the first controller, comprising: ,
A control method for an information processing apparatus, comprising: prohibiting a write operation of the memory by the first controller when the power supply is stopped for a predetermined time. A control program for an information processing apparatus having a capacitor for accumulating charges supplied from a power supply, a first controller operated by a power supply voltage received via the capacitor, and a memory accessed by the first controller, the program comprising: ,
A control program for an information processing apparatus, which causes a computer to execute processing for prohibiting a write operation of the memory by the first controller when the power supply is stopped for a predetermined time.

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