JP6541750B2 - Electronic device, power control method to control unit of electronic device - Google Patents

Description

  The present invention relates to an electronic device and a method of controlling power to a control unit of the electronic device.

Conventionally, it is known that, in an electronic device to which a plurality of power supply voltages are supplied from a power supply control device, it is necessary to prevent the wraparound of the power supply when the power of the entire system is turned on and off. Moreover, also in a general application specific integrated circuit (ASIC), the specification is such that the IO power supply, the CORE power supply, and a plurality of power supplies are supplied. At that time, in order to avoid a state in which the output of the IO terminal of the ASIC becomes unstable, it is necessary to supply IO power earlier than CORE power at power ON, and disconnect IO power after CORE power at power OFF. It is known that there is.
There is known a technique of controlling power supply timing using a delay circuit in order to protect the timing of a plurality of power supplies in an electronic device or ASIC as described above (Patent Document 1).

  There is also known a technique for monitoring the level of the power supply voltage of the previous stage using a comparator or a reset IC and controlling the power supply of the subsequent stage when the supply timing of the plurality of power supplies exceeds or falls below a predetermined value.

Unexamined-Japanese-Patent No. 2004-266661 Japanese Patent Laid-Open No. 2000-12202

The output of the power supply control circuit for power on and the output of the power supply control circuit for power off are connected to the enable terminal of the power generation circuit of multiple power supplies. Therefore, according to the power status (power ON / OFF) of the electronic device or ASIC, the connection destination of the enable terminal of the power generation circuit is the output of the power control circuit for power ON and the output of the power control circuit for power OFF. Required a selector circuit to switch at Therefore, the configuration of the power supply control circuit as a whole becomes complicated and the cost increases.
The present invention has been made to solve the above-described problems, and an object of the present invention is to control startup and shutdown of a plurality of power supplies required by a control unit of an electronic device with a simple circuit configuration. It is to provide a mechanism that can be done efficiently.

The electronic device of the present invention for achieving the above object has the following configuration.
When a control unit, a first voltage generation unit that generates a first voltage supplied to the control unit from the input voltage when the first activation signal is input, and a second activation signal are input, Second voltage generation means for generating a second voltage supplied to the control unit from an input voltage , and power on control for outputting the first validation signal and the second validation signal according to a power on instruction Means, first blocking means for blocking the input of the first validation signal output from the power on control means to the first voltage generating means, and the second valid signal output from the power on control means According to the second shutoff means for shutting off the input of the activation signal to the second voltage generation means, and the instruction to turn off the power supply , the first shutoff means inputs the first validation signal to the first voltage generation means. The first shutoff signal to shut off is output to the first shutoff means And a second blocking signal to block the input to the second voltage generating means of the second enable signal to said second breaking means, and a power supply OFF control means for outputting to the second shut-off means The power supply ON control means outputs the second activation signal when the first voltage generated by the first voltage generation means to which the first activation signal is input is equal to or higher than a predetermined voltage. The OFF control means has a delay circuit, and uses one of the first blocking signal and the second blocking signal without referring to the first voltage and the second voltage using the delay circuit. the timing of outputting, wherein Rukoto is delayed with respect to the timing of outputting the other of the blocking signal.

  According to the present invention, startup control and shutdown control of a plurality of power sources required by the control unit of the electronic device can be efficiently performed with a simple circuit configuration.

FIG. 1 is a view showing an appearance of an image forming apparatus to which a power control device can be applied. FIG. 2 is a block diagram showing an internal configuration of the image forming apparatus shown in FIG. It is a block diagram explaining the detailed structure of the power supply control part shown in FIG. It is a figure explaining the structure of the switch of the power supply control part shown in FIG. It is a flowchart explaining the control method of a power supply control apparatus. It is a flowchart explaining the control method of a power supply control apparatus. It is a block diagram explaining the structure of the power supply ON control part shown in FIG. It is a timing chart explaining operation of a power ON control part shown in FIG. It is a block diagram explaining the structure of the power supply OFF control part shown in FIG. FIG. 5 is a diagram showing an internal circuit configuration of the discharge circuit shown in FIG. 3; 5 is a timing chart illustrating the operation of the power-off control unit illustrated in FIG. It is a block diagram explaining the composition of a power control device. It is a block diagram explaining the composition of a power control device.

Next, the best mode for carrying out the present invention will be described with reference to the drawings.
<Description of system configuration>
First Embodiment
FIG. 1 is a view showing an appearance of an image forming apparatus to which a power control apparatus according to the present embodiment can be applied. Although the power control device shown in this embodiment can be applied, the electronic apparatus is not limited to the above image forming apparatus, but may be a printing apparatus, an image processing apparatus, a facsimile apparatus, a scanner apparatus, an information processing apparatus, an MFP (Multi Function Printer), etc. Is included. In the present embodiment, an example will be described in which the power supply control device supplies DC power of different potentials to the control unit of the electronic device. Here, the electronic apparatus includes the image forming apparatus, the printing apparatus, the composite image processing apparatus, the facsimile apparatus, the scanner apparatus, and the information processing apparatus.

  In FIG. 1, the image forming apparatus 1 includes a scanner unit 10 which is an image input device, a printer unit 20 which is an image output device, and an operation unit 30 which is a user interface. Furthermore, the image forming apparatus 1 includes a controller unit 40 that controls the entire image forming apparatus, an outlet 3 serving as a supply source for supplying power to the image forming apparatus, and a main switch 50 for supplying power to the image forming apparatus. Configured A power plug 3 is connected to an AC outlet (not shown).

  The scanner unit 10 converts the information of an image into an electrical signal by inputting the reflected light obtained by exposing and scanning an image on a document to a CCD. Furthermore, the scanner unit 10 converts the electrical signal into a luminance signal of R, G, and B, and outputs the luminance signal to the controller unit 40 as image data. A document is set on the tray 102 of the document feeder 101. When the user gives an instruction to start reading from the operation unit 30, the controller unit 40 gives an instruction to read an original to the scanner unit 10. When the scanner unit 10 receives this instruction, the scanner unit 10 feeds documents one by one from the tray 102 of the document feeder 101 to perform a document reading operation. The document reading is configured to perform single-sided and double-sided reading of a document by controlling conveyance of the document according to the reading conditions set from the operation unit.

  The printer unit 20 is an image forming device that forms the image data received from the controller unit 40 on a sheet. In the present embodiment, the image forming method is an electrophotographic method using a photosensitive drum or a photosensitive belt, but the present invention is not limited to this. For example, an ink jet method in which ink is ejected from a minute nozzle array to print on a sheet is also applicable. Further, the printer unit 20 is provided with a plurality of sheet cassettes 201, 202, and 203 which can select different sheet sizes or different sheet orientations. The sheet after printing is discharged to the discharge tray 204. The controller unit 40 is a part that controls the operation of the image forming apparatus 1, and performs data transmission / reception, data conversion, and power control.

FIG. 2 is a block diagram showing an internal configuration of the image forming apparatus shown in FIG. Hereinafter, the power supply process of the image forming apparatus 1 will be described with reference to FIG.
In FIG. 2, first, when the image forming apparatus 1 is turned on, the user turns on the main switch 50 to set the AC power supplied from the power plug 3 to the DC power of a predetermined potential in the power control unit 60. Convert. Thus, the image data is supplied to the scanner unit 10, the printer unit 20, the operation unit 30, and the controller unit 40.
Even when the power of the image forming apparatus 1 is turned off, when the user turns off the main switch 50, the power control unit 60 stops the power to the scanner unit 10, the printer unit 20, the operation unit 30, and the controller unit 40.

When the image forming apparatus 1 performs a printing operation, job data is transferred to the controller unit 40 through the network 2 and temporarily stored in a memory of the controller unit 40. Here, the memory includes a RAM 402 and a hard disk (HDD) 404 which will be described later.
The controller unit 40 converts the stored job data into image data and transfers the image data to the printer unit 20. The printer unit 20 prints the image data received under the control of the controller unit 40 on a recording sheet and discharges it out of the apparatus.

  When the image forming apparatus 1 performs the scan operation, the user sets the document on the scanner unit 10 and then operates the button while referring to the screen of the operation unit 30 to instruct the operation start after setting the scan operation. Do. Under the control of the controller unit 40, the scanner unit 10 optically reads an original and converts it into image data. And the converted image data. After being temporarily stored in the memory in the controller unit 40, the data is transferred to the destination specified by the operation unit 30 in advance.

  When the image forming apparatus 1 performs a copy operation, the user sets a document in the scanner unit 10 and then operates the button while referring to the screen of the operation unit 30 to set the copy operation and then start the copy operation. To indicate. Under the control of the controller unit 40, the scanner unit 10 optically reads an original and converts it into image data. After the converted image data is temporarily stored in the memory of the controller unit 40, the controller unit 40 converts the data format usable by the printer unit 20, and the printer unit 20 prints the image data on a recording sheet. Discharge to the outside of the device.

FIG. 3 is a block diagram for explaining the detailed configuration of the power control unit 60 shown in FIG.
In FIG. 3, the power control unit 60 includes a main switch 50, a power plug 3 serving as a power supply source, and an ACDC conversion unit 600 that converts AC power input from the power plug 3 into DC power. Further, the power control unit 60 includes a first power generation unit 601 that generates a plurality of power supply voltages, a second power generation unit 602, and a third power generation unit 603.
Further, the power control unit 60 includes a power on control unit 611 that controls power on of the first power generation unit 601, the second power generation unit 602, and the third power generation unit 603. Furthermore, the power control unit 60 includes a power OFF control unit 631 that controls power OFF, and SW 621, SW 622, and SW 623 for executing power OFF. Furthermore, the power control unit 60 includes a discharge circuit 624 for controlling the fall time of the power-off of the first power generation unit 601, the second power generation unit 602, and the third power generation unit 603, a discharge circuit 625, and a discharge circuit. 626 is provided.
Here, the first power generation unit 601, the second power generation unit 602, and the third power generation unit 603 are configured of a DCDC converter with an enable control function. Also, SW 621, SW 622, and SW 623 for performing the power-off have a hard wire configuration of switching FETs 648, 649, and 650 as shown in FIG. 4.
The SW 621, SW 622, and SW 623 have a function of disabling the enable signals EN 1, EN 2, and EN 3 of the first power generation unit 601, the second power generation unit 602, and the third power generation unit 603. As described above, in the present embodiment, the power-off control unit 631 performs the power-off instruction with different delay times in association with the first power generation unit 601, the second power generation unit 602, and the third power generation unit 603. The details will be described later with reference to FIG.
The discharge circuit 624, the discharge circuit 625, and the discharge circuit 626 have a discharge function of causing the power supplies V1, V2, and V3 to fall at high speed. Since the scanner unit 10, the printer unit 20, the operation unit 30, and the controller unit 40 to which the power supplies V1, V2, and V3 are supplied have capacitor components, the capacitor components are charged when the power is turned on. .
In order to quickly lower the power supplies V1, V2, and V3 after the power-off, it is necessary to remove the charges in the capacitor component. Therefore, the discharge circuit 624, the discharge circuit 625, and the discharge circuit 626 are configured as the output of each power generation unit. Here, enable control at power ON and OFF of the power generation unit of each power source can be realized by the hard wire configuration by the switching FETs 648, 649, 650 because the control method of power ON and the control method of power OFF are different. It is composed of As a result, regardless of whether the power-on control unit 611 controls the enable signals EN1, EN2, EN3 to be valid / invalid, the power-off control unit 631 forcibly disables the enable signals EN1, EN2, EN3. Because
Therefore, a simple circuit configuration as in this embodiment can be realized, which does not require a selector circuit as described in the prior art.

  The plurality of power supplies V2 and V3 generated by the second power generation unit 602 and the third power generation unit 603 are respectively supplied to the CPU 401 in the controller 40. In fact, other power supplies other than the power supplies V2 and V3 generated by the second power generation unit 602 and the third power generation unit 603 are also supplied to the scanner unit 10, the printer unit 20, the operation unit 30, the controller unit 40, and the like. Be done. Here, to simplify the description, power supply to the CPU 401 in the controller 40 will be described.

  The controller 40 is electrically connected to the scanner unit 10 and the printer unit 20. On the other hand, the controller 40 is connected to a PC, an external device, and the like via the LAN 2 and the like. This makes it possible to input and output image data and device information.

  The CPU 401 generally controls access to various connected devices based on a control program and the like stored in the ROM 403, and also centrally controls various processes performed inside the controller. A RAM 402 is a system work memory for the CPU 401 to operate, and is also a memory for temporarily storing image data. The RAM 402 is configured of an SRAM that holds the stored content even after the power is turned off and a DRAM in which the stored content is erased after the power is turned off. The ROM 403 stores a boot program of the apparatus. An HDD 404 is a hard disk drive and can store system software and image data.

The operation unit I / F 405 is an interface unit for connecting the system bus 407 and the operation unit 30. The operation unit I / F 405 outputs image data to be displayed on the operation unit 30 from the system bus 407 to the reception operation unit 30, and outputs information input from the operation unit 30 to the system bus 407.
A LAN controller 406 is connected to the LAN 2 and the system bus 407 to control input / output of information.

  An image processing unit 409 is for performing image processing, can read out image data stored in the RAM 402, and can perform image processing such as enlargement or reduction such as JPEG or JBIG and color adjustment.

  The scanner image processing unit 410 corrects, processes, and edits image data received from the scanner unit 10 via the scanner I / F 411. The scanner image processing unit 410 determines whether the received image data is a color document or a black-and-white document, a text document or a photo document, and the like. Then, the determination result is attached to the image data. Such accompanying information is referred to as attribute data.

  The printer image processing unit 412 performs image processing on the image data while referring to the attribute data attached to the image data. The image data after the image processing is output to the printer unit 20 via the printer I / F 413.

Hereinafter, the power control process flow when the main switch 50 is turned on or off will be described.
FIG. 5 is a flow chart for explaining a control method of the power control device showing the present embodiment. This example is an example of the power ON process in the power control unit 60. Each step is realized by sequence control performed by hardware in the power supply control unit 60. Hereinafter, the power control process for starting up each power generation unit will be described in detail while confirming that each power generation unit has reached a predetermined potential after the main switch 50 is turned on.
The ACDC conversion unit 600 converts AC power from the outlet 3 into DC power, and supplies power to the power ON control unit 611, the power OFF control unit 631, and the first power generation unit 601. The main switch 50 is turned on (S101). Thereafter, in response to the POWER_ON signal becoming valid, the power-on control unit 611 enables the enable signal EN1 of the first power generation unit 601 (S102). The first power supply generation unit 601 raises the power supply V1 from the input power supply from the ACDC conversion unit 600 and the enable signal EN1 from the power-on control unit 611. The power supply V1 is an input power supply of the second power generation unit 602 and the third power generation unit 603.

  The power supply V1 is also input to the power on control unit 611. The power supply ON control unit 611 monitors the voltage value of the power supply V1 from the first power supply generation unit 601, and detects that the power supply V1 has exceeded a predetermined voltage value set in advance (S103). The unit enable signal EN2 is enabled (S104). The second power supply generation unit 602 generates and outputs a power supply V2 from the input power supply V1 from the first power supply generation unit 601 and the enable signal EN2 from the power-on control unit 611.

  The power supply V2 is input to the power on control unit 611. The power-on control unit 611 monitors the voltage value of the power supply V2, and detects that the power supply V2 has exceeded the predetermined voltage value set in advance (S105), and enables the enable signal EN3 of the third power generation unit 603. (S106). The third power supply generation unit 603 generates a power supply V3 from the power supply V1 from the first power supply generation unit 601 and the enable signal EN3 from the power-on control unit 611, and outputs the power supply V3.

FIG. 6 is a flow chart for explaining the control method of the power control device showing the present embodiment. This example is an example of the power OFF process in the power control unit 60. Each step is realized by sequence control performed by hardware in the power supply control unit 60. Hereinafter, the power control process when the main switch 50 is turned off will be described in detail.
When the main switch 50 is turned off and the delay time Td3 elapses (S201), the power-off control unit 631 turns off the SW 623 (power-off instruction) in response to the invalidation of the POWER_ON signal (S202). Thereby, the enable signal EN3 of the third power generation unit 603 is invalidated. Then, the output of the power supply V3 of the third power generation unit 603 is stopped (S203). As a result, the third power generation unit 603 transitions to the power off state.

  Similarly, when the main switch 50 is turned off and the delay time Td2 elapses (S204), the power-off control unit 631 turns off the SW 622 (S205). Thus, the enable signal EN2 of the second power generation unit 603 is invalidated, and the output of the power supply V2 of the second power generation unit 602 is stopped (S206). When the main switch 50 is turned off and the delay time Td1 elapses (S207), the power-off control unit 631 turns off the SW 621 (S208). Thereby, the enable signal EN1 of the first power generation unit 601 is invalidated, and the output of the power supply V1 of the first power generation unit 601 is stopped (S209).

FIG. 7 is a block diagram for explaining the configuration of the power ON control unit 611 shown in FIG.
In FIG. 7, the power ON control unit 611 includes a buffer 613, a comparator 614, a comparator 615, a resistive voltage dividing circuit 616 for generating the reference voltage Vref1, and a resistive voltage dividing circuit 617 for generating the reference voltage Vref2. Ru.

As described above, when the main switch 50 is turned on, the power-on control unit 611 detects that the main switch 50 is turned on. The detected signal is output via the buffer 613 with the enable signal EN1 of the first power generation unit 601 set to Hi.
The comparator 614 inputs the power supply V1 from the first power generation unit 601 to the + input terminal, and inputs a predetermined reference voltage Vref1 set in advance to the − input terminal.

  The reference voltage Vref1 is generated by dividing the power supply V0 by the resistance voltage dividing circuit 616. When the power supply V1 exceeds the reference voltage Vref1, the enable signal EN2 of the second power generation unit 602 is set to Hi and is output.

  Here, a value for determining that the power supply V1 has risen is set to the reference voltage Vref1. Similarly, the comparator 615 inputs the voltage of the input power supply V2 from the second power supply generation unit to the + input terminal, and inputs a predetermined reference voltage Vref2 set in advance to the − input terminal of the comparator. The reference voltage Vref2 is generated by dividing the power supply V0 by the resistor divider circuit 617.

  When the power supply V2 exceeds the reference voltage Vref2, the enable signal EN3 of the second power generation unit 603 is set to Hi and is output. Thus, when the power is on, the power on sequence is generated using the comparator and the reference voltage Vref. This prevents the power generation unit of the subsequent stage of the failed power generation unit from outputting the power when the power generation unit does not output power because an electrical failure occurs in any of the plurality of power generation units. In order to If the power generation unit downstream of the failed power generation unit outputs a power, there is a possibility that the current loop described in the background art may occur.

FIG. 8 is a timing chart for explaining the operation of the power ON control unit 611 shown in FIG. Hereinafter, the operation of the power ON control unit 611 in accordance with the control flow of power ON shown in FIG. 5 will be described.
The power sources V1, V2, and V3 output from the first power generation unit 601, the second power generation unit 602, and the third power generation unit 603 start rising when the enable signals EN1, EN2, and EN3 become Hi. At that time, rise times Tr1 and Tr2 are reached until the reference voltages Vref1 (dividing circuit 616), Vref2 (dividing circuit 617) and Vref3 (618) are reached to determine that the power supplies V1, V2 and V3 have risen. , Tr3 occurs.
That is, when the main switch 50 is turned on, the power supply V1 rises after Tr1, the power supply V2 rises after Tr1 + Tr2, and the power supply V3 rises after Tr1 + Tr2 + Tr3.

FIG. 9 is a block diagram for explaining the configuration of the power-off control unit 631 shown in FIG. Hereinafter, the operation of the power-off control unit 613 according to the control flow of power-on illustrated in FIG. 6 will be described. This example is an example in which the delay circuit is configured by an analog circuit from a resistor and a capacitor. Here, as for the delay time, in FIG. 9, the power OFF controller 631 has inverters 632, AND gate circuits 633, 634, 635, delay circuits 636, 637, 638 consisting of a resistor R and a capacitor C and a Schmitt buffer 639. , 640, 641. Here, the delay circuit 636 is composed of a resistor 642 and a capacitor 645. The delay circuit 637 is composed of a resistor 643 and a capacitor 646. Furthermore, the delay circuit 638 is composed of a resistor 644 and a capacitor 647. The delay time for turning off each of the delay circuits 636 to 638 is determined by the respective resistors 642 and 645, the resistor 643 and the capacitor 646, and the resistor 644 and the capacitor 647.

  As described above, when the main switch 50 is turned off, the power-off control unit detects that the POWER_ON signal is low and the main switch 50 is turned off. The POWER_ON signal is input to the inverter 632 to output a POWER_OFF signal that is the logic inversion of the POWER_ON signal.

  The AND gate circuit 633 is a 2-input 1-output logic circuit. The POWER_OFF signal is input to one of the two inputs. The other one of the two inputs receives the signal DELAY1 obtained by delaying the POWER_OFF signal by the delay circuit 636 and the Schmitt buffer 639. At this time, the delay time Td1 for POWER_OFF of DELAY1 is determined from the resistance value of the resistor R642 of the delay circuit 636 and the capacitance value of the capacitor C (645). The AND gate circuit 633 outputs an OFF1 signal which is an AND of POWER_OFF and DELAY1.

  The OFF1 signal is input to the SW 621 as a control signal for disabling the enable signal EN1 of the first power generation unit 601. As a result, the output power source V1 can start falling at a desired timing. Furthermore, the OFF1 signal is also input to the discharge circuit 624 as a control signal for completing the fall of the output power source V1 of the first power source generation unit 601 within a predetermined time. The AND gate circuit 634 is also a 2-input 1-output logic circuit. The POWER_OFF signal is input to one of the two inputs. A signal DELAY 2 obtained by delaying the OFF 1 signal by the delay circuit 637 and the Schmitt buffer 640 is input to the other one of the two inputs.

  At this time, the delay time Td2 for POWER_OFF of DELAY2 is determined from the resistance value of the resistor R643 of the delay circuit 637 and the capacitance value of the capacitor C646. The AND gate circuit 634 outputs an OFF2 signal which is an AND of POWER_OFF and DELAY2. The OFF2 signal is input to the SW 622 as a control signal for disabling the enable signal EN2 of the second power generation unit 602. As a result, the output power supply V2 can be started to fall at a desired timing. Furthermore, the OFF2 signal is also input to the discharge circuit 625 as a control signal for completing the fall of the output power source V2 of the second power source generation unit 602 within a predetermined time. The AND gate circuit 635 is also a 2-input 1-output logic circuit. The POWER_OFF signal is input to one of the two inputs. A signal DELAY3 obtained by delaying the OFF2 signal by the delay circuit 638 and the Schmitt buffer 641 is input to the other one of the two inputs.

  At this time, the delay time Td3 for POWER_OFF of DELAY3 is determined from the resistance value of the resistor R644 of the delay circuit 638 and the capacitance value of the capacitor C647. The AND gate circuit 635 outputs an OFF3 signal which is an AND of POWER_OFF and DELAY3. The OFF3 signal is input to the SW 623 as a control signal for disabling the enable signal EN3 of the third power generation unit 603. Thereby, the output power supply V3 can be started to fall at a desired timing. Furthermore, the OFF3 signal is also input to the discharge circuit 626 as a control signal for completing the fall of the output power source V3 of the third power source generation unit 603 within a predetermined time.

  Thus, when the power is turned off, the power off sequence is generated using the delay circuit and the AND circuit. This is because a case where an electrical failure occurs in any of the plurality of power generation units and the power does not stop is very rare as compared with the above-described power-on case. It is assumed that an electrical failure occurs in a power generation unit of any of the plurality of power generation units, and a state in which the power is not shut off occurs. In this case, if the first power generation unit 601 can reliably turn off the power, the second power generation unit 602 and the third power generation unit 603 are also turned off, so generation of a long-term sneak current can be avoided.

FIG. 10 is a diagram showing an internal circuit configuration of the discharge circuits 624, 625, 626 shown in FIG.
In FIG. 10, each discharge circuit is composed of FETs 645 to 647 for discharging the output power supplies V1 to V3 and resistors 642 to 644 for adjusting the fall times Tf1 to Tf3 of the output power supplies V1 to V3. As the resistance values of the resistors 642, 643 and 644 become smaller, it becomes possible to shorten the fall times Tf1, Tf2 and Tf3.

FIG. 11 is a timing chart for explaining the operation of the power OFF control unit 631 shown in FIG. Hereinafter, the operation of the power-off control unit 631 in accordance with the control flow of power-off illustrated in FIG. 6 will be described.
In FIG. 11, the power supplies V1, V2, and V3 output from the first power generation unit 601, the second power generation unit 602, and the third power generation unit 603 are SW1 62, SW 622, and SW 623 according to OFF1 signal, OFF2 signal, and OFF3 signal. Is turned off. As a result, the enable signals EN1, EN2, and EN3 become low and start falling.

At that time, the timing at which the power supplies V1, V2, and V3 start to fall is after Td1, Td2, and Td3 from POWER_OFF, respectively. Here, the power supplies V1, V2 and V3 are supplied to the scanner unit 10, the printer unit 20, the operation unit 30, and the controller unit 40, but in order to prevent the wraparound of the power supplies, And in reverse order.
As a result, the power supplies V3, V2, and V1 are turned off in this order. Therefore, the power supply V3 starts falling after the power supply V3 has completed falling. Then, after the power supply V2 has completed falling, the power supply V1 starts falling. Thus, the resistance values of the resistors 642, 643, and 644 and the capacitance values of the capacitors 645, 646, and 647 are set so that the delay times Td3 to Td1 and the fall times Tf1 to Tf3 become Td3 + Tf3 <Td2 + Tf2 <Td1. Set
From the above, it becomes possible to control a plurality of power ON / OFF with a simple circuit configuration which does not require a power supply control circuit for power ON and a selector circuit for switching the power control circuit for power OFF.

Second Embodiment
In this embodiment, in the power supply ON control unit 611 shown in FIG. 4 in the first embodiment, a balance formed by a reset IC instead of the voltage dividing circuit and the comparator is shown. Furthermore, a case is shown where the power supply OFF control unit 631 shown in FIG. 9 in the first embodiment is configured by flip-flop circuits instead of the delay circuit and the Schmitt buffer. Description of the same configuration as the hardware described in the first embodiment is omitted.

FIG. 12 is a block diagram for explaining the configuration of the power supply control device showing the present embodiment. This example is another configuration example of the power ON control unit 651 shown in FIG.
In FIG. 12, the power on control unit 651 includes a buffer 653, a reset IC 654, and a reset IC 655. When the main switch is turned on, the power on control unit 651 detects that the main switch is turned on.

  The detected signal is output via the buffer 613 with the enable signal EN1 of the first power generation unit 601 set to Hi. The reset IC 654 inputs the power supply V1 from the first power generation unit 601 to the input terminal, and inputs a predetermined reference voltage Vref1 set in advance to the reference voltage terminal. The reference voltage Vref1 is generated by dividing the power supply V0 by the resistor divider circuit 656. When the power supply V1 exceeds the reference voltage Vref1, the enable signal EN2 of the second power generation unit 602 is set to Hi and is output. Here, a value for determining that the power supply V1 has risen is set to the reference voltage Vref1.

  Similarly, the reset IC 655 inputs the voltage of the input power supply V2 from the second power supply generation unit to the input terminal, and inputs a predetermined reference voltage Vref2 set in advance to the reference voltage terminal. The reference voltage Vref2 is generated by dividing the power supply V0 by the resistor divider circuit 657. When the power supply V2 exceeds the reference voltage Vref2, the enable signal EN2 of the second power generation unit 603 is set to Hi and is output.

FIG. 13 is a block diagram for explaining the configuration of the power control apparatus showing the present embodiment. The present example is another configuration example of the power OFF control unit 661 shown in FIG. This example is an example in which the delay circuit is configured by a flip flop.
In FIG. 13, the power-off control unit 661 includes an inverter 662, AND gate circuits 663, 664 and 665, flip flop circuits 673, 674 and 675, and a clock generator 676. When the main switch 50 is turned off, the power-off control unit detects that the POWER_ON signal is low and the main switch 50 is turned off. Here, a common clock is input from the clock generator 676 to each of the flip-flop circuits 673, 674, 675. The gate outputs of the AND gate circuits 663 and 664 are input to the D inputs of the flip flop circuits 674 and 675, respectively.

  The POWER_ON signal is input to the inverter 662, and outputs the POWER_OFF signal that is the logic inversion of the POWER_ON signal. The AND gate circuit 663 is a 2-input 1-output logic circuit. The POWER_OFF signal is input to one of the two inputs. A signal DELAY1 obtained by delaying the POWER_OFF signal by the flip-flop circuit 673 is input to the other one of the two inputs. At this time, the flip-flop circuit 673 synchronizes the input POWER_OFF signal with the clock signal generated by the clock generator 676 and outputs a clock synchronization signal of the POWER_OFF signal.

  Therefore, the delay time Td1 for POWER_OFF of DELAY1 is determined by the period of one pulse of the clock generated by the clock generator 676. The AND gate circuit 663 outputs an OFF1 signal which is an AND of POWER_OFF and DELAY1. The OFF1 signal is input to the SW 621 as a control signal for disabling the enable signal EN1 of the first power generation unit 601. As a result, the output power source V1 can start falling at a desired timing.

  Furthermore, the OFF1 signal is also input to the discharge circuit 624 as a control signal for completing the fall of the output power source V1 of the first power source generation unit 601 within a predetermined time. Similarly, the AND gate circuit 664 and the AND gate circuit 665 are two-input one-output logic circuits. The POWER_OFF signal is input to one of the two inputs. Signals DELAY2 and DELAY3 obtained by delaying the DELAY1 signal and DELAY2 signal by flip-flop circuits 674 and 675 are input to the other one of the two inputs.

  At this time, the flip-flop circuits 673 and 674 synchronize the input POWER_OFF signal with the clock signal generated by the clock generator 676 and output a clock synchronization signal of the POWER_OFF signal. The OFF2 signal and the OFF3 signal which are output signals of the AND gate circuit 664 and the AND gate circuit 665 are SW622 as a control signal for invalidating the enable signals EN2 and EN3 of the second power generation unit 602 and the second power generation unit 603, It is input to the SW 623. As a result, the output power supplies V2 and V3 can be started to fall at a desired timing.

  Furthermore, the OFF2 signal and the OFF3 signal are used as a control signal for completing the fall of the output power supplies V2 and V3 of the second power supply generation unit 602 and the second power supply generation unit 603 within a predetermined time, and the discharge circuit 625 and discharge circuit 626. Is also input.

  Each process of the present invention can also be realized by executing software (program) acquired via a network or various storage media with a processing device (CPU, processor) such as a personal computer (computer).

  The present invention is not limited to the above embodiments, and various modifications (including organic combinations of the respective embodiments) are possible based on the spirit of the present invention, which are excluded from the scope of the present invention is not.

1 Image forming apparatus 60 power control unit

Claims (11)

A control unit,
First voltage generation means for generating a first voltage supplied to the control unit from an input voltage when a first validation signal is input ;
A second voltage generation unit configured to generate a second voltage supplied to the control unit from an input voltage when a second validation signal is input ;
Power-on control means for outputting the first validation signal and the second validation signal according to a power-on instruction;
First blocking means for blocking the input to the first voltage generation means of the first validation signal output from the power ON control means;
Second blocking means for blocking the input to the second voltage generating means of the second validation signal output from the power ON control means;
According to the instruction to turn off the power, a first shutoff signal that causes the first shutoff means to shut off the input of the first validation signal to the first voltage generation means is output to the first shutoff means, and Power supply OFF control means for outputting, to the second blocking means, a second blocking signal for causing the second blocking means to block input of the second validation signal to the second voltage generating means ;
The power ON control means outputs the second activation signal when the first voltage generated by the first voltage generation unit to which the first activation signal is input is equal to or higher than a predetermined voltage.
The power supply OFF control means has a delay circuit, and using the delay circuit, without referring to the first voltage and the second voltage, one of the first shutoff signal and the second shutoff signal. the timing for outputting the electronic apparatus, wherein Rukoto is delayed with respect to the timing of outputting the other of the blocking signal. The delay circuit includes a capacitor and a resistor,
The electronic device according to claim 1, wherein the timing is based on a time determined by a capacitance of the capacitor and a resistance value of the resistor. The power supply OFF control means, by said first enable signal blocks the input to the first voltage generating means, to stop thereby generating said first voltage to said first voltage generating means, that The electronic device according to claim 1, characterized in that Said first blocking means is a switch for switching the shut-off and the first enable signal input to the first voltage generating means, the power supply OFF control means outputs the first cut-off signal the electronic device according to claim 3 by OFF the switch, which cuts off the first input of the enable signal to the first voltage generating means, characterized in that. The power ON control means includes a comparator for comparing the first voltage and the predetermined voltage,
The power ON control means outputs the second validation signal to be input to the second voltage generation means when it is determined by the comparator that the first voltage has reached the predetermined voltage. The electronic device according to claim 1.   The electronic device according to claim 1, wherein the electronic device has at least one of a copy function, a print function, a scan function, and a fax function.   The said control part is CPU, The electronic device in any one of the Claims 1 thru | or 6 characterized by the above-mentioned. The electronic device according to any one of claims 1 to 7, wherein an input voltage of the first voltage generation means and an input voltage of the second voltage generation means are equal . The electronic device according to any one of claims 1 to 7, wherein an input voltage of the first voltage generation unit and an input voltage of the second voltage generation unit are different. 10. The electronic device according to any one of claims 1 to 9, wherein the power-off control means does not output the first shut-off signal and the second shut-off signal according to the power-on instruction. machine. When a control unit, a first voltage generation unit that generates a first voltage supplied to the control unit from the input voltage when the first activation signal is input, and a second activation signal are input, A second voltage generation unit configured to generate a second voltage supplied to the control unit from an input voltage ;
Power-on control means for outputting the first validation signal and the second validation signal according to a power-on instruction;
First blocking means for blocking the input to the first voltage generation means of the first validation signal output from the power ON control means;
Second blocking means for blocking the input to the second voltage generating means of the second validation signal output from the power ON control means;
According to the instruction to turn off the power, a first shutoff signal that causes the first shutoff means to shut off the input of the first validation signal to the first voltage generation means is output to the first shutoff means, and A control unit of an electronic device comprising: a power-off control means for outputting to the second blocking means a second blocking signal for causing the second blocking means to block the input of the second validation signal to the second voltage generation means; Power control method, and
The power ON control means outputs the second activation signal when the first voltage generated by the first voltage generation unit to which the first activation signal is input is equal to or higher than a predetermined voltage. Control process,
The power supply OFF control means has a delay circuit, and using the delay circuit, without referring to the first voltage and the second voltage, one of the first shutoff signal and the second shutoff signal. the timing for outputting the power control method of the control unit of the electronic apparatus; and a second control step of Ru is delayed with respect to the timing of outputting the other of the blocking signal.

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