JP2023097849A - Current resonance dc/dc converter - Google Patents

Abstract

To provide a current resonance DC/DC converter capable of outputting required DC power while suppressing peak current below an allowable current value even when input voltage is low.SOLUTION: A current resonance DC/DC converter 10A comprises: a secondary circuit 12 including a boost circuit; and a storage unit 14 for storing a lower limit value of drive frequency and a boosting ratio determined in advance so that a current flowing a primary circuit 11 and the secondary circuit 12 does not exceed an allowable current value and an output power of the secondary circuit 12 is maximized, as a lower limit drive frequency and an optimum boosting ratio for each input voltage V1. A control unit 13 controls the primary circuit 11 and the secondary circuit 12 so that the boosting ratio coincides with an optimum boosting ratio corresponding to the input voltage V1 and the drive frequency does not fall below the lower limit drive frequency corresponding to the DC voltage V1 when stepping up the input voltage V1 by operating the boost circuit, to output from the secondary circuit 12.SELECTED DRAWING: Figure 1

Description

The present invention relates to a current resonant DC/DC converter with a boost function.

A device called V2H (Vehicle to Home) that extracts DC power from an on-board battery for driving electric vehicles such as electric vehicles (EVs) and plug-in hybrid vehicles (PHEVs) is usually installed in the vehicle. It includes a bidirectional DC/DC converter that boosts the DC voltage output by the battery (hereinafter also referred to as “input voltage”), and a bidirectional DC/AC inverter that converts the boosted DC voltage into AC voltage. Among these, as a bidirectional DC/DC converter, a current resonance type DC/DC converter of the CLLC system suitable for miniaturization and high efficiency is attracting attention.

A V2H device conforming to the CHAdeMO standard should support a wide range of input voltages from 150V to 450V. However, since the CLLC type current resonance type DC/DC converter must output a predetermined voltage in bidirectional operation, the degree of freedom of the transformer transformation ratio is low, and the LLC type current resonance type DC/DC converter alone has a low degree of freedom. and a buck-boost chopper. Therefore, when the input voltage is relatively low, the CLLC type current resonance type DC/DC converter may not be able to output the DC power required by the bidirectional DC/AC inverter. That is, the CLLC type current resonance type DC/DC converter cannot handle a wide range of input voltages.

As one method for solving this problem, conventionally, it has been studied to provide a boost function to the secondary side circuit of an LLC type current resonance type DC/DC converter. For example, in Non-Patent Document 1, two switching elements S _S2 and S _S3 are provided in the secondary side rectifier circuit of an LLC type current resonance type DC/DC converter, and the delay time T _D ( = T ₀ - T ₁ , T ₃ - T ₄ ) to achieve a boost (more powerful boost). In the current resonance type DC/DC converter described in Non-Patent Document 1, the boost rate T _D−N (=the ratio of the delay time T _D in one drive cycle T _S ) and the drive frequency F of the primary side circuit The boost rate M is represented by a function with as a parameter (especially see Fig. 2).

Yungtaek Jang, et al., “Implementation of 3.3-kW GaN-Based DC-DC Converter for EV On-Board Charger with Series-Resonant Converter that Employs Combination of Variable-Frequency and Delay-Time Control”, Proc. of APEC2016, pp.1292-1299

However, in this conventional LLC type current resonance type DC/DC converter, in order to obtain a desired step-up ratio M, what is the combination of the boost ratio T _D−N and the drive frequency F among the infinite combinations that exist? It is not decided whether to select for For this reason, in this current resonance type DC/DC converter, as a result of setting the boost rate too high or driving frequency F too low, the resonance current (peak current) flowing in the primary side circuit and the secondary side circuit is reduced in advance. Sometimes, the specified allowable current value was exceeded.

The present invention has been made in view of the above circumstances, and is capable of outputting the required large DC power while suppressing the peak current below the allowable current value even when the input voltage is relatively low. An object of the present invention is to provide a current resonant DC/DC converter that supports a wide range of input voltages.

In order to solve the above problems, a current resonant DC/DC converter according to the present invention includes a primary side circuit configured by a bridge circuit including a plurality of switching elements, a boost circuit and a rectifier circuit including a plurality of switching elements. a current resonance circuit including a resonance coil and a resonance capacitor; a transformer provided between the primary side circuit and the secondary side circuit; a switching element forming the primary side circuit; and a control unit for controlling on/off of switching elements constituting a secondary circuit, wherein the current flowing through the primary circuit and the secondary circuit does not exceed a predetermined allowable current value. and the lower limit value of the driving frequency of the switching element constituting the primary circuit and the boost rate of the boost circuit, which are determined in advance so as to maximize the power output from the secondary circuit, are set in the primary circuit. The control unit boosts the DC voltage input to the primary side circuit by the boost operation of the boost circuit and boosts the secondary voltage. When outputting from the side circuit, the primary side circuit is set so that the boost rate approaches the optimum boost rate corresponding to the DC voltage and the driving frequency does not fall below the lower limit driving frequency corresponding to the DC voltage. It is configured to control ON/OFF of the switching element and the switching element forming the secondary side circuit.

In this configuration, the driving frequency is such that the current (peak current) flowing through the primary circuit and the secondary circuit does not exceed a predetermined allowable current value, and the power output from the secondary circuit is maximized. The lower limit value (lower limit driving frequency) and the boost rate (optimum boost rate) for each DC voltage input to the primary side circuit are determined in advance by simulation, actual machine evaluation, etc., and the control unit controls the primary side according to this It controls the circuit and the secondary circuit. Therefore, according to this configuration, even when the input voltage is low, it is possible to output the required large DC power from the secondary side circuit while suppressing the peak current to the allowable current value or less.

In order to reliably output the required DC power from the secondary side circuit, the control section of the DC/DC converter boosts the DC voltage input to the primary side circuit by a boost operation, and sets the drive frequency in advance. After increasing the boost rate from zero to the optimum boost rate corresponding to the DC voltage while maintaining the predetermined upper limit drive frequency, the drive frequency is lowered toward the lower limit drive frequency corresponding to the DC voltage. It is preferable to be configured as follows.

The control unit of the DC/DC converter increases the drive frequency to the upper limit drive frequency while maintaining the boost rate at the optimum boost rate when completing the boost operation of the DC voltage input to the primary side circuit. After that, the boost rate may be reduced to zero.

Further, the control unit of the DC/DC converter changes the drive frequency in a state where the boost rate approaches the optimum boost rate corresponding to the DC voltage input to the primary side circuit, and outputs the voltage from the secondary side circuit. It may be configured to control ON/OFF of the switching element forming the primary side circuit and the switching element forming the secondary side circuit so that the power supplied becomes the desired output power.

According to the present invention, even when the input voltage is relatively low, it is possible to output the required large DC power while suppressing the peak current below the allowable current value, and is compatible with a wide range of input voltage. A DC/DC converter can be provided.

1 is a circuit diagram of a DC/DC converter according to an embodiment of the invention; FIG. It is a block diagram which shows the usage aspect of the DC/DC converter based on an Example. FIG. 4 is a diagram showing control timings of switching elements constituting the DC/DC converter according to the embodiment, in which (A) is an example of control timing when boosting is not performed, and (B) is an example of control timing when boosting is performed; It is a figure which shows an example. 3A is a diagram showing the current paths of the DC/DC converter according to the embodiment, (A) is the current path in period 1-1 of FIG. 3B, (B) is the current path in period 1-2, (C ) is a diagram showing a current path in period 1-3. 3A is a diagram showing the current paths of the DC/DC converter according to the embodiment, where (A) is the current path in period 2-1 of FIG. 3B, (B) is the current path in period 2-2, (C ) is a diagram showing current paths in period 2-3. FIG. 4 is a diagram showing the relationship between drive frequency, output voltage and boost rate in the DC/DC converter according to the example; FIG. 4 is a flow chart showing a start-up process executed by the controller of the DC/DC converter according to the embodiment; FIG. 4 is a flowchart showing normal processing and termination processing executed by the control unit of the DC/DC converter according to the embodiment after starting processing; FIG. 4 is a schematic diagram showing an outline of start-up processing executed by the controller of the DC/DC converter according to the embodiment; It is a circuit diagram of a DC/DC converter according to a first modification of the present invention. FIG. 4 is a circuit diagram of a DC/DC converter according to a second modified example of the invention; FIG. 11 is a circuit diagram of a DC/DC converter according to a third modified example of the invention;

Hereinafter, embodiments of a current resonance type DC/DC converter according to the present invention will be described with reference to the accompanying drawings.

[Example]
FIG. 1 shows a current resonant DC/DC converter 10A according to an embodiment of the invention. The DC/DC converter 10A is a CLLC type DC/DC converter that operates bidirectionally, and as shown in FIG. The V2H device 110 mainly converts the DC power of the on-vehicle battery 100 for driving the electric vehicle into predetermined AC power and outputs it to the load 130, and converts the AC power of the commercial power system 140 into the predetermined DC power. A charging operation of converting and outputting to the vehicle-mounted battery 100 can be performed.

In the discharge operation, the DC/DC converter 10A boosts the DC voltage output by the vehicle battery 100, that is, the voltage V1 appearing at the primary side input/output terminals T1 and T1′, and converts the boosted DC voltage, that is, the voltage V2. Output from the secondary side input/output terminals T2 and T2'. On the other hand, in the charging operation, the DC/DC converter 10A steps down the DC voltage output by the bidirectional DC/AC inverter 120, that is, the voltage V2 appearing at the secondary side input/output terminals T2 and T2', and A voltage, that is, a voltage V1 is output from the primary side input/output terminals T1 and T1'.

The DC/DC converter 10A includes a primary side circuit 11 configured by a bridge circuit including a plurality of switching elements, a secondary side circuit 12 configured by a boost circuit and a rectifier circuit including a plurality of switching elements, and a resonance coil. a current resonance circuit including L1, L2 and resonance capacitors C9 and C10; a transformer TR provided between a primary circuit 11 and a secondary circuit 12; and a control unit 13 for controlling ON/OFF of switching elements forming the side circuit 12 .

The primary side circuit 11 includes a first switching element Q1, a second switching element Q2, a third switching element Q3, and a fourth switching element Q4. The first switching element Q1 constitutes the upper arm of the first leg, and the second switching element Q2 constitutes the lower arm of the first leg. The third switching element Q3 constitutes the upper arm of the second leg, and the fourth switching element Q4 constitutes the lower arm of the second leg. A connection point of the first switching element Q1 and the second switching element Q2 is connected to one end of the primary winding of the transformer TR via the resonance capacitor C9 and the resonance coil L1, and is connected to the third switching element Q3 and the fourth switching element Q4. is connected to the other end of the primary winding.

The resonance coil L1 may be the leakage inductance of the transformer TR, or may be a separate coil. Also, the resonance coil L1 may be a combination of the leakage inductance and another coil.

The first to fourth switching elements Q1 to Q4 are turned on/off (switched) under the control of the control section 13. FIG. As the first to fourth switching elements Q1 to Q4, power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors), silicon power MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors), and silicon carbide power MOSFETs are used. can be used.

First to fourth diodes D1 to D4 are connected in anti-parallel to the first to fourth switching elements Q1 to Q4, respectively. The first to fourth diodes D1 to D4 may be parasitic diodes that are parasitic (built into) the first to fourth switching elements Q1 to Q4, respectively, or may be external diodes.

First to fourth capacitors C1 to C4 are connected in parallel to the first to fourth switching elements Q1 to Q4, respectively. The first to fourth capacitors C1 to C4 may be parasitic capacitances that are parasitic (built into) the first to fourth switching elements Q1 to Q4, respectively, or may be external capacitors.

The first switching element Q1 and the third switching element Q3 that constitute the upper arm are connected to the primary side input/output terminal T1 on the high potential side. Also, the second switching element Q2 and the fourth switching element Q4 that constitute the lower arm are connected to the primary side input/output terminal T1' on the low potential side.

The secondary circuit 12 includes a fifth switching element Q5, a sixth switching element Q6, a seventh switching element Q7, and an eighth switching element Q8. The fifth switching element Q5 constitutes the upper arm of the third leg, and the sixth switching element Q6 constitutes the lower arm of the third leg. The seventh switching element Q7 constitutes the upper arm of the fourth leg, and the eighth switching element Q8 constitutes the lower arm of the fourth leg. A connection point of the fifth switching element Q5 and the sixth switching element Q6 is connected to one end of the secondary winding of the transformer TR via a resonance capacitor C10 and a resonance coil L2, and a seventh switching element Q7 and an eighth switching element Q8. is connected to the other end of the secondary winding.

Of the fifth to eighth switching elements Q5 to Q8, the sixth switching element Q6 and the eighth switching element Q8, which constitute the "boost circuit" of the present invention, are turned on/off (switched) under the control of the control section 13. . On the other hand, the fifth switching element Q5 and the seventh switching element Q7 continue to be off under the control of the controller 13 . Power semiconductor elements such as IGBTs, silicon power MOSFETs, and silicon carbide power MOSFETs can be used as the fifth to eighth switching elements Q5 to Q8.

Fifth to eighth diodes D5 to D8 are connected in anti-parallel to the fifth to eighth switching elements Q5 to Q8, respectively. The fifth to eighth diodes D5 to D8 may be parasitic diodes that are parasitic (built into) the fifth to eighth switching elements Q5 to Q8, respectively, or may be external diodes. The fifth to eighth diodes D5 to D8 constitute the "rectifier circuit" of the present invention during discharge operation.

Fifth to eighth capacitors C5 to C8 are connected in parallel to the fifth to eighth switching elements Q5 to Q8, respectively. The fifth to eighth capacitors C5 to C8 may be parasitic capacitances that are parasitic (incorporated) in the fifth to eighth switching elements Q5 to Q8, respectively, or may be external capacitors.

The control unit 13 is configured by a control IC such as a microcomputer or FPGA (Field-Programmable Gate Array). The control unit 13 controls the first to fourth switching elements Q1 to Q4 forming the primary side circuit 11 and the fifth to eighth switching elements forming the secondary side circuit 12 based on a command and feedback information from the host controller. It controls the elements Q5-Q8. The command received by the control unit 13 from the host controller includes a start command, a stop command, an output power command value, and the like. The feedback information received by the control unit 13 during the discharge operation includes the voltage value of the input voltage V1, the voltage value of the output voltage V2, the current value of the current (output current) flowing out from the secondary side input/output terminal T2, and the like. is The feedback information may include the current value of the current (input current) flowing into the primary side input/output terminal T1.

As shown in FIG. 3A, the control unit 13 turns on/off the first switching element Q1 and the second switching element Q2 that constitute the first leg in opposite phases. At this time, the control unit 13 controls both the first switching element Q1 and the second switching element Q2 so that the OFF time of the second switching element Q2 is slightly longer than the ON time of the first switching element Q1. can be set to OFF state, ie dead time. The same applies to the third switching element Q3 and the fourth switching element Q4 that constitute the second leg.

Further, when the input voltage V1 is relatively high, as shown in FIG. The element Q8 is also kept off to stop the boost circuit, causing the fifth to eighth diodes D5 to D8 to perform diode bridge rectification. At this time, the control unit 13 can cause the output power to follow the command value by changing the driving period TS (=1/driving frequency).

On the other hand, when the input voltage V1 is relatively low, as shown in FIG. When the switching element Q3 is turned on, the sixth switching element Q6 and the eighth switching element Q8 are turned on for a period TB (hereinafter referred to as "boost period") to operate the boost circuit. At this time, the control unit 13 can cause the output power to follow the command value by changing at least one of the boost period TB and the drive period TS. However, since a large current that rises sharply flows during the boost period TB, frequent changes in the boost period TB may cause unexpected situations. Therefore, it is desirable to follow the output power mainly by changing the driving period TS (driving frequency).

As will be described later, when the control unit 13 activates the boost circuit, the secondary circuit 12 is short-circuited via the transformer TR to generate a large resonant current. A large output current can be obtained by accumulating a large amount of energy resulting from this in the resonance coil L2 and releasing it at an appropriate timing.

When the boost circuit operates, one drive period TS is composed of six periods 1-1, 1-2, 1-3, 2-1, 2-2, and 2-3.

Period 1-1 is the boost period. During this period, the secondary winding of the transformer TR is short-circuited by the sixth switching element Q6 and the eighth diode D8 which are turned on, so that as shown in FIG. Terminal T1→first switching element Q1 (on state)→resonance capacitor C9→resonance coil L1→primary winding of transformer TR→fourth switching element Q4 (on state)→primary side input/output terminal T1′” path , and a circulation path of "secondary winding of transformer TR→resonance coil L2→resonance capacitor C10→sixth switching element Q6 (on state)→eighth diode D8". A large amount of energy is accumulated.

Period 1-2 is the transmission period. During this period, since the sixth switching element Q6 is turned off, the energy accumulated in the resonance coil L2 is released, and as shown in FIG. Eighth diode D8→secondary winding of transformer TR→resonance coil L2→resonance capacitor C10→fifth diode D5→secondary side input/output terminal T2”, and the output voltage V2 is boosted. The degree of boost depends on the length of period 1-1 (boost period TB).

Periods 1-3 are regeneration periods. During this period, the energy accumulated in the resonance coil L1 is released by turning off the first switching element Q1 and the fourth switching element Q4, and as shown in FIG. A current flows through the path of input/output terminal T1′→second diode D2→resonant capacitor C9→resonant coil L1→primary winding of transformer TR→third diode D3→primary side input/output terminal T1′. energy is regenerated in The current in the primary circuit 11 and the current in the secondary circuit 12 that continues to flow from period 1-2 gradually decrease.

In the period 2-1, a large amount of energy is accumulated in the resonance coils L1 and L2 due to the resonance current in the direction opposite to that in the period 1-1 (see FIG. 5A).

In the period 2-2, the energy accumulated in the resonance coil L2 is released through a path different from that in the period 1-2, and the output voltage V2 is boosted (see FIG. 5B).

In the period 2-3, the energy accumulated in the resonance coil L1 is released through a path different from that in the period 1-3, and regenerated to the vehicle battery 100 (see FIG. 5(C)).

As shown in FIG. 1 , the DC/DC converter 10A further includes a storage section 14 . The storage unit 14 is configured by, for example, a nonvolatile memory or the like. The storage unit 14 stores information required when the control unit 13 controls the primary circuit 11 and the secondary circuit 12 .

Next, the characteristics of the DC/DC converter 10A according to this embodiment, which are necessary for understanding the meaning of the information stored in the storage unit 14, will be described.

First, when the discharge operation is performed under the conditions of the input voltage V1=263 V and the constant resistance load, what is the relationship between the drive frequency and boost rate (=boost period TB/drive period TS) and the output voltage V2? FIG. 6 shows the result of a simulation to see if there is a relationship. Boost rates were 0% (no boost), 10%, 20%, 25% and 30%.

As shown by these results, the higher the boost rate of the DC/DC converter 10A, the higher (1) the peak of the output voltage V2 and (2) the higher the driving frequency at which the output voltage V2 reaches its peak. and (3) the output voltage V2 is sensitive to the driving frequency. Also, the peaks of the currents (resonant currents) flowing through the primary circuit 11 and the secondary circuit 12 show a tendency similar to that of the output voltage V2. Therefore, in the DC/DC converter 10A, when the input voltage V1 is low and the boost rate must be set relatively high, the driving frequency is reduced to suppress the peak current to a predetermined allowable current value or less. must be strictly controlled. In particular, when lowering the drive frequency from a relatively high frequency in order to make the output power follow the command value, it is necessary to know exactly how much the drive frequency can be lowered. Note that the allowable current value is a value determined based on how much current a circuit component (for example, a power semiconductor element used as a switching element) can flow. When a current exceeding the allowable current value flows through the circuit component, problems such as thermal destruction occur.

Next, when the discharge operation is performed under the conditions of input voltage V1 = 150 V, output voltage V2 = 450 V, allowable current value = 35.5 A, resonance frequency of the resonance circuit = 110 kHz, how far can the drive frequency be lowered? Table 1 shows the result of simulating whether it is possible and the output power at that time. Boost rates were set to 20%, 25%, 30%, 35%, and 40%.

As shown by this result, the higher the boost rate, the higher the lower limit of the drive frequency of the DC/DC converter 10A. 130 kHz to 211 kHz), and the output power varies depending on the boost rate when the operating frequency is set to the lower limit (for example, when the boost rate is set to 30%, the highest output power is 2.69 kW). become). As described above, Table 1 shows simulation results under the condition of the input voltage V1=150 V, and the results will differ from Table 1 if the conditions of the input voltage V1 are different.

例えば、入力電圧Ｖ１＝１５０Ｖに対応する最適ブースト率および下限駆動周波数については、表１にしたがい、３０％および１８９ｋＨｚを記憶しておく。＊＊＊で示した他の入力電圧Ｖ１に対応する最適ブースト率および下限駆動周波数は、入力電圧Ｖ１の条件を変えて行ったシミュレーションの結果から導き出すことができる。 Based on such characteristics, in the DC/DC converter 10A according to the present embodiment, the current (peak current) flowing through the primary side circuit 11 and the secondary side circuit 12 is stored in the storage unit 14 as a predetermined allowable current value (for example, 35.5 A), and the lower limit of the drive frequency and the boost rate that are predetermined so that the power (output power) output from the secondary side circuit 12 is maximized. A lower limit drive frequency and an optimum boost rate are stored for each DC voltage (input voltage V1) input to the side circuit 11 (see Table 2).

For example, according to Table 1, 30% and 189 kHz are stored for the optimum boost rate and lower limit drive frequency corresponding to the input voltage V1=150V. The optimum boost rate and lower limit driving frequency corresponding to other input voltages V1 indicated by *** can be derived from the results of simulations performed under different conditions of the input voltage V1.

Next, with reference to FIGS. 7 to 9, the processing executed by the control unit 13 during the discharge operation based on the optimum boost rate and lower limit drive frequency for each input voltage V1 stored in the storage unit 14 will be described.

In step S1, the control unit 13 receives an output power command value together with a discharge operation start command (start command) from the host controller.

In step S2, the control section 13 measures the input voltage V1. In this embodiment, "measurement" is performed by receiving an electrical signal relating to the input voltage V1 output by the voltage sensor as feedback information.

In step S<b>3 , the control unit 13 reads from the storage unit 14 the optimal boost rate and the lower limit driving frequency corresponding to the measured input voltage V<b>1 . For example, when the input voltage V1 is 150 V, the optimum boost rate of 30% and the lower limit drive frequency of 189 kHz are read (see Table 2).

In step S4, the control unit 13 turns on the first to fourth switching elements Q1 to Q4 that constitute the primary circuit 11 at a predetermined upper limit drive frequency fm (for example, 220 kHz, which is twice the resonance frequency). / off. Also, the control unit 13 starts to turn on/off the fifth to eighth switching elements Q5 to Q8 that constitute the secondary circuit 12 at a boost rate of 0%. However, while the boost rate is 0%, the controller 13 does not turn on the fifth to eighth switching elements Q5 to Q8 (see FIG. 3A).

In step S5, the controller 13 compares the measured input voltage V1 with a predetermined boost start voltage. If the input voltage V1 is higher than the boost start voltage, it is determined that boosting is not necessary, and the process proceeds to step S10. On the other hand, in other cases, the process proceeds to step S6 for boosting.

In step S6, the controller 13 increases the boost rate by a predetermined amount (eg, 1%). As a result, the fifth to eighth switching elements Q5 to Q8 forming the secondary circuit 12 are turned on/off at the increased boost rate. More specifically, the sixth switching element Q6 and the eighth switching element Q8 are turned on/off at the increased boost rate while the fifth switching element Q5 and the seventh switching element Q7 are kept off. As the boost rate increases, so does the output power.

In step S7, the control section 13 measures the output power. In this embodiment, an electrical signal related to the output voltage V2 output by the voltage sensor and an electrical signal related to the output current output by the current sensor that detects the current flowing from the secondary side input/output terminal T2 are received as feedback information. A "measurement" is made by computing the electrical signals together.

In step S8, the controller 13 compares the output power measured in step S7 with the output power command value received in step S1. If both match, there is no need to further change the operating point (boost rate and drive frequency), so proceed to [A]. This completes the startup process of the DC/DC converter 10A. On the other hand, if the two do not match, that is, if the output power has not reached the output power command value, the process proceeds to step S9 to continue changing the operating point.

At step S9, the controller 13 compares the current boost rate with the optimal boost rate read at step S3. If both match, it is inappropriate to further increase the boost rate, so the process proceeds to step S10. On the other hand, if the two do not match, that is, if the current boost rate has not reached the optimum boost rate, there is room for the output power to approach the output power command value by increasing the boost rate, so the process returns to step S6.

The control unit 13 repeatedly executes steps S6 to S9 until the output power matches the output power command value or the boost rate matches the optimum boost rate.

In step S10, the controller 13 reduces the driving frequency by a predetermined amount (eg, 1 kHz). As a result, the first to fourth switching elements Q1 to Q4 forming the primary side circuit 11 and the fifth to eighth switching elements Q5 to Q8 forming the secondary side circuit 12 are turned on/off at the lowered drive frequency. It will turn off. Output power increases as the drive frequency decreases.

In step S11, the control unit 13 measures the output power using the same method as in step S7.

In step S12, the controller 13 compares the output power measured in step S11 with the output power command value received in step S1. If both match, there is no need to further change the operating point, so proceed to [A]. This completes the startup process of the DC/DC converter 10A. On the other hand, if the two do not match, that is, if the output power has not reached the output power command value, the process returns to step S10 to continue changing the operating point (driving frequency).

The control unit 13 repeatedly executes steps S10 to S12 until the output power matches the output power command value. If the host controller is functioning normally and there is no error in the information stored in the storage unit 14, the drive frequency will not fall below the lower limit drive frequency before the output power matches the output power command value. However, in order to reliably prevent element destruction due to the peak current exceeding the allowable current value, it is preferable that the control unit 13 determines whether the drive frequency is below the lower limit drive frequency after executing step S10. . If this determination is not made, the reading of the lower limit drive frequency in step S3 can be omitted.

In this way, the control unit 13 increases the boost rate from 0% to the optimum boost rate corresponding to the DC voltage V1 while maintaining the drive frequency at the upper limit drive frequency fm, and then changes the drive frequency to the DC voltage V1. It is lowered toward the corresponding lower limit drive frequency (see the thick solid line arrow “Example” in FIG. 9 and the curve C3). As a result, the DC/DC converter 10A can reliably prevent the peak current from exceeding the allowable current value while reliably outputting the output power as instructed by the host controller. If the drive frequency and the boost rate are changed simultaneously, the drive frequency will drop to the lower limit drive frequency before the boost rate increases to the optimum boost rate, and the drive frequency cannot be lowered any further. Therefore, it may not be possible to output the output power as instructed (see the dashed arrow “comparative example” in FIG. 9).

As can be seen from FIG. 6, the output voltage V2 is very sensitive to some increased boost rate. Output current and output power show similar trends. For this reason, it is preferable that the follow-up of the output power to the command value (particularly, the final fine adjustment) is performed by changing the drive frequency rather than by the boost rate. This is the reason why the boost rate is increased to the optimum boost rate and the drive frequency is lowered toward the lower limit drive frequency while the boost rate is maintained at the optimum boost rate.

In step S13 executed after the start-up process, the control unit 13 determines whether or not a stop command has been received from the host controller. When the stop command is received, the process proceeds to end processing (steps S14 to S18). On the other hand, if no stop command has been received, the process proceeds to normal processing (steps S19 to S26).

In steps S14 and S15, the control unit 13 increases the drive frequency by a predetermined amount (for example, 1 kHz) until it reaches the upper limit drive frequency fm.

In steps S16 and S17, the controller 13 decreases the boost rate by a predetermined amount (for example, 1%) until it reaches 0%.

In step S18, which is executed after the drive frequency reaches the upper limit drive frequency fm and the boost rate reaches 0%, the control unit 13 controls the first to fourth switching elements Q1 to Q4 constituting the primary circuit 11. on/off. In addition, since the fifth to eighth switching elements Q5 to Q8 (fifth switching element Q5 and seventh switching element Q7 are maintained in the off state, sixth switching element Q6 and eighth It can be said that the ON/OFF of the switching element Q8) ends when the boost rate becomes 0%.

By this termination process, the DC/DC converter 10A can safely terminate the discharge operation.

In step S19, the control unit 13 receives an output power command value from the host controller. The control unit 13 may suspend execution of step S19 until the output power command value is changed. In other words, the control unit 13 may perform normal processing only when the output power command value is changed.

In step S20, the control section 13 measures the input voltage V1 by the same method as in step S2.

In step S<b>21 , the control unit 13 reads from the storage unit 14 the optimum boost rate and the lower limit drive frequency corresponding to the measured input voltage V<b>1 .

At step S22, the controller 13 compares the current boost rate with the optimum boost rate read at step S21. If the two do not match, the process proceeds to step S23 to increase or decrease the boost rate, and then proceeds to step S24. On the other hand, if both match, the process proceeds to step S24 without going through step S23.

In step S23, the control unit 13 increases or decreases the boost rate by a predetermined amount (for example, 1%) so as to approach the optimum boost rate.

In step S24, the control unit 13 measures the output power using the same method as in steps S7 and S11.

In step S25, the controller 13 compares the output power measured in step S24 with the output power command value received in step S19. If both match, there is no need to further change the operating point, so proceed to [A]. On the other hand, if the two do not match, it is necessary to continue changing the operating point (driving frequency), so the process proceeds to step S26.

In step S26, the control unit 13 increases or decreases the driving frequency by a predetermined amount (for example, 1 kHz) so that the output power approaches the output power command value. More specifically, the control unit 13 increases the driving frequency when the output power is greater than the output power command value, and decreases the driving frequency when the output power is less than the output power command value.

Unless a stop command is received from the host controller, the control unit 13 repeats normal processing (steps S19 to S26). As a result, the DC/DC converter 10A can continue to output power according to the latest command value issued from the host controller while preventing the peak current from exceeding the allowable current value.

In order to more reliably prevent element destruction due to the peak current exceeding the allowable current value, it is preferable that the control unit 13 determines whether the drive frequency is below the lower limit drive frequency after executing step S26. . If this determination is not made, the reading of the lower limit drive frequency in step S21 can be omitted.

[Modification]
Although the embodiments of the current resonant DC/DC converter according to the present invention have been described above, the configuration of the present invention is not limited to this. Hereinafter, representative modifications of the present invention will be described.

- FIG. 10 shows a current resonant DC/DC converter 10B according to a first modification of the present invention. The DC/DC converter 10B according to this modification differs from the DC/DC converter 10A according to the embodiment in that the resonance coil L2 and the resonance capacitor C10 on the secondary side are omitted. When bidirectional operation is not required, the number of parts can be reduced by adopting the configuration of this modified example.

- FIG. 11 shows a current resonance type DC/DC converter 10C according to a second modification of the present invention. In the DC/DC converter 10C according to this modification, the resonance coil L2 and the resonance capacitor C10 are omitted, and the fifth switching element Q5, the seventh switching element Q7, the fifth capacitor C5 and the seventh capacitor C7 are omitted. It is different from the DC/DC converter 10A according to the embodiment in that the secondary side circuit 15 is provided with a secondary side circuit 15 that is designed to be a secondary side circuit. In the example, the upper arm of the 3rd leg (Q5, D5, C5) and the upper arm of the 4th leg (Q7, D7, C7) were only utilized as part of the "rectifier circuit". Therefore, when bidirectional operation is unnecessary and diode bridge rectification is used for rectification on the secondary side, the configuration of this modified example may be adopted and switching elements Q5 and Q7 and capacitors C5 and C7 may be omitted. There is no problem in operation.

- FIG. 12 shows a current resonant DC/DC converter 10D according to a third modification of the present invention. The DC/DC converter 10D according to this modification differs from the embodiment in that the resonance coil L2 and the resonance capacitor C10 are omitted and that the secondary circuit 16 is provided instead of the secondary circuit 15. It is different from the DC/DC converter 10A concerned. The secondary circuit 16 includes fifth to eighth diodes D5 to D8, a connection point between the fifth diode D5 and the sixth diode D6 (one end of the secondary winding of the transformer TR), and a seventh diode D7 and an eighth diode. A ninth switching element Q9 and a tenth switching element Q10 as a "boost circuit" connected in series between the connection point of D8 (the other end of the secondary winding of the transformer TR) and the ninth switching element Q9. A ninth diode D9 connected in parallel and a tenth diode D10 connected in parallel to the tenth switching element Q10 are provided. The control unit 13 turns on/off the ninth switching element Q9 like the sixth switching element Q6, and turns on/off the tenth switching element Q10 like the eighth switching element Q8, thereby switching the secondary side circuit 16. Boost can be operated. The configuration of this modified example can be employed when bidirectional operation is not required. In addition, in this modified example, the fifth to tenth diodes D5 to D10 form a "rectifier circuit".

In the embodiment and the first to third modifications, the resonance capacitor C9 and the resonance coil L1 are collectively arranged on one end side of the primary winding of the transformer TR. They may be arranged separately on one end side and the other end side, or may be collectively arranged on the other end side of the primary winding. Further, in the embodiment, the resonance capacitor C10 and the resonance coil L2 are collectively arranged on one end side of the secondary winding of the transformer TR. may be arranged separately, or may be arranged collectively on the other end side of the secondary winding.

The control unit 13 of the embodiment and the first modification may turn on/off the fifth to eighth switching elements Q5 to Q8 to perform synchronous rectification when the boost operation is not performed. In this case, the fifth to eighth switching elements Q5 to Q8 and the fifth to eighth diode elements D5 to D8 constitute the "rectifier circuit" of the present invention.

・In the startup process, the control unit 13 of the embodiment (and the first to third modifications) increases the boost rate from zero to the optimum boost rate corresponding to the input voltage V1, and then changes the drive frequency to correspond to the input voltage V1. , but the order is not limited to this. For example, the control unit 13 may start decreasing the drive frequency after starting to increase the boost rate (before the boost rate reaches the optimum boost rate). Alternatively, the control unit 13 may start increasing the boost rate and lowering the drive frequency, and thereafter allow the boost rate to reach the optimum boost rate before the drive frequency reaches the lower limit drive frequency.

・In the end processing, the control unit 13 of the embodiment (and the first to third modifications) starts decreasing the boost rate toward 0% after increasing the drive frequency to the upper limit drive frequency fm. It is not limited to this. For example, the control unit 13 may start increasing the driving frequency and decreasing the boost rate at the same time, or may decrease the boost rate first.

10A, 10B, 10C, 10D current resonance type DC/DC converter 11 primary side circuit 12 secondary side circuit (embodiment, first modification)
13 control unit 14 storage unit 15 secondary circuit (second modification)
16 secondary circuit (third modification)
100 vehicle battery 110 V2H device 120 bi-directional DC/AC inverter 130 load

Claims (4)

a primary side circuit composed of a bridge circuit including a plurality of switching elements; a secondary side circuit composed of a boost circuit and a rectifier circuit including a plurality of switching elements; and a current resonance circuit including a resonant coil and a resonant capacitor. , a control for controlling on/off of a transformer provided between the primary circuit and the secondary circuit, a switching element forming the primary circuit, and a switching element forming the secondary circuit; A current resonant DC/DC converter comprising:
The electric current flowing through the primary circuit and the secondary circuit is determined in advance so that the current flowing through the secondary circuit does not exceed a predetermined allowable current value and the power output from the secondary circuit is maximized. a storage unit that stores the lower limit of the driving frequency of the switching element constituting the primary side circuit and the boost rate of the boost circuit as the lower limit driving frequency and the optimum boost rate for each DC voltage input to the primary side circuit; further prepared,
When boosting the DC voltage input to the primary side circuit and outputting the DC voltage from the secondary side circuit by the boost operation of the boost circuit, the control unit increases the boost rate to the optimum DC voltage corresponding to the DC voltage. Switching elements constituting the primary side circuit and switching elements constituting the secondary side circuit so that the boost rate is approached and the drive frequency does not fall below the lower limit drive frequency corresponding to the DC voltage. A current resonance type DC/DC converter characterized by controlling ON/OFF. When the DC voltage input to the primary circuit starts to be boosted by the boost operation, the control unit increases the boost rate from zero while maintaining the drive frequency at a predetermined upper limit drive frequency. 2. The current resonance according to claim 1, wherein after increasing to the optimum boost rate corresponding to the voltage, the driving frequency is decreased toward the lower limit driving frequency corresponding to the DC voltage. type DC/DC converter. The control unit increases the drive frequency to the upper limit drive frequency while maintaining the boost rate at the optimum boost rate when ending the boosting of the DC voltage input to the primary side circuit by the boost operation. 3. A current resonance type DC/DC converter according to claim 2, wherein said boost rate is reduced to zero after the current resonance type DC/DC converter. The control unit changes the drive frequency in a state in which the boost rate approaches an optimum boost rate corresponding to the DC voltage input to the primary circuit so that the power output from the secondary circuit is 4. The on/off control of a switching element forming the primary side circuit and a switching element forming the secondary side circuit is controlled so as to obtain a desired output power. A current resonant DC/DC converter according to any one of the preceding paragraphs.

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