JP2023082523A - Power supply device - Google Patents

Abstract

To provide a power supply device capable of suppressing cyclic current of an input side circuit.SOLUTION: A power supply device comprises: a first bridge circuit; a transformer to whose first coil an AC voltage outputted from the first bridge circuit is inputted, and from whose second coil an induced AC voltage is outputted; a second bridge circuit that converts the AC voltage outputted from the second coil of the transformer into a DC voltage and outputs the resultant to a load; and a controller that controls a phase difference between a first drive pulse to be outputted to switch elements in the first bridge circuit and a second drive pulse to be outputted to switch elements in the second bridge circuit to control the DC voltage to be outputted from the second bridge circuit. The controller performs control of increasing or decreasing a duty ratio of the first drive pulse to be larger or lower than a standard value on the basis of a first voltage inputted to the first bridge circuit and a second voltage of the load.SELECTED DRAWING: Figure 1

Description

The present invention relates to a power supply device.

Patent Document 1 describes a DAB (Dual Active Bridge) type DC-DC converter. DAB can be isolated, and can easily perform step-up/step-down operation and bidirectional power conversion.

However, DAB has the characteristic that when the voltage difference between the input side (primary side) and the output side (secondary side) is large, the current circulating in the input side circuit increases. This characteristic does not deteriorate even if the phase difference between the input side and the output side, which is the command value of the output current, is 0°.

Therefore, under conditions such as drooping (short circuit) on the output side, where a significant input-output voltage difference occurs, the current increases beyond the normal operating range in almost all elements in which current is flowing. As a result, there is a problem that circuit stress and loss significantly increase.

Patent Literature 2 describes a switching power supply device that solves the above problem by controlling the phase (phase between phases) of switch elements in an arm.

U.S. Pat. No. 5,027,264 JP 2018-26961 A

In a three-phase power supply, the phase difference between the three phases is fixed at 120°. Therefore, the switching power supply device described in Patent Document 2 cannot be applied to the three-phase case.

SUMMARY OF THE INVENTION An object of the present invention is to provide a power supply device capable of suppressing a circulating current in an input-side circuit.

A power supply device according to one embodiment of the present invention includes
a first bridge circuit including a plurality of arms each having a high-side switching element and a low-side switching element, and converting a DC voltage into an AC voltage for output;
A transformer including a first winding and a second winding, wherein an alternating voltage output from the first bridge circuit is input to the first winding and an induced alternating voltage is output from the second winding. and,
A second bridge that includes a plurality of arms each having a high-side switch element and a low-side switch element, and converts an AC voltage output from the second winding of the transformer to a DC voltage for output to a load. a circuit;
outputting a plurality of first drive pulses to the switch elements in the first bridge circuit to switch the switch elements in the first bridge circuit, and outputting a plurality of second drive pulses to the second bridge; output to the switch elements in the circuit to cause the switch elements in the second bridge circuit to perform a switching operation to determine the phase difference between the plurality of first drive pulses and the plurality of second drive pulses. a control unit that controls the DC voltage output from the second bridge circuit by controlling the
with
The control unit
Based on the first voltage input to the first bridge circuit and the second voltage of the load, control is performed to make the duty ratio of the plurality of first drive pulses smaller or larger than a standard value;
It is characterized by

In the power supply device,
The control unit
performing control to make the duty ratio smaller or larger than the standard value based on the value of the ratio of the second voltage to the first voltage;
It is characterized by

In the power supply device,
The control unit
As the value of the ratio becomes smaller, control is performed such that the duty ratio is made smaller or larger than the standard value;
It is characterized by

In the power supply device,
The control unit
When the value of the ratio is within a predetermined range including 1, performing control to maintain the duty ratio at the standard value;
It is characterized by

In the power supply device,
The control unit
performing control to adjust the duty ratio according to the phase difference;
It is characterized by

In the power supply device,
each of the first bridge circuit and the second bridge circuit is a three-phase bridge circuit,
The transformer is a three-phase transformer,
The control unit
Perform control to fix the phase difference between the three arms of the first bridge circuit and the three arms of the second bridge circuit at 120°;
It is characterized by

The power supply device of one embodiment of the present invention has the effect of suppressing circulating current in the input-side circuit.

FIG. 1 is a diagram showing the configuration of a power supply device according to an embodiment. FIG. 2 is a diagram showing waveforms of respective parts on the primary side of the power supply device of the comparative example. FIG. 3 is a diagram illustrating functional blocks of a control unit of the power supply device according to the embodiment; FIG. 4 is a diagram illustrating an example of a duty ratio of the power supply device according to the embodiment when the phase difference is 0°. FIG. 5 is a diagram showing an example of the duty ratio of the power supply device according to the embodiment when the phase difference is 0°. FIG. 6 is a diagram showing waveforms of respective parts on the primary side of the power supply device according to the embodiment. FIG. 7 is a diagram showing the relationship between the duty ratio and the effective value of the output AC voltage of the first bridge circuit in the embodiment.

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of a power supply device of the present invention will be described in detail below with reference to the drawings. It should be noted that the present invention is not limited by this embodiment.

<Embodiment>
(overall structure)
FIG. 1 is a diagram showing the configuration of a power supply device according to an embodiment. The power supply device 1 is of the DAB (Dual Active Bridge) type and is a bidirectional DC-DC converter. In the embodiment, the power supply device 1 receives the DC voltage Vin output from the power supply 2 and smoothed by the capacitor 3 , and outputs the DC voltage Vout to the load 4 .

The voltage Vin corresponds to an example of the "first voltage" of the present disclosure. The voltage Vout corresponds to an example of the "second voltage" of the present disclosure.

The power supply device 1 includes a first voltage sensor 11, a primary-side first bridge circuit 12, a reactor 13, a transformer 14, a secondary-side second bridge circuit 15, a capacitor 16, and a second voltage sensor. 17 and a control unit 18 .

The first voltage sensor 11 detects the voltage Vin and outputs it to the controller 18 .

The first bridge circuit 12 is a single-phase full bridge circuit including transistors Tr1 to Tr4.

Although the first bridge circuit 12 is a single-phase full bridge circuit in the embodiment, the present disclosure is not limited to this. The first bridge circuit 12 may be a three-phase bridge circuit including three arms.

Although each transistor is a MOSFET in the present disclosure, it is not limited to this. Each transistor may be a silicon power device, a GaN power device, a SiC power device (eg, an IGBT (Insulated Gate Bipolar Transistor)), or the like.

Each transistor has a parasitic diode (body diode) that allows current to actively flow, or has a diode connected in anti-parallel. A parasitic diode is a pn junction between the back gate and the source and drain of a MOSFET.

The source of transistor Tr1 is electrically connected to the drain of transistor Tr2. A drain of the transistor Tr1 is electrically connected to a drain of the transistor Tr3. The source of transistor Tr3 is electrically connected to the drain of transistor Tr4. The source of transistor Tr2 is electrically connected to the source of transistor Tr4.

Each of the transistors Tr1 to Tr4 corresponds to an example of the "switch element" of the present disclosure.

Each of the transistors Tr1 and Tr3 corresponds to an example of the "high-side switch element" of the present disclosure. Each of the transistors Tr2 and Tr4 corresponds to an example of the "low-side switch element" of the present disclosure.

The transistors Tr1 and Tr2 correspond to an example of the "arm" of the present disclosure. Similarly, the transistors Tr3 and Tr4 correspond to an example of the "arm" of the present disclosure.

One input terminal 12a of the first bridge circuit 12 is a connection point between the drain of the transistor Tr1 and the drain of the transistor Tr3. The other input terminal 12b of the first bridge circuit 12 is a connection point between the source of the transistor Tr2 and the source of the transistor Tr4.

One output terminal 12c of the first bridge circuit 12 is a connection point between the source of the transistor Tr1 and the drain of the transistor Tr2. The other output terminal 12d of the first bridge circuit 12 is a connection point between the source of the transistor Tr3 and the drain of the transistor Tr4.

The input terminal 12a is electrically connected to one end (high potential side end) of the capacitor 3 . The input terminal 12b is electrically connected to the other end (low potential side end) of the capacitor 3 .

A voltage Vin is supplied between the input terminal 12a and the input terminal 12b.

One end of the reactor 13 is electrically connected to the output terminal 12c. Although the reactor 13 is arranged on the primary side in the embodiment, the present disclosure is not limited to this. The reactor 13 may be arranged on the secondary side, or may be arranged on both the primary side and the secondary side.

The transformer 14 includes a first winding 14a, a second winding 14b, and a core 14c. The first winding 14a and the second winding 14b are wound around the core 14c.

The transformer 14 corresponds to an example of the "transformer" of the present disclosure.

Although the transformer 14 is a single-phase transformer in the embodiment, the present disclosure is not limited to this. The transformer 14 is preferably a three-phase transformer when the first bridge circuit 12 and the second bridge circuit 15 are three-phase bridge circuits.

The turns ratio between the first winding 14a and the second winding 14b is exemplified as 1:1, but the present disclosure is not limited to this.

One end of the first winding 14 a is electrically connected to the other end of the reactor 13 . The other end of the first winding 14a is electrically connected to the output terminal 12d.

The first bridge circuit 12 outputs the voltage Vin or the voltage -Vin between the output terminal 12c and the output terminal 12d.

For example, when the transistors Tr1 and Tr4 are turned on and the transistors Tr2 and Tr3 are turned off, the first bridge circuit 12 applies the voltage Vin between the output terminals 12c and 12d. Output.

For example, when the transistors Tr1 and Tr4 are controlled to be off and the transistors Tr2 and Tr3 are controlled to be on, the first bridge circuit 12 applies the voltage -Vin between the output terminals 12c and 12d. output between

The second bridge circuit 15 is a single-phase full bridge circuit including transistors Tr5 to Tr8.

Although the second bridge circuit 15 is a single-phase full bridge circuit in the embodiment, the present disclosure is not limited to this. The second bridge circuit 15 may be a three-phase bridge circuit including three arms.

The source of transistor Tr5 is electrically connected to the drain of transistor Tr6. A drain of the transistor Tr5 is electrically connected to a drain of the transistor Tr7. The source of transistor Tr7 is electrically connected to the drain of transistor Tr8. The source of transistor Tr6 is electrically connected to the source of transistor Tr8.

Each of the transistors Tr5 to Tr8 corresponds to an example of the "switch element" of the present disclosure.

Each of the transistors Tr5 and Tr7 corresponds to an example of the "high-side switch element" of the present disclosure. Each of the transistors Tr6 and Tr8 corresponds to an example of the "low-side switch element" of the present disclosure.

Transistors Tr5 and Tr6 correspond to an example of the "arm" of the present disclosure. Similarly, the transistors Tr7 and Tr8 correspond to an example of the "arm" of the present disclosure.

One input terminal 15a of the second bridge circuit 15 is a connection point between the source of the transistor Tr5 and the drain of the transistor Tr6. The other input terminal 15b of the second bridge circuit 15 is a connection point between the source of the transistor Tr7 and the drain of the transistor Tr8.

One output terminal 15c of the second bridge circuit 15 is a connection point between the drain of the transistor Tr5 and the drain of the transistor Tr7. The other output terminal 15d of the second bridge circuit 15 is a connection point between the source of the transistor Tr6 and the source of the transistor Tr8.

The input terminal 15a is electrically connected to one end of the second winding 14b. The input terminal 15b is electrically connected to the other end of the second winding 14b.

The output terminal 15c is electrically connected to one end (high potential side end) of the capacitor 16 . The output terminal 15d is electrically connected to the other end (low potential side end) of the capacitor 16 .

The voltage across capacitor 16 is voltage Vout. One end (high potential side end) of the capacitor 16 is electrically connected to one end (high potential side end) of the load 4 . The other end (low potential side end) of the capacitor 16 is electrically connected to the other end (low potential side end) of the load 4 .

The second voltage sensor 17 detects the voltage Vout and outputs it to the controller 18 .

The control section 18 controls the first bridge circuit 12 and the second bridge circuit 15 .

For example, the control unit 18 controls the switching frequencies of the transistors Tr1 to Tr8 to be the same and the duty ratio to 0.5.

The duty ratio is the ratio of the ON time (or OFF time) of the switch element to one cycle of control. In the present disclosure, the duty ratio is the on-time of the high-side transistors Tr1 and Tr3 (the off-time of the low-side transistors Tr2 and Tr4) for one cycle of control.

In DAB, the phase difference between the input side bridge circuit and the output side bridge circuit is the command value of the output current. Therefore, the control section 18 controls the output current (power) by controlling the phase difference between the first bridge circuit 12 and the second bridge circuit 15 .

(Control of Comparative Example)
In Patent Document 1, the duty ratio of the drive pulse (gate signal) is set to 0.5 (hereinafter referred to as "standard value").

FIG. 2 is a diagram showing waveforms of respective parts on the primary side of the power supply device of the comparative example. FIG. 2 is a diagram showing waveforms of respective parts on the primary side of the power supply device 1 when the load 4 is short-circuited (voltage Vout is 0 V) and the duty ratios of the transistors Tr1 to Tr8 are standard values. It should be noted that the load 4 is in a short-circuited state, and the gate signals from the transistors Tr5 to Tr8 do not produce any difference in results (no voltage is generated on the input terminals 15a and 15b). Illustration and description are omitted.

A waveform 101 indicates a drive pulse input to the gate of the transistor Tr1. A waveform 102 represents a drive pulse input to the gate of the transistor Tr2. A waveform 103 represents a drive pulse input to the gate of the transistor Tr3. A waveform 104 indicates a drive pulse input to the gate of the transistor Tr4. A waveform 105 indicates the voltage applied to the reactor 13 . A waveform 106 indicates the current flowing through the reactor 13 .

Note that the description of the dead time is omitted in FIG.

A period from timing _t0 to timing _t2 is one cycle of control. Since the duty ratios of transistors Tr1 to Tr8 are standard values, the period from timing _t0 to timing _t1 and the period from timing _t1 to timing _t2 have the same length.

At timing _t0 , as indicated by a waveform 101, a high level drive pulse is input to the gate of the transistor Tr1. As indicated by waveform 102, a low-level drive pulse is input to the gate of transistor Tr2. As indicated by waveform 103, a low-level drive pulse is input to the gate of transistor Tr3. As indicated by waveform 104, a high-level drive pulse is input to the gate of transistor Tr4.

At this time, as indicated by waveform 105 , voltage Vin is applied to reactor 13 . Therefore, as indicated by waveform 106, the reactor current flowing through reactor 13 increases linearly.

At timing _t1 , as indicated by waveform 101, a low-level drive pulse is input to the gate of transistor Tr1. As indicated by waveform 102, a high-level drive pulse is input to the gate of transistor Tr2. As indicated by a waveform 103, a high level drive pulse is input to the gate of the transistor Tr3. As indicated by waveform 104, a low-level drive pulse is input to the gate of transistor Tr4.

At this time, a voltage -Vin is applied to the reactor 13 as indicated by a waveform 105 . Therefore, as indicated by a waveform 106, the reactor current flowing through the reactor 13 linearly decreases.

In the comparative example, when the ratio of the voltage Vout to the voltage Vin is small (or when the voltage difference between the voltage Vin and the voltage Vout is large), the reactor 13 is energized. Therefore, in the comparative example, a large reactor current (circulating current) flows through the reactor 13 as indicated by the waveform 106 .

(Control of embodiment)
In the embodiment, the control unit 18 drives the transistors Tr1 to Tr4 on the primary side based on the ratio of the voltage Vout to the voltage Vin (hereinafter sometimes referred to as "input/output voltage ratio"). The pulse duty ratio is made smaller or larger than the standard value.

From the viewpoint of the period during which the voltage is applied to the reactor 13, making the duty ratio of the driving pulse smaller than the standard value is equivalent to making it larger. For example, setting the duty ratio of the drive pulse to 0.9 and setting the duty ratio of the drive pulse to 0.1 are equivalent because the period during which the voltage is applied to the reactor 13 is the same.

FIG. 3 is a diagram illustrating functional blocks of a control unit of the power supply device according to the embodiment;

The control unit 18 includes a deviation calculation unit 21, a phase difference calculation unit 22, a duty ratio calculation unit 23, a signal output unit 24, a pulse generation unit 25, a primary side pulse drive unit 26, and a secondary side pulse and a drive unit 27 .

The deviation calculator 21 calculates a deviation ε between the voltage command value Vcom and the voltage Vout by subtracting the voltage Vout from the voltage command value Vcom.

The phase difference calculator 22 calculates the phase difference φ between the first bridge circuit 12 on the primary side and the second bridge circuit 15 on the secondary side based on the deviation ε. As described above, in DAB, the voltage Vout and the output current Iout are controlled by the phase difference φ between the first bridge circuit 12 on the primary side and the second bridge circuit 15 on the secondary side.

The duty ratio calculator 23 calculates the duty ratio based on the voltage Vin and the voltage Vout, taking into consideration the phase difference φ.

4 and 5 are diagrams showing an example of the duty ratio of the power supply device according to the embodiment when the phase difference is 0°.

In FIG. 4, a waveform 111 shows an example of the relationship between the input/output voltage ratio and the duty ratio when the duty ratio of the drive pulse input to the transistors Tr1 to Tr4 on the primary side is made smaller than the standard value. . A waveform 112 shows an example of the relationship between the input/output voltage ratio and the duty ratio when the duty ratio of the drive pulse input to the transistors Tr1 to Tr4 on the primary side is made larger than the standard value.

As shown by waveforms 111 and 112 , the duty ratio calculator 23 may set the input/output voltage ratio between 1.0 and 0.9 as a dead zone 113 .

As an example, the duty ratio calculator 23 sets the duty ratio to 0.5 (standard value) when the input/output voltage ratio is between 1.0 and 0.9.

As shown by a waveform 111, the duty ratio calculator 23 reduces the duty ratio as the input/output voltage ratio becomes smaller than 0.9.

As indicated by the waveform 111, the duty ratio calculator 23 linearly decreases the duty ratio, but the present disclosure is not limited to this. It is preferable that the duty ratio calculation unit 23 monotonically decrease the duty ratio.

As shown by a waveform 112, the duty ratio calculator 23 increases the duty ratio as the input/output voltage ratio becomes smaller than 0.9.

As shown by the waveform 112, the duty ratio calculator 23 linearly increases the duty ratio, but the present disclosure is not limited to this. It is preferable that the duty ratio calculation unit 23 monotonically increases the duty ratio.

In FIG. 5, a waveform 116 shows an example of the relationship between the input/output voltage ratio and the duty ratio when the duty ratio of the drive pulse input to the transistors Tr1 to Tr4 on the primary side is made smaller than the standard value. . A waveform 117 shows an example of the relationship between the input/output voltage ratio and the duty ratio when the duty ratio of the drive pulse input to the transistors Tr1 to Tr4 on the primary side is made larger than the standard value.

As shown by a waveform 116, the duty ratio calculator 23 reduces the duty ratio as the input/output voltage ratio becomes smaller than 1.0.

As shown by the waveform 116, the duty ratio calculator 23 linearly decreases the duty ratio, but the present disclosure is not limited to this. It is preferable that the duty ratio calculation unit 23 monotonically decrease the duty ratio.

As shown by a waveform 117, the duty ratio calculator 23 increases the duty ratio as the input/output voltage ratio becomes smaller than 1.0.

As shown by the waveform 117, the duty ratio calculator 23 linearly increases the duty ratio, but the present disclosure is not limited to this. It is preferable that the duty ratio calculation unit 23 monotonically increases the duty ratio.

The duty ratio calculator 23 may eliminate the dead zone 113 (see FIG. 4), as shown by waveforms 116 and 117 .

By the way, the case where the phase difference φ is not 0° means the case where power is required to be output to the load 4 side.

Therefore, the duty ratio calculator 23 adds a value corresponding to the phase difference φ to the waveform 111 or 116, and adjusts the duty ratio so as to approach the standard value (see arrow 114 in FIG. 4 and arrow 118 in FIG. 5). can be

Further, the duty ratio calculator 23 subtracts a value corresponding to the phase difference φ from the waveform 112 or 117, and adjusts the duty ratio so as to approach the standard value (see arrow 115 in FIG. 4 and arrow 119 in FIG. 5). can be

Referring to FIG. 3 again, the signal output unit 24 outputs the first signal S1 and the second signal S2 each having the duty ratio calculated by the duty ratio calculation unit 23 and having a phase difference φ between them. do. The first signal S1 is a reference signal that serves as a basis for drive pulses input to the gates of the transistors Tr1 to Tr4 on the primary side. The second signal S2 is a reference signal that is the basis of the drive pulse that is input to the gates of the transistors Tr5 to Tr8 on the secondary side.

Based on the first signal S1, the pulse generator 25 generates a first pulse group S3 including four pulses each having a waveform input to the gates of the transistors Tr1 to Tr4 on the primary side. Based on the second signal S2, the pulse generator 25 generates a second pulse group S4 including four pulses each having a waveform to be input to the gates of the transistors Tr5 to Tr8 on the secondary side.

The primary side pulse driving section 26 outputs the first driving pulse group S5 obtained by converting the voltage level of the first pulse group S3 to the gates of the transistors Tr1 to Tr4.

The secondary pulse driving section 27 outputs the second driving pulse group S6 obtained by converting the voltage level of the second pulse group S4 to the gates of the transistors Tr5 to Tr8.

FIG. 6 is a diagram showing waveforms of respective parts on the primary side of the power supply device according to the embodiment. FIG. 6 shows each part on the primary side of the power supply when the load 4 is short-circuited (voltage Vout is 0 V) and the duty ratio of the transistors Tr1 to Tr8 is 0.9 (equivalent to 0.1). FIG. 4 is a diagram showing waveforms; It should be noted that the load 4 is in a short-circuited state, and the gate signals from the transistors Tr5 to Tr8 do not produce any difference in results (no voltage is generated on the input terminals 15a and 15b). Illustration and description are omitted.

A waveform 121 indicates a drive pulse input to the gate of the transistor Tr1. A waveform 122 represents a drive pulse input to the gate of the transistor Tr2. A waveform 123 represents a drive pulse input to the gate of the transistor Tr3. A waveform 124 represents the drive pulse input to the gate of the transistor Tr4. A waveform 125 indicates the voltage applied to the reactor 13 . A waveform 126 indicates the current flowing through the reactor 13 .

Note that the dead time is omitted in FIG.

A period from timing _t10 to timing _t14 is one cycle of control.

In FIG. 6, the phases from waveform 121 to waveform 124 are unchanged as in the comparative example. However, the present disclosure is not limited to this. The phases of waveforms 121 through 124 may be changed.

At timing _t10 , as indicated by waveform 121, a high-level drive pulse is input to the gate of transistor Tr1. As indicated by waveform 122, a low-level drive pulse is input to the gate of transistor Tr2. As indicated by a waveform 123, a high level drive pulse is input to the gate of the transistor Tr3. As indicated by waveform 124, a low-level drive pulse is input to the gate of transistor Tr4.

At this time, no voltage is applied to the reactor 13 as indicated by a waveform 125 . Therefore, as indicated by waveform 126, the reactor current flowing through reactor 13 neither increases nor decreases.

At timing _t11 , as indicated by waveform 121, a high-level drive pulse is input to the gate of transistor Tr1. As indicated by waveform 122, a low-level drive pulse is input to the gate of transistor Tr2. As indicated by waveform 123, a low-level drive pulse is input to the gate of transistor Tr3. As indicated by waveform 124, a high level drive pulse is input to the gate of transistor Tr4.

At this time, a voltage Vin is applied to the reactor 13 as indicated by a waveform 125 . Therefore, as indicated by a waveform 126, the reactor current flowing through the reactor 13 increases linearly.

At timing _t12 , as indicated by waveform 121, a high-level drive pulse is input to the gate of transistor Tr1. As indicated by waveform 122, a low-level drive pulse is input to the gate of transistor Tr2. As indicated by a waveform 123, a high level drive pulse is input to the gate of the transistor Tr3. As indicated by waveform 124, a low-level drive pulse is input to the gate of transistor Tr4.

At this time, no voltage is applied to the reactor 13 as indicated by a waveform 125 . Therefore, as indicated by waveform 126, the reactor current flowing through reactor 13 neither increases nor decreases.

At timing _t13 , as indicated by waveform 121, a low-level drive pulse is input to the gate of transistor Tr1. As indicated by a waveform 122, a high level driving pulse is input to the gate of the transistor Tr2. As indicated by a waveform 123, a high level drive pulse is input to the gate of the transistor Tr3. As indicated by waveform 124, a low-level drive pulse is input to the gate of transistor Tr4.

At this time, as indicated by a waveform 125, the voltage -Vin is applied to the reactor 13. FIG. Therefore, as indicated by a waveform 126, the reactor current flowing through the reactor 13 linearly decreases.

Power supply device 1 according to the embodiment applies a voltage to reactor 13 only for a period of 2/10 of one cycle, as indicated by waveform 125 . That is, power supply device 1 according to the embodiment can suppress the period during which voltage is applied to reactor 13 as compared with the comparative example (see waveform 106 in FIG. 2). Therefore, the power supply device 1 of the embodiment can suppress the reactor current flowing through the reactor 13 as compared with the comparative example, as indicated by the waveform 126 .

FIG. 7 is a diagram showing the relationship between the duty ratio and the effective value of the output AC voltage of the first bridge circuit in the embodiment. The effective value of the output AC voltage of the first bridge circuit 12 on the primary side is normalized by setting the value of the output AC voltage to 1 when the duty ratio is the standard value (0.5).

As shown by the waveform 131, as the duty ratio increases or decreases from the standard value, the effective value of the output AC voltage of the first bridge circuit 12 on the primary side decreases. That is, as the duty ratio increases or decreases from the standard value, the effective value of the voltage applied to the reactor 13 is suppressed. Therefore, the reactor current flowing through the reactor 13 is suppressed.

As described above, the power supply device 1 of the embodiment can suppress the circulating current in the primary side circuit when the input/output voltage ratio is small.

As a result, the power supply device 1 according to the embodiment can suppress significant increases in stress and loss in the primary-side circuit.

Note that the control unit 18 may reduce or increase the duty ratio from the standard value based on the input/output voltage difference, which is the difference between the voltage Vin and the voltage Vout, instead of the input/output voltage ratio. That is, the controller 18 may make the duty ratio smaller or larger than the standard value as the input/output voltage difference increases.

In addition, the present disclosure does not require changing the phase of the drive pulse input to the transistors Tr1 to Tr4, and it is sufficient to change only the duty ratio. Therefore, the present disclosure is also applicable to a three-phase DAB in which the phase difference between three arms in the first bridge circuit 12 and between three arms in the second bridge circuit 15 is fixed at 120°. is.

While several embodiments of the invention have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and modifications can be made without departing from the scope of the invention. These embodiments and their modifications are included in the scope and gist of the invention, as well as the scope of the invention described in the claims and equivalents thereof.

1 power supply device 2 power supply 3, 16 capacitor 4 load 11 first voltage sensor 12 first bridge circuit 13 reactor 14 transformer 15 second bridge circuit 17 second voltage sensor 18 control section 21 deviation calculation section 22 phase difference calculation section 23 duty ratio Calculation section 24 Signal output section 25 Pulse generation section 26 Primary side pulse drive section 27 Secondary side pulse drive section

Claims (6)

a first bridge circuit including a plurality of arms each having a high-side switching element and a low-side switching element, and converting a DC voltage into an AC voltage for output;
A transformer including a first winding and a second winding, wherein an alternating voltage output from the first bridge circuit is input to the first winding and an induced alternating voltage is output from the second winding. and,
A second bridge that includes a plurality of arms each having a high-side switch element and a low-side switch element, and converts an AC voltage output from the second winding of the transformer to a DC voltage for output to a load. a circuit;
outputting a plurality of first drive pulses to the switch elements in the first bridge circuit to switch the switch elements in the first bridge circuit, and outputting a plurality of second drive pulses to the second bridge; output to the switch elements in the circuit to cause the switch elements in the second bridge circuit to perform a switching operation to determine the phase difference between the plurality of first drive pulses and the plurality of second drive pulses. a control unit that controls the DC voltage output from the second bridge circuit by controlling the
with
The control unit
Based on the first voltage input to the first bridge circuit and the second voltage of the load, control is performed to make the duty ratio of the plurality of first drive pulses smaller or larger than a standard value;
A power supply device characterized by: The control unit
performing control to make the duty ratio smaller or larger than the standard value based on the value of the ratio of the second voltage to the first voltage;
The power supply device according to claim 1, characterized in that: The control unit
As the value of the ratio becomes smaller, control is performed such that the duty ratio is made smaller or larger than the standard value;
3. The power supply device according to claim 2, characterized by: The control unit
When the value of the ratio is within a predetermined range including 1, performing control to maintain the duty ratio at the standard value;
4. The power supply device according to claim 2 or 3, characterized in that: The control unit
performing control to adjust the duty ratio according to the phase difference;
The power supply device according to any one of claims 2 to 4, characterized in that: each of the first bridge circuit and the second bridge circuit is a three-phase bridge circuit,
The transformer is a three-phase transformer,
The control unit
Perform control to fix the phase difference between the three arms of the first bridge circuit and the three arms of the second bridge circuit at 120°;
The power supply device according to any one of claims 1 to 5, characterized in that:

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