JP2023077915A - Power conversion device, method for controlling power conversion device, and program - Google Patents

Abstract

To provide a power conversion device having high reliability, a method for controlling the power conversion device, and a program.SOLUTION: A power conversion device of an embodiment has a power converter and a converter control part. The power converter includes at least one arm unit in which there is connected in series a plurality of unit converters having an energy storage element and a plurality of switching elements. The converter control part switches between a first control state in which the unit converters are made output a voltage of the energy storage element and a second control state in which the unit converters are shorted, thereby controlling conversion operation of the power converter. The converter control part has a state count computation part for calculating the number of unit converters to which the control state is allocated, a list computation part for generating list information of voltage magnitude relations for each second time interval which is longer than a first time interval in which voltages are detected, and a unit converter selection part for selecting a unit converter the control state of which is to be changed. The unit converter selection part selects another unit converters in place of a unit converter whose voltage has exceeded a threshold.SELECTED DRAWING: Figure 1

Description

TECHNICAL FIELD Embodiments of the present invention relate to a power conversion device, a power conversion device control method, and a program.

In recent years, practical use of a modular multilevel converter (MMC) has been promoted as a power converter. MMC is equipped with an arm unit containing multiple unit converters (hereinafter referred to as "cells") connected in series, and by adding the voltages output by each cell, it is possible to generate power corresponding to high voltage and large capacity. is a converter. Power converters are used, for example, in DC power transmission systems and reactive power compensators. For example, a power converter for a DC power transmission system is connected between an AC system and a DC system to mutually convert the respective powers. For example, a power converter for a reactive power compensator is connected to an AC system and adjusts the reactive power at the interconnection point.

In the power converter, switching elements included in the power converter are controlled when mutual conversion of electric power is performed or when adjustment of reactive power is performed. As a switching control method in a power converter, for example, phase shift PWM (Pulse Width Modulation) that synthesizes multistage stepped sine waves in the entire arm unit by evenly shifting the phase of the triangular wave carrier assigned to each cell. : pulse width modulation) method is known. However, in the phase shift PWM method, the frequency of the triangular wave carrier needs to be higher than the frequency of the AC system, resulting in increased loss in switching control (switching loss).

In relation to this, for example, Patent Document 1 and Patent Document 2 disclose techniques related to one-pulse control in which each cell is switched once in one cycle of the voltage of the AC system. However, in the conventional switching control, when the switching frequency is lowered, there is a problem that the variation in the voltage of the capacitor provided in each cell increases. For this reason, in a power converter, as a method for equalizing the voltages of the capacitors provided in each cell during switching control, a method for adjusting the rising phase and the falling phase of the output voltage of each cell, A method of changing the order of rise and fall of the output voltage according to the magnitude relationship of the capacitor voltage has been proposed.

The method of changing the order of rise and fall of the output voltage according to the magnitude relationship of the voltage of the capacitor provided in each cell obtains the voltage of the capacitor of each cell provided in the arm unit at regular intervals and compares it with the magnitude relationship. This can be realized by selecting a cell to be subjected to switching control. However, in this method, the time required for processing (so-called sorting processing) to rearrange the obtained voltages of the capacitors of each cell in order based on the magnitude relationship is longer than the time interval required for processing to perform switching control. There was a case. In this case, it is not easy to control to reduce the difference in the amount of charge of the capacitors provided in each cell (balance so that the amount of charge is relatively uniform). For this reason, if the cells to be subjected to switching control are selected after the sorting process is completed, it is not possible to obtain sufficient balance performance to balance the capacitor voltages, which is a factor that increases the fluctuation range of the capacitor voltages. It is also conceivable that When the fluctuation width of the capacitor voltage increases, the voltage that can be output from each cell decreases, which imposes restrictions on the operation of the power converter. Furthermore, the increase in the fluctuation range of the capacitor voltage causes the maximum value of the capacitor voltage to increase, which may be a cause of failure of the capacitor and switching elements. In this case, the reliability of the power converter is greatly reduced.

JP 2014-233126 A JP 2015-159687 A

The problem to be solved by the present invention is to provide a highly reliable power converter, a control method for the power converter, and a program by controlling a unit converter included in the power converter.

A power converter according to an embodiment has a power converter and a converter control section. A power converter is a plurality of unit converters having an energy storage element for storing power and a plurality of switching elements capable of adjusting storage of power in the energy storage element or discharge of the power stored in the energy storage element. has at least one arm unit connected in series. The converter control section includes at least a first control state for outputting a voltage between terminals of the energy storage element between a first terminal and a second terminal of the unit converter, and the first terminal of the unit converter. and a second control state in which the second end is short-circuited to control the power conversion operation in the power converter. The converter control section has a state number calculation section, a list calculation section, and a unit converter selection section. The state number calculation unit assigns one of the unit converters belonging to the arm unit to one of the control states according to an arm voltage command value that is a target value of an arm voltage to be output from the arm unit. Calculate the number of states representing the number of devices. Based on the voltage between the terminals of the energy storage element detected at a predetermined first time interval, the list calculation unit generates list information representing the magnitude relationship of the voltage between the terminals at a predetermined time interval longer than the first time interval. every second time interval of . The unit converter selector changes the current control state based on the polarity of the arm current flowing through the arm unit, the number of states, the list information, and the voltage across the terminals of the energy storage element. Select a converter. When the polarity of the arm current is a charging polarity for accumulating power in the energy storage element of the unit converter in the first control state, the unit converter selection unit selects the first time period. When the voltage across the terminals of the energy storage element of the first unit converter, which is the unit converter in the first control state, detected at intervals exceeds a first threshold higher than the rated voltage, the first One unit converter is changed to the second control state, and among the unit converters in the second control state, the same number of other unit converters as the first unit converters are changed to the first control state. is selected as the unit converter to be changed to the state, and the polarity of the arm current is a discharge period in which the polarity of the arm current discharges power from the energy storage element of the unit converter in the first control state, if the When the voltage across the terminals of the energy storage element of the second unit converter, which is the unit converter in the first control state, detected at a first time interval exceeds a second threshold lower than the rated voltage the second unit converter is changed to the second control state, and among the unit converters in the second control state, the same number of the other unit converters as the second unit converters, Select as the unit converter to be changed to the first control state.

The figure which shows an example of a structure of the power converter device which concerns on 1st Embodiment. The figure which shows an example of a structure of the cell in the leg with which a power converter is provided. The figure which shows an example of a structure of the converter control part with which a power converter device is provided. 4 is a timing chart for explaining an example of operation timing of a first operation in the power converter; 4 is a timing chart for explaining an example of operation timing of a second operation in the power converter; The figure which shows an example of a structure of the power converter device which concerns on 2nd Embodiment. The figure which shows an example of a structure of the cell in the leg with which a power converter is provided. A timing chart explaining an example of operation timing of the 3rd operation in a power converter. The timing chart explaining an example of the operation timing of the 4th operation|movement in a power converter device.

Hereinafter, a power conversion device, a control method for the power conversion device, and a program according to embodiments will be described with reference to the drawings.

(First embodiment)
[Configuration of power converter]
FIG. 1 is a diagram illustrating an example of the configuration of a power converter according to the first embodiment. FIG. 1 shows, for example, an example of a power converter 1 that is provided at an interconnection point between an AC system and a DC system and converts AC power supplied by the AC system and DC power supplied by the DC system to each other. showing. The AC system may be, for example, an AC power supply or an AC load. The DC system may be, for example, a DC power supply or a DC load. The power conversion device 1 includes a power converter 10 and a converter control section 50 .

The power converter 10 is a double star-connected modular multilevel converter (MMC) that mutually converts AC power and DC power under the control of the converter control unit 50 . The power converter 10 includes a plurality of legs 12 between a positive terminal P of the DC system and a negative terminal N of the DC system. The number of legs 12 provided in the power converter 10 corresponds to the number of phases of AC power supplied by the AC system. FIG. 1 shows a case where an AC system supplies three-phase AC power of a first phase (R phase), a second phase (S phase), and a third phase (T phase). Therefore, FIG. 1 shows the configuration of the power converter 10 including three legs 12, ie, a leg 12-R, a leg 12-S, and a leg 12-T. Each of Leg 12-R, Leg 12-S, and Leg 12-T have the same configuration.

In each leg 12, an AC terminal CA is connected to a corresponding phase terminal of the AC system. More specifically, in the leg 12-R corresponding to the R phase, the AC terminal CA-R is connected to the AC terminal R of the R phase of the AC system, and in the leg 12-S corresponding to the S phase, the AC terminal CA -S is connected to the S-phase AC terminal S of the AC system, and in the leg 12-T corresponding to the T-phase, the AC terminal CA-T is connected to the T-phase AC terminal T of the AC system. FIG. 1 shows a case where AC terminals CA of respective legs 12 are connected to corresponding phase terminals of an AC system via transformers TR.

In each leg 12, the terminal opposite the AC terminal CA is connected to the respective DC terminal of the DC system. More specifically, in each leg 12, a terminal having the same potential as the positive electrode of the DC voltage output by the power converter 10 is connected to the positive terminal P, and the negative electrode of the DC voltage output by the power converter 10 is connected to the positive terminal P. A terminal having the same potential is connected to the negative terminal N. In the following description, the terminal of leg 12 connected to positive terminal P is also referred to as DC terminal CP of leg 12, and the terminal of leg 12 connected to negative terminal N is also referred to as DC terminal CN of leg 12. say.

Each leg 12 has, for example, two reactors 14 and two arm units 16 . Each arm unit 16 includes, for example, n (n is a natural number) cells 162 (cells 162-1 to 162-n) connected in series. In FIG. 1, each component included in the leg 12 corresponds to either the positive electrode side or the negative electrode side of the DC system, or to which phase of the AC system. In order to distinguish, each symbol is followed by "- (hyphen)" and the letter "P" representing the positive electrode side or the letter "N" representing the negative electrode side, followed by a hyphen and the letter "R" representing the R phase. "R", the letter "S" representing the S phase, or the letter "T" representing the T phase. In the following description, it is not necessary to distinguish whether each component corresponds to the positive electrode side or the negative electrode side of the DC system or to which phase of the AC system. , omit the hyphen attached to the code of each component and the character for identification following the hyphen.

In each leg 12, the positive side reactor 14-P and the positive side arm unit 16-P are connected in series, and the negative side reactor 14-N and the negative side arm unit 16-N are connected in series. It is connected to the. In each leg 12, the connection point between the reactor 14-P and the reactor 14-N is the DC terminal CP. In each leg 12, the terminal opposite to the reactor 14-P in the arm unit 16-P is the DC terminal CP of the leg 12, and the terminal opposite to the reactor 14-N in the arm unit 16-N is the DC terminal of the leg 12. terminal CN. In other words, in each leg 12, the cells 162-1 to 162-n and the reactor 14-P are serially connected in this order from the DC terminal CP side toward the AC terminal CA side to the AC terminal CA. It is connected. Furthermore, in each leg 12, the cells 162-n to 162-1 and the reactor 14-N are serially connected in this order from the DC terminal CN side toward the AC terminal CA side and connected to the AC terminal CA. It is

The leg 12 is an example of a "phase unit" in the claims. The arm unit 16-P (which may include the reactor 14-P) is an example of the "first arm unit" in the claims, and the arm unit 16-N (which may include the reactor 14-N) , is an example of the "second arm unit" in the claims. Cell 162 is an example of a "unit converter" in the claims. The reactor 14 is an example of an "inductance element" in the claims.

1 shows the case where the reactor 14 is arranged on the AC terminal CA side of the arm unit 16 in each leg 12, but the reactor 14 is located on the opposite side of the arm unit 16 to the AC terminal CA side. (that is, the DC terminal CP side or the DC terminal CN side) or any position in the arm unit 16 (that is, the position between any two cells 162 connected in series in the arm unit 16). good too. The reactor 14 may be replaced with a transformer with a special winding structure having a leakage reactance sufficient to replace the function of the reactor. In this case, reactor 14 may be integrated with transformer TR.

Each arm unit 16, in response to control from the converter controller 50 for each series-connected cell 162, multi-level, stepped sine wave representing the AC waveform supplied to the corresponding phase of the AC system. Generates a waveform AC voltage.

Here, an example of the configuration of the cell 162 included in the arm unit 16 will be described. Cell 162 is, for example, a half-bridge circuit. FIG. 2 is a diagram showing an example of the configuration of the cells 162 in the leg 12 included in the power converter 10. As shown in FIG. The cell 162 comprises two switching elements Q (switching element Q1 and switching element Q2), two diodes D (diode D1 and diode D2), and a capacitor C. The switching element Q is, for example, an insulated gate bipolar transistor (IGBT). The switching element Q is not limited to IGBT. The switching element Q may be any element as long as it is a self arc-extinguishing semiconductor switching element capable of realizing a converter or an inverter.

In cell 162, switching element Q1 and switching element Q2 are connected in series with each other. In the cell 162, the series circuit of the switching element Q1 and the switching element Q2 and the capacitor C are connected in parallel with each other. In cell 162, each switching element Q and corresponding diode D are connected in parallel with each other. In the cell 162, the connection point between the emitter of the switching element Q1 and the collector of the switching element Q2 becomes the positive terminal TP(+) connected to the positive terminal P side in the leg 12, and the emitter of the switching element Q2 and the capacitor C is a negative terminal TN(−) connected to the negative terminal N side of the leg 12 .

A control signal from the converter control unit 50 is input to the gates of the switching element Q1 and the switching element Q2 provided in the cell 162 (a control voltage is applied or a control current is supplied). A gate signal gtp is input as a control signal from the converter control unit 50 to the gate of the switching element Q1, and a gate signal gtn is input as a control signal from the converter control unit 50 to the gate of the switching element Q2. . Thereby, each of the switching element Q1 and the switching element Q2 is switched to either an ON state or an OFF state by the converter control section 50 . In the following description, when a control signal (gate signal gtp, gate signal gtn) of "1 ("High" level)" is input, each switching element Q is turned on, and "0 ("Low" level) is input. , to which the control signals (gate signal gtp, gate signal gtn) are input, are turned off.

Capacitor C is charged or discharged depending on the state of the respective switching element Q. FIG. In the cell 162, the voltage between the terminals of the capacitor C (hereinafter referred to as “capacitor voltage Vc”) is the voltage between the positive terminal TP and the negative terminal TN of the cell 162 (hereinafter referred to as “cell voltage Vo”). occur. More specifically, when the converter control unit 50 sets the control signal (gtp, gtn) to (1, 0), for example, current flows through the positive terminal TP, the switching element Q1, the capacitor C, and the negative terminal TN in this order. Thus, cell voltage Vo of cell 162 matches capacitor voltage Vc. That is, when the converter control unit 50 sets the control signal (gtp, gtn) to (1, 0), the capacitor C is inserted between the positive terminal TP and the negative terminal TN of the cell 162, and the capacitor voltage Vc is output as the cell voltage Vo. In the following description, when the converter control section 50 sets the control signals (gtp, gtn) to (1, 0), it is called "insertion", and the state of the cell 162 in this case is called "insertion state". On the other hand, when the converter control unit 50 sets the control signal (gtp, gtn) to (0, 1), for example, current flows in the order of the positive terminal TP, the switching element Q2, and the negative terminal TN, and the cell voltage Vo of the cell 162 becomes 0 [V]. That is, when the converter control unit 50 sets the control signal (gtp, gtn) to (0, 1), the positive terminal TP and the negative terminal TN of the cell 162 are short-circuited, and the current flows without passing through the capacitor C. As a result, the cell voltage Vo of the cell 162 becomes 0 [V]. In the following description, setting the control signals (gtp, gtn)=(0, 1) by the converter control section 50 is called "bypass", and the state of the cell 162 in this case is called "bypass state".

The cell 162 is not limited to the configuration shown in FIG.

The switching element Q1 and the diode D1 are examples of the "switching element" and the "first switching element" in the claims, and the switching element Q2 and the diode D2 are examples of the "switching element" and the "first switching element" in the claims. 2 switching element”. The on state is an example of a "conducting state" in the scope of claims, and the off state is an example of a "non-conducting state" in the scope of claims. Capacitor C is an example of an "energy storage element" in the claims. The positive terminal TP is an example of the "first end" in the claims, and the negative terminal TN is an example of the "second end" in the claims. The insert state is an example of a "first control state" in the claims, and the bypass state is an example of a "second control state" in the claims.

By connecting a plurality of cells 162 having such a configuration in series, the arm unit 16 outputs a voltage obtained by adding the cell voltage Vo of each cell 162 controlled to the insert state. Therefore, the arm unit 16 outputs a voltage corresponding to the number of cells 162 controlled to the insert state by the converter control section 50 . Thereby, the arm unit 16 generates a multilevel waveform according to control from the converter control section 50 .

By the way, in cell 162, the control signals (gtp, gtn)=(1, 1) should be prohibited. This is because when the control signals (gtp, gtn)=(1, 1), both the switching elements Q1 and Q2 are turned on and both ends of the capacitor C are short-circuited. For this reason, the converter control section 50 requires a very short time when changing from the control signal (gtp, gtn)=(1,0) to the control signal (gtp, gtn)=(0,1) or vice versa. Control is performed so as to provide a period during which the control signals (gtp, gtn)=(0, 0) transitionally, that is, a so-called dead time. When stopping the operation of the cell 162, the converter control unit 50 may fix the control signal (gtp, gtn)=(0, 0). In the following description, the converter control unit 50 fixes all control signals (gtp, gtn) to (0, 0) to stop the operation of all the cells 162 of the arm unit 16 provided in the power converter 10. This is called "gate block", and the state of the cell 162 in this case is called "gate block state".

Returning to FIG. 1, the converter control unit 50 is based on the operating state of the power converter 1 and the detected values (current value, current flow direction (polarity), voltage value) at each position in the power converter 1. Then, an AC voltage command value and a DC voltage command value including the frequency of the AC system are calculated. For this reason, the converter control unit 50 acquires, for example, a detection value output by a detector (described later) provided at a desired position inside or outside the power conversion device 1 at each predetermined (constant) acquisition cycle TS1. . Then, the converter control unit 50 obtains a voltage command value for each arm unit 16, including the voltage component represented by the calculated AC voltage command value and DC voltage command value. The converter control unit 50 generates a control signal for controlling (switching control) the switching element Q in the cell 162 provided in each arm unit 16 based on the determined voltage command value. The converter control section 50 then outputs the generated control signal to the corresponding cell 162 . For example, when the converter control unit 50 controls the arm unit 16-PR, which corresponds to the R phase of the AC system and is connected to the positive electrode side of the DC system, the AC terminal CA-R An arm voltage command value Varm* to be output to the arm unit 16-PR is calculated based mainly on the AC voltage component to be output and mainly on the DC voltage component to be output between the DC terminal CP-R and the DC terminal CN-R. . In the following description, the positive polarity of arm voltage Varm and arm voltage command value Varm* is defined in the direction in which the potential on the cell 162-1 side becomes higher when viewed from the cell 162-n side. Based on the calculated arm voltage command value Varm*, the converter control unit 50 controls each cell 162 (cells 162-1-PR to 162-nP- R), gate signals gtp (gate signals gtp-1-PR to gtp-nPR) and gate signals gtn (gate signals gtn-1-P- R˜gtn-nPR). The converter control section 50 outputs each of the generated gate signal gtp and gate signal gtn to the corresponding cell 162 . The same applies when the converter control section 50 controls other arm units 16 . The converter control unit 50 includes, for example, an insert number calculation unit 52, a sort list calculation unit 54, a cell selection control unit 56, and a gate signal generation unit 58.

Converter control part 50 controls operation of electric power converter 10, for example because hardware processors, such as CPU (Central*Processing*Unit), run a program (software). The converter control unit 50 is implemented by hardware (including circuitry) such as LSI (Large Scale Integration), ASIC (Application Specific Integrated Circuit), FPGA (Field-Programmable Gate Array), and GPU (Graphics Processing Unit). It may be realized by cooperation of software and hardware. The converter control section 50 may be realized by a dedicated LSI. The program may be stored in advance in a storage device (a storage device having a non-transitory storage medium) such as an HDD (Hard Disk Drive) or a flash memory provided in the converter control unit 50 or the power conversion device 1. , stored in a detachable storage medium (non-transitory storage medium) such as a DVD or CD-ROM, and the storage medium is installed in the drive device provided in the converter control unit 50 or the power conversion device 1 may be installed in the HDD or flash memory provided in the converter control unit 50 or the power converter 1 .

In the power converter 1, current detectors and voltage detectors are provided at desired positions to detect current values, current polarities, and voltage values. In the example of FIG. 1, each leg 12 includes a current detector for detecting the positive arm current Ip flowing from the positive terminal P side to the AC terminal CA side, and a current detector for detecting the positive arm current Ip flowing from the AC terminal CA side to the negative terminal N side A current detector is provided for detecting the negative-side arm current In flowing through the . More specifically, in the leg 12-R, between the arm unit 16-PR and the reactor 14-PR, there is a positive arm current Ipr that flows from the positive terminal P side to the AC terminal CA-R side. is provided, and the negative arm current Inr flowing from the AC terminal CA-R side to the negative side terminal N side between the arm unit 16-NR and the reactor 14-NR A current detector is provided for detecting the Other legs 12 are similar. Although not shown in FIG. 2, each cell 162 is also provided with a voltage detector for detecting the capacitor voltage Vc. The R-phase AC current Isr, the S-phase AC current Iss, and the T-phase AC current Ist are directly detected by providing current detectors at the AC terminals R, S, and T, respectively. may be detected indirectly by calculating the positive arm current Ip and the negative arm current In detected in each leg 12 . For example, the R-phase alternating current Isr may be indirectly detected by calculating the difference between the positive arm current Ipr and the negative arm current Inr (that is, Inr−Ipr). Furthermore, FIG. 1 does not show voltage detectors, but shows the case where the R-phase AC voltage Vsr, the S-phase AC voltage Vss, and the T-phase AC voltage Vst are detected. .

FIG. 3 is a diagram showing an example of the configuration of the converter control section 50 included in the power converter 1. As shown in FIG.

At least the arm voltage command value Varm* to be output by the arm unit 16 is input to the insert number calculation unit 52 . The arm voltage command value Varm* is the voltage to be output to the AC system or the DC system, which is obtained as a result of calculation such as voltage/current control based on the operating state of the power conversion device 1 and each detection value in the power conversion device 1. It is a value (real value) obtained by distributing the component to each arm unit 16 . The insert number calculation unit 52 represents the number (integer value) of the cells 162 assigned to the insert state (to be put in the insert state) among the cells 162 provided in each arm unit 16 according to the arm voltage command value Varm*. The number Ncells is calculated (calculated) for each arm unit 16 . The insert number calculation unit 52 outputs the calculated insert number Ncells to the cell selection control unit 56 .

There are various methods for the insert number calculation unit 52 to calculate (calculate) the insert number Ncells. For example, the insert number calculation unit 52 divides the arm voltage command value Varm* by the average value or rated value of the capacitor voltage Vc of the cell 162 belonging to the arm unit 16, and approximates the value to an integer, thereby approximating the cell to be placed in the inserted state. Calculate the number of inserts Ncells representing 162 numbers. In this case, the converter control unit 50 controls the cells 162 belonging to the arm unit 16 once within one cycle of the AC voltage in the AC system (insert state and bypass state), and performs 1-pulse control. Become. For example, the insert number calculation unit 52 generates the modulated wave based on the arm voltage command value Varm* and the phase-shifted waves of the same number as the number of cells 162 belonging to the arm unit 16 (“n” in FIG. 1). Triangular wave carriers are compared, and the number of triangular wave carrier waves in which the value of the arm voltage command value Varm* (modulation wave) exceeds the value of the triangular wave carrier (becomes larger than the value of the triangular wave carrier) is the number of cells 162 that are placed in the insert state. is calculated as the number of inserts Ncells. In this case, the converter control unit 50 performs multi-pulse control in which the cells 162 belonging to the arm unit 16 are controlled multiple times (inserted state and bypass state) within one cycle of the AC voltage in the AC system. . For example, the insert number calculation unit 52 generates a modulated wave based on the arm voltage command value Varm* and the same number of cells 162 belonging to the arm unit 16 ("n" in FIG. 1), the levels of which are shifted from each other. Triangular wave carriers are compared, and the number of triangular wave carrier waves in which the value of the arm voltage command value Varm* (modulation wave) exceeds the value of the triangular wave carrier (becomes larger than the value of the triangular wave carrier) is the number of cells 162 that are placed in the insert state. is calculated as the number of inserts Ncells. Also in this case, the converter control section 50 performs multi-pulse control. The method by which the insert number calculation unit 52 calculates (calculates) the insert number Ncells is not limited to the method described above, and the value (real value) distributed for each arm unit 16 is used to determine the number of cells 162 (integer Any method can be used as long as it can be expressed as a numerical value.

The insert number calculator 52 is an example of a "state number calculator" in the claims. The number of inserts Ncells is an example of the "number of states" in the claims.

The sort list computing unit 54 computes (generates) a sort list representing the magnitude relationship between the capacitor voltages Vc of the cells 162 included in the power converter 10 for each arm unit 16 . The sorted list calculation unit 54 generates a sorted list, for example, for each predetermined (constant) calculation period TS2. The sort list contains voltages of capacitor voltages Vc of at least two or more cells 162 belonging to the same arm unit 16 (capacitor voltages Vc-1 to Vc-n of cells 162-1 to 162-n in FIG. 3). The values are sorted in descending or ascending order based on the magnitude relationship of the values. The calculation cycle TS2 in which the sort list calculation unit 54 generates the sort list is a cycle of time intervals longer than the acquisition cycle TS1 in which each detection value in the power converter 1 is acquired (TS2>TS1). This is because it is considered that it takes time to rearrange the acquired voltage values of the plurality of capacitor voltages Vc in the sort list calculation unit 54 . Therefore, the sort list calculation unit 54 performs sorting based on the voltage values of the capacitor voltage Vc acquired in the acquisition cycle TS1 that matches the timing of generating the next sort list in the computation cycle TS2, that is, the timing of updating the sort list. Generate a list. For example, the sort list calculation unit 54 secures the time required for the process of sorting the voltage values of the capacitor voltage Vc, and then the voltage of the capacitor voltage Vc acquired in the acquisition cycle TS1 immediately before the timing of starting the generation of the sort list. Generates a sorted list by permuting the values. The voltage value of the capacitor voltage Vc used when the sorted list calculation unit 54 generates the sorted list is not limited to the value obtained at the timing immediately before starting the generation of the sorted list described above. An average value or a maximum value of the voltage values of the capacitor voltage Vc corresponding to the same capacitor C acquired in step 1 may be used. In the following description, it is assumed that the sort list calculation unit 54 generates a sort list in which the voltage values of the capacitor voltage Vc are sorted in descending order. The sort list calculator 54 outputs the generated sort list to the cell selection controller 56 .

The sort list calculator 54 is an example of a "list calculator" in the scope of claims. A sort list is an example of "list information" in the claims.

The cell selection control unit 56 changes the current control at least at each timing when the number of inserts Ncells output by the number-of-inserts calculation unit 52 changes, that is, at each control timing for controlling the cell 162 (putting it in the insert state and the bypass state). Select the cell 162 whose state you want to change. More specifically, the cell selection control unit 56 starts selecting the cells 162 when the number of inserts Ncells has changed. Then, the cell selection control unit 56 determines the polarity of the arm current Iarm (that is, the positive side arm current Ip and the negative side arm current In) flowing through the arm unit 16 to be controlled, and the control target output by the sort list calculation unit 54. By referring to the sort list of the arm unit 16, the cell 162 to be changed to the insert state or the cell 162 to be changed to the bypass state is selected.

When the number of inserts Ncells increases, the cell selection control unit 56 accumulates power in the capacitor C of the cell 162 whose polarity of the arm current Iarm is in the inserted state, thereby increasing the amount of charge in the entire arm unit 16. In the period (charging period) in which the charging polarity is to allow the current to be changed to the insert state, the cell 162 having the capacitor C in which the stored power is small is preferentially selected from among the cells 162 currently in the bypass state as the cell 162 to be changed to the insert state. . In this case, the cell selection control unit 56 refers to the sort list and sequentially selects cells 162 having capacitors C with relatively low capacitor voltages Vc. The charge polarity is the polarity in which the arm current Iarm flows in the same direction as the positive side arm current Ip and the negative side arm current In shown in FIG. On the other hand, when the number of inserts Ncells increases, the cell selection control unit 56 discharges the power accumulated in the capacitor C of the cell 162 whose polarity of the arm current Iarm is in the inserted state, and the arm unit 16 In a period (discharge period) with a discharge polarity that increases the overall amount of discharge, the cell 162 having a capacitor C with a large amount of stored power is preferentially changed from among the cells 162 currently in the bypass state to the insert state. cell 162 to be used. In this case, the cell selection control unit 56 refers to the sort list and sequentially selects cells 162 having capacitors C with relatively high capacitor voltages Vc. The discharge polarity is the polarity in which the arm current Iarm flows in the opposite direction to the positive side arm current Ip and the negative side arm current In shown in FIG.

When the number of inserts Ncells is decreased, the cell selection control unit 56 accumulates power in the capacitor C of the cell 162 whose polarity of the arm current Iarm is in the inserted state, thereby increasing the charge amount of the entire arm unit 16. In the period (charging period) in which the charging polarity is to allow the charging to be performed, the cell 162 having the capacitor C in which a large amount of power is stored is preferentially selected as the cell 162 to be changed to the bypass state from among the cells 162 currently in the insert state. . In this case, the cell selection control unit 56 refers to the sort list and sequentially selects cells 162 having capacitors C with relatively high capacitor voltages Vc. On the other hand, when the number of inserts Ncells decreases, the cell selection control unit 56 discharges the power accumulated in the capacitor C of the cell 162 in which the polarity of the arm current Iarm is in the inserted state. During a period (discharge period) that has a discharge polarity that increases the overall discharge amount, among the cells 162 that are currently in the inserted state, the cell 162 that has a capacitor C with a small amount of stored power is preferentially changed to the bypass state. cell 162 to be used. In this case, the cell selection control unit 56 refers to the sort list and sequentially selects cells 162 having capacitors C with relatively low capacitor voltages Vc.

As a result, the cell 162 having a capacitor C with a relatively high capacitor voltage Vc has a short charging time and a long discharging time preferentially. The voltage Vc will be uniformed. On the other hand, the cell 162 having a capacitor C with a relatively low capacitor voltage Vc is preferentially charged for a long time and discharged for a short time. The capacitor voltage Vc will be uniformed.

Furthermore, the cell selection control unit 56 performs control to reduce the difference in the amount of charge in the capacitor C (balance so that the amount of charge is relatively uniform) in each cell 162 provided in the arm unit 16 . Hereinafter, the control in which the charge amount of the capacitor C (more specifically, the capacitor voltage Vc) in the cell selection control section 56 is balanced to be uniform is referred to as "balance control". In the balance control in the cell selection control unit 56, the capacitor voltage Vc of the cells 162 belonging to the same arm unit 16 is obtained every acquisition cycle TS1, that is, in a cycle shorter than the calculation cycle TS2 in which the sort list calculation unit 54 generates the sort list. (In FIG. 3, capacitor voltages Vc-1 to Vc-n of cells 162-1 to 162-n) are obtained. Then, the cell selection control unit 56 compares the acquired voltage value of each capacitor voltage Vc with the upper threshold value Vc-max and the lower threshold value Vc-min of the capacitor voltage Vc in the capacitor C. FIG. As a result of this comparison, if the capacitor voltage Vc of the cell 162 in the inserted state exceeds the threshold Vc-max during the charging period, the cell selection control unit 56 prevents further charging of the cell 162 ( In other words, the cells 162 are controlled to the bypass state so as not to be overcharged, and instead, the same number of other cells 162 having capacitors C with a low voltage value of the capacitor voltage Vc are preferentially selected from among the cells 162 in the bypass state. to change to the insert state. On the other hand, when the capacitor voltage Vc of the cell 162 in the inserted state exceeds the threshold value Vc-min during the discharge period, the cell selection control unit 56 prevents further discharge from the cell 162 (that is, excessive instead, from among the cells 162 in the bypass state, preferentially select the same number of other cells 162 equipped with capacitors C having a high voltage value of the capacitor voltage Vc, Change to insert state. For the threshold Vc-max and the threshold Vc-min, for example, values are set in consideration of the allowable fluctuation range of the capacitor C with respect to the rated capacitor voltage command value Vc*. More specifically, the threshold Vc-max is, for example, the upper limit value of the fluctuation range of the capacitor voltage Vc during normal operation of the power converter 10, and Vc-max=Vc*×, which is higher than the rated capacitor voltage command value Vc*. It is set to about 1.1. The threshold Vc-min is, for example, the lower limit value of the fluctuation range of the capacitor voltage Vc during normal operation of the power converter 10, and is set to about Vc-min=Vc*×0.9, which is lower than the rated capacitor voltage command value Vc*. be done. Threshold Vc-max and threshold Vc-min may be set based on average voltage Vc-ave (fluctuation value) of capacitor voltage Vc in capacitor C provided in arm unit 16 . The threshold Vc-max is, for example, about Vc-max=Vc-ave×1.1, which is higher than the average voltage Vc-ave so that the capacitor voltage Vc of the capacitor C does not vary from the average voltage Vc-ave by a certain amount or more. set. The threshold Vc-min is, for example, about Vc-min=Vc-ave×0.9, which is lower than the average voltage Vc-ave so that the capacitor voltage Vc of the capacitor C does not vary from the average voltage Vc-ave by a certain amount or more. set.

The cell selection control unit 56 generates a cell control state CL* for each cell 162. FIG. At this time, the cell selection control unit 56 controls the calculation (generation) timing of the sort list in the sort list calculation unit 54, the balance control timing in the sort list calculation unit 54, the converter control unit 50, and the converter control unit 50. The cell control state CL* may be generated at any timing that matches the timing of the operating cycle of the component (so-called operating clock or operation clock). The cell control state CL* includes at least information indicating whether the corresponding cell 162 is to be controlled to the insert state or the bypass state. The cell selection control section 56 outputs the cell control state CL* corresponding to each cell 162 to the gate signal generation section 58 . FIG. 3 shows the cell control states CL*-1 to CL*-n corresponding to the cells 162-1 to 162-n, respectively.

The cell selection control section 56 is an example of a "unit converter selection section" in the claims. The acquisition period TS1 is an example of a "first time interval" in the scope of claims, and the calculation period TS2 is an example of a "second time interval" in the scope of claims. The threshold Vc-max is an example of a "first threshold" in the scope of claims, and the threshold Vc-min is an example of a "second threshold" in the scope of claims.

The gate signal generator 58 generates control signals (gate signals) to be output to all the cells 162 included in each arm unit 16 according to each cell control state CL* output by the cell selection controller 56 . More specifically, the gate signal generator 58 generates a gate signal gtp corresponding to the switching element Q1 provided in each cell 162 and a gate signal gtn corresponding to the switching element Q2. FIG. 3 shows gate signals gtp-1 to gtp-n and gate signals gtn-1 to gtn-n corresponding to the cells 162-1 to 162-n, respectively. At this time, the gate signal generator 58 may generate the gate signal gtn by logically inverting the gate signal gtp, for example. However, even in this case, as described above, a short dead time is provided in order to prevent both ends of the capacitor C provided in the cell 162 from being short-circuited. The gate signal generator 58 outputs each generated gate signal to the corresponding cell 162 (more specifically, the switching element Q included in the cell 162).

FIG. 3 shows a configuration in which the gate signal generator 58 generates a gate signal corresponding to each cell 162 and outputs it to the corresponding cell 162. For example, the cell selection controller 56 is in the cell control state CL* may be output to each cell 162 and a gate signal corresponding to the cell control state CL* may be generated within each cell 162 . In this case, each cell 162 is configured to have components having functions equivalent to those of the gate signal generator 58 .

With such a configuration, the converter control unit 50 controls the cells 162 in the respective arm units 16 provided in the power converter 10 to supply the power converter 10 with AC power of the AC system and DC power of the DC system. and convert to each other.

By the way, in the conventionally well-known phase shift PWM method, an individual triangular wave carrier and voltage command value (modulation wave) are assigned to each cell, and a control signal (gate signal) is calculated for each cell. On the other hand, in the converter control unit 50, the insert number calculation unit 52 is, for example, a triangular wave carrier that is not assigned to each cell 162, and a modulated wave based on the arm voltage command value Varm* for each arm unit 16 Based on this, the insert number Ncells representing the number of cells 162 to be put into the insert state is calculated (calculated). Then, in the converter control unit 50, the cell selection control unit 56 refers to the polarity of the arm current Iarm and the sort list output by the sort list calculation unit 54, triggered by at least the change in the number of inserts Ncells. to select the cell 162 to be changed to the insert state or the bypass state. Thereby, the gate signal generator 58 generates a gate signal for turning on or off the switching element Q included in each cell 162 . That is, in the converter control section 50, there are no triangular wave carriers and voltage command values (modulation waves) individually assigned to each cell.

Furthermore, in the conventional phase-shift PWM method, by adjusting the amplitude of the voltage command value (modulation wave) for each cell, the average power flowing into and out of the cell over a relatively long period can be manipulated to equalize the capacitor voltage. Plan. For this reason, in the conventional phase-shift PWM method, it takes a long time to balance the charge amounts of the capacitors provided in the respective cells so that they become relatively uniform. On the other hand, in the converter control unit 50 of the embodiment, the cell selection control unit 56 changes the charge amount of the capacitor C included in the cell 162 relative to each timing of switching control of the switching element Q in the cell 162, for example. balance can be controlled so as to be substantially uniform. Therefore, in the converter control unit 50 of the embodiment, it is possible to equalize the charging amount of the capacitor C in a shorter time than the conventional phase shift PWM method. As a result, the power converter 10 suppresses the fluctuation range of the capacitor voltage Vc by the balance control of the capacitor voltage Vc by the converter control unit 50 of the embodiment, secures the voltage that can be output for each cell 162, and operates. constraints can be alleviated. In the power converter 10, the balance control of the capacitor voltage Vc by the converter control unit 50 of the embodiment suppresses the maximum value of the capacitor voltage Vc, thereby reducing the risk of failure of the capacitor C and the switching element Q included in the cell 162. can do.

For these reasons, the power converter 1 can simultaneously obtain high capacitor voltage balance performance in the power converter 10 and high reliability with a reduced risk of failure. Moreover, in the power converter 1, balance control by the converter control unit 50 (more specifically, the cell selection control unit 56) is performed when the capacitor voltage Vc exceeds the threshold Vc-max or the threshold Vc-min. Therefore, in the power converter 10, for example, even when the fluctuation width of the capacitor voltage Vc is narrow, such as during low-power operation, the period of switching control for the cell 162 is short, that is, the switching frequency is You can prevent it from getting too high. Furthermore, in the power conversion device 1, for example, even when a system failure or the like occurs, the balance control by the converter control unit 50 operates so as to suppress the capacitor voltage Vc from deviating from the normal voltage range. , it is possible to reduce the risk of a state where the protection device of the power converter 10 is activated and the operation is stopped when the capacitor voltage Vc reaches an overvoltage or an undervoltage. Therefore, in the power conversion device 1, it is possible to improve the continuous performance of operation when a system fault occurs.

[First operation of the power converter]
Next, an example of the operation of the power converter 1, that is, the control of the cell 162 in the converter control unit 50 will be described. In the following description, the leg 12-R, the leg 12-S, and the leg 12-T provided in the power converter 10 are represented, and the arm unit 16-P provided in the leg 12-R The control for -R will be explained. In the following description, for ease of explanation, it is assumed that the converter control unit 50 itself performs the operation of each component included in the converter control unit 50 .

FIG. 4 is a timing chart explaining an example of the operation timing of the first operation in the power conversion device 1. As shown in FIG. An example of the operation of the power conversion device 1 shown in FIG. It is an example of operation. FIG. 4 shows an example of balance control of the converter control unit 50 when the capacitor voltage Vc-5 of the cell 162-5 provided in the arm unit 16 exceeds the threshold Vc-min (when it falls below the threshold Vc-min). is shown. FIG. 4 shows arm voltage command value Varm*, arm current Iarm, arm voltage Varm generated by arm unit 16 based on arm voltage command value Varm*, and cell 162-1 to cell 162- The temporal changes of the gate signals gtp-1 to gtp-6 output to the switching element Q1 provided in 6 are shown on the same time axis. FIG. 4 also shows a schematic change in the capacitor voltage Vc (Vc-5) of the cell 162-5 whose balance is controlled by the converter control section 50 on the same time axis. Furthermore, FIG. 4 shows an example of a sort list calculated (generated) by the converter control unit 50 (more specifically, the sort list calculation unit 54). In the first operation shown in FIG. 4, the sort list is generated (updated) for each cycle of the arm voltage command value Varm*. FIG. 4 also shows an example of an acquisition cycle TS1 for acquiring the voltage value of the capacitor voltage Vc-5 and an example of the calculation cycle TS2 for creating the sort list.

The arm voltage command value Varm* includes the frequency of the AC system and the DC component. As described above, the converter control unit 50 (more specifically, the insert number calculation unit 52) determines the insert number Ncells represented by a stepped pseudo sine wave based on the arm voltage command value Varm*. is calculated (calculated). In FIG. 4, the number of inserts Ncells is an integer value with a minimum value of "0" and a maximum value of "n (here, "6")". The number of inserts Ncells is calculated, for example, by dividing the arm voltage command value Varm* by the average value or rated value of the capacitor voltages Vc of the cells 162 belonging to the arm unit 16 and approximating the value to an integer. That is, the operation timing of the power converter 1 shown in FIG. 4 is the operation timing when the converter control section 50 performs 1-pulse control. The number of inserts Ncells represents the equivalent of the arm voltage Varm shown in FIG.

The converter control unit 50 (more specifically, the cell selection control unit 56 and the gate signal generation unit 58) controls the insert state cells 162 belonging to the arm unit 16 to change to the insert number Ncells each time the insert number Ncells changes. The gate signal gtp output to each cell 162 is controlled so as to match the number (integer value) of cells 162 to be put into the insert state indicated by Ncells. Each gate signal gtp turns on the switching element Q1 when it is "1 ("High" level)" and turns off the switching element Q1 when it is "0 ("Low" level). be. Here, the gate signal gtn to be output to the switching element Q2 included in the cell 162 can be generated by logically inverting the gate signal gtp as described above. Therefore, illustration of the gate signal gtn is omitted in FIG. Thus, in FIG. 4, the cell 162 is in the insert state when the gate signal gtp is "1" and in the bypass state when the gate signal gtp is "0". Furthermore, dead time is omitted in FIG. 4 for ease of explanation. When the capacitor voltage Vc of the cells 162 is uniformly controlled, the arm voltage Varm is approximately the voltage value obtained by multiplying the number (integer value) of cells 162 to be placed in the inserted state represented by the number of inserts Ncells by the capacitor voltage Vc.

The arm current Iarm includes the frequency of the AC system and the DC component. In the arm unit 16, when the arm current Iarm is positive (Iarm>0), the capacitor C included in the inserted cell 162 is charged, and the capacitor voltage Vc increases during this charging period. In the arm unit 16, when the arm current Iarm is negative (Iarm<0), the capacitor C included in the inserted cell 162 is discharged, and the capacitor voltage Vc drops during this discharging period. In the arm unit 16, regardless of the polarity of the arm current Iarm, the capacitor C included in the bypassed cell 162 is neither charged nor discharged, and maintains the current capacitor voltage Vc.

At time t0 shown in FIG. 4, the number of inserts Ncells is "3". And since the polarity of the arm current Iarm at this time is negative, the converter control part 50 determines with it being discharge polarity. For this reason, the converter control unit 50 refers to the sort list and selects the cell 162 having the capacitor C in which a large amount of power is stored as the cell 162 to be placed in the insert state. More specifically, converter control 50 selects cells 162-1 and 162-2 which are the three highest capacitor voltages Vc (Vc-1, Vc-2, and Vc-3) in the sort list. , and cell 162-3. Therefore, at time t0 shown in FIG. 4, the converter control unit 50 causes the gate signals gtp-1, gtp-2, and gtp- 3 is set to "1". Here, cell 162-5 is in a bypass state because gate signal gtp-5 is "0". Therefore, the capacitor C-5 of the cell 162-5 is neither charged nor discharged, and maintains the current capacitor voltage Vc-5.

After that, at time t1, when the number of inserts Ncells changes (increases) to "4", the converter control unit 50 determines that the polarity of the arm current Iarm at this time is negative (discharge polarity). Therefore, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently bypassed and has the capacitor C with the next highest amount of stored power as the cell 162 to be placed in the insert state. Here, converter control 50 has already selected three cells 162 that are the third highest capacitor voltages Vc in the sort list, so the next highest capacitor voltage Vc (i.e., the fourth Select cell 162-4 with high Vc-4). At time t1, the converter control unit 50 sets the gate signal gtp-4 to "1" in order to further insert the selected cell 162-4. At this time as well, since the cell 162-5 is in the bypass state, the cell 162-5 continues to maintain the current capacitor voltage Vc-5.

After that, at time t2, when the number of inserts Ncells changes (increases) to "5", the converter control unit 50 determines that the polarity of the arm current Iarm at this time is positive (charging polarity). Therefore, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently bypassed and has a capacitor C with a small amount of stored power as the cell 162 that is to be placed in the insert state. Here, the converter control unit 50 selects the cell 162-6 that is the first (that is, Vc-6) in the sort list with the lowest capacitor voltage Vc. At time t2, the converter control section 50 sets the gate signal gtp-6 to "1" in order to further insert the selected cell 162-6. At this time as well, since the cell 162-5 is in the bypass state, the cell 162-5 continues to maintain the current capacitor voltage Vc-5.

After that, at time t3, when the number of inserts Ncells changes (increases) to "6", the converter control unit 50 determines that the polarity of the arm current Iarm at this time is positive (charging polarity). Therefore, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently bypassed and has the capacitor C with the next lowest stored power as the cell 162 to be placed in the insert state. Here, since the converter control unit 50 has already selected one cell 162 that has the first lowest capacitor voltage Vc in the sort list, the next lowest capacitor voltage Vc (that is, the second lowest Vc-5), cell 162-5 is selected. At time t3, the converter control unit 50 sets the gate signal gtp-5 to "1" in order to further insert the selected cell 162-5. As a result, the capacitor C-5 of the cell 162-5 is charged, and the capacitor voltage Vc-5 rises (increases) as the cell 162-5 is charged.

After that, at time t4, when the number of inserts Ncells changes (decreases) to "5", the converter control unit 50 determines that the polarity of the arm current Iarm at this time is positive (charging polarity). Therefore, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently inserted and has a capacitor C with a large amount of stored power as the cell 162 that is to be bypassed. Here, the converter control section 50 selects the cell 162-1 that is the first (that is, Vc−1) in the sort list with the highest capacitor voltage Vc. At time t4, the converter control unit 50 sets the gate signal gtp-1 to "0" in order to bring the selected cell 162-1 into the bypass state. At this time as well, since the cell 162-5 is in the inserted state, the capacitor C-5 continues to be charged and the capacitor voltage Vc-5 rises.

After that, at time t5, when the number of inserts Ncells changes to "4" (decreases), the converter control unit 50 selects the second highest capacitor voltage Vc in the sort list as at time t4 (that is, Vc-2), and the gate signal gtp-2 is set to "0" in order to bypass the selected cell 162-2. At this time as well, since the cell 162-5 is in the inserted state, the capacitor C-5 continues to be charged and the capacitor voltage Vc-5 rises.

After that, at time t6, when the polarity of the arm current Iarm becomes negative (discharge polarity), the cell 162-5 in the inserted state discharges the power accumulated in the capacitor C-5. Therefore, the capacitor voltage Vc-5 drops (decreases) as the discharge progresses.

After that, at time t7, when the number of inserts Ncells changes (decreases) to "3", the converter control unit 50 determines that the polarity of the arm current Iarm at this time is negative (discharge polarity). Therefore, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently inserted and has a capacitor C with a small amount of stored power as the cell 162 to be bypassed. Here, the converter control unit 50 selects the cell 162-6 that is the first (that is, Vc-6) in the sort list with the lowest capacitor voltage Vc. At time t6, the converter control section 50 sets the gate signal gtp-6 to "0" in order to bring the selected cell 162-6 into the bypass state. At this time as well, since the cell 162-5 is in the inserted state, the power stored in the capacitor C-5 continues to be discharged, and the capacitor voltage Vc-5 continues to drop.

After that, at time t8, when the capacitor voltage Vc-5 of cell 162-5 exceeds the threshold Vc-min, converter control unit 50 refers to the sort list to put cell 162-5 in the bypass state. selects the cell 162 that is currently bypassed and has a capacitor C with high stored power as the cell 162 to be inserted instead of the bypassed cell 162-5. Here, the converter control section 50 selects the cell 162-1 that is the first (that is, Vc−1) in the sort list with the highest capacitor voltage Vc. At time t8, the converter control unit 50 sets the gate signal gtp-5 to "0" in order to bring the cell 162-5 into the bypass state. As a result, the discharge from the cell 162-5 is stopped and the discharge from the capacitor C-5 provided in the cell 162-5 is continued, so that the capacitor voltage Vc-5 is reduced to This eliminates the case where the threshold value Vc-min is significantly decreased. That is, the capacitor voltage Vc-5 is maintained at a voltage value close to the threshold Vc-min as indicated by the solid line in FIG. Furthermore, at time t8, the converter control unit 50 sets the gate signal gtp-1 to "1" in order to put the selected cell 162-1 into the insert state. As a result, the capacitor voltage of the cell 162-1 is output as an alternative, and the arm voltage Varm deviates (includes error) from the ideal stepped waveform according to the arm voltage command value Varm*. disappears.

After that, at time t9, when the number of inserts Ncells changes (decreases) to "2", the converter control unit 50 determines that the polarity of the arm current Iarm at this time is negative (discharge polarity). Therefore, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently inserted and has a capacitor C with a small amount of stored power as the cell 162 to be bypassed. Here, since the converter control unit 50 has already selected the two cells 162 having the first and second lowest capacitor voltages Vc in the sort list, the next lowest capacitor voltage Vc (that is, Select cell 162-4, which has the third lowest Vc-4). At time t9, the converter control unit 50 sets the gate signal gtp-4 to "0" in order to bring the selected cell 162-4 into the bypass state. At time t9, the converter control unit 50 may select the cell 162-1 placed in the insert state instead of the cell 162-5 placed in the bypass state at time t8, and put it in the bypass state. Also at this time, since the cell 162-5 is in the bypass state, the capacitor voltage Vc-5 of the cell 162-5 continues to be maintained at a voltage value close to the current threshold Vc-min.

After that, from time t10 to time t11, each time the number of inserts Ncells changes (decreases) to "1" and "0" in sequence, the converter control unit 50 changes the capacitor voltage The cells 162 with the fourth and sixth lowest Vc (that is, Vc-3, Vc-1) are sequentially selected, and the gate signal gtp is set to "0" to bypass the selected cells 162. do. More specifically, converter control section 50 selects cell 162-3 at time t10 to set gate signal gtp-3 to "0", and selects cell 162-1 to set gate signal gtp-3 at time t11. Change 1 to 0. Also at this time, since the cell 162-5 is in the bypass state, the capacitor voltage Vc-5 of the cell 162-5 continues to be maintained at a voltage value close to the current threshold Vc-min.

After that, at time t12, the sort list is updated. Here, in the updated sorted list, the descending order of the voltage values of the capacitor voltage Vc is assumed to be the same as in the sorted list before updating.

After that, at time t13, when the number of inserts Ncells changes (increases) to "1", the converter control unit 50 determines that the polarity of the arm current Iarm at this time is negative (discharge polarity). Therefore, the converter control unit 50 refers to the sort list and selects the cell 162 that is currently bypassed and has a capacitor C with a large amount of stored power as the cell 162 to be placed in the insert state. Here, the converter control section 50 selects the cell 162-1 that is the first (that is, Vc−1) in the sort list with the highest capacitor voltage Vc. At time t13, the converter control unit 50 sets the gate signal gtp-1 to "1" in order to put the selected cell 162-1 into the insert state. Also at this time, since the cell 162-5 is in the bypass state, the capacitor voltage Vc-5 of the cell 162-5 continues to be maintained at a voltage value close to the current threshold Vc-min.

After that, from time t14 to time t15, each time the number of inserts Ncells changes (increases) to "2" and "3" in sequence, the converter control unit 50 changes the capacitor voltage The cells 162 with the second and third highest Vc (that is, Vc-2, Vc-3) are sequentially selected, and the gate signal gtp is set to "1" in order to insert the selected cells 162. do. More specifically, the converter control unit 50 selects the cell 162-2 at time t14 to set the gate signal gtp-2 to "1", and selects the cell 162-3 to set the gate signal gtp-2 at time t15. Change 3 to 1. Also at this time, since the cell 162-5 is in the bypass state, the capacitor voltage Vc-5 of the cell 162-5 continues to be maintained at a voltage value close to the current threshold Vc-min.

In this way, the converter control unit 50 determines the discharge polarity or the charge polarity based on the polarity of the arm current Iarm each time the number of inserts Ncells changes (increases or decreases), and creates a sort list. A cell 162 whose control state is to be in the insert state or the bypass state is selected by reference, and the gate signal gtp of the selected cell 162 is controlled. At this time, if the capacitor voltage Vc in any of the cells 162 exceeds the threshold Vc-max (exceeds the threshold Vc-max) or exceeds the threshold Vc-min (below the threshold Vc-min ), the converter control unit 50 performs balance control. That is, the converter control unit 50 performs balance control when the capacitor voltage Vc exceeds the threshold Vc-max or the threshold Vc-min regardless of the sort list calculation (generation) timing or switching control timing. conduct. In the balance control, the converter control unit 50 puts the cells 162 in which the capacitor voltage Vc exceeds the threshold Vc-max or the threshold Vc-min into the bypass state. As a result, the bypassed cell 162 stops charging to or discharging from the capacitor C. FIG. Then, the converter control unit 50 refers to the sort list, selects a cell 162 as a substitute for the bypassed cell 162 from among the cells 162 currently in the bypass state, and puts the selected cell 162 in the insert state. As a result, in the power converter 10, the capacitor C provided in the cell 162 is no longer charged or discharged (without being overcharged or overdischarged), and the charge amount of the capacitor C is relatively It can be balanced to be uniform. In the first operation of power converter 1 shown in FIG. 4, at time t8, capacitor voltage Vc-5 of cell 162-5 exceeds threshold Vc-min, but Balance control is similar for other cells 162 . In the first operation of the power converter 1 shown in FIG. 4, at time t8, the cell 162-1 is selected as a substitute for the cell 162-5. The same is true for In the first operation of the power converter 1 shown in FIG. 4, the balance control in the converter control unit 50 is the balance control when the capacitor voltage Vc-5 of the cell 162-5 exceeds the threshold Vc-min. However, if the balance control when the capacitor voltage Vc of any cell 162 provided in the arm unit 16 exceeds the threshold Vc-max is equivalent to the balance control of the first operation described above. good.

[Second operation of power converter]
In the first operation described above, the converter control section 50 performs single-pulse control, but the converter control section 50 can also perform double-pulse control. Next, as another operation of the power conversion device 1 (another example of balance control in the converter control unit 50), an operation when the converter control unit 50 performs multi-pulse control will be described.

FIG. 5 is a timing chart explaining an example of the operation timing of the second operation in the power conversion device 1. As shown in FIG. The second operation shown in FIG. 5 is also an operation when the number of cells 162 provided in the arm unit 16 is six (n=6), similar to the first operation shown in FIG. The number of inserts Ncells is, for example, a modulated wave based on the arm voltage command value Varm* and triangular wave carriers that are the same as the number of cells 162 belonging to the arm unit 16 (here, "6") and are shifted in phase and level from each other. , and the number of triangular carrier waves in which the value of the arm voltage command value Varm* (modulated wave) exceeds the value of the triangular carrier. In the second operation, the converter control unit 50 performs multi-pulse control for controlling the cells 162 belonging to the arm unit 16 multiple times within one period of the arm voltage command value Varm*. The operation timing of the device 1 is shown by enlarging a part of the range within one cycle of the arm voltage command value Varm*.

In the second operation shown in FIG. 5, for example, in the discharge polarity (discharge period) in which the polarity of the arm current Iarm is negative (Iarm<0), the number of insert state cells 162 represented by the insert number Ncells is " This is an example of a case where balance control is performed during the period of "2" before changing from "2" to "1", that is, during the period during which the number of cells 262 in the inserted state remains "2" and does not change. In the second operation shown in FIG. 5, the sort list calculation unit 54 generates the sort list in a shorter calculation cycle TS2 than in the first operation shown in FIG. However, even in the second operation shown in FIG. 5, the calculation period TS2 is a period of time intervals longer than the acquisition period TS1 (TS2>TS1). FIG. 5 shows an example of balance control of the converter control unit 50 when the capacitor voltage Vc-3 of the cell 162-3 provided in the arm unit 16 exceeds the threshold Vc-min (when it falls below the threshold Vc-min). is shown.

At time t0 shown in FIG. 5, the number of inserts Ncells is "2". For this reason, the converter control unit 50 refers to the sort list and selects the cell 162 having the capacitor C in which a large amount of power is stored as the cell 162 to be placed in the insert state. More specifically, converter control unit 50 selects cell 162-1 and cell 162-3, which are the two highest capacitor voltages Vc (Vc-1 and Vc-3) in the sort list. there is Therefore, at the time t0 shown in FIG. 5, the converter control section 50 sets the gate signals gtp-1 and gtp-3 to "1" in order to put the selected two cells 162 into the insert state. I have to. As a result, the power stored in the capacitor C-3 is discharged from the cell 162-3, and the capacitor voltage Vc-3 drops (decreases) along with the discharge.

After that, at time t1, when the capacitor voltage Vc-3 of the cell 162-3 exceeds the threshold Vc-min, the converter control unit 50 refers to the sort list to put the cell 162-3 in the bypass state. selects the cell 162 that is currently bypassed and has a capacitor C with high stored power as the cell 162 to be inserted instead of the bypassed cell 162-3. Here, the converter control unit 50 selects the cell 162-2 that has the third highest capacitor voltage Vc (that is, Vc-2) in the sort list. At time t1, the converter control unit 50 sets the gate signal gtp-3 to "0" in order to bring the cell 162-3 into the bypass state. As a result, the discharge from the cell 162-3 is stopped and the discharge from the capacitor C-3 provided in the cell 162-3 is continued. case), the capacitor voltage Vc-3 does not drop significantly below the threshold Vc-min. That is, the capacitor voltage Vc-3 is maintained at a voltage value close to the threshold Vc-min as indicated by the solid line in FIG. Furthermore, at time t1, the converter control section 50 sets the gate signal gtp-2 to "1" in order to put the selected cell 162-2 into the insert state. This causes the capacitor voltage of cell 162-2 to be output instead and the arm voltage Varm to be maintained.

After that, at time t2, the sort list is updated. Here, it is assumed that the sort list has been updated so that the capacitor voltage Vc-3 of the cell 162-3 is the lowest capacitor voltage Vc.

After that, at time t3, when the number of inserts Ncells changes to "1" (decreases), the converter control unit 50 refers to the sort list to refer to the capacitor that is currently in the insert state and has less power stored. Select the cell 162 with C as the cell 162 to be bypassed. Here, the converter control unit 50 selects the cell 162-2 which has the lower capacitor voltage Vc (that is, Vc-2) in the sort list among the cells 162-1 and 162-2 which are in the inserted state. to select. At time t3, the converter control unit 50 sets the gate signal gtp-2 to "0" in order to bring the selected cell 162-2 into the bypass state. At this time as well, since the cell 162-3 is in the bypass state, the capacitor voltage Vc-3 of the cell 162-3 continues to be maintained at a voltage value close to the current threshold Vc-min.

In this way, the converter control unit 50 changes (increases) the number of inserts Ncells in the second operation (multi-pulse control) as in the first operation (single-pulse control) shown in FIG. or decrease), based on the polarity of the arm current Iarm, determine the discharge polarity or the charge polarity, refer to the sort list, and select the cell 162 that causes the control state to be the insert state or the bypass state. , controls the gate signal gtp of the selected cell 162 . At this time, also in the second operation, when the capacitor voltage Vc in any of the cells 162 exceeds the threshold Vc-max (exceeds the threshold Vc-max) or exceeds the threshold Vc-min (threshold Vc-min), the converter control section 50 performs balance control. That is, even in the second operation, the converter control unit 50 determines whether the capacitor voltage Vc exceeds the threshold Vc-max or the threshold Vc-min regardless of the sort list calculation (generation) timing or the switching control timing. Balance control is performed when Also in the balance control of the second operation, the converter control section 50 puts the cells 162 in which the capacitor voltage Vc exceeds the threshold Vc-max or the threshold Vc-min into the bypass state. As a result, the bypassed cell 162 stops charging to or discharging from the capacitor C also in the second operation. Then, in the second operation, the converter control unit 50 also refers to the sort list and selects the cell 162 to substitute for the cell 162 put into the bypass state from among the cells 162 currently in the bypass state. to put it in the insert state. As a result, even in the second operation, in the power converter 10, the capacitor C included in the cell 162 is no longer charged or discharged (without being overcharged or overdischarged), and the capacitor C can be balanced so that the amount of charge in is relatively uniform. In the second operation of power converter 1 shown in FIG. 5, at time t1, capacitor voltage Vc-3 of cell 162-3 exceeds threshold Vc-min, Balance control is similar for other cells 162 . In the second operation of the power converter 1 shown in FIG. 5, at time t1, the cell 162-2 is selected as a substitute for the cell 162-3. The same is true for In the second operation of the power converter 1 shown in FIG. 5, the balance control in the converter control unit 50 is the balance control when the capacitor voltage Vc-3 of the cell 162-3 exceeds the threshold Vc-min. However, if the balance control when the capacitor voltage Vc of any cell 162 provided in the arm unit 16 exceeds the threshold Vc-max is equivalent to the balance control of the second operation described above. good.

With such a configuration and operation, in the power converter 1, the converter control unit 50 changes (increases or decreases) the number of inserts Ncells of the cells 162 for each arm unit 16 included in the power converter 10. At each timing, based on the polarity of the arm current Iarm, it is determined whether the polarity is discharging or charging. Then, in the power conversion device 1, the converter control unit 50 refers to the sort list calculated (generated) for each arm unit 16, and selects the cell 162 whose control state is set to the insert state or the bypass state. , changes the control state of the selected cell 162 . At this time, if the capacitor voltage Vc in any cell 162 exceeds the threshold Vc-max or the threshold Vc-min, the converter control unit 50 puts that cell 162 into a bypass state, refers to the sort list, A substitute cell 162 is selected from among the cells 162 currently in the bypass state and placed in the insert state. As a result, in the power conversion device 1, overcharging or overdischarging of the capacitor C included in the cell 162 in which the capacitor voltage Vc exceeds the threshold Vc-max or the threshold Vc-min can be prevented, and the charge amount of the capacitor C is It can be balanced to be relatively uniform. As a result, in the power converter 1, in the power converter 10, the risk of failure of the capacitor C and the switching element Q provided in the cell 162 can be reduced. It is possible to reduce the risk of a state in which the protection device of the power converter 10 is activated and the operation is stopped due to overvoltage or undervoltage. As a result, in the power conversion device 1, it is possible to realize a highly reliable power conversion device with improved continuous operation performance when a system fault occurs.

As described above, in the power converter 1 of the first embodiment, the converter control unit 50 changes (increases) the number of inserts Ncells of the cells 162 for each arm unit 16 included in the power converter or decrease), the polarity of the arm current Iarm is used to determine whether the polarity is discharging or charging. Then, in the power conversion device 1 of the first embodiment, the converter control unit 50 refers to the sort list calculated (generated) for each arm unit 16, and changes the control state to the insert state or the bypass state. Select a cell 162 to change the control state of the selected cell 162 . At this time, in the power conversion device 1 of the first embodiment, when the capacitor voltage Vc in any of the cells 162 exceeds the threshold Vc-max or the threshold Vc-min, the converter control unit 50 causes the cell 162 to A bypass state is set, a sort list is referred to, and a substitute cell 162 is selected from among the cells 162 currently in the bypass state and put in the insert state. As a result, in the power conversion device 1 of the first embodiment, overcharging or overdischarging of the capacitor C included in the cell 162 in which the capacitor voltage Vc exceeds the threshold Vc-max or the threshold Vc-min can be prevented. The charge on capacitor C can be balanced so that it is relatively even. As a result, in the power converter 1 of the first embodiment, in the power converter 10, the failure risk of the capacitor C and the switching element Q provided in the cell 162 can be reduced. Also, it is possible to reduce the risk of a state where the protection device of the power converter 10 is activated and the operation is stopped due to the capacitor voltage Vc becoming overvoltage or undervoltage. As a result, in the power conversion device 1 of the first embodiment, it is possible to realize a highly reliable power conversion device with improved continuous operation performance when a system fault occurs.

In the power conversion device 1 of the first embodiment described above, the power converter 10 is provided, for example, at the interconnection point between the AC system and the DC system, and according to the control from the converter control unit 50, the AC system A double star connection MMC that mutually converts the AC power supplied by the DC system and the DC power supplied by the DC system has been described. However, the power converter 10 may be a power converter with other configurations.

(Second embodiment)
[Configuration of power converter]
A second embodiment will be described below. FIG. 6 is a diagram illustrating an example of the configuration of a power converter according to the second embodiment. FIG. 6 shows, for example, an example of a power conversion device 2 that is connected to an AC system and adjusts the reactive power of the AC system. For example, when the power conversion device 2 is configured to include an energy storage element such as a storage battery in the cell 262 described later, it can adjust the active power of the AC system. The AC system may be, for example, an AC power supply or an AC load, as in the first embodiment. The power conversion device 2 includes a power converter 20 and a converter control section 50a. In FIG. 6, components having the same functions as those of the power converter 1 of the first embodiment are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

Power converter 20 is a single delta-connected modular multi-level converter (MMC) that converts AC power under the control of converter control section 50a. Power converter 20 includes a plurality of legs 22 between lines of the AC system. The number of legs 22 provided in the power converter 20 corresponds to the number of inter-line phases of AC power supplied by the AC system. FIG. 6 shows a case where the AC system supplies three-phase AC power of a first phase (R phase), a second phase (S phase), and a third phase (T phase). Therefore, FIG. 6 shows the configuration of the power converter 20 including three legs 22, ie, the leg 22-RS, the leg 22-ST, and the leg 22-TR. Each of Leg 22-RS, Leg 22-ST, and Leg 22-TR have the same configuration.

In each leg 22, AC terminal CA is connected to a terminal of one phase of the AC system and AC terminal CB is connected to a terminal of any other phase in the AC system that is different from the phase connected to AC terminal CA. connected to the terminal. More specifically, in the leg 22-RS corresponding to the phase between the R phase and the S phase, the AC terminal CA-R is connected to the R-phase AC terminal R of the AC system, and the AC terminal CB-S is connected to the AC system. is connected to the S-phase AC terminal S of the . In the leg 22-ST corresponding to the phase between the S phase and the T phase, the AC terminal CA-S is connected to the AC terminal S of the AC system, and the AC terminal CB-T is connected to the AC terminal T of the T phase of the AC system. be done. In the leg 22-TR corresponding to the phase between the T phase and the R phase, the AC terminal CA-T is connected to the AC terminal T of the AC system, and the AC terminal CB-R is connected to the AC terminal R of the AC system. FIG. 6 shows a case where AC terminals CA of respective legs 22 are connected to corresponding phase terminals of the AC system via transformers TR.

Each leg 22 has, for example, a reactor 14 and an arm unit 26 . Each arm unit 26 includes, for example, n (n is a natural number) cells 262 (cells 262-1 to 262-n) connected in series. In FIG. 6, in order to distinguish which phase of the AC system or between which phases each component of the leg 22 corresponds to, each symbol is followed by a "- (hyphen)". , the letter "R" representing the R phase, the letter "S" representing the S phase, the letter "T" representing the T phase, the letter "RS" representing the phase between the R phase and the S phase, the S phase and the T phase or the letter "TR" representing the phase between the T phase and the R phase. In the following description, when it is not distinguished which phase of the AC system each component corresponds to or between which phases, hyphens and hyphens attached to the symbols of each component The character for identification following is omitted.

In each leg 22 , the reactor 14 is connected in series to the AC terminal CA side of the arm unit 26 . In each leg 22, one end of the reactor 14 that is not connected to the arm unit 26 serves as an AC terminal CA. In each leg 22 , the terminal on the side opposite to the reactor 14 in the arm unit 26 serves as the AC terminal CB of the leg 22 . In other words, in each leg 22, the reactor 14 and the cells 262-1 to 262-n are serially connected in this order from the AC terminal CA side toward the AC terminal CB side and connected to the AC terminal CA. ing.

The leg 22 is an example of a "phase unit" in the claims. The arm unit 26 (which may include the reactor 14) is an example of an "arm unit" in the claims. The cell 262 is an example of a "unit converter" in the claims. The reactor 14 is an example of an "inductance element" in the claims.

6 shows the case where the reactor 14 is arranged on the AC terminal CA side of the arm unit 26 in each leg 22, but the reactor 14 is located on the opposite side of the arm unit 26 to the AC terminal CA side. (that is, on the side of the AC terminal CB) or any position within the arm unit 26 (that is, a position between any two cells 262 connected in series in the arm unit 26). The reactor 14 may be replaced with a transformer with a special winding structure that has a leakage reactance sufficient to replace the function of the reactor. In this case, reactor 14 may be integrated with transformer TR.

Each arm unit 26 generates a stepped sine wave (multi-level waveform) representing an AC waveform supplied between corresponding phases of the AC system in response to control from the converter control section 50a for each cell 262 connected in series. ) to generate an alternating voltage.

Here, an example of the configuration of the cell 262 included in the arm unit 26 will be described. Cell 262 is, for example, a full bridge circuit. FIG. 7 is a diagram showing an example of the configuration of the cells 262 in the leg 22 included in the power converter 20. As shown in FIG. The cell 262 includes four switching elements Q (switching element Q1 to switching element Q4), four diodes D (diode D1 to diode D4), and a capacitor C. The switching element Q is, for example, an insulated gate bipolar transistor (IGBT), like the switching element Q included in the cell 162 of the first embodiment. Therefore, the switching element Q is not limited to an IGBT, and may be any element as long as it is a self arc-extinguishing semiconductor switching element capable of realizing a converter or an inverter.

In cell 262, switching element Q1 and switching element Q2 are connected in series, and switching element Q3 and switching element Q4 are connected in series. In the cell 262, the series circuit of the switching elements Q1 and Q2, the series circuit of the switching elements Q3 and Q4, and the capacitor C are connected in parallel with each other. In cell 262, each switching element Q and corresponding diode D are connected in parallel with each other. In the cell 262, the connection point between the emitter of the switching element Q1 and the collector of the switching element Q2 is the positive terminal TP(+) connected to the AC terminal CA side in the leg 22, and the emitter of the switching element Q3 and the switching element Q4. A connection point with the collector is a negative terminal TN(−) connected to the AC terminal CB side of the leg 22 .

A control signal from the converter control section 50a is input to each gate of the switching element Q1 to the switching element Q4 provided in the cell 262 (a control voltage is applied or a control current is supplied). A gate signal gta as a control signal from the converter control unit 50a is input to the gate of the switching element Q1, and a gate signal gtb is input as a control signal from the converter control unit 50a to the gate of the switching element Q2, A gate signal gtc is input as a control signal from the converter control section 50a to the gate of the switching element Q3, and a gate signal gtd is input as a control signal from the converter control section 50a to the gate of the switching element Q4. . As a result, each of the switching elements Q1 to Q4 is switched to either an ON state or an OFF state by the converter control section 50a. In the following description, when a control signal of "1 ("High" level)" (gate signal gta, gate signal gtb, gate signal gtc, and gate signal gtd) is input, each switching element Q is turned on. , "0 ("Low" level)" control signals (gate signal gta, gate signal gtb, gate signal gtc, and gate signal gtd) are input, and each switching element Q is turned off.

Capacitor C is charged or discharged depending on the state of the respective switching element Q. FIG. In the cell 262 , the voltage across the capacitor C (capacitor voltage Vc) is generated as the voltage across the terminals TP and TN of the cell 262 (cell voltage Vo). More specifically, when the converter control unit 50a sets the control signal (gta, gtb, gtc, gtd)=(1, 0, 0, 1), for example, the positive terminal TP, the switching element Q1, the capacitor C, Current flows through the switching element Q4 and the negative terminal TN in this order, and the cell voltage Vo of the cell 262 matches the capacitor voltage Vc. That is, the converter control unit 50a sets the control signal (gta, gtb, gtc, gtd)=(1, 0, 0, 1) so that the capacitor C between the positive terminal TP and the negative terminal TN of the cell 262 is inserted, and the capacitor voltage Vc is output as the cell voltage Vo. In the following description, when the converter control section 50a sets the control signals (gta, gtb, gtc, gtd)=(1, 0, 0, 1), this is referred to as "positive voltage insertion". is referred to as the "positive voltage insert state". On the other hand, when the converter control unit 50a sets the control signal (gta, gtb, gtc, gtd)=(0, 1, 1, 0), for example, the positive terminal TP, the switching element Q2, the capacitor C, the switching element Q3, Current flows in order of the negative terminal TN, and the cell voltage Vo of the cell 262 coincides with the inversion of the capacitor voltage Vc. In other words, the converter control unit 50a sets the control signal (gta, gtb, gtc, gtd) to (0, 1, 1, 0) so that the capacitor C is placed between the positive terminal TP and the negative terminal TN of the cell 262 is inserted in the opposite direction, and the negative capacitor voltage Vc is output as the cell voltage Vo. In the following description, when the converter control section 50a sets the control signals (gta, gtb, gtc, gtd)=(0, 1, 1, 0), this is referred to as "negative voltage insertion". is called a "negative voltage insert state". Further, when the converter control unit 50a sets the control signal (gta, gtb, gtc, gtd)=(1,0,1,0) or (0,1,0,1), for example, the positive terminal TP, Current flows in the order of the diode D1, the switching element Q3, and the negative terminal TN, or the order of the positive terminal TP, the switching element Q2, the diode D4, and the negative terminal TN, and the cell voltage Vo of the cell 262 becomes 0 [V]. That is, when the converter control unit 50a sets the control signal (gta, gtb, gtc, gtd) to (1, 0, 1, 0) or (0, 1, 0, 1), the positive terminal of the cell 262 TP and the negative terminal TN are short-circuited, and the current flows without passing through the capacitor C, so that the cell voltage Vo of the cell 262 becomes 0 [V]. In the following description, the converter control unit 50a makes the control signal (gta, gtb, gtc, gtd) = (1, 0, 1, 0) or (0, 1, 0, 1) as "bypass , and the state of the cell 262 in this case is called a "bypass state."

The cell 262 is not limited to the configuration shown in FIG. 7, and may have any configuration as long as it realizes the same functions as the cell 262. FIG.

The switching element Q1 and the diode D1 are examples of the "switching element" and the "first switching element" in the claims, and the switching element Q2 and the diode D2 are examples of the "switching element" and the "first switching element" in the claims. The switching element Q3 and the diode D3 are examples of the "switching element" and the "third switching element" in the claims, and the switching element Q4 and the diode D4 are examples of the is an example of a "switching element" and a "fourth switching element" in the range of . The series circuit of the parallel circuit of the switching element Q1 and the diode D1 and the parallel circuit of the switching element Q2 and the diode D2 is an example of the "first series circuit" in the claims. and the series circuit of the parallel circuit of the switching element Q4 and the diode D4 are an example of the "second series circuit" in the claims. The on state is an example of a "conducting state" in the scope of claims, and the off state is an example of a "non-conducting state" in the scope of claims. Capacitor C is an example of an "energy storage element" in the claims. The positive terminal TP is an example of the "first end" in the claims, and the negative terminal TN is an example of the "second end" in the claims. The positive voltage insert state is an example of the "first first control state" in the claims, and the negative voltage insert state is an example of the "second first control state" in the claims, The bypass state is an example of a "second control state" in the claims.

By connecting a plurality of cells 262 having such a configuration in series, the arm unit 26 adds the cell voltage Vo of each cell 262 controlled to the insert state (positive voltage insert state or negative voltage insert state). output voltage. Therefore, the arm unit 26 outputs a voltage corresponding to the number of cells 262 controlled to the insert state (positive voltage insert state or negative voltage insert state) by the converter control section 50a. Thereby, the arm unit 26 generates a multi-level waveform according to the control from the converter control section 50a. The cell 262 may be provided in each arm unit 16 included in the power converter 10 of the first embodiment instead of the cell 162 of the first embodiment.

By the way, in cell 262, control signals (gta, gtb) = (1, 1) or control signals (gtc, gtd) = (1, 1) should be prohibited. When the control signals (gta, gtb) = (1, 1), both the switching elements Q1 and Q2 are turned on, and when the control signals (gtc, gtd) = (1, 1), This is because both the switching element Q3 and the switching element Q4 are turned on, and both ends of the capacitor C are short-circuited in either case. Therefore, the converter control section 50a converts the control signals (gta, gtb, gtc, gtd) to (1, 0, 0, 1), (0, 1, 1, 0), (1, 0, 1, 0), and (0, 1, 0, 1), for a very short time, the control signal (gta, gtb) = (0, 0) or the control signal ( gtc, gtd)=(0, 0) (so-called dead time). When stopping the operation of the cell 262, the converter control unit 50a may fix the control signal (gta, gtb, gtc, gtd)=(0, 0, 0, 0). In the following description, the converter control unit 50a fixes all the control signals (gta, gtb, gtc, gtd) to (0, 0, 0, 0) and controls all the arm units 26 included in the power converter 20. Stopping the operation of the cell 262 is called "gate block", and the state of the cell 262 in this case is called "gate block state".

Returning to FIG. 6, the converter control unit 50a, like the converter control unit 50 included in the power conversion device 1 of the first embodiment, controls the operating state of the power conversion device 2 and each position in the power conversion device 2. AC voltage command value including the frequency of the AC system is calculated based on the detected value of (current value, current flow direction (polarity), voltage value). For this reason, like the converter control unit 50, the converter control unit 50a, for example, a detection value output by a detector (described later) provided at a desired position inside or outside the power conversion device 2, a predetermined (constant ) at each acquisition cycle TS1. Then, converter control section 50a obtains a voltage command value for each arm unit 26 that includes the voltage component represented by the calculated AC voltage command value. The converter control unit 50a generates a control signal for controlling switching of the switching element Q in the cell 262 provided in each arm unit 26 based on the obtained voltage command value. The converter control unit 50a then outputs the generated control signal to the corresponding cell 262 . For example, when the converter control unit 50a controls the arm unit 26-RS, which is the arm unit 26 between the R phase and the S phase of the AC system, An arm voltage command value Varm* corresponding to the arm voltage Varm-R to be output to is calculated. In the following description, the positive polarity of arm voltage Varm and arm voltage command value Varm* is defined in the direction in which the potential on the cell 262-1 side becomes higher when viewed from the cell 262-n side. Then, based on the calculated arm voltage command value Varm*, the converter control unit 50a controls each of the cells 262 (cells 262-1-RS to 262-n-RS) provided in the arm unit 26-RS. Gate signals gta (gate signals gta-1-RS to gta-n-RS), gate signals gtb (gate signals gtb-1-RS to gtb-n-RS), gate signals gtc ( gate signals gtc-1-RS to gtc-n-RS) and gate signals gtd (gate signals gtd-1-RS to gtd-n-RS). The converter control unit 50a outputs the generated gate signal gta, gate signal gtb, gate signal gtc, and gate signal gtd to the corresponding cells 262, respectively. The same is true when the converter control section 50a controls other arm units 16. FIG. The converter control section 50a includes, for example, an insert number calculation section 52a, a sort list calculation section 54a, a cell selection control section 56a, and a gate signal generation section 58a.

Converter control part 50a controls operation of electric power converter 20, for example by hardware processors, such as CPU, running a program (software). The converter control unit 50a may be implemented by hardware (including circuitry) such as LSI, ASIC, FPGA, and GPU, or may be implemented by cooperation of software and hardware. The converter control unit 50a may be realized by a dedicated LSI. The program may be stored in advance in a storage device (a storage device having a non-transitory storage medium) such as an HDD or flash memory provided in the converter control unit 50a or the power conversion device 2, or may be stored in a DVD or CD- It is stored in a removable storage medium (non-transitory storage medium) such as a ROM, and when the storage medium is attached to the drive device provided in the converter control unit 50a or the power conversion device 2, the converter control unit 50a or may be installed in the HDD or flash memory provided in the power converter 2 .

Similarly to the power conversion device 1 of the first embodiment, the power conversion device 2 is also provided with current detectors and voltage detectors at desired positions to detect current values, current polarities, and voltage values. The example of FIG. 6 shows a case where each leg 22 is provided with a current detector for detecting an arm current I flowing from the AC terminal CA side to the AC terminal CB side. More specifically, the leg 22-RS is provided between the reactor 14-RS and the arm unit 26-RS for detecting arm current Irs flowing from the AC terminal CA-R side to the AC terminal CB-S side. A current detector is provided. Other legs 22 are the same. Although not shown in FIG. 7, each cell 262 is also provided with a voltage detector for detecting the capacitor voltage Vc. The R-phase AC current Ir, the S-phase AC current Is, and the T-phase AC current It are directly detected by current detectors provided at the AC terminals R, S, and T, respectively. may be detected indirectly by calculating the arm current I detected in each leg 22 . For example, the R-phase AC current Ir is obtained by calculating the difference between the arm current Irs between the R-phase and the S-phase and the arm current Itr between the T-phase and the R-phase (that is, Irs-Itr). may be indirectly detected by Furthermore, FIG. 6 does not show the voltage detectors, but shows the case where the R-phase AC voltage Vsr, the S-phase AC voltage Vss, and the T-phase AC voltage Vst are detected. .

In the converter control unit 50a, the arm unit 16 provided in the power conversion device 1 of the first embodiment is replaced with the arm unit 26 in the power conversion device 2, so that the control signal (gate signal) to be output is changed to the arm unit 26 corresponds to each cell 262 provided by . However, the configuration of the converter control section 50a is the same as the configuration of the converter control section 50 included in the power converter 1 of the first embodiment shown in FIG. Therefore, illustration of an example of the configuration of the converter control unit 50a provided in the power conversion device 2 is omitted, and below, each component provided in the converter control unit 50 of the first embodiment and the converter control unit 50a A description will be given of the different operations of each of the constituent elements of the .

The insert number calculator 52a performs the same processing as the insert number calculator 52 of the first embodiment. The insert number calculation unit 52a calculates (calculates) the insert number Ncells for each arm unit 26 based on the arm voltage command value Varm*. However, unlike the insert number calculation section 52, the insert number calculation section 52a calculates the number of inserts Ncells including information indicating whether the insert state is the positive voltage insert state or the negative voltage insert state to each arm unit. It calculates (calculates) every 26. More specifically, for example, the insert number calculation unit 52a calculates the number (integer value, absolute value) of the cells 162 to be assigned to the insert state (to be put in the insert state) among the cells 262 provided in the arm unit 26 and the positive voltage insert A signed insert number Ncells representing whether to set the state or the negative voltage insert state (polarity, sign) is calculated (calculated). Like the insert number calculator 52, the insert number calculator 52a also performs single-pulse control and multi-pulse control by calculating (calculating) the insert number Ncells. The insert number calculation unit 52a outputs the calculated insert number Ncells to the cell selection control unit 56a. The insert number calculator 52a is an example of a "state number calculator" in the claims.

The sorted list calculator 54a performs the same processing as the sorted list calculator 54 of the first embodiment. The sort list calculation unit 54 a calculates (generates) a sort list representing the magnitude relationship of the capacitor voltages Vc of the cells 262 included in the power converter 20 for each arm unit 26 . The sort list calculation unit 54a also generates a sort list for each predetermined (constant) calculation cycle TS2 (TS2>TS1) longer than the acquisition cycle TS1. The method of generating the sorted list in the sorted list calculator 54a is the same as that of the sorted list calculator 54a. The sort list calculation unit 54a outputs the generated sort list to the cell selection control unit 56a. The sort list calculator 54a is an example of a "list calculator" in the scope of claims.

The cell selection control unit 56a performs the same processing as the cell selection control unit 56 of the first embodiment. The cell selection control unit 56a controls the cells 262 at least at each timing when the number of inserts Ncells output by the number-of-insertions calculation unit 52a changes, that is, controls the cells 262 (puts them in a positive voltage insert state, a negative voltage insert state, and a bypass state). At each control timing, the sort list is referenced to select the target cell 262 whose current cell control state CL* is to be changed.

When the absolute value of the number of inserts Ncells increases, the cell selection control unit 56a switches to the insert state (positive voltage insert state or negative voltage insert state) depending on the combination of the polarities of the arm voltage command value Varm* and the arm current Iarm. During the charging polarity period (charging period) in which power is stored in the capacitor C of the cell 262 that is currently bypassed and the amount of charge in the entire arm unit 26 is increased, the cell 262 that is currently in the bypass state is stored. A cell 262 having a capacitor C with less power is preferentially selected as the cell 262 to be changed to the insert state. In this case, the cell selection control unit 56a refers to the sort list, sequentially selects the cell 262 having the capacitor C with the relatively low voltage value of the capacitor voltage Vc, and selects the cell control state CL* representing the selected cell 262. to generate The charge polarities are as follows: (1) the arm voltage command value Varm* is a polarity in which the potential on the cell 262-1 side shown in FIG. (2) the arm voltage command value Varm* is such that the potential on the cell 262-1 side shown in FIG. 6 is lower than that on the cell 262-n side. and the arm current Iarm has a polarity that flows in the opposite direction to the arm current I shown in FIG. On the other hand, when the absolute value of the number of inserts Ncells increases, the cell selection control unit 56a selects the insert state (positive voltage insert state or negative voltage insert state) from the combination of the polarities of the arm voltage command value Varm* and the arm current Iarm. During the period (discharge period) that is the discharge polarity for increasing the discharge amount of the entire arm unit 26 by discharging the power accumulated in the capacitor C of the cell 262 that is currently in the bypass state, the current in the cell 262 that is in the bypass state , a cell 262 having a capacitor C with a large amount of stored power is preferentially selected as the cell 262 to be changed to the insert state. In this case, the cell selection control unit 56a refers to the sort list, sequentially selects the cell 262 including the capacitor C having the relatively high capacitor voltage Vc, and selects the cell control state CL* representing the selected cell 262. to generate The discharge polarities are as follows: (1) the arm voltage command value Varm* is such that the potential on the cell 262-1 side shown in FIG. If the polarity is opposite to the arm current I shown, or if (2) the arm voltage command value Varm* is such that the potential on the cell 262-1 side shown in FIG. and the arm current Iarm has a polarity that flows in the direction of the arm current I shown in FIG.

When the absolute value of the number of inserts Ncells decreases, the cell selection control unit 56a accumulates power in the capacitor C of the cell 262 in the inserted state from the combination of the arm voltage command value Varm* and the arm current Iarm. In the period (charging period) in which the charging polarity increases the amount of charge in the entire arm unit 26, the cells 262 currently in the insert state (positive voltage insert state or negative voltage insert state) are stored. Cells 262 with capacitors C having higher power are preferentially selected as cells 262 to be changed to the bypass state. In this case, the cell selection control unit 56a refers to the sort list, sequentially selects the cell 262 including the capacitor C having the relatively high capacitor voltage Vc, and selects the cell control state CL* representing the selected cell 262. to generate On the other hand, when the absolute value of the number of inserts Ncells decreases, the cell selection control unit 56a selects the combination of the polarities of the arm voltage command value Varm* and the arm current Iarm to store in the capacitor C of the cell 262 in the inserted state. During the period (discharge period) that is the discharge polarity that increases the amount of discharge of the entire arm unit 26 by discharging the power that is being supplied to the cell 262 that is currently in the insert state (positive voltage insert state or negative voltage insert state). Therefore, a cell 262 having a capacitor C with a small amount of stored power is preferentially selected as the cell 262 to be changed to the bypass state. In this case, the cell selection control unit 56a refers to the sort list, sequentially selects the cell 262 having the capacitor C with the relatively low voltage value of the capacitor voltage Vc, and selects the cell control state CL* representing the selected cell 262. to generate

As a result, the cell 262 having a capacitor C with a relatively high capacitor voltage Vc has a short charging time and a long discharging time preferentially. The voltage Vc will be uniformed. On the other hand, the cell 262 having a capacitor C with a relatively low capacitor voltage Vc has a preferentially long charging time and a short discharging time. The capacitor voltage Vc will be uniformed.

Similarly to the cell selection control unit 56 of the first embodiment, the cell selection control unit 56a also reduces the difference in the charge amount of the capacitor C between the cells 262 provided in the arm unit 26 (the charge amount is relatively Control the balance so that it is balanced evenly). In the balance control in the cell selection control unit 56a, as in the cell selection control unit 56, the same arm unit The voltage values of the capacitor voltages Vc of the cells 262 belonging to 26 are obtained, and the obtained voltage values of the respective capacitor voltages Vc are compared with the threshold Vc-max and the threshold Vc-min. Similarly to the cell selection control unit 56, the cell selection control unit 56a controls the cell 262 whose capacitor voltage Vc exceeds the threshold Vc-max or the threshold Vc-min to the bypass state based on the result of the comparison. From among the cells 162 in the bypass state, the same number of other cells 162 are selected instead to change to the insert state (positive voltage insert state or negative voltage insert state). In this case, the cell selection control unit 56a generates a cell control state CL* representing the cell 262 to be placed in the bypass state and the cell 262 to be placed in the insert state (positive voltage insert state or negative voltage insert state).

The cell selection control section 56a outputs the cell control state CL* corresponding to each cell 262 to the gate signal generation section 58a. The cell selection control section 56a is an example of a "unit converter selection section" in the claims. The acquisition cycle TS1 is an example of a "first time interval" in the scope of claims, and the calculation cycle TS2 is an example of a "second time interval" in the scope of claims. The threshold Vc-max is an example of a "first threshold" in the scope of claims, and the threshold Vc-min is an example of a "second threshold" in the scope of claims.

The gate signal generator 58a performs the same processing as the gate signal generator 58 of the first embodiment. The gate signal generator 58a generates control signals (gate signals) to be output to all the cells 262 included in each arm unit 26 according to each cell control state CL* output by the cell selection controller 56a. More specifically, the gate signal generation unit 58a generates a gate signal gta corresponding to the switching element Q1 included in each cell 262 and a gate signal gtb corresponding to the switching element Q2 in order to realize the cell control state CL*. , a combination of the gate signal gtc corresponding to the switching element Q3 and the gate signal gtd corresponding to the switching element Q4. At this time, the gate signal generation unit 58a also provides a short dead time in order to prevent both ends of the capacitor C included in the cell 262 from being short-circuited. The gate signal generator 58a outputs each generated gate signal to the corresponding cell 262 (more specifically, the switching element Q included in the cell 262).

Also in the power conversion device 2, for example, the cell selection control unit 56a outputs the cell control state CL* to each cell 262, and generates a gate signal corresponding to the cell control state CL* in each cell 262. may be configured. In this case, each cell 262 is configured to have a component having a function equivalent to that of the gate signal generator 58a.

With such a configuration, the converter control unit 50a controls the cells 262 in the respective arm units 26 provided in the power converter 20 to supply the power converter 20 with reactive power of the AC system (active power can also be adjusted).

[Third operation of the power converter]
Next, an example of the operation of the power conversion device 2, that is, the control of the cell 262 in the converter control section 50a will be described. In the following description, the arm unit 26-RS included in the leg 22-RS is used as a representative of the leg 22-RS, the leg 22-ST, and the leg 22-TR included in the power converter 20. The control for is explained. In the following description, for ease of explanation, it is assumed that the converter control unit 50a itself performs the operation of each component included in the converter control unit 50a.

FIG. 8 is a timing chart illustrating an example of operation timing of the third operation in the power conversion device 2. FIG. An example of the operation of the power conversion device 2 shown in FIG. 8 is the operation when the arm unit 26-RS (hereinafter simply referred to as the “arm unit 26”) has three cells 262 (n=3). An example. FIG. 8 shows an example of balance control of the converter control unit 50a when the capacitor voltage Vc-2 of the cell 262-2 provided in the arm unit 26 exceeds the threshold Vc-min (when it falls below the threshold Vc-min). is shown. In FIG. 8, similarly to the respective operations in the power conversion device 1 of the first embodiment, the arm unit 26 generated based on the arm voltage command value Varm*, the arm current Iarm, and the arm voltage command value Varm* A temporal change in the arm voltage Varm is shown on the same time axis. In FIG. 8, instead of the gate signal gtp shown in each operation in the power conversion device 1, the cell control state CL*-1 to cell 262-1 to cell 262-3 changed by the converter control unit 50a The temporal change of the control state CL*-3 is shown on the same time axis. FIG. 8 also shows a schematic change in the capacitor voltage Vc (Vc-2) of the cell 262-2 whose balance is controlled by the converter control section 50a on the same time axis. In FIG. 8, as with each operation in the power converter 1, the dead time is omitted for ease of explanation. Further, FIG. 8 shows an example of a sort list calculated (generated) by the converter control section 50a (more specifically, the sort list calculation section 54a). In the third operation shown in FIG. 8, similarly to the first operation in the power converter 1 of the first embodiment shown in FIG. 4, a sort list is generated for each cycle of the arm voltage command value Varm*. (updated). FIG. 8 also shows an example of an acquisition cycle TS1 for acquiring the voltage value of the capacitor voltage Vc-2 and an example of a calculation cycle TS2 for creating a sort list.

In power converter 20, arm voltage command value Varm* includes the frequency of the AC system. The converter control unit 50a (more specifically, the insert number calculation unit 52a) calculates (calculates) the insert number Ncells represented by a stepped pseudo sine wave based on the arm voltage command value Varm*. do. In FIG. 8, the number of inserts Ncells is an integer value with a minimum value of "-n (here, "-3")" and a maximum value of "n (here, "3")". The number of inserts Ncells represents the number of cells 262 that are positive (ie, '0' to '3') to be in a positive voltage insert state, and negative (ie, '-1' to '-3') to be in a negative voltage insert state. It represents the number of cells 262 that will cause the The number of inserts Ncells is calculated, for example, by dividing the arm voltage command value Varm* by the average value or rated value of the capacitor voltages Vc of the cells 262 belonging to the arm unit 26 and approximating it to an integer. That is, the operation timing of the power conversion device 2 shown in FIG. 8 is the same as the first operation in the power conversion device 1 of the first embodiment, and the operation timing when the converter control unit 50a performs 1-pulse control. is. Therefore, the number of inserts Ncells represents the arm voltage Varm shown in FIG.

The converter control unit 50a (more specifically, the cell selection control unit 56a) selects cells in the insert state (positive voltage insert state or negative voltage insert state) belonging to the arm unit 26 each time the number of inserts Ncells changes. 262 generates a cell control state CL* for each cell 262 to match the number (integer value) of cells 262 to be placed in the insert state (either the positive voltage insert state or the negative voltage insert state) represented by the insert number Ncells. . When the arm voltage command value Varm* is positive (Varm*>0), the number of inserts Ncells becomes a value equal to or greater than "0", so the converter control unit 50a puts each cell 262 in the positive voltage insert state or Generate a cell control state CL* that causes the bypass state. On the other hand, when the arm voltage command value Varm* is negative (Varm*<0), the number of inserts Ncells is less than or equal to "0". Alternatively, it generates a cell control state CL* that causes a bypass state. Each cell control state CL* represents a positive voltage insert state when "1", a bypass state when "0", and a negative voltage insert state when "-1". is.

The converter control unit 50a (more specifically, the gate signal generation unit 58a) controls output to all the cells 262 included in each arm unit 26 according to the cell control state CL* generated by the cell selection control unit 56a. Generates signals (gate signal gta, gate signal gtb, gate signal gtc, and gate signal gtd). In each arm unit 26, each cell 262 is brought into the positive voltage insert state, the bypass state, or the negative voltage insert state by the gate signal output from the gate signal generator 58a, thereby reducing the arm voltage Varm to Output. When the capacitor voltage Vc of the cells 262 is uniformly controlled, the arm voltage Varm is approximately equal to the number (integer value) of the cells 262 to be placed in the insert state (positive voltage insert state or negative voltage insert state) represented by the insert number Ncells. A voltage value obtained by multiplying the capacitor voltage Vc.

Arm current Iarm includes the frequency of the AC system. In the arm unit 26, when the arm voltage command value Varm* is positive (Varm*>0) and the arm current Iarm is positive (Iarm>0), the capacitor C included in the cell 262 in the positive voltage insertion state is charged. , the capacitor voltage Vc rises during this charging period. In the arm unit 26, when the arm voltage command value Varm* is negative (Varm*<0) and the arm current Iarm is negative (Iarm<0), the capacitor C included in the cell 262 in the negative voltage insertion state is charged. , the capacitor voltage Vc rises during this charging period. In the arm unit 26, when the arm voltage command value Varm* is positive (Varm*>0) and the arm current Iarm is negative (Iarm<0), the capacitor C included in the cell 262 in the positive voltage insertion state is discharged. , the capacitor voltage Vc drops during this discharging period. In the arm unit 26, when the arm voltage command value Varm* is negative (Varm*<0) and the arm current Iarm is positive (Iarm>0), the capacitor C included in the cell 262 in the negative voltage insertion state is discharged. , the capacitor voltage Vc drops during this discharging period. In this way, in the arm unit 26, the charging period starts when the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm are equal, and when the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm are different. discharge period. In the arm unit 26, regardless of the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm, the capacitor C included in the bypassed cell 262 is neither charged nor discharged, and maintains the current capacitor voltage Vc. .

At time t0 shown in FIG. 8, the number of inserts Ncells is "0". The polarity of the arm current Iarm at this time is positive. The converter control unit 50a may arbitrarily decide whether to determine the charging polarity or the discharging polarity when the number of inserts Ncells or the arm current Iarm is "0". In any event, the converter control unit 50a generates a cell control state CL* indicating that all cells 262 are to be bypassed to match the number of inserts Ncells. Here, the cell 262-2 is in the bypass state because the cell control state CL*-2 is "0". Therefore, the capacitor C-2 of the cell 262-2 is neither charged nor discharged, and maintains the current capacitor voltage Vc-2.

After that, at time t1, when the number of inserts Ncells changes to "1" (the absolute value increases), the converter control unit 50a determines that the polarity of the arm voltage command value Varm* at this time is positive and the arm current It is determined that the polarity of Iarm is positive (charging polarity). Therefore, the converter control unit 50a refers to the sort list and selects the cell 262 that is currently bypassed and has a capacitor C with a small amount of stored power as the cell 262 to be placed in the positive voltage insert state. Here, converter control 50a selects cell 262-3 with the lowest capacitor voltage Vc (ie, Vc-3) in the sort list. At time t1, converter control section 50a sets cell control state CL*-3 to "1" in order to bring selected cell 262-3 into the positive voltage insert state. At this time as well, since the cell 262-2 is in the bypass state, the cell 262-2 continues to maintain the current capacitor voltage Vc-2.

After that, from time t2 to time t3, each time the number of inserts Ncells sequentially changes to "2" and "3" (the absolute value increases), the converter control unit 50a changes the sort list In order to sequentially select the cells 262 with the second and third lowest capacitor voltages Vc (that is, Vc-2, Vc-1), and put the selected cells 262 in the positive voltage insert state, the cell control state Set CL* to "1". More specifically, the converter control unit 50a selects the cell 262-2 at time t2 to set the cell control state CL*-2 to "1", and selects the cell 262-1 at time t3 to control the cell. Set state CL*-1 to "1". The converter control unit 50a sets the cell control state CL*-2 to "1" at time t2, so that the capacitor C-2 of the cell 262-2 is charged, and the capacitor voltage Vc-2 changes to It rises (increases).

After that, at time t4, when the polarity of the arm current Iarm becomes negative (discharge polarity), the cell 262-2 in the positive voltage insertion state discharges the power accumulated in the capacitor C-2. Therefore, the capacitor voltage Vc-2 drops (decreases) as the discharge progresses.

After that, at time t5, when the number of inserts Ncells changes to "2" (the absolute value decreases), the converter control unit 50a determines that the polarity of the arm voltage command value Varm* at this time is positive and the arm current It is determined that the polarity of Iarm is negative (discharge polarity). Therefore, the converter control unit 50a refers to the sort list and selects the cell 262 that is currently in the positive voltage insertion state and has a capacitor C with a small amount of stored power as the cell 262 to be put into the bypass state. Here, converter control 50a selects cell 262-3 with the lowest capacitor voltage Vc (ie, Vc-3) in the sort list. At time t5, the converter control unit 50a sets the cell control state CL*-3 to "0" in order to bring the selected cell 262-3 into the bypass state. At this time as well, since the cell 262-2 is in the positive voltage insertion state, the power stored in the capacitor C-2 continues to be discharged, and the capacitor voltage Vc-2 drops.

After that, at time t6, when the capacitor voltage Vc-2 of the cell 262-2 exceeds the threshold Vc-min, the converter control unit 50a refers to the sort list to put the cell 262-2 into the bypass state. selects the cell 262 with capacitor C that is currently bypassed and has more power stored as the cell 262 to be put into the positive voltage insert state instead of the bypassed cell 262-2. Here, cell 262-3 is the only cell 262 in the positive voltage insert state. Therefore, converter control unit 50a selects cell 262-3, which has the lowest capacitor voltage Vc in the sort list (that is, Vc-3) but is currently in the bypass state. At time t6, the converter control unit 50a sets the cell control state CL*-2 to "0" in order to bring the cell 262-2 into the bypass state. As a result, the discharge from the cell 262-2 is stopped and the discharge from the capacitor C-2 provided in the cell 262-2 is continued, so that the capacitor voltage Vc-2 is reduced to This eliminates the case where the threshold value Vc-min is significantly decreased. That is, the capacitor voltage Vc-2 is maintained at a voltage value close to the threshold Vc-min as indicated by the solid line in FIG. Furthermore, at time t6, converter control section 50a sets cell control state CL*-3 to "1" in order to bring selected cell 262-3 into the positive voltage insert state. As a result, the capacitor voltage of the cell 262-3 is output as an alternative, and the arm voltage Varm deviates (includes error) from the ideal stepped waveform according to the arm voltage command value Varm*. disappears.

After that, at time t7, when the number of inserts Ncells changes to "1" (the absolute value decreases), the converter control unit 50a determines that the polarity of the arm voltage command value Varm* at this time is positive and the arm current It is determined that the polarity of Iarm is negative (discharge polarity). Therefore, the converter control unit 50a refers to the sort list and selects the cell 262 that is currently in the positive voltage insertion state and has a capacitor C with a small amount of stored power as the cell 262 to be put into the bypass state. Here, converter control 50a selects cell 262-3 with the lowest capacitor voltage Vc (ie, Vc-3) in the sort list. At time t7, the converter control unit 50a sets the cell control state CL*-3 to "0" in order to bring the selected cell 262-3 into the bypass state. Also at this time, since the cell 262-2 is in the bypass state, the capacitor voltage Vc-2 of the cell 262-2 continues to be maintained at a voltage value close to the current threshold Vc-min.

After that, at time t8, when the number of inserts Ncells changes to "0" (the absolute value decreases), the converter control unit 50a selects cells 262 from the lowest capacitor voltage Vc in the sort list as at time t5. is selected, and the cell control state CL* is set to "0" to put the selected cell 262 into the bypass state. Here, since the only cell 262 in the positive voltage insert state is the cell 262-1, the converter control unit 50a selects the sort list with the highest capacitor voltage Vc (that is, Vc-1), but , select cell 262-1, which is currently in the positive voltage insert state. Also at this time, since the cell 262-2 is in the bypass state, the capacitor voltage Vc-2 of the cell 262-2 continues to be maintained at a voltage value close to the current threshold Vc-min.

After that, at time t9, when the number of inserts Ncells changes to "-1" (the absolute value increases), the converter control unit 50a determines that the polarity of the arm voltage command value Varm* at this time is negative and the arm It is determined that the polarity of the current Iarm is negative (charging polarity). Therefore, the converter control unit 50a refers to the sort list and selects the cell 262 that is currently bypassed and has a capacitor C with less stored power as the cell 262 to be placed in the negative voltage insert state. Here, converter control 50a selects cell 262-3 with the lowest capacitor voltage Vc (ie, Vc-3) in the sort list. At time t9, the converter control unit 50a sets the cell control state CL*-3 to "-1" in order to bring the selected cell 262-3 into the negative voltage insert state. Also at this time, since the cell 262-2 is in the bypass state, the capacitor voltage Vc-2 of the cell 262-2 continues to be maintained at a voltage value close to the current threshold Vc-min.

After that, from time t10 to time t11, each time the number of inserts Ncells sequentially changes to "-2" and "-3" (the absolute value increases), the converter control unit 50a, like at time t9, Cells 262 having the second and third lowest capacitor voltages Vc (that is, Vc-2, Vc-1) in the sort list are sequentially selected, and the selected cells 262 are placed in the negative voltage insert state. Set the control state CL* to "-1". More specifically, the converter control unit 50a selects the cell 262-2 at time t10 to set the cell control state CL*-2 to "-1", and selects the cell 262-1 at time t11 to set the cell Control state CL*-1 is set to "-1". At time t10, the converter control unit 50a sets the cell control state CL*-2 to "-1", so that the capacitor C-2 of the cell 262-2 is charged, and the capacitor voltage Vc-2 changes to increases (increases).

After that, at time t12, the sort list is updated. Also, when the polarity of the arm current Iarm becomes positive (discharge polarity), the cell 262-2 in the negative voltage insert state discharges the power stored in the capacitor C-2. Therefore, the capacitor voltage Vc-2 drops (decreases) as the discharge progresses.

After that, at time t13, when the number of inserts Ncells changes to "-2" (the absolute value decreases), the converter control unit 50a determines that the polarity of the arm voltage command value Varm* at this time is negative and the arm The polarity of the current Iarm is determined to be positive (discharge polarity). Therefore, the converter control unit 50a refers to the sort list and selects the cell 262 that is currently in the negative voltage insertion state and has the capacitor C with the small amount of stored power as the cell 262 to be put into the bypass state. Here, converter control 50a selects cell 262-1 with the lowest capacitor voltage Vc (ie, Vc-1) in the sort list. At time t13, the converter control unit 50a sets the cell control state CL*-1 to "0" in order to bring the selected cell 262-1 into the bypass state. At this time as well, since the cell 262-2 is in the negative voltage insert state, the capacitor C-2 continues to be discharged, and the capacitor voltage Vc-2 continues to drop.

After that, from time t14 to time t15, each time the number of inserts Ncells sequentially changes to "-1" and "0" (the absolute value decreases), the converter control unit 50a performs sorting in the same manner as at time t13. Cell control state CL Set * to "0". More specifically, the converter control unit 50a selects the cell 262-2 at time t14 to set the cell control state CL*-2 to "0", and selects the cell 262-3 at time t15 to control the cell. Set state CL*-3 to "0". At time t14, the converter control unit 50a sets the cell control state CL*-2 to "0", so that the discharge from the capacitor C-2 of the cell 262-2 is stopped, and the capacitor voltage Vc-2 is now voltage value.

In this way, the converter control unit 50a, based on the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm, each time the number of inserts Ncells changes (the absolute value increases or decreases). , determine the discharge polarity or the charge polarity, refer to the sort list, select the cell 262 whose control state (cell control state CL*) is to be the positive voltage insert state, the bypass state, or the negative voltage insert state, Controls the control state of the selected cell 262, namely gate signal gta, gate signal gtb, gate signal gtc, and gate signal gtd. At this time, if the capacitor voltage Vc in any of the cells 262 exceeds the threshold Vc-max (exceeds the threshold Vc-max) or exceeds the threshold Vc-min (below the threshold Vc-min ), the converter control unit 50a performs balance control. That is, the converter control unit 50a performs balance control when the capacitor voltage Vc exceeds the threshold Vc-max or the threshold Vc-min regardless of the sort list calculation (generation) timing or switching control timing. conduct. In the balance control, the converter control section 50a puts the cell 262 in which the capacitor voltage Vc exceeds the threshold Vc-max or the threshold Vc-min into the bypass state. As a result, the bypassed cell 262 stops charging to or discharging from the capacitor C. FIG. Then, the converter control unit 50a refers to the sort list, selects a cell 262 as a substitute for the cell 262 placed in the bypass state from among the cells 262 currently in the bypass state, and selects the cell 262 in the insert state (positive voltage insert state). state, or negative voltage insert state). As a result, in the power converter 10, the capacitor C provided in the cell 262 is no longer charged or discharged (without being overcharged or overdischarged), and the charge amount of the capacitor C becomes relatively It can be balanced to be uniform. In the third operation of the power converter 2 shown in FIG. 8, at time t6, the capacitor voltage Vc-2 of the cell 262-2 exceeds the threshold Vc-min. Balance control is similar for other cells 262 . In the third operation of the power conversion device 2 shown in FIG. 8, at time t6, the cell 262-3 is selected as a substitute for the cell 262-2. The same is true for In the third operation of the power conversion device 2 shown in FIG. 8, the balance control in the converter control unit 50a is the balance control when the capacitor voltage Vc-2 of the cell 262-2 exceeds the threshold Vc-min. However, if the balance control when the capacitor voltage Vc of any cell 262 provided in the arm unit 26 exceeds the threshold Vc-max is equivalent to the balance control of the first operation described above. good.

[Fourth operation of the power converter]
In the above-described third operation, the converter control section 50a performs single-pulse control, but the converter control section 50a can also perform double-pulse control. Next, as another operation of the power conversion device 2 (another example of balance control in the converter control unit 50a), an operation when the converter control unit 50a performs multi-pulse control will be described.

FIG. 9 is a timing chart illustrating an example of operation timing of the fourth operation in the power conversion device 2. As shown in FIG. The fourth operation shown in FIG. 9 is also an operation when the number of cells 262 provided in the arm unit 26 is three (n=3), similar to the third operation shown in FIG. In the fourth operation, the number of inserts Ncells is, for example, the modulated wave based on the arm voltage command value Varm* and the same number as the number of cells 262 belonging to the arm unit 26 (here, "3"). By comparing each triangular wave carrier, the value of the arm voltage command value Varm* (modulation wave) is calculated as the number of triangular carrier waves exceeding the value of the triangular wave carrier. That is, the fourth operation shown in FIG. 9 is the operation timing when the converter control section 50a performs multi-pulse control. Therefore, the operation timing of the fourth operation shown in FIG. 9 shows an enlarged partial range within one cycle of the arm voltage command value Varm*.

The fourth operation shown in FIG. 9 is, for example, in a discharge polarity (discharge period) in which the arm voltage command value Varm* is positive (Varm*>0) and the arm current Iarm is negative (Iarm<0). , the number of cells 262 in the positive voltage insert state represented by the number of inserts Ncells is "2" before changing from "2" to "1", that is, the number of cells 262 in the positive voltage insert state is "2". is an example of a case where balance control is performed during a period in which there is no change in . In the fourth operation shown in FIG. 9, the sort list calculation unit 54a generates the sort list in a shorter calculation cycle TS2 than in the third operation shown in FIG. However, even in the fourth operation shown in FIG. 9, the calculation period TS2 is a period of time intervals longer than the acquisition period TS1 (TS2>TS1). FIG. 9 shows an example of balance control of the converter control unit 50a when the capacitor voltage Vc-3 of the cell 262-3 provided in the arm unit 26 exceeds the threshold Vc-min (when it falls below the threshold Vc-min). is shown.

At time t0 shown in FIG. 9, the number of inserts Ncells is "2". For this reason, the converter control unit 50a refers to the sort list and selects the cell 262 having the capacitor C in which a large amount of power is stored as the cell 262 to be brought into the positive voltage insertion state. More specifically, converter control unit 50a selects cell 262-1 and cell 262-3, which are the two highest capacitor voltages Vc (Vc-1 and Vc-3) in the sort list. there is Therefore, at time t0 shown in FIG. 9, the converter control unit 50a sets the cell control state CL*-1 and the cell control state CL*-3 to bring the selected two cells 262 into the positive voltage insert state. are set to "1". As a result, the power stored in the capacitor C-3 is discharged from the cell 262-3, and the capacitor voltage Vc-3 drops (decreases) along with the discharge.

After that, at time t1, when the capacitor voltage Vc-3 of the cell 262-3 exceeds the threshold Vc-min, the converter control unit 50a refers to the sort list to put the cell 262-3 in the bypass state. selects the cell 262 with capacitor C that is currently bypassed and has more power stored as the cell 262 to be put into the positive voltage insert state instead of the bypassed cell 262-3. Here, cell 262-2 is the only cell 262 in the bypass state. Therefore, converter control section 50a selects cell 262-2, which is the third highest capacitor voltage Vc in the sort list (that is, Vc-2) but is currently in the bypass state. At time t1, the converter control unit 50a sets the cell control state CL*-3 to "0" in order to bring the cell 262-3 into the bypass state. As a result, the discharge from the cell 262-3 is stopped and the discharge from the capacitor C-3 provided in the cell 262-3 is continued. case), the capacitor voltage Vc-3 does not drop significantly below the threshold Vc-min. That is, the capacitor voltage Vc-3 is maintained at a voltage value close to the threshold Vc-min as indicated by the solid line in FIG. Furthermore, at time t1, converter control section 50a sets cell control state CL*-2 to "1" in order to bring selected cell 262-2 into the positive voltage insert state. This causes the capacitor voltage of cell 262-2 to be output instead and the arm voltage Varm to be maintained.

After that, at time t2, the sort list is updated. Here, it is assumed that the sort list is updated so that the capacitor voltage Vc-3 of the cell 262-3 is the lowest capacitor voltage Vc.

After that, at time t3, when the number of inserts Ncells changes to "1" (decreases), the converter control unit 50a refers to the sort list to refer to the current positive voltage insert state, and the accumulated power is The cell 262 with less capacitor C is selected as the cell 262 to be bypassed. Here, the converter control unit 50a selects the cell 262 that has the lower capacitor voltage Vc (that is, Vc-2) in the sort list among the cells 262-1 and 262-2 that are in the positive voltage insertion state. Select -2. At time t3, the converter control unit 50a sets the cell control state CL*-2 to "0" in order to bring the selected cell 262-2 into the bypass state. Also at this time, since the cell 262-3 is in the bypass state, the capacitor voltage Vc-3 of the cell 262-3 continues to be maintained at a voltage value close to the current threshold Vc-min.

Thus, the converter control unit 50a changes the number of inserts Ncells (absolute value increases or decreases), based on the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm, determine the discharge polarity or charge polarity, refer to the sort list, and control state Select a cell 262 that causes (cell control state CL*) to be in a positive voltage insert state, a bypass state, or a negative voltage insert state, and determine the control state of the selected cell 262, namely gate signal gta, gate signal gtb, gate signal gtc, and the gate signal gtd. At this time, also in the fourth operation, when the capacitor voltage Vc in any of the cells 262 exceeds the threshold Vc-max (exceeds the threshold Vc-max) or exceeds the threshold Vc-min (threshold Vc-min), the converter control section 50a performs balance control. That is, even in the fourth operation, the converter control unit 50a determines whether the capacitor voltage Vc exceeds the threshold Vc-max or the threshold Vc-min regardless of the sort list calculation (generation) timing or the switching control timing. Balance control is performed when Also in the balance control of the fourth operation, the converter control section 50a puts the cell 262 in which the capacitor voltage Vc exceeds the threshold Vc-max or the threshold Vc-min into the bypass state. As a result, the bypassed cell 262 stops charging to or discharging from the capacitor C also in the fourth operation. Then, in the fourth operation, the converter control unit 50a also refers to the sort list and selects the cell 262 to substitute for the bypassed cell 262 from among the cells 262 currently in the bypass state. to the insert state (positive voltage insert state or negative voltage insert state). As a result, even in the fourth operation, in the power converter 10, the capacitor C included in the cell 262 is no longer charged or discharged (without being overcharged or overdischarged), and the capacitor C can be balanced so that the amount of charge in is relatively uniform. In the fourth operation of the power converter 2 shown in FIG. 9, at time t1, the capacitor voltage Vc-3 of the cell 262-3 exceeds the threshold Vc-min. Balance control is similar for other cells 262 . In the fourth operation of the power converter 2 shown in FIG. 9, at time t1, the cell 262-2 is selected as a substitute for the cell 262-3. The same is true for In the fourth operation of the power conversion device 2 shown in FIG. 9, the balance control in the converter control unit 50a is the balance control when the capacitor voltage Vc-3 of the cell 262-3 exceeds the threshold Vc-min. However, if the balance control when the capacitor voltage Vc of any cell 262 provided in the arm unit 26 exceeds the threshold Vc-max is equivalent to the balance control of the fourth operation described above. good.

With such a configuration and operation, in the power converter 2, the converter control unit 50a changes (increases or decreases) the number of inserts Ncells of the cells 262 for each arm unit 26 included in the power converter 20. At each timing, it is determined whether the polarity is discharging or charging based on the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm. Then, in the power conversion device 2, the converter control unit 50a refers to the sort list calculated (generated) for each arm unit 26, and sets the control state to a positive voltage insert state, a bypass state, or a negative voltage insert state. Select the cell 262 that is to be set to change the control state of the selected cell 262 . At this time, if the capacitor voltage Vc in any of the cells 262 exceeds the threshold Vc-max or the threshold Vc-min, the converter control unit 50a puts the cell 262 into a bypass state, refers to the sort list, A replacement cell 262 is selected from among the cells 262 currently in the bypass state and brought into the insert state (positive voltage insert state or negative voltage insert state). As a result, even in the power conversion device 2, overcharging or overdischarging of the capacitor C provided in the cell 262 in which the capacitor voltage Vc exceeds the threshold Vc-max or the threshold Vc-min can be prevented, and the charge amount of the capacitor C can be It can be balanced to be relatively uniform. As a result, in the power converter 2, the risk of failure of the capacitor C and the switching element Q included in the cell 262 can be reduced in the power converter 20. For example, even when a system accident occurs, the capacitor voltage Vc It is possible to reduce the risk of a state in which the protective device of the power converter 10 is activated and the operation is stopped due to overvoltage or undervoltage. As a result, even in the power converter 2, it is possible to realize a highly reliable power converter with improved continuous operation performance when a system fault occurs.

As described above, in the power conversion device 2 of the second embodiment, as in the power conversion device 1 of the first embodiment, the converter control unit 50a controls each arm unit 26 included in the power converter 20. , it is determined whether the polarity is discharge or charge based on the polarity of the arm voltage command value Varm* and the polarity of the arm current Iarm at each timing when the number Ncells of cells 262 to be inserted changes (increases or decreases). do. Then, in the power conversion device 2 of the second embodiment, the converter control unit 50a refers to the sort list calculated (generated) for each arm unit 26, and sets the control state to the positive voltage insertion state, the bypass state, or the like. Alternatively, select a cell 262 to be placed in the negative voltage insert state and change the control state of the selected cell 262 . At this time, in the power converter 2 of the second embodiment, when the capacitor voltage Vc in any of the cells 262 exceeds the threshold Vc-max or the threshold Vc-min, the converter control unit 50a causes the cell 262 to A bypass state is set, a sort list is referred to, and an alternative cell 262 is selected from among the cells 262 currently in the bypass state and put into the insert state (positive voltage insert state or negative voltage insert state). As a result, in the power conversion device 2 of the second embodiment, as in the power conversion device 1 of the first embodiment, the capacitor voltage Vc exceeds the threshold Vc-max or the threshold Vc-min. Overcharging and overdischarging of C can be prevented, and the charge amount of capacitor C can be balanced so as to be relatively uniform. As a result, in the power converter 2 of the second embodiment, as in the power converter 1 of the first embodiment, the failure risk of the capacitor C and the switching element Q provided in the cell 262 in the power converter 20 is reduced. For example, even when a system fault or the like occurs, the capacitor voltage Vc reaches an overvoltage or an undervoltage, which causes the protective device of the power converter 10 to operate and stop the operation. Risk can be mitigated. As a result, even with the power conversion device 2 of the second embodiment, it is possible to realize a highly reliable power conversion device with improved continuous operation performance when a system fault occurs.

As described above, in the power conversion device of each embodiment, the converter control unit that changes the control state of the unit converter in the arm unit provided in the power converter changes the power every predetermined (constant) acquisition cycle TS1. Acquire the capacitor voltage of the capacitor provided in the converter. Then, in the power conversion device of each embodiment, when the capacitor voltage of any of the unit converters exceeds the threshold (upper threshold Vc-max or lower threshold Vc-min), the converter control unit Regardless of the timing of controlling each unit converter, the control state of the unit converter whose capacitor voltage exceeds the threshold is changed to stop charging or discharging the capacitor. In other words, in the power conversion device of each embodiment, the converter control unit stops charging and discharging the unit converter whose capacitor voltage exceeds the threshold, and excludes it from the unit converters that output the capacitor voltage in the arm unit. . Then, in the power conversion device of each embodiment, as a substitute for the unit converter whose charging and discharging is stopped due to the capacitor voltage exceeding the threshold, among the unit converters that did not output the capacitor voltage in the arm unit , change the control state of the same number of other unit converters to start charging and discharging. As a result, in the power conversion device of each embodiment, the charge amount of the capacitor provided in the unit converter is balanced so that it becomes relatively uniform, and the failure risk of the capacitor and switching element provided in the unit converter can be reduced. can be done. As a result, in the power conversion device of each embodiment, for example, when a system fault or the like occurs in an AC system to which the power conversion device is connected, the capacitor voltage reaches overvoltage or undervoltage, thereby protecting the power converter. It is possible to reduce the risk that the device will operate and stop operating. As a result, in the power conversion device of each embodiment, it is possible to realize a highly reliable power conversion device with improved continuous operation performance when a system fault occurs.

In the power converter of each embodiment described above, the insert number calculation unit provided in the converter control unit calculates (calculates) the insert number Ncells representing the number of cells (integer value) to be placed in the inserted state, and the converter A case has been described where the cell selection control section provided in the control section selects cells to be changed to the insert state or the bypass state, triggered by a change in the number of inserts Ncells. However, the trigger for the cell selection control unit to select a cell is not limited to the change in the number of inserts Ncells. For example, instead of the number of cells to be inserted Ncells, which indicates the number of cells to be placed in the insert state, the cell selection control unit changes to the insert state or the bypass state when the number of cells (integer value) to be placed in the bypass state is changed. You may select the cell that The operation and processing of the power conversion device and converter control unit in this case may be equivalent to the operation and processing of the power conversion device and converter control unit in each of the above-described embodiments.

According to at least one embodiment described above, an energy storage element (C) for storing power and a plurality of switching elements capable of regulating the storage of power in the energy storage element or the discharge of power stored in the energy storage element. A power converter (10) having at least one arm unit (16) in which a plurality of unit converters (162) having elements (Q, D) are connected in series, and at least a first end of the unit converter ( A first control state (insertion state) for outputting a voltage (Vc) across the terminals of the energy storage element between TP) and a second end (TN), and short-circuiting the first end and the second end of the unit converter. a converter control unit (50) that controls the power conversion operation of the power converter by switching to one of the control states of a second control state (bypass state) that causes the The number of states representing the number of unit converters belonging to the arm unit whose control state is switched according to the arm voltage command value (Varm*), which is the target value of the arm voltage (Varm) to be output from the arm unit. A state number calculator (52) for calculating (the number of inserts Ncells) and a list representing the magnitude relationship between the terminal voltages based on the terminal voltages of the energy storage elements detected at the predetermined first time interval (TS1). A list calculator (54) that generates information (sorted list) for each predetermined second time interval (TS2) longer than the first time interval, the polarity of the arm current (Iarm) flowing through the arm unit, a unit converter selection unit (56) for selecting a unit converter whose current control state is to be changed based on the number of states, the list information, and the voltage across the terminals of the energy storage element; The part detects the polarity of the arm current at the first time interval in the charging period in which the polarity of the arm current is the charging polarity for accumulating power in the energy storage element of the unit converter in the first control state. Second control of the first unit converter when the voltage across the terminals of the energy storage element of the first unit converter, which is the unit converter, exceeds a first threshold (Vc-max) higher than the rated voltage state, and among the unit converters in the second control state, the same number of other unit converters as the first unit converter are selected as unit converters to be changed to the first control state, and the polarity of the arm current is a discharge period in which the discharge polarity is for discharging power from the energy storage element of the unit converter in the first control state, the second When the voltage across the terminals of the energy storage element of the unit converter exceeds a second threshold (Vc-min) lower than the rated voltage, the second unit converter is changed to the second control state, and the second By selecting the same number of other unit converters as the second unit converters among the unit converters in the controlled state as the unit converters to be changed to the first controlled state, the energy storage elements included in the unit converters are increased. A highly reliable power converter can be realized by suppressing an increase in the fluctuation width of the voltage between terminals.

While several embodiments of the invention have been described, these embodiments have been presented by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and modifications can be made without departing from the scope of the invention. These embodiments and their modifications are included in the scope and spirit of the invention, as well as the scope of the invention described in the claims and equivalents thereof.

1, 2... power converter, 10... power converter, 12, 12-R, 12-S, 12-T... leg, 14, 14-PR, 14-NR, 14-P-S, 14-NS, 14-PT, 14-NT, 14-RS, 14-ST, 14-TR Reactor, 16, 16-PR, 16- NR, 16-P-S, 16-NS, 16-PT, 16-N-T Arm units, 162, 162-1, 162-n, 162-1-P-R , 162-nPR, 162-1-NR, 162-nNR, 162-1-PS, 162-nPS, 162-1-NS, 162 -nNS, 162-1-PT, 162-nPT, 162-1-NT, 162-nNT ... cell, 20 ... power converter , 22, 22-RS, 22-ST, 22-TR... legs, 26, 26-RS, 26-ST, 26-TR... arm units, 262, 262-1, 262-n, 262- 1-RS, 262-n-RS, 262-1-ST, 262-n-ST, 262-1-TR, 262-n-TR... cell, 50, 50a... converter control section, 52 , 52a . , Q4 Switching element D, D1, D2, D3, D4 Diode C Capacitor TR Transformer R, S, T AC terminal P Positive Side terminal, N: Negative side terminal, CA, CA-R, CA-S, CA-T, CB, CB-R, CB-S, CB-T: AC terminal, CP, CP-R, CP-S, CP-T, CN, CN-R, CN-S, CN-T... DC terminal, TP... Positive terminal, TN... Negative terminal

Claims (12)

A plurality of unit converters having an energy storage element for storing power and a plurality of switching elements capable of adjusting the storage of power in the energy storage element or the discharge of the power stored in the energy storage element are connected in series. a power converter having at least one arm unit;
at least a first control state for outputting a voltage across the terminals of the energy storage element between the first end and the second end of the unit converter; and the first end and the second end of the unit converter. A converter control unit that controls the power conversion operation in the power converter by switching to either control state from a second control state that short-circuits the
with
The converter control unit
A state representing the number of the unit converters assigned to one of the control states among the unit converters belonging to the arm unit according to an arm voltage command value that is a target value of the arm voltage to be output from the arm unit a state number calculator that calculates the number of
Based on the voltage across the terminals of the energy storage element detected at a predetermined first time interval, list information representing the magnitude relationship between the voltages across the terminals is displayed for a predetermined second time longer than the first time interval. a list operation unit that generates for each interval;
A unit converter that selects the unit converter that changes the current control state based on the polarity of the arm current flowing through the arm unit, the number of states, the list information, and the voltage across the terminals of the energy storage element. a device selection unit;
with
The unit converter selection unit
When the polarity of the arm current is the charging polarity for accumulating power in the energy storage element of the unit converter in the first control state,
The voltage across the terminals of the energy storage element of the first unit converter, which is the unit converter in the first control state, detected at the first time interval exceeds a first threshold higher than the rated voltage. At that time, the first unit converter is changed to the second control state, and among the unit converters in the second control state, the same number of the other unit converters as the first unit converter is changed. , as the unit converter to change to the first control state,
When the polarity of the arm current is a discharge period in which the discharge polarity discharges power from the energy storage element of the unit converter in the first control state,
The voltage across the terminals of the energy storage element of the second unit converter, which is the unit converter in the first control state, detected at the first time interval exceeds a second threshold lower than the rated voltage. At that time, the second unit converter is changed to the second control state, and among the unit converters in the second control state, the same number of the other unit converters as the second unit converter is changed. , selecting as said unit converter to change to said first control state;
Power converter. The unit converter selection unit
When selecting the unit converter to be changed to the first control state from among the unit converters in the second control state,
during the charging period, preferentially selecting the unit converter having the energy storage element with a relatively low inter-terminal voltage of the energy storage element included in the list information;
during the discharge period, preferentially selecting the unit converter having the energy storage element having a relatively high voltage across the terminals of the energy storage element included in the list information;
When selecting the unit converter to be changed to the second control state from among the unit converters in the first control state,
during the charging period, preferentially selecting the unit converter having the energy storage element having a relatively high voltage across the terminals of the energy storage element included in the list information;
In the discharge period, preferentially selecting the unit converter having the energy storage element with a relatively low inter-terminal voltage of the energy storage element included in the list information.
The power converter according to claim 1. The unit converter selection unit
Triggered by the change in the number of states, starting selection of the unit converter to change the control state;
selecting the unit converter to be changed to the first control state from among the unit converters in the second control state when the absolute value of the number of states assigned to the first control state increases;
selecting the unit converter to be changed to the second control state from among the unit converters in the first control state when the absolute value of the number of states assigned to the first control state decreases;
The power converter according to claim 1 or 2. The state number calculator approximates to an integer a value obtained by dividing the arm voltage command value by an average value or a rated value of the voltage across the terminals of the energy storage element of the unit converter belonging to the arm unit, calculating the value of the approximation result as the number of states to be assigned to the first control state;
The power converter according to any one of claims 1 to 3. The state number calculation unit
A modulated wave based on the arm voltage command value is compared with each triangular wave carrier phase-shifted by the same number as the number of unit converters belonging to the arm unit, and the value of the modulated wave is the triangular wave carrier. calculating the number of triangular wave carriers larger than the value as the number of states to be assigned to the first control state;
The power converter according to any one of claims 1 to 3. The state number calculation unit
A modulated wave based on the arm voltage command value is compared with each triangular wave carrier whose level is shifted by the same number as the number of unit converters belonging to the arm unit, and the value of the modulated wave is compared with that of the triangular wave carrier. calculating the number of triangular wave carriers larger than the value as the number of states to be assigned to the first control state;
The power converter according to any one of claims 1 to 3. The unit converter includes a series circuit in which two switching elements, a first switching element and a second switching element, are connected in series and the energy storage element is connected in parallel. A half bridge circuit having a connection point with a second switching element as the first end and a connection point between the second switching element and the energy storage element as the second end,
The converter control unit
setting the unit converter to the first control state by setting the first switching element to a conducting state and setting the second switching element to a non-conducting state;
setting the unit converter to the second control state by setting the first switching element to a non-conducting state and setting the second switching element to a conducting state;
The power converter according to any one of claims 1 to 6. The unit converter includes a first series circuit in which two switching elements of a first switching element and a second switching element are connected in series, and two switching elements of a third switching element and a fourth switching element. A second series circuit in which switching elements are connected in series and the energy storage element are connected in parallel, a connection point between the first switching element and the second switching element is defined as the first end, A full bridge circuit having a connection point between the switching element of No. 3 and the fourth switching element as the second end,
The converter control unit
By setting the first switching element in a conducting state, the second switching element in a non-conducting state, the third switching element in a non-conducting state, and the fourth switching element in a conducting state, the setting the unit converter to the first control state, which is the first control state in which a positive voltage is output;
By setting the first switching element in a non-conducting state, the second switching element in a conducting state, the third switching element in a conducting state, and the fourth switching element in a non-conducting state, the setting the unit converter to a second first control state, which is the first control state in which a negative voltage is output;
The first switching element is rendered conductive, the second switching element is rendered non-conductive, the third switching element is rendered conductive, and the fourth switching element is rendered non-conductive; 1 switching element is rendered non-conductive, the second switching element is rendered conductive, the third switching element is rendered non-conductive, and the fourth switching element is rendered conductive; placing the device in the second control state,
determining the first first control state and the second first control state according to the polarity of the arm voltage represented by the arm voltage command value;
The power converter according to any one of claims 1 to 6. The power converter has a phase unit in which two arm units, a first arm unit and a second arm unit, are connected in series for each AC phase, and the first arm unit belonging to each of the phase units. A connection point between the arm unit and the second arm unit is an AC terminal connected to the corresponding AC phase, and the first arm unit and the second arm unit are connected to one end or in series. An inductance element is connected to an arbitrary position between each of the unit converters connected, and terminals of the first arm unit and the second arm unit opposite to the AC terminals are DC terminals. is a double star-connected modular multi-level converter,
The converter control unit
an AC voltage command value and a DC voltage command value are distributed to the first arm unit and the second arm unit belonging to each of the phase units to obtain the respective arm voltage command values;
changing the control state according to the distributed arm voltage command value for each arm unit;
The power converter according to any one of claims 1 to 8. The power converter has the arm unit connected between AC terminals of AC phases, and has an inductance at one end of each arm unit or at an arbitrary position between unit converters connected in series. A single delta-connected modular multi-level converter with connected elements,
The converter control unit
An AC voltage command value is distributed to each of the arm units between the AC terminals to obtain each of the arm voltage command values,
changing the control state according to the distributed arm voltage command value for each arm unit;
The power converter according to any one of claims 1 to 8. A plurality of unit converters having an energy storage element for storing power and a plurality of switching elements capable of adjusting the storage of power in the energy storage element or the discharge of the power stored in the energy storage element are connected in series. a power converter having at least one arm unit;
at least a first control state for outputting a voltage across the terminals of the energy storage element between the first end and the second end of the unit converter; and the first end and the second end of the unit converter. A control method for a power conversion device comprising:
The computer of the converter control unit,
A state representing the number of the unit converters assigned to one of the control states among the unit converters belonging to the arm unit according to an arm voltage command value that is a target value of the arm voltage to be output from the arm unit calculate the number,
Based on the voltage across the terminals of the energy storage element detected at a predetermined first time interval, list information representing the magnitude relationship between the voltages across the terminals is displayed for a predetermined second time longer than the first time interval. generate for each interval,
when selecting the unit converter whose current control state is to be changed based on the polarity of the arm current flowing through the arm unit, the number of states, the list information, and the voltage across the terminals of the energy storage element; ,
When the polarity of the arm current is the charging polarity for accumulating power in the energy storage element of the unit converter in the first control state,
The voltage across the terminals of the energy storage element of the first unit converter, which is the unit converter in the first control state, detected at the first time interval exceeds a first threshold higher than the rated voltage. At that time, the first unit converter is changed to the second control state, and among the unit converters in the second control state, the same number of the other unit converters as the first unit converter is changed. , as said unit converter to change to said first control state,
When the polarity of the arm current is a discharge period in which the discharge polarity discharges power from the energy storage element of the unit converter in the first control state,
The voltage across the terminals of the energy storage element of the second unit converter, which is the unit converter in the first control state, detected at the first time interval exceeds a second threshold lower than the rated voltage. At that time, the second unit converter is changed to the second control state, and among the unit converters in the second control state, the same number of the other unit converters as the second unit converter is changed. , selecting as the unit converter to change to the first control state;
A control method for a power converter. A plurality of unit converters having an energy storage element for storing power and a plurality of switching elements capable of adjusting the storage of power in the energy storage element or the discharge of the power stored in the energy storage element are connected in series. a power converter having at least one arm unit;
at least a first control state for outputting a voltage across the terminals of the energy storage element between the first end and the second end of the unit converter; and the first end and the second end of the unit converter. A program for controlling a power conversion device comprising:
In the computer of the converter control unit,
A state representing the number of the unit converters assigned to one of the control states among the unit converters belonging to the arm unit according to an arm voltage command value that is a target value of the arm voltage to be output from the arm unit calculate the number,
Based on the voltage between the terminals of the energy storage element detected at a predetermined first time interval, list information representing the magnitude relationship of the voltage between the terminals is sent to a predetermined second time interval longer than the first time interval. generated for each time interval,
When selecting the unit converter whose current control state is to be changed based on the polarity of the arm current flowing through the arm unit, the number of states, the list information, and the voltage across the terminals of the energy storage element ,
When the polarity of the arm current is the charging polarity for accumulating power in the energy storage element of the unit converter in the first control state,
The voltage across the terminals of the energy storage element of the first unit converter, which is the unit converter in the first control state, detected at the first time interval exceeds a first threshold higher than the rated voltage. when the first unit converter is changed to the second control state, and among the unit converters in the second control state, the same number of other unit converters as the first unit converter is selected as the unit converter to be changed to the first control state,
When the polarity of the arm current is a discharge period in which the discharge polarity discharges power from the energy storage element of the unit converter in the first control state,
The voltage across the terminals of the energy storage element of the second unit converter, which is the unit converter in the first control state, detected at the first time interval exceeds a second threshold lower than the rated voltage. when the second unit converter is changed to the second control state, and among the unit converters in the second control state, the same number of other unit converters as the second unit converter as the unit converter to change to the first control state.
program.

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