JP2023055236A - Surge absorption device - Google Patents

Abstract

To extend a surge protection period by operating a double protection circuit even when a first surge absorption element fails due to surge applied to a commercial power supply.SOLUTION: A first varistor 220 and a first fuse 210 are connected in series between power supply lines. A failure display circuit 230 and a double protection circuit 240 are connected in parallel to the fuse 210. When the first varistor 220 fails due to surge applied to a commercial power supply and the first fuse 210 blows out, the double protection circuit 240 is operated and a surge protection period is extended. Further, the failure display circuit 230 notifies that a first surge absorption element has failed.SELECTED DRAWING: Figure 2

Description

The present invention relates to a surge absorber that absorbs an external surge applied between power lines.

External surges applied between power supply lines (lightning surges caused by induced lightning, switching surges generated by circuit breakers, etc., or surges generated by electrostatic induction, electromagnetic induction noise, etc.) Some are equipped with surge absorbers that absorb them.

FIG. 6 shows a diagram showing the configuration of a conventional surge absorber. Surge absorber 601 is connected between power lines (eg, live line 106 and neutral line 107 of commercial power supply 101). Here, let C be the connection point between the surge absorber 601 and the live line 106 , and D be the connection point between the surge absorber 601 and the neutral line 107 . A surge absorber 601 has a fuse 602 and a varistor 603 connected in series between power lines, and a failure display circuit 610 connected in parallel to the varistor 603 .

The failure display circuit 610 is composed of a current limiting capacitor 611 , an LED 612 , a current limiting resistor 613 and a diode 614 . A current limiting capacitor 611, an LED 612, and a current limiting resistor 613 are connected in series between electrodes of the varistor 603 (connection point A and connection point B). The LED 612 is an element that lights up when a driving current is supplied from the power line through the fuse 602 and goes out when the driving current supply is stopped due to melting of the fuse 602 or the like. A diode 614 is connected in parallel with the LED 612 in the opposite polarity direction. That is, the anode of the LED 612 is connected to the cathode of the diode 614 , and the cathode of the LED 612 is connected to the anode of the diode 614 . When a reverse voltage is applied to the LED 612 (negative voltage to the anode of the LED 612 and positive voltage to the cathode), the reverse withstand voltage is smaller than that of a normal silicon diode (for example, about 5 V). put away. Therefore, a diode 614 is connected in parallel with the LED 612 in the reverse polarity direction to limit the reverse voltage applied to the LED 612 .

FIG. 7 shows the voltage-current characteristics of the varistor. A varistor is an element whose resistance value increases when the voltage applied across it decreases, and whose resistance value abruptly decreases when the voltage applied to the varistor exceeds a specified value. The voltage at which the resistance suddenly drops is called the varistor voltage (strictly speaking, the voltage between the varistor electrodes when a direct current of 1 mA is applied to the varistor is the varistor voltage). Here, the varistor voltage of the varistor 603 is defined as V1.

A surge absorption element such as the varistor 603 deteriorates each time a surge voltage is applied. As the deterioration progresses, eventually a short circuit failure occurs between the electrodes. If a surge voltage is applied in a short-circuit fault state, an abnormal current continues to flow through the varistor 603, possibly causing the varistor to explode or catch fire. Therefore, the fuse 602 is connected in series with the varistor 603, and even if the varistor 603 is short-circuited, a surge current flows and the fuse 602 blows, thereby preventing an abnormal current from continuing to flow through the varistor 603 for a long period of time. .

In FIG. 6, in normal operation (when the varistor 603 is not short-circuited), the fuse 602 is not blown. By visually observing the lighting of the LED 612, it can be confirmed that the surge absorber 601 is normal (that is, the varistor 603 is normal).

Here, an abnormal voltage is applied to the surge absorber 601 due to an external surge, and when the voltage applied to the surge absorber 601 exceeds the varistor voltage V1 of the varistor 603, the voltage VCD across the surge absorber 601 is clamped to the varistor voltage V1. be. This prevents an abnormal voltage from entering the AC/DC converter 104 . At this time, since a current also flows through the failure display circuit 610, the LED 612 is lit.

On the other hand, if an abnormal current continues to flow through the fuse 602 and the varistor 603 in an abnormal state (when the varistor 603 has a short-circuit failure), the fuse 602 will melt. When the fuse 602 blows, no current flows through the failure display circuit 610, so the LED 612 goes out. By visually checking whether the LED 612 is turned off, it can be confirmed that the surge absorber 601 is abnormal (that is, the varistor 603 is short-circuited) (see, for example, Patent Document 1).

JP 2012-222960 A

However, in the conventional surge absorber 601, when the varistor 603 is normal, a current always flows through the surge absorber 601, so that the surge absorber 601 consumes power. In addition, the varistor 603 may be short-circuited, and an abnormal current may continue to flow through the fuse 602 and the varistor 603, blowing the fuse. When fuse 602 blows, there is a problem that AC/DC converter 104 cannot be protected from external surges until surge absorber 601 is replaced.

The present invention reduces the power consumption of the surge absorber during normal operation, and even if the varistor short-circuits and the fuse blows, it is possible to protect against external surges until the surge absorber is replaced. It is an object of the present invention to provide a surge absorber that is

A surge absorber according to the present invention is a surge absorber connected between power lines to absorb a surge voltage applied between the power lines, wherein the surge absorber is connected between the power lines and applied between the power lines. a first surge absorbing element that has a high resistance when the voltage applied does not exceed a predetermined voltage and clamps the voltage when the predetermined voltage is exceeded; A first fuse that melts when one surge absorbing element short-circuits and an abnormal current flows and is connected in parallel to the first fuse, and if the first surge absorbing element short-circuits, the surge is absorbed. and a notifying circuit that is connected in parallel to the first fuse and that outputs a signal for notifying an abnormality when the first fuse blows. is.

According to the surge absorber of the present invention, while reducing the power consumption of the surge absorber in the normal state, even if the varistor short-circuits and the fuse blows, the surge absorber is replaced. Protection from surges is possible.

It is a figure which shows the connection structure of a commercial power supply, a power supply device, and load. It is a figure which shows the structure of the surge absorption apparatus in 1st Embodiment. It is a figure which shows operation|movement of the surge absorption apparatus in 1st Embodiment. It is a figure which shows the structure of the surge absorption apparatus in 2nd Embodiment. It is a figure which shows operation|movement of the surge absorption apparatus in 2nd Embodiment. It is a figure which shows the structure of the conventional surge absorber. FIG. 4 is a diagram showing voltage-current characteristics of a varistor;

FIG. 1 is a diagram showing the configuration of a commercial power supply 101, a power supply device 102, and a load 103. As shown in FIG.

The commercial power supply 101 supplies AC power to the power supply device 102 . The power supply device 102 is composed of an AC/DC converter 104 and a surge absorber 105 . AC/DC converter 104 converts AC power supplied from commercial power supply 101 into DC power and supplies power to load 103 . The load 103 is a circuit having electronic components, such as a control circuit for controlling the operation of the image forming apparatus.

A surge absorber 105 is connected between a live line 106 and a neutral line 107 as power supply lines. Surge absorber 105 protects AC/DC converter 104 from abnormal voltage by absorbing abnormal voltage caused by an external surge applied between power lines. External surges include lightning surges caused by lightning strikes and induced lightning, switching surges generated by circuit opening/closing operations of circuit breakers, etc., and surges generated by electrostatic induction, electromagnetic induction noise, and the like.

(First embodiment)
FIG. 2 is a diagram showing the configuration of the surge absorber 105 according to the first embodiment of the invention. In FIG. 2, the same components as in FIG. 1 are denoted by the same reference numerals.

The surge absorber 105 is composed of a first fuse 210 , a first varistor 220 , a failure indication circuit 230 and a double protection circuit 240 . Here, let C be the connection point between the surge absorber 105 and the live line 106 , and D be the connection point between the surge absorber 105 and the neutral line 107 . The first fuse 210 and the first varistor 220 are connected in series between the power supply lines (the live 106 line and the neutral line 107 of the commercial power supply 101).

A failure display circuit 230 as an alarm circuit is connected in parallel with the first fuse 210 and is composed of a current limiting capacitor 231 , an LED 232 , a current limiting resistor 233 and a diode 234 . The current limiting capacitor 231, the LED 232, and the current limiting resistor 233 are connected in series between the electrodes of the first fuse 210 (connection point A and connection point B). A diode 234 is connected in parallel with the LED 232 in the opposite polarity direction. That is, the anode of the LED 232 is connected to the cathode of the diode 234 , and the cathode of the LED 232 is connected to the anode of the diode 234 .

A double protection circuit 240 is connected in parallel to the first fuse 210 and comprises a second fuse 241 and a second varistor 242 . The second fuse 241 and the second varistor 242 are connected in series between the electrodes of the first fuse 210 (connection point A and connection point B).

Here, the first varistor 220 and the second varistor 242 function as a first surge absorption element and a second surge absorption element, respectively, which absorb an external surge voltage. The varistor voltage (predetermined voltage) of the first varistor 220 and the second varistor 242 is V1. The first varistor 220 and the second varistor 242 clamp the voltage VCD across the surge absorber 105 to the varistor voltage V1 when the voltage across the surge absorber 105 exceeds the varistor voltage V1. This prevents an abnormal voltage from entering the AC/DC converter 104 . When the first varistor 220 is normal, the second varistor 242 has a high resistance, so no current flows through the double protection circuit 240 and does not contribute to surge absorption protection. However, if the first varistor 220 short-circuits and the first fuse 210 blows, the double protection circuit 240 contributes to surge absorption protection.

Next, operation of the surge absorber 105 in the first embodiment will be described. FIG. 3 is a diagram showing the operation of the surge absorber 105 in the first embodiment.

In FIG. 3, the voltage VCD across the surge absorber 105 (shown in FIG. 3A) when the voltage VIN of the commercial power supply 101 changes as shown in FIG. ), and the failure/non-failure state of the first varistor 220 (FIG. 3(c)). In FIG. 3A, periods 0≦t<t1, t1≦t≦t2, t2<t<t3, t3≦t≦t4, t4<t≦t5, t5<t≦t6, t6<t≦t7, The operation at t7<t will be described.

[0≦t<t1]
During this period, voltage VIN of commercial power supply 101 does not exceed varistor voltage V1 of first varistor 220 . In other words, it is a period during which no surge occurs. During this period, voltage VIN of commercial power supply 101 does not exceed varistor voltage V1 of first varistor 220 . Therefore, the resistance value of the first varistor 220 is sufficiently high (high resistance), current does not flow through the LED 232 in the failure display circuit 230, and the LED 232 is in the off state. The operator can confirm that the surge absorber 105 is normal (that is, the first varistor 220 is normal) by visually checking whether the LED 232 is turned off.

Also, during this period, the resistance value of the first varistor 220 is sufficiently high, so that no current flows through the first varistor 220 . Moreover, since the varistor 242 also has a high resistance, current does not flow. Therefore, the voltage VCD across the surge absorber 105 becomes equal to the voltage VIN of the commercial power supply 101 .

[t1≤t≤t2]
During this period, an external surge is applied to the commercial power supply 101 and the voltage VIN of the commercial power supply 101 is equal to or higher than the varistor voltage V1. Here, in the external surge occurring during the period [t1≦t≦t2], the first varistor 220 is not short-circuited and the first fuse 210 is not blown.

During this period, the voltage VIN of the commercial power supply 101 exceeds the varistor voltage V1, but the first fuse 210 is not blown. Also, since the first varistor 220 is normal, no current flows through the double protection circuit 240 either. Since the voltage drop across the first fuse 210 is very small, no current flows through the LED 232 in the fault display circuit 230, and the LED 232 is in the off state. The operator can confirm that the surge absorber 105 is normal (that is, the first varistor 220 is normal) by visually checking that the LED is turned off.

Also, during this period, the voltage VIN of the commercial power supply 101 exceeds the varistor voltage V1 of the first varistor 220, so the voltage VCD across the surge absorber 105 is clamped to the varistor voltage V1 of the first varistor 220. . Therefore, the voltage VCD across the surge absorber 105 becomes equal to the varistor voltage V1 of the first varistor 220 .

Thus, when an external surge exceeding varistor voltage V1 is applied to commercial power supply 101, voltage VCD is clamped to varistor voltage V1. As a result, the AC/DC converter 104 located downstream of the surge absorber 105 can be protected from external surges.

[t2<t<t3]
During this period, voltage VIN of commercial power supply 101 does not exceed varistor voltage V1 of first varistor 220 . In other words, it is a period during which no surge occurs. Since the operation of the surge absorber 105 is the same as in the period [0≦t<t1], the explanation is omitted.

[t3≤t≤t4]
During this period, an external surge is applied to the commercial power supply 101 and the voltage VIN of the commercial power supply 101 is equal to or higher than the varistor voltage V1. Further, due to this external surge, deterioration of the first varistor 220 progresses at t=t3, causing a short-circuit failure, and abnormal current continues to flow, causing the first fuse 210 to blow. Since the first varistor 220 is short-circuited and the first fuse 210 is blown, the failure display circuit 230 and the double protection circuit 240 connected in parallel with the first fuse 210 are connected to the connection point C. A voltage VCD between points D is applied. Therefore, the double protection circuit 240 is brought into a state of contributing to surge absorption protection. Note that the second fuse 241 is not blown.

During this period, the voltage VCD between the connection point C and the connection point D is applied to the failure indication circuit 230 , so current flows through the failure indication circuit 230 . That is, the LED 232 is lit by the current flowing through the route of the commercial power supply 101, the current limiting capacitor 231, the LED 232, the current limiting resistor 233, and the first varistor 220. FIG. The operator can confirm that the surge absorber 105 is abnormal (that is, the first varistor 220 is short-circuited) by visually checking the lighting of the LED.

Also, during this period, the voltage VIN of the commercial power supply 101 exceeds the varistor voltage V1 of the second varistor 242, so the voltage VCD across the surge absorber 105 is clamped to the varistor voltage V1 by the second varistor 242. . Therefore, the voltage VCD across the surge absorber 105 becomes equal to the varistor voltage V1.

In this way, in a state in which deterioration of the first varistor 220 progresses to cause a short-circuit failure and the first fuse 210 blows, the double protection circuit 240 contributes to surge absorption protection. Even if an external surge exceeding the varistor voltage V1 is applied to the commercial power supply 101, the second varistor 240 clamps the voltage VCD across the surge absorber 105 to the varistor voltage V1. As a result, the voltage VCD across the surge absorber 105 is limited to the varistor voltage V1, and the AC/DC converter 104 behind the surge absorber 105 can be protected from external surges.

[t4<t≦t5]
During this period, an external surge is applied to the commercial power supply 101, but the voltage VIN of the commercial power supply 101 is equal to or lower than the varistor voltage V1 of the second varistor 242. FIG.

In this period, the first varistor 220 is short-circuited, the first fuse 210 is blown, and a current is flowing through the fault indication circuit 230 . Since the operation of the failure display circuit 230 is the same as in the period [t3≤t≤t4], the description is omitted.

In this period, since the voltage VIN of the commercial power supply 101 does not exceed the varistor voltage V1, the resistance value of the second varistor 242 is sufficiently high (high resistance), and the second fuse 241 is not blown. no current flows through the second varistor 242 . Therefore, the voltage VCD across the surge absorber 105 becomes equal to the voltage VIN of the commercial power supply 101 .

[t5<t≦t6]
During this period, the voltage VIN of the commercial power supply 101 does not exceed the varistor voltage V1. In other words, it is a period during which no surge occurs. In this period, the first varistor 220 is short-circuited, the first fuse 210 is blown, and a current is flowing through the fault indication circuit 230 . Since the voltage VIN of the commercial power supply 101 is negative, current flows through the route of the commercial power supply 101, the first varistor 220, the current limiting resistor 233, the diode 234, and the current limiting capacitor 231. The reverse voltage across the LED 232 becomes the forward voltage across the diode 234, thus protecting the LED 232.

Note that during this period, the voltage VIN of the commercial power supply 101 does not exceed the varistor voltage V1, and the operation of the double protection circuit 240 is the same as during the period [t4<t≦t5], so the description is omitted.

[t6 < t ≤ t7]
During this period, the voltage VIN of the commercial power supply 101 does not exceed the varistor voltage V1. In other words, it is a period during which no surge occurs. Since the operation is the same as in the period [t4<t≦t5], the explanation is omitted.

[t<t]
During this period, the voltage VIN of the commercial power supply 101 does not exceed the varistor voltage V1. In other words, it is a period during which no surge occurs. Since the operation is the same as in the period [t5<t≦t6], the explanation is omitted.

As described above, according to the first embodiment, when the surge absorber 103 is normal (when the first varistor 220 is normal), no current flows through the surge absorber 601. Power consumption can be reduced. In addition, in the event of an abnormality (a state in which the first varistor 220 is short-circuited and the fuse 210 is blown), the double protection circuit 240 operates to prevent AC /DC converter 104 can be protected from external surges.

In this embodiment, the LED 232 is used as the signal transmission element, but other signal transmission means (photocoupler, etc.) may be used. In addition, although a varistor is used as a surge absorbing element in this embodiment, other surge absorbing elements (arrestor, etc.) may be used. Also, two Zener diodes connected in series with opposite polarities may be used as the surge absorbing element.

In the present embodiment, the varistor voltage of the first varistor 220 and the varistor voltage of the second varistor 242 are set to V1, but the varistor voltage of the first varistor 220 and the varistor voltage of the second varistor 242 are different. can be Assuming that the varistor voltage of the first varistor 220 is V11 and the varistor voltage of the second varistor is V12, the voltage VDC is clamped to the varistor voltage V11 during the period t1<t<t2, and the voltage VDC is clamped to the varistor voltage V11 during the period t3<t<t4. It is clamped to the varistor voltage V12.

(Second embodiment)
FIG. 4 is a diagram showing the configuration of a surge absorber 105 according to the second embodiment of the invention. In FIG. 4, the same components as those in FIG. 2 are denoted by the same reference numerals, and description overlapping with that of the first embodiment is omitted.

The surge absorber 105 is composed of a first fuse 210 , a first varistor 220 , a failure indication circuit 410 and a double protection circuit 240 . Here, let C be the connection point between the surge absorber 105 and the live line 106 , and D be the connection point between the surge absorber 105 and the neutral line 107 . The first fuse 210 and the first varistor 220 are connected in series between the power supply lines (the live line 106 and the neutral line 107 of the commercial power supply 101).

A failure display circuit 410 as an alarm circuit is connected in parallel with the first fuse 210 and comprises a transformer 411 , a rectifier circuit 412 and a controller 413 . A primary side of the transformer 411 is connected in parallel with the first fuse 210 . One end of the secondary side of the transformer 411 is connected to GND, and the other end is connected to the input part of the rectifier circuit 412 . Controller 413 is connected to the output of rectifier circuit 412 . The controller 413 includes a central processing unit (CPU) (not shown), a memory (not shown), and the like, and controls the entire electronic device in which the power supply device is mounted.

A rectifier circuit 412 is composed of a diode 414 and a capacitor 415 . The anode of diode 414 is connected to the input of rectifier circuit 412 . The cathode of diode 414 is connected to the output of rectifier circuit 412 . One end of the capacitor 415 is connected to GND and the other end is connected to the output of the rectifier circuit 412 . Here, the voltage applied to the capacitor 415 is VE.

A double protection circuit 240 is connected in parallel to the first fuse 210 and comprises a second fuse 241 and a second varistor 242 . The second fuse 241 and the second varistor 242 are connected in series between the electrodes of the first fuse 210 (connection point A and connection point B).

Here, the varistor voltage of the first varistor 220 and the second varistor 242 is V1. In the first varistor 220 and the second varistor 242, when the voltage across the surge absorber 105 exceeds the varistor voltage V1, the voltage VCD across the surge absorber 105 is clamped to the varistor voltage V1. This prevents an abnormal voltage from entering the AC/DC converter 104 . As in the first embodiment, when the first varistor 220 is normal, the second varistor 242 has a high resistance. It does not contribute to absorption maintenance. However, if the first varistor 220 short-circuits and the first fuse 210 blows, the double protection circuit 240 contributes to surge absorption protection.

Next, operation of the surge absorber 105 in the second embodiment will be described. FIG. 5 is a diagram showing the operation of surge absorber 105 in the second embodiment. FIG. 5 shows the voltage VCD across the surge absorber 105 (shown in FIG. 5A) and the voltage VE across the capacitor 415 (shown in FIG. b) shown), and the failure/non-failure state of the first varistor 220 (FIG. 5(c)).

The operation in the periods 0≦t<t1, t1≦t≦t2, t2<t<t3, t3≦t≦t4, and t4<t will now be described.

[0≦t<t1]
During this period, the voltage VIN of the commercial power supply 101 does not exceed the varistor voltage V1. In other words, it is a period during which no surge occurs. Since the operation is the same as the period [0≦t<t1] of the first embodiment, the explanation is omitted.

[t1≤t≤t2]
During this period, an external surge is applied to the commercial power supply 101 and the voltage VIN of the commercial power supply 101 is equal to or higher than the varistor voltage V1. Here, in the external surge occurring during the period [t1≦t≦t2], the first varistor 220 is not short-circuited and the first fuse 210 is not blown.

During this period, the voltage VIN of the commercial power supply 101 exceeds the varistor voltage V1, but the first fuse 210 is not blown. Since the voltage drop across the first fuse 210 is very small, the voltage VE applied to the capacitor 415 in the fault indication circuit 410 is sufficiently low (approximately 0V). Since the voltage applied to controller 413 is sufficiently low, controller 413 can confirm that surge absorber 105 is normal (ie, first varistor 220 is normal).

Also, during this period, the voltage VIN of the commercial power supply 101 exceeds the varistor voltage V1, so the voltage VCD across the surge absorber 105 is clamped to the varistor voltage V1. Therefore, the voltage VCD across the surge absorber 105 becomes equal to the varistor voltage V1 of the first varistor 220 .

Thus, when an external surge exceeding the varistor voltage V1 of the first varistor 220 is applied to the commercial power supply 101, the voltage VCD across the surge absorber 105 is clamped to the varistor voltage V1. As a result, the voltage VCD across the surge absorber 105 is limited to the varistor voltage V1, and the AC/DC converter 104 behind the surge absorber 105 can be protected from external surges.

[t2<t<t3]
During this period, the voltage VIN of the commercial power supply 101 does not exceed the varistor voltage V1. In other words, it is a period during which no surge occurs. Since the operation of the surge absorber 105 is the same as in the period [0≦t<t1], the explanation is omitted.

[t3≤t≤t4]
During this period, an external surge is applied to the commercial power supply 101 and the voltage VIN of the commercial power supply 101 is equal to or higher than the varistor voltage V1. Further, due to this external surge, deterioration of the first varistor 220 progresses at t=t3, causing a short-circuit failure, and abnormal current continues to flow, causing the first fuse 210 to blow. Since the first varistor 220 is short-circuited and the first fuse 210 is blown, the connection point C is connected to the failure display circuit 410 and the double protection circuit 240 which are connected in parallel to the first fuse 210 . A voltage VCD between points D is applied. Note that the second fuse 241 is not blown. Here, when the turns ratio of the transformer 411 is n and the forward voltage of the diode 414 is VF, the voltage VE applied to the capacitor 415 is VE=VCD/n-VF.
Thus, the voltage VE applied to the capacitor 415 in the failure display circuit 410 is high. Since the voltage applied to the controller 413 is sufficiently high, the controller 413 can confirm that the surge absorber 105 is abnormal (that is, the first varistor 220 is short-circuited).

Also, during this period, the voltage VIN of the commercial power supply 101 exceeds the varistor voltage V1 of the second varistor 242, so the voltage VCD across the surge absorber 105 is clamped to the varistor voltage V1 of the second varistor 242. . Therefore, the voltage VCD across the surge absorber 105 becomes equal to the varistor voltage V1 of the second varistor 242 .

In this way, when an external surge exceeding the varistor voltage V1 of the second varistor 242 is applied to the commercial power supply 101 while the first fuse 210 is blown, the voltage VCD across the surge absorber 105 is reduced to the varistor voltage. It is clamped to voltage V1. As a result, the voltage VCD across the surge absorber 105 is limited to the varistor voltage V1 of the second varistor 242, and the AC/DC converter 104 behind the surge absorber 105 can be protected from external surges.

[t4<t]
During this period, an external surge is applied to the commercial power supply 101, but the voltage VIN of the commercial power supply 101 is equal to or lower than the varistor voltage V1 of the second varistor 242. FIG. During this period, the first varistor 220 is short-circuited and the first fuse 210 is melted, so that the voltage VCD is applied to the failure display circuit 410 . Since the operation of the failure display circuit 410 is the same as in the period [t3≤t≤t4], the description is omitted.

Also, during this period, the voltage VIN of the commercial power supply 101 does not exceed the varistor voltage V1 of the second varistor 242, so the resistance value of the second varistor 242 is sufficiently high (high resistance), No current flows through the varistor 242 . Therefore, the voltage VCD across the surge absorber 105 becomes equal to the voltage VIN of the commercial power supply 101 .

Note that the controller 413 determines that the surge absorber 105 is abnormal (that is, the first varistor 220 is short-circuited) because the voltage VE applied to the capacitor 415 is sufficiently high as after the period t3. . The controller 413 notifies the operator that the surge absorber 105 is abnormal by displaying a warning on the display 440 .

Further, as a warning method, a warning sound may be emitted from a speaker, or information may be transmitted to another device (not shown) using a communication line.

As described above, the second embodiment also has the same effect as the first embodiment.

104 AC/DC converter 105 surge absorber 210 first fuse 220 first varistor 230 fault indication circuit 232 LED
240 double protection circuit 242 second varistor

Claims (7)

A surge absorber that is connected between power lines and absorbs a surge voltage applied between the power lines,
a first surge absorbing element connected between the power lines, having a high resistance when the voltage applied between the power lines does not exceed a predetermined voltage, and clamping the voltage when the voltage exceeds the predetermined voltage;
a first fuse that is connected in series to the first surge absorbing element and melts when the first surge absorbing element short-circuits and an abnormal current flows;
a protection circuit connected in parallel to the first fuse and performing surge absorption protection when the first surge absorption element is short-circuited;
a notification circuit connected in parallel to the first fuse and outputting a signal for notifying an abnormality when the first fuse blows;
A surge absorber characterized by comprising: The protection circuit includes a second surge absorbing element and a second fuse that is connected in series to the second surge absorbing element, and that is fused when the second surge absorbing element short-circuits and an abnormal current flows. The surge absorber according to claim 1, characterized by comprising: The notification circuit is
a capacitor;
a signal transmission element connected in series with the capacitor and having polarity;
a resistor connected in series with the signal transmission element to limit current flowing through the capacitor and the signal transmission element;
a diode connected in parallel in a direction opposite in polarity to the signal transmission element;
3. The surge absorber according to claim 1, wherein when said first fuse blows, a current flows through said signal transmission element as said signal. The notification circuit is
a transformer whose primary side is connected in parallel with the first fuse;
rectifying means for rectifying the voltage output to the secondary side of the transformer,
one end of the secondary side of the transformer is connected to the rectifying means, the other end of the secondary side of the transformer is connected to GND,
3. The surge absorber according to claim 1, wherein when said first fuse blows, a voltage is output to the secondary side of said transformer, and said signal is output based on said voltage. 5. The surge absorber according to claim 1, wherein said first surge absorber element is a varistor, an arrester, or two Zener diodes connected in series with opposite polarities. 2. The surge absorbing device according to claim 1, wherein said protection circuit is connected in parallel with said first fuse and in series with said first surge absorbing element. 4. The surge absorber according to claim 3, wherein said signal transmission element is an LED or a photocoupler.

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