JP2023054298A - game machine - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a game machine capable of improving the processing speed of arithmetic processing means without increasing cost.

SOLUTION: A game machine includes ROM where a program for operating arithmetic processing means and data are stored and RAM. A specific performance control program (a program for executing reproduction data generation processing and lamp control data generation processing and an LED driver) among a plurality of light emission control programs stored in the ROM and related to light emission control is transferred to the RAM, and the specific light emission control program transferred to the RAM is executed.

SELECTED DRAWING: Figure 32

COPYRIGHT: (C)2023,JPO&INPIT

Description

The present invention relates to gaming machines such as pachislot machines.

Conventionally, a plurality of reels each having a plurality of patterns arranged on its surface, game medals, coins, etc. (hereinafter referred to as "game media") are inserted, and the player's operation of the start lever is detected, It detects that a player has pressed a start switch requesting the start of rotation of a plurality of reels and a stop button provided corresponding to each of the plurality of reels, and requests stoppage of the rotation of the relevant reel. a stop switch that outputs a signal; a stepping motor that is provided corresponding to each of a plurality of reels and transmits the respective driving force to each reel; and a reel control device that controls the operation of and rotates and stops each reel, and when it detects that the start lever has been operated, a lottery is performed based on a random number value, and the result of this lottery (hereinafter referred to as " A so-called pachislot machine is known that stops the rotation of the reels based on the timing of detecting that the stop button has been operated.

As a game machine of this kind, Patent Document 1 proposes a game machine that causes a CPU to execute a program stored in a ROM. Further, Patent Document 2 proposes a gaming machine that transfers a program stored in a ROM to a RAM by boot processing at startup and causes a CPU to execute the program transferred to the RAM.

JP-A-2000-296223 JP 2008-148891 A

In a conventional game machine in which a program stored in a ROM is executed by an arithmetic processing means such as a CPU, the arithmetic processing means accesses the ROM each time the program is executed. It slowed down the processing speed of On the other hand, a conventional game machine, which causes an arithmetic processing means such as a CPU to execute a program transferred to a RAM, requires an increased RAM capacity, resulting in increased costs.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a game machine capable of improving the processing speed of arithmetic processing means without increasing costs.

The game machine according to the present invention is
Effect control means (sub-control circuit 42) for controlling game effects,
A light emitting means (light source section) that emits light under the control of the effect control means;
and a light emission driving means (driver IC 128a etc.) for driving and controlling the light emitting means,
The production control means is
Arithmetic processing means (sub CPU 81) that performs arithmetic processing;
a first storage means (sub ROM 82) in which programs and data for operating the arithmetic processing means are stored;
a rewritable second storage means (sub-RAM 83) having a higher access speed than the first storage means;
The arithmetic processing means has light emission control means (lamp control task) for performing light emission control of the light emission means,
The light emission control means includes transfer means (ramp function RAM transfer processing) for transferring a specific light emission control program among a plurality of light emission control programs related to light emission control stored in the first storage means to the second storage means. have
the transfer means transfers the specific light emission control program only once when the initialization process after power-on is completed and the light emission control means is activated;
The specific light emission control program includes a process of acquiring lamp data (reproduction data generation process), a process of generating control data based on the acquired lamp data (lamp control data generation process), and the generated control A program for executing a process (lamp driver) for registering data and transmitting the control data to the light emission driving means,
A light emission control program other than the specific light emission control program is executed while being stored in the first storage means.

In addition, in the gaming machine according to the present invention,
Processing by the specific light emission control program may have a relatively higher processing load than processing by a light emission control program other than the specific light emission control program.

According to the present invention, it is possible to provide a gaming machine capable of improving the processing speed of the arithmetic processing means without incurring costs.

It is an explanatory view explaining the functional flow in the gaming machine of one embodiment of the present invention. 1 is a perspective view showing an example of the external configuration of a gaming machine according to an embodiment of the present invention; FIG. 1 is a front view of a gaming machine according to an embodiment of the present invention with a front panel removed; FIG. It is an LED arrangement port diagram in the gaming machine of one embodiment of the present invention. 1 is a perspective view showing the internal structure of the gaming machine of one embodiment of the present invention, with the front door opened. FIG. 1 is a block diagram showing the overall configuration of a circuit included in a gaming machine according to one embodiment of the present invention; FIG. It is a block diagram showing an internal configuration of a sub-control circuit in the gaming machine of one embodiment of the present invention. It is a figure which shows the data structure of the control data of the 1st mode in the gaming machine of one Embodiment of this invention. It is a figure which shows the data structure of the control data of 2nd mode in the gaming machine of one Embodiment of this invention. It is a figure which shows the data structure of the control data of the 3rd mode in the gaming machine of one Embodiment of this invention. It is a figure which shows an example of the symbol arrangement table in the gaming machine of one Embodiment of this invention. It is a figure which shows the day-by-month table in the gaming machine of one Embodiment of this invention. It is a diagram showing a date and time storage area in the gaming machine of one embodiment of the present invention. It is a figure which shows the reproduction|regeneration state management storage area|region in the gaming machine of one Embodiment of this invention. FIG. 4 is a diagram showing a specific example of a reproduction state management storage area in which lamp data is stored in the gaming machine according to one embodiment of the present invention; FIG. 4 is a diagram showing an example of reproduction of lamp data in the gaming machine of one embodiment of the present invention; FIG. 10 is a diagram showing a specific example of a reproduction state management storage area storing interrupt return lamp data in the gaming machine according to the embodiment of the present invention; FIG. 10 is a diagram showing an example of reproduction of ramp data for recovery from interruption in the gaming machine according to one embodiment of the present invention; 4 is a flowchart showing power-on processing of the main control circuit in the gaming machine of one embodiment of the present invention; 4 is a flowchart showing interrupt processing of the main CPU in the gaming machine of one embodiment of the present invention; 4 is a flowchart showing power-on processing of the sub-control circuit in the gaming machine of one embodiment of the present invention; FIG. 4 is a flow chart showing main board communication tasks performed by a sub CPU in one embodiment of the present invention; FIG. It is a flow chart which shows the production|presentation registration task performed by sub CPU in one Embodiment of this invention. It is a flowchart which shows the content determination processing of production|presentation in one Embodiment of this invention. 7 is a flow chart showing an example of processing when a no-operation command is received according to an embodiment of the present invention; 4 is a flow chart showing date and time update processing in one embodiment of the present invention. 4 is a flow chart showing a sound control task performed by a sub CPU in one embodiment of the present invention; 4 is a flow chart showing sound function RAM transfer processing in one embodiment of the present invention. FIG. 4 is a schematic diagram showing, in source code, a specific example of a sound control task and sound function RAM transfer processing in one embodiment of the present invention; 4 is a flow chart showing a lamp control task performed by a sub CPU in one embodiment of the present invention; 4 is a flowchart showing lamp data reading processing in one embodiment of the present invention. 4 is a flow chart showing ramp function RAM transfer processing in one embodiment of the present invention. FIG. 4 is a schematic diagram showing, in source code, specific examples of a ramp control task, ramp data read processing, and ramp function RAM transfer processing in one embodiment of the present invention; FIG. 4 is a conceptual diagram for explaining a method of manufacturing a program to be executed by a sub CPU in one embodiment of the present invention;

A pachislot, which is a game machine representing an embodiment of the present invention, will be described below with reference to FIGS. 1 to 34. FIG.
In the present embodiment, a pachislot machine having a function of activating a replay time (hereinafter referred to as "RT"), which is a game state in which the probability of winning a replay becomes higher than in normal times when a specific combination of symbols is displayed, is described. explain.

<Function flow>
First, referring to FIG. 1, the functional flow of pachislot will be described.
In the pachislot machine of this embodiment, medals are used as game media for playing games. As game media, coins, game balls, game point data or tokens, etc. can be applied in addition to medals.

When the player inserts medals and operates the start lever, one value (hereinafter referred to as random number) is extracted from random numbers within a predetermined numerical range (eg, 0 to 65535).

The internal lottery means performs a lottery based on the extracted random number value to determine an internal winning combination. This internal lottery means is handled by a main control circuit, which will be described later. A combination of symbols permitted to be displayed along a prize determination line, which will be described later, is determined by determining the internal winning combination. As for the types of symbol combinations, there are two types of symbol combinations: those related to "win", in which the player is given benefits such as payout of medals, activation of replay, activation of bonus, etc., and other so-called "losing". is provided.

Further, when the start lever is operated, the plurality of reels are rotated. Thereafter, when the player presses a stop button corresponding to a predetermined reel, the reel stop control means controls to stop the rotation of the reel based on the internal winning combination and the timing at which the stop button is pressed. conduct. This reel stop control means is provided by a main control circuit, which will be described later.

In pachislot, basically, control is performed to stop the rotation of the relevant reel within a specified time (190 msec or 75 msec) from when the stop button is pressed. In this embodiment, the number of symbols that move with the rotation of the reels within the specified time is called "the number of sliding symbols". When the specified period is 190 msec, the maximum number of sliding symbols is set at 4 symbols, and when the specified period is 75 msec, the maximum number of sliding symbols is determined at 1 symbol.

When an internal winning combination that permits display of a combination of symbols relating to a prize is determined, the reel stop control means normally displays the combination of symbols within a prescribed time of 190 msec (for 4 symbols). Stop the rotation of the reel so that it is displayed as much as possible. In addition, the reel stop control means, for example, during the operation of the challenge bonus (CB), which is the second type special bonus, and the middle bonus (MB) that continuously activates the CB, the specified The rotation of the reels is stopped so that the combination of symbols is displayed as much as possible along the winning determination line within 75 msec (one symbol frame). Further, the reel stop control means utilizes various specified times corresponding to the game state to rotate the reels so that a combination of symbols whose display is not permitted by the internal winning combination is not displayed along the winning determination line. stop.

When all of the plurality of reels stop rotating in this way, the winning determination means determines whether or not the combination of symbols displayed along the winning determination line is related to winning. A main control circuit, which will be described later, serves as the winning determination means. When the winning determining means determines that the game is related to winning, the player is given a privilege such as payout of medals. In pachislot, a series of the above-described sequences are performed as one game.

In addition, in the pachislot machine, in the above-mentioned series of flows, various productions are performed by using the display of images by a display device, the output of light by various lamps, the output of sound by a speaker, or a combination of these. will be

When the start lever is operated, a random number for effect (hereinafter referred to as a random number for effect) is extracted in addition to the random number used for determining the internal winning combination described above. When the random number for effect is extracted, the effect content determining means determines by lottery the effect content to be executed this time out of the plurality of types of effect contents associated with the internal winning combination. A sub-control circuit, which will be described later, serves as this effect content determining means.

When the content of the performance is determined, the performance execution means executes the corresponding performance in conjunction with each opportunity such as when the reels start rotating, when each reel stops rotating, and when it is determined whether or not a prize is awarded. In this way, in pachislot, the player is provided with an opportunity to know or predict the determined internal winning combination (in other words, the combination of symbols to aim for) by executing the performance contents associated with the internal winning combination. It is provided, and it is possible to improve the interest of the player.

<Structure of Pachislot>
Next, the structure of the pachislot according to the present embodiment will be described with reference to FIGS. 2 to 4. FIG.

[Appearance structure]
FIG. 2 is a perspective view showing the external structure of the pachislot machine 1. As shown in FIG. FIG. 3 is a front view of the pachislot machine 1 according to the present embodiment with the front panel 10 removed.

As shown in FIG. 2, the pachislot machine 1 has an exterior body 2. As shown in FIG. The exterior body 2 has a cabinet 2a for housing reels, circuit boards, etc., and a front door 2b attached to the cabinet 2a so as to be openable and closable.
Handles 7 are provided on both sides of the cabinet 2a (only the handle 7 on one side is shown in FIG. 2). The handle 7 is a concave portion that is used to hold the pachislot slot machine 1 when carrying it.

Inside the cabinet 2a, three reels 3L, 3C and 3R are arranged side by side. The reels 3L, 3C, and 3R are hereinafter referred to as the left reel 3L, middle reel 3C, and right reel 3R, respectively. Each of the reels 3L, 3C, and 3R includes a reel body formed in a cylindrical shape, a translucent sheet material attached to the peripheral surface of the reel body, and a reel for irradiating the sheet material with light from the inside of the reel body. and a light source. A plurality of (for example, 21) patterns are drawn on the surface of the sheet material at predetermined intervals along the circumferential direction. Here, a part of the red 7 patterns (not shown) is a translucent part. In addition, the reel body is provided with a reel backlight that illuminates the back surface of the sheet material. This reel backlight is turned on and off under the control of a sub-control circuit 42, which will be described later.

The front door 2 b includes a door body 9 , a front panel 10 and a light-emitting display device 11 .
The door body 9 is attached to the cabinet 2a using a hinge (not shown) so that it can be opened and closed. The hinge is provided at the left end of the door body 9 when the door body 9 is viewed from the front of the pachislot machine 1 .

As shown in FIG. 2 , the light-emitting display device 11 is provided on the upper portion of the door body 9 . The light-emitting display device 11 is composed of a dot matrix portion 119 (see FIG. 3) formed by a plurality of light source portions arranged in a matrix and a portion of the front panel 10 facing the dot matrix portion 119 .

The dot matrix unit 119 lights (blinks) a light source unit at an arbitrary location to illuminate an arbitrary location (firework pattern in this embodiment) of the design applied to the front panel 10 from the back. As a result, an effect is performed in which an arbitrary portion of the design applied to the front panel 10 is made to emit light.

Display windows 4L, 4C, and 4R for displaying patterns drawn on the three reels 3L, 3C, and 3R are provided below the light-emitting display device 11 . The display windows 4L, 4C, and 4R are hereinafter referred to as a left display window 4L, a middle display window 4C, and a right display window 4R, respectively.

The display windows 4L, 4C, 4R are made of a transparent member such as an acrylic plate. The display windows 4L, 4C, and 4R are provided at positions overlapping the arrangement areas of the three reels when viewed from the front (player's side), and positioned in front of the three reels (player's side). provided in Therefore, the player can visually recognize the three reels provided behind the display windows 4L, 4C and 4R through the display windows 4L, 4C and 4R.

In the present embodiment, the display windows 4L, 4C, and 4R display three consecutively arranged symbols out of a plurality of types of symbols drawn on each reel when the rotation of the corresponding reels provided behind them stops. It is set to a size that can display one pattern. That is, within the frames of the display windows 4L, 4C and 4R, upper, middle and lower areas are provided for each reel, and one symbol is displayed in each area.

The front panel 10 is attached to the top of the door body 9 . The front panel 10 has an upper display section 101 , a reel illumination section 102 , reel side effect display sections 103 A and 103 B, edge effect display sections 104 A and 104 B, and a reel lower display section 105 .

The upper display section 101 is arranged above the light-emitting display device 11 , and the reel illumination section 102 is arranged between the reels 3L, 3C, 3R and the light-emitting display device 11 . The reel side effect display portions 103A and 103B are arranged on the sides of the reels 3L, 3C and 3R, and the edge effect display portions 104A and 104B are arranged on the side of the reel side effect display portion 103. The reel bottom display section 105 is arranged below the reels 3L, 3C, and 3R.

The upper display unit 101, the reel illumination unit 102, the reel side effect display units 103A and 103B, the edge effect display units 104A and 104B, and the reel lower display unit 105 are provided with various lamp groups 111 to 117 provided on the door body 9 and described later. covering. These upper display portions 101, 102, 103A, 103B, 104A, 104B, and 105 are irradiated with light from various lamp groups 111 to 117 and emit light.

For example, the reel side effect display section 103A is provided with three BET light emitting sections aligned in the vertical direction. The number of lit-up three BET light emitting parts indicates the number of medals used for one game.

In this embodiment, the number of medals used in one game is set to 1-3. For example, when the number of medals used in one game is set to "1", one BET light emitting portion (for example, the lowest BET light emitting portion) lights up, and the other BET light emitting portions (middle and one in line) light up. The BET light emitting part located at the top) goes out.

As shown in FIG. 2, a pedestal portion 12 is formed in the center of the door body 9 . The pedestal 12 is provided with various devices (a medal slot 13, a MAX bet button 14, a 1 bet button 15, a start lever 16, and stop buttons 17L, 17C, 17R) to be operated by the player.

A medal slot 13 is provided for receiving medals dropped into the pachislot machine 1 from the outside by a player. The medals accepted from the medal slot 13 are used for one game with a preset number (for example, 3) as the upper limit, and the amount exceeding the preset number is deposited inside the pachi-slot machine 1.例文帳に追加(so-called credit function).

A MAX bet button 14 and a 1 bet button 15 are provided to determine the number of medals deposited inside the pachi-slot machine 1 to be used for one game. Although not shown in FIG. 2, the pedestal portion 12 is provided with a checkout button. This checkout button is provided for withdrawing (discharging) medals deposited inside the pachi-slot machine 1 to the outside.

A start lever 16 is provided to start rotation of all the reels (3L, 3C, 3R). The stop buttons 17L, 17C and 17R are provided corresponding to the left reel 3L, the middle reel 3C and the right reel 3R, respectively, and each stop button is provided to stop the rotation of the corresponding reel. The stop buttons 17L, 17C, and 17R are hereinafter referred to as the left stop button 17L, middle stop button 17C, and right stop button 17R, respectively.

A 7-segment display 6 made up of a 7-segment LED (Light Emitting Diode) is provided on the base portion 12 . This 7-segment display 6 displays the number of medals to be paid out to the player as a privilege (hereinafter referred to as the number of payouts), the number of medals deposited inside the pachislot machine 1 (hereinafter referred to as the number of credits), and the number of medals for playing the game. Information such as the number of inserted medals (hereinafter referred to as the number of bets) is digitally displayed.

A medal payout port 18, a medal tray 19, speakers 20L and 20R, and the like are provided at the lower portion of the door body 9. As shown in FIG. The medal payout port 18 guides to the outside the medals discharged by driving the medal payout device 33, which will be described later. A medal receiving tray 19 stores medals ejected from the medal pay-out port 18.例文帳に追加Also, the speakers 20L and 20R output sounds such as sound effects and music corresponding to the content of the presentation.

Further, the door body 9 is provided with a waist panel display portion 106 . The waist panel display section 106 is arranged above the speakers 20L and 20R. The waist panel display portion 106 covers a light source portion (port No. 53) provided on the door body 9 and described later. Then, the waist panel display section 106 emits light when irradiated with light from the light source section (port No. 53).

[Various lamp groups]
FIG. 4 is an LED layout port diagram for pachislot 1. As shown in FIG.

As shown in FIG. 4, the door body 9 is provided with a 337-port light source. At least one LED is arranged in each light source unit as a light emitter. In addition, you may arrange|position other light-emitting bodies, such as an organic electroluminescence, in each light source part.

The light source units associated with ports No. 0 to No. 30 form a first lamp group 111 . The first lamp group 111 irradiates the upper display section 101 (see FIG. 3) with light. The light source units associated with ports No. 49 to No. 52 form a second lamp group 112 . The second lamp group 112 illuminates the reel illumination section 102 (see FIG. 3).

The light source units associated with the No. 66 to No. 70 ports form the third lamp group 113 , and the light source units associated with the No. 71 to No. 75 ports form the fourth lamp group 114 . The third lamp group 113 emits light to the reel side effect display portion 103A (see FIG. 3), and the fourth lamp group 114 emits light to the reel side effect display portion 103B (see FIG. 3). The light source units associated with the No. 68 to No. 70 ports of the third lamp group 113 face the three BET light emitting units described above, and light up to cause the facing BET light emitting units to emit light.

The light source units associated with ports No. 54 to No. 59 form a fifth lamp group 115 , and the light source units associated with ports No. 60 to No. 65 form a sixth lamp group 116 . The fifth lamp group 115 emits light to the edge effect display portion 104A (see FIG. 3), and the sixth lamp group 116 emits light to the edge effect display portion 104B (see FIG. 3).

The light source units associated with ports No. 108 to No. 156 form a seventh lamp group 117 . The seventh lamp group 117 irradiates the reel lower display portion 105 (see FIG. 3) with light. The light source units associated with the No. 108 to No. 121 ports of the seventh lamp group 117 display the number of stored medals, which is the number of medals deposited inside the pachislot machine 1, for example.

The light source units associated with ports No. 122 to No. 142 of the seventh lamp group 117 display, for example, the number of medals won during the bonus. The light source units associated with ports No. 143 to No. 156 of the seventh lamp group 117 display, for example, the number of medals to be paid out.

The light source units associated with ports No. 31 to No. 48 and No. 76 to No. 93 form an eighth lamp group 118 . The light source units associated with ports No. 31 to No. 36 of the eighth lamp group 118 function as a reel light source (reel backlight) for the left reel 3L. In addition, the light source units associated with ports No. 37 to No. 42 function as reel light sources (reel backlights) for the middle reel 3C, and the light source units associated with ports No. 43 to No. 48 function as light sources for the reels of the middle reel 3C. It functions as a 3R reel light source (reel backlight).

The light source unit associated with the No. 53 port illuminates the waist panel display unit 106 (see FIG. 3). The light source unit associated with the No. 157 port irradiates the MAXBET button 14 with light. Light is applied to the left stop button 17L. The light source unit associated with the No. 158 port illuminates the left stop button 17L. The light source unit associated with the No. 159 port illuminates the middle stop button 17C. The light source unit associated with the No. 160 port illuminates the right stop button 17R.

The light source sections associated with ports No. 161 to No. 337 form a dot matrix section 119 . The dot matrix portion 119 functions as a light source of the light emitting display device 11. FIG. Each port of the dot matrix section 119 is provided with one LED.

[Internal structure]
Next, the internal structure of pachislot 1 will be described with reference to FIG. FIG. 5 is a perspective view showing the internal structure of the pachislot machine 1. As shown in FIG.

The cabinet 2a is formed in a substantially rectangular parallelepiped shape with one open surface on the front side. A main substrate 31 constituting a main control circuit 41 (see FIG. 6), which will be described later, is provided in the upper part of the cabinet 2a. The main control circuit 41 is a circuit that controls the main operations of the game in the pachislot 1, such as determining internal winning combinations, spinning and stopping each reel, and determining whether or not a prize has been won, and the flow between the operations. A specific configuration of the main control circuit 41 will be described later.

Three reels (a left reel 3L, a middle reel 3C and a right reel 3R) are provided in the central portion within the cabinet 2a. Although not shown in FIG. 5, each reel is connected to a corresponding stepping motor (one of stepping motors 61L, 61C, and 61R in FIG. 6) through a gear having a predetermined reduction ratio. .

A medal payout device 33 (hereinafter referred to as a hopper 33) having a structure capable of accommodating a large amount of medals and discharging them one by one is provided in the lower part of the cabinet 2a. A power supply device 34 is provided on one side (the left side in the example shown in FIG. 5) of the hopper 33 in the cabinet 2a to supply necessary power to each device of the pachi-slot machine 1. As shown in FIG.

A sub-board 32 that constitutes a sub-control circuit 42 (see FIGS. 6 and 7), which will be described later, is provided on the upper portion of the back side of the front door 2b (the portion on the side opposite to the display screen side). The sub-control circuit 42 is a circuit that controls execution of effects such as video display. A specific configuration of the sub-control circuit 42 will be described later.

Further, a selector 35 is provided at a substantially central portion on the back side of the front door 2b. The selector 35 is a device for selecting whether or not the material, shape, etc. of medals inserted from the outside through the medal slot 13 (see FIG. 2) are appropriate. guide to. Although not shown in FIG. 5, a medal sensor 35S (see FIG. 6) is provided on the path through which the medals pass in the selector 35 to detect that a proper medal has passed.

<Structure of circuit provided by pachislot>
Next, the circuit configuration of the pachi-slot machine 1 will be described with reference to FIGS. 6 and 7. FIG.
FIG. 6 is a block diagram of the entire circuit provided in the pachi-slot machine 1. As shown in FIG. FIG. 7 is a block configuration diagram showing the internal configuration of the sub-control circuit.

The pachi-slot machine 1 includes a main control circuit 41, a sub-control circuit 42, and peripheral devices (actuators) electrically connected to these circuits.

[Main control circuit]
The main control circuit 41 is mainly composed of a microcomputer 50 installed on the circuit board (main board 31). Other components of the main control circuit 41 include a clock pulse generation circuit 54, a frequency divider 55, a random number generator 56, a sampling circuit 57, a display drive circuit 64, a hopper drive circuit 65, and a payout completion signal circuit. 66 included.

The microcomputer 50 includes a main CPU 51 , a main ROM (Read Only Memory) 52 and a main RAM (Random Access Memory) 53 .

The main ROM 52 stores control programs for various processes executed by the main CPU 51, data tables such as an internal lottery table, data for transmitting various control instructions (commands) to the sub-control circuit 42, and the like. . The main RAM 53 is provided with a storage area for storing various data such as an internal winning combination determined by executing the control program.

A clock pulse generation circuit 54 , a frequency divider 55 , a random number generator 56 and a sampling circuit 57 are connected to the main CPU 51 . A clock pulse generating circuit 54 and a frequency divider 55 generate clock pulses. The main CPU 51 executes the control program based on the generated clock pulse. Also, the random number generator 56 generates a random number within a predetermined range (0 to 65535, for example). The sampling circuit 57 then extracts one value from the generated random numbers.

Various switches and sensors are connected to the input port of the microcomputer 50 . The main CPU 51 receives input signals from various switches and the like, and controls operations of peripheral devices such as stepping motors 61L, 61C, and 61R.

The stop switch 17S represents a specific example of stop operation detection means according to the present invention, and indicates that each of the left stop button 17L, middle stop button 17C, and right stop button 17R has been pressed by the player (stop operation). ). The start switch 16S represents a specific example of start operation detection means according to the present invention, and detects that the start lever 16 has been operated by the player (start operation). The settlement switch 14S detects that the settlement button has been pressed by the player.

The medal sensor 35</b>S represents a specific example of the insertion operation detection means according to the present invention, and detects that the medal inserted into the medal insertion slot 13 has passed through the selector 35 . Also, the bet switch 12S detects that the bet button (MAX bet button 14 or 1 bet button 15) has been pressed by the player.

Peripheral devices whose operations are controlled by the microcomputer 50 include three stepping motors 61L, 61C, 61R, a 7-segment display 6, and a hopper 33. A drive circuit for controlling the operation of each peripheral device is connected to the output port of the microcomputer 50 .

A motor drive circuit 62 controls driving of three stepping motors 61L, 61C and 61R provided corresponding to the left reel 3L, middle reel 3C and right reel 3R, respectively. The reel position detection circuit 63 detects a reel index indicating that the reel has made one rotation for each reel by means of an optical sensor having a sensor light-emitting portion and a sensor light-receiving portion.

Each of the three stepping motors 61L, 61C, and 61R has a momentum proportional to the number of pulse outputs, and has a configuration capable of stopping the rotating shaft at a specified angle. Also, the driving force of each stepping motor is transmitted to the corresponding reel via a gear having a predetermined reduction ratio. Each time one pulse is output to each stepping motor, the corresponding reel rotates at a constant angle. The three reels 3L, 3C, 3R and the three stepping motors 61L, 61C, 61R represent one specific example of the variable display means according to the present invention.

After detecting the reel index of each reel, the main CPU 51 counts the number of times a pulse is output to the corresponding stepping motor to determine the rotation angle of each reel (specifically, how many symbols the reel has). only rotated).

Here, management of the rotation angle of each reel will be specifically described. The number of pulses output to each stepping motor is counted by a pulse counter (not shown) provided in the main RAM 53 . Then, each time the pulse counter counts the pulse output a predetermined number of times (for example, 16 times) required for one symbol rotation, the value of the symbol counter (not shown) provided in the main RAM 53 is changed to "1". ” is added. A symbol counter is provided for each reel. The symbol counter value is cleared when the reel position detection circuit 63 detects the reel index.

That is, in this embodiment, by managing the value of the symbol counter, it is managed how many symbols have been rotated since the reel index was detected. Therefore, the position of each symbol on each reel is detected with reference to the position where the reel index is detected.

Note that the display drive circuit 64 controls the operation of the 7-segment display 6 . A hopper drive circuit 65 controls the operation of the hopper 33 . The payout completion signal circuit 66 manages medal detection performed by the medal detector 33S provided in the hopper 33, and checks whether or not the number of medals discharged outside from the hopper 33 has reached a predetermined payout number. Also, the main control circuit 41 is connected to an external terminal board 18S. The main control circuit 41 is connected to the hall computer or calling device 100 via the external terminal board 18S.

[Sub control circuit]
As shown in FIG. 7 , the sub-control circuit 42 is electrically connected to the main control circuit 41 and performs processing such as determination and execution of effects based on commands transmitted from the main control circuit 41 . The sub-control circuit 42 includes a sub-CPU 81 , sub-ROM 82 , sub-RAM 83 (calculation storage means), oscillation circuit 84 , backup RAM 85 , RTC (Real-Time Clock) 86 , battery 87 and sound IC 88 .

The sub CPU 81 controls the output of sound and light in accordance with the control program stored in the sub ROM 82 in response to commands transmitted from the main control circuit 41 . The sub CPU 81 constitutes a control section and arithmetic processing means.

The sub-ROM 82 represents a specific example of storage means according to the gaming machine of the present invention, and basically has a program storage area and a data storage area. Thus, the sub ROM 82 constitutes first storage means in which programs and data for operating the sub CPU 81 are stored.

Various control programs executed by the sub CPU 81 are stored in the program storage area. Note that the control program stored in the program storage area includes, for example, a main board communication task for controlling communication with the main control circuit 41, a random number value for effect extraction, determination of effect contents (effect data), and An effect registration task for performing registration, a lamp control task for controlling the output of light from the dot matrix unit 119 of the light-emitting display device 11 and various lamp groups based on the determined content of the effect, and sound output from the speakers 20L and 20R. programs such as a sound control task for controlling the

The data storage area includes, for example, a storage area for storing various data tables, a storage area for storing effect data that constitutes various effect contents, a storage area for storing sound data related to BGM and sound effects, and a light on/off pattern. Various storage areas are included, such as a storage area for storing lamp data related to. The lamp data will be described later with reference to FIGS. 14 to 18. FIG.

The sub-RAM 83 has a higher access speed than the sub-ROM 82 and constitutes a rewritable second storage means, and is composed of, for example, a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory). .

The sub-RAM 83 has a storage area for registering the determined effect content and effect data, and an effect state storage area for storing various data such as game states and internal winning combinations transmitted from the main control circuit 41 . The oscillation circuit 84 constitutes clock generation means for generating (oscillating) a clock of a predetermined frequency, for example, 22 MHz, for operating the sub CPU 81 .

The backup RAM 85 is composed of FRAM (Ferroelectric Random Access Memory) (registered trademark), which is a rewritable nonvolatile memory that does not require a power source, for example. The backup RAM 85 may be configured by connecting the battery 87 that supplies power to the RTC 86 to the SRAM as well.

The backup RAM 85 has a date and time storage area for storing the date and time measured by the RTC 86, a game information area for storing information on the game state of the sub-control circuit 42 and information on performance, and a storage area for storing error information history. , and a storage area for storing various settings of the pachi-slot 1 set in the hall menu.

In addition, the game information area of the backup RAM 85 can be stored in the sub-RAM 83 at an arbitrary timing (for example, when the power supply to the sub-control circuit 42 is interrupted (when a power failure occurs), when a start command is received, etc.). The state storage area is copied to the game information area of the backup RAM 85, and is copied to the effect state storage area of the sub-RAM 83 immediately after the power-on process (see FIG. 19). By copying the game information area of the backup RAM 85 to the effect state storage area of the sub-RAM 83, the pachi-slot machine 1 can restart the game effect executed before the power is turned on.

The RTC 86 operates with power supplied from a power supply board (not shown) like the electronic components mounted on the sub-control circuit 42 when the pachi-slot machine 1 is powered on. For example, it operates by the power supplied from the battery 87 and constitutes a clock means for clocking the date and time.

The RTC 86 is connected to the sub CPU 81 by an I2C (Inter-Integrated Circuit), and transmits to the sub CPU 81 date and time data representing the date and time measured in response to a request from the sub CPU 81 . The battery 87 is composed of a primary battery such as a coin-shaped lithium battery, or a lithium ion secondary battery.

Speakers 20L and 20R are connected to the sound IC 88 . The sound IC 88 outputs audio signals such as BGM from the speakers 20L and 20R according to the sound data transmitted from the sub CPU 81 .

The sub control circuit 42 includes driver ICs 128a to 128c for driving the eighth lamp group 118, driver ICs 121a to 121b for driving the first lamp group 111, and driver IC 127a for driving the seventh lamp group 117. 127 d and driver ICs 129 a to 129 g for driving the dot matrix section 119 .

These driver ICs and the sub CPU 81 are connected by serial bus communication. The sub CPU 81 incorporates two communication circuits (not shown) for serial bus communication. Channel 0 is connected to driver ICs 128a to 128c, driver ICs 121a to 121b, and driver ICs 127a to 127d. 129g is connected.

In this embodiment, the first lamp group 111, the seventh lamp group 117, the eighth lamp group 118, and the dot matrix section 119 constitute a light emitting section. Driver ICs 128a to 128c, driver ICs 121a to 121b, driver ICs 127a to 127d, and driver ICs 129a to 129g (hereinafter also simply referred to as "driver ICs") constitute light emission driving means.

In this embodiment, each driver IC has 24 output terminals. Therefore, each driver IC can drive 24 LEDs from channel 0 to channel 23 .

Each driver IC has an output setting terminal. Each driver IC sets the output of the output terminal to either constant current output or sink output according to the state (High/Low) of the output setting terminal. Therefore, the output terminal of each driver IC can be set to either constant current output or sink output according to the connection state of the LED.

Each driver IC incorporates a 6-bit register corresponding to each channel, and outputs a drive signal having a duty ratio corresponding to the value set in the register to each channel at a cycle of 63 μs.

For example, when the register value is 63, the driver IC outputs a drive signal with a duty ratio of 100% (that is, a pulse width of 63 μs) to the corresponding channel, and the LED of the corresponding channel emits light with the highest luminance.

On the other hand, when the register value is 0, the driver IC outputs a drive signal with a duty ratio of 0% (that is, a pulse width of 0) to the corresponding channel, and the LED of the corresponding channel is turned off.

In this embodiment, the sub CPU 81 and each driver IC communicate with each other by a serial bus communication method. In the serial bus communication, each driver IC is connected to each lamp group 111, 117, 118 and dot by synchronous serial communication using two lines of a data line and a clock line or three lines of a data line, a clock line and a select line. Control data for controlling the light emission mode of the LEDs of the matrix section 119 is transmitted.

The sub CPU 81 has a plurality of output ports for outputting control data, and can transmit control data from each output port to a plurality of driver ICs. In this embodiment, the sub CPU 81 has a first port and a second port for outputting control data. Driver ICs 128a to 128c, driver ICs 121a to 121b, and driver ICs 127a to 127d are connected to the first port. Driver ICs 129a to 129g are connected to the second port.

Each driver IC has a plurality of address terminals, and a unique address is assigned within the output port of the sub CPU 81 according to the level (High/Low) of each address terminal.

As will be described with reference to FIGS. 8 to 10, the control data transmitted from each output port of the sub CPU 81 includes a first mode for setting the brightness of the LEDs of all channels to each driver IC, and There are three modes: a second mode that sets the brightness of the LEDs on the channel, and a third mode that includes a command to turn off the LEDs on all channels.

8 to 10, the first line represents the bit order in the control data, the second line represents the type of each parameter included in the control data, and the third line represents error detection data to be described later. represents E.

The error detection data E is inserted at a predetermined position of the control data regardless of the position of each parameter in the control data. Therefore, in FIGS. 8 to 10, the type of each parameter included in the control data and the error detection data E are shown in two lines. That is, in FIGS. 8 to 10, each bit indicated by "E" in the third line corresponds to the error detection data E, and each bit not indicated by "E" in the third line is It corresponds to the parameter shown in the second line.

8 to 10, the fourth line represents control data actually transmitted from each output port of the sub CPU 81. In FIGS. In addition, in the control data shown in the fourth line, "*" represents a value ("0" or "1") set according to the control data.

(first mode)
As shown in FIG. 8, the control data in the first mode includes, as a header, head detection bit HD, device identifier DEV, address ADR, mode MD, and error detection data E ( For example, a fixed value "0").

Specifically, the header of the control data in the first mode consists of 22 bits. The head detection bit HD is assigned to 9 bits from the 1st bit to the 9th bit. The head detection bit HD is a fixed value as shown.

The device identifier DEV is assigned to four bits from the 11th bit to the 14th bit. The device identifier DEV represents the type of each driver IC. Therefore, driver ICs of the same type have the same value.

The address ADR is assigned to 5 bits from the 15th bit to the 18th bit and the 20th bit. Address ADR represents an address for identifying the driver IC. That is, the address ADR represents the address set to the address terminal of the driver IC to which the control data is to be transmitted.

Specifically, each of the driver ICs 128a to 128c has five terminals (not shown) for setting addresses. An address is set to identify the

Mode MD is assigned to 1 bit of the 21st bit. Mode MD indicates whether the control data is in the first mode or the second mode. In this embodiment, the mode MD is set to "0" in the case of the first mode, and is set to "1" in the case of the second mode.

The error detection data E is assigned to each of the 10th, 19th and 22nd bits. In this embodiment, the error detection data E is a fixed value, for example, "0". In addition to the fixed value, the error detection data E may be a value based on a predetermined rule (for example, a cyclic value of a predetermined cycle) or may be a parity bit.

The control data in the first mode includes, as a payload, luminance data L for channels 0 to 23 (in the figure, the subscript of L indicates the channel number), error detection data E, and an end bit END. include.

Each of the luminance data L0 to L23 of channel 0 to channel 23 is assigned in units of 6 bits from the head of the payload. The error detection data E is the same as the error detection data E of the header, and is inserted at a 9-bit cycle from the 9th bit of the payload. An end bit END represents the last bit of the control data. In this embodiment, the end bit END is a fixed value, for example, "0".

As described above, the payload of the control data in the first mode is not affected by the data pattern of the luminance data L by not synchronizing the period of the error detection data E with the period of the luminance data L. It is defined so that anomalies can be detected on the receiving side of the control data.

The driver IC that has received the control data in the first mode corresponds to channel 0 to channel 23 if the assigned address is equal to the address ADR of the control data, and if the device identifier registered in advance is equal to the device identifier DEV. The register values are updated to luminance data L0 to L23.

(second mode)
As shown in FIG. 9, the header of the control data in the second mode is the same as the header of the control data in the first mode, so description thereof will be omitted.

The control data in the second mode includes, as a payload, the number of channels CHN, the channel number CH (the suffix of CH in the figure is sequentially assigned from a), and the luminance data L (the suffix of L in the figure are sequentially attached from a), error detection data E, and an end bit END.

The number of channels CHN is assigned to 5 bits from the beginning of the payload. The number of channels CHN represents the number of channels to be updated. That is, the number of channels CHN represents the number of pairs of channel number CH and luminance data L that follow.

The channel number CH is represented by 5 bits and represents any channel number from channel 0 to channel 23 . Each luminance data La to Lg is represented by 6 bits following the channel number CH.

The error detection data E is the same as the error detection data E in the first mode control data, and is inserted from the 9th bit of the payload at a 9-bit cycle. The end bit END is the same as the end bit END in the first mode control data.

As described above, the payload of the control data in the second mode is not affected by the data pattern of the luminance data L by not synchronizing the period of the error detection data E with the period of the luminance data L. It is defined so that anomalies can be detected on the receiving side of the control data.

If the assigned address is equal to the address ADR of the control data and the device identifier DEV is equal to the device identifier registered in advance, the driver IC receives the control data of the second mode. is updated to each luminance data L.

(Third mode)
As shown in FIG. 10, the control data in the third mode includes head detection bit HD, reset command RST, error detection data E, and end bit END.

The head detection bit HD is the same as the head detection bit HD in the header of the control data in the first mode, and is assigned to 9 bits from the 1st bit to the 9th bit. The reset command RST is assigned to 8 bits from the 11th bit to the 18th bit. In this embodiment, the reset command RST is a fixed value as shown.

The error detection data E is the same as the head detection bit HD in the header of the control data in the first mode, and is assigned to the 1st bit of the 10th bit. The end bit END is the same as the end bit END in the first mode control data. The driver IC that receives the control data of the third mode updates the values of the registers corresponding to all channels to zero.

In this way, when the channels are individually controlled, the data length of the control data can be shortened compared to the first mode by transmitting the control data in the second mode. On the other hand, when controlling the channel as a whole, the data length of the control data can be shortened compared to the second mode by transmitting the control data in the first mode which does not require the channel number.

Also, when the LEDs of all channels are to be turned off, by transmitting the control data in the third mode, the data length of the control data can be shortened compared to the first and second modes.

As described above, the transmission load between the sub CPU 81 and the driver IC can be reduced by selecting a mode in which the data length of the control data is shortened according to the application of the light emitter driven by the driver IC. , the responsiveness of the LED can be improved.

In this embodiment, the LEDs forming the dot matrix section 119 form the first light emitter group, and the LEDs forming the first lamp group 111, the seventh lamp group 117, and the eighth lamp group 118 form the second light emitter group. It constitutes a group of light emitters.

The sub CPU 81 transmits control data from the second port to the driver IC that drives the LEDs of the first light emitter group in the second mode. The sub CPU 81 transmits control data from the first port to the driver IC that drives the LEDs of the second light emitter group in the first mode. The sub CPU 81 transmits the control data in the third mode from the corresponding port when all the LEDs are turned off, such as when the power is turned on or when the effect is switched.

In addition, the second lamp group 112, the third lamp group 113, the fourth lamp group 114, the fifth lamp group 115, the sixth lamp group 116, and other light source units related to the ports according to the present embodiment are respectively unnecessary. It is controlled by the sub CPU 81 via the illustrated driver IC.

<Structure of Data Table Stored in Main ROM>
Next, configurations of various data tables stored in the main ROM 52 will be described.

[Pattern arrangement table]
First, the symbol layout table will be described with reference to FIG. The symbol layout table defines the correspondence relationship between the position of each symbol in the rotational direction of each of the left reel 3L, the middle reel 3C and the right reel 3R and the data specifying the type of symbol placed at each position.

In the symbol arrangement table, when the reel index is detected, the position of the symbol of each reel arranged in the middle area within the frames of the display windows 4L, 4C, 4R is defined as "0". Then, on each reel, "0" to "20" corresponding to the symbol counter are assigned to each symbol as symbol positions in the order of progression in the reel rotation direction (downward direction in FIG. 11) with symbol position "0" as a reference. assigned.

That is, by referring to the value of the symbol counter (“0” to “20”) and the symbol layout table, the symbols are displayed in the upper, middle and lower areas of each reel within the frames of the display windows 4L, 4C and 4R. It is possible to specify the type of pattern that is being used. For example, when the value of the symbol counter corresponding to the left reel 3L is "7", the upper, middle and lower areas of the left reel 3L within the frame of the display window 4 each have " Symbols corresponding to "Don 1", "Bell 2" at symbol position "7", and "Replay" at symbol position "6" are displayed.

<Data table stored in sub ROM>
[Monthly day table]
As shown in FIG. 12, in the monthly day table, the number of days in a leap year and the number of days in a non-leap year are associated with each month. The month-by-month table is referred to by the sub CPU 81 that executes date and time update processing (see FIG. 26), which will be described later. Thus, the sub-ROM 82 for storing the day-of-month table constitutes a day-of-month table storage means.

<Storage Area Assigned to Sub-RAM>
[Date and time storage area]
As shown in FIG. 13, the date and time storage area is sub-RAM 83, each area for storing "year", "month", "date", "day of the week", "hour", "minute" and "second". assigned to. That is, the date and time data is stored in the date and time storage area.

In the following explanation, the values of the fields that make up the date/time storage area are represented as date/time storage area (year), date/time storage area (month), date/time storage area (day), date/time storage area (day of the week), and date/time storage area (hour). , date and time storage area (minutes), and date and time storage area (seconds). The date/time storage area is used by the sub CPU 81 that executes date/time update processing (see FIG. 26), which will be described later.

<Lamp data>
In this embodiment, the sub-ROM 82 stores lamp data (also referred to as “light emission data”), which is effect data relating to the pattern of extinguishing (increase or decrease) of light spots, and a plurality of parts data. Thus, the sub-ROM 82 constitutes light emission data storage means and pattern data storage means.

Each part data includes identification information for identifying the part data, attribute data indicating the attribute of the part data, and pattern data indicating a pattern of extinguishing (including increase/decrease) of light points. Each lamp data represents the order of the identification information of the parts data.

The pattern data consists of a plurality of luminance patterns ordered in reproduction order. Each luminance pattern represents the luminance to be set for each channel of each driver IC to be controlled. In each luminance pattern, the luminance set in the channel of the driver IC is represented by 8 bits in consideration of the versatility of the pattern data.

Note that the brightness set to the channel of the driver IC may be represented by 16 bits, 32 bits, or 64 bits, as long as the versatility of the pattern data is ensured. The last luminance pattern in the pattern data represents the end block.

Attribute data of part data includes shot, shot+chain, and loop. The part data whose attribute data is shot is reproduced only once in the lamp data of 1.

Shot+Chain represents continuous play. Parts data whose attribute data is shot+chain are continuously reproduced in ramp data of 1. Therefore, in one ramp data, if the parts data whose attribute data is shot+chain are continuous, the series of parts data whose attribute data is shot+chain is repeatedly reproduced.

That is, after the parts data corresponding to the last identification information in the lamp data is reproduced, if the attribute data included in the parts data corresponding to the last identification information in the lamp data represents shot + chain, the lamp data is Part data whose attribute data indicates shot+chain is searched from the beginning of the identification information, and continuous reproduction is started from the detected part data.

A loop represents repeated playback. The part data whose attribute data is a loop is repeatedly reproduced in the lamp data of 1. That is, when the identification information of the part data whose attribute data is a loop is included in the lamp data, this part data is repeatedly reproduced.

A specific example of lamp data in this embodiment will be described. Lamp data corresponding to the effect to be executed is selected by the sub CPU 81 and read into the reproduction state management storage area of the sub RAM 83 shown in FIG.

In FIG. 14, the reproduction state management storage area stores an entry part number storage area for storing a part number for identifying the part data being reproduced, and a part number as identification information for identifying the part data. The part number storage area, the end code storage area for storing the end code representing the end of the ramp data, and the parts data of the identification information represented by the ramp data include parts data whose attribute data is shot + chain or loop. and a chain/loop setting area indicating whether or not there is. The number of parts number storage areas included in the reproduction state management storage area is equal to the number of parts data represented by the lamp data.

FIG. 15 shows a specific example of the playback state management storage area. In the example shown in FIG. 15, the entry part number storage area stores "1" (the number assigned to the intro) as the entry part number, and the part number storage area stores "1" to "8" as the part numbers. , the end code is stored in the end code storage area, and "TRUE" is stored in the chain/loop setting area.

If the part data of the identification information represented by the lamp data does not include part data whose attribute data is shot + chain or loop, "FALSE" is stored in the chain/loop setting area. . Further, when "FALSE" is stored in the chain/loop setting area, repeated reproduction of the part data is not performed without retrieving the attribute data. (One-time playback)

FIG. 16 shows an example of reproduction of lamp data based on the reproduction state management storage area shown in FIG. The part data with the part number "1" has shot set in the attribute data, and a brightness pattern representing an intro effect for 30 seconds, for example, set in the pattern data.

Each part data having a part number of "2" to "8" has shot+chain set as attribute data, and a brightness pattern representing, for example, 30 seconds of continuous performance is set as pattern data. In the illustrated example, the reproduction time of all the part data with the part numbers "1" to "8" is 30 seconds, but the length of the part data may be different from each other.

As indicated by the arrows in the figure, when lamp data reproduction is started, the part data with the part number "1" is reproduced for 30 seconds, and then the parts with the part numbers "2" to "8" are reproduced. Data is played for 30 seconds. At this time, updating the part number from "1" to "2" is managed by updating the value of the entry part number storage area of the playback state management storage area from "1" to "2". be.

When the end code is detected based on the value of the entry part number storage area, the attribute data of the part data whose part number is "8" that was played last is shot + chain, so the part at the beginning of the lamp data Parts data whose attribute data is shot+chain are searched from the parts data numbered "1".

In the illustrated example, part data with a part number of "2" is detected. Therefore, "2" is set in the entry part number storage area, and a series of part data with part numbers "2" to "8" is generated from the part data with the part number "2" as indicated by the arrow in the figure. Plays continuously. Thereafter, a series of part data with part numbers "2" to "8" are repeatedly reproduced unless the lamp data is updated.

When an error in Pachi-slot 1 is detected during reproduction of lamp data, the sub CPU 81 reproduces lamp data for error. Therefore, the reproduction of the lamp data that was being reproduced when the error was detected is interrupted. When recovering from the error, the sub CPU 81 reproduces the lamp data that was reproduced when the error was detected.

At this time, if the interrupted ramp data is reproduced from the beginning, the content of the effect may not match the game state. Therefore, the sub-ROM 82 stores lamp data for recovery from interruption corresponding to the lamp data. The lamp data for recovery from interruption is different from the normal lamp data in that the part number of the part data whose attribute data does not represent shot+chain is removed.

FIG. 17 shows a reproduction state management storage area in which lamp data for recovery from interruption is stored. In the reproduction state management storage area shown in FIG. 17, "2" is stored in the reproduction state management storage area, and the attribute data for the lamp data stored in the reproduction state management storage area shown in FIG. "1" (the number to which the intro is assigned), which is the part number of the part data that does not represent the , is removed.

Therefore, as shown in FIG. 18, the reproduction of the interrupt recovery ramp data starts from the part data whose attribute data indicates shot+chain and whose part number is "2". In this way, the sub CPU 81 prevents the reproduction of the interrupt return lamp data from being reproduced at the time of error recovery, thereby preventing the effect content from becoming inappropriate for the game state (reproducing the intro despite the fact that the effect is in progress). are preventing.

It should be noted that the sub CPU 81 uses the reproduction state management storage area in the attribute search cueing process (step S611 in FIG. 30), which will be described later, to perform cueing for repeated reproduction. 15 to 18 are also specific examples of the attribute search cue processing.

Instead of storing the lamp data for recovery from interruption corresponding to the lamp data in the sub ROM 82, the sub CPU 81 converts the lamp data reproduced at the time of error detection into the lamp data for recovery from interruption when recovering from an error. can be

Specifically, the sub CPU 81 converts the lamp data stored in the reproduction state management storage area into the interrupt return lamp data by removing the part number of the part data whose attribute data does not represent shot + chain. You may make it

<Description of the operation of the main control circuit>
Next, with reference to FIG. 19, the contents of various processes executed by the main CPU 51 of the main control circuit 41 using programs will be described.

[Power-on processing]
First, power-on processing of the main control circuit 41 of the pachi-slot machine 1, which is controlled by the main CPU 51, will be described with reference to FIG.

First, when the pachi-slot machine 1 is powered on, the main CPU 51 performs an initialization process when the power is turned on (S1). In this initialization process, it is determined whether the backup has been performed normally, whether the setting has been changed appropriately, etc., and the initialization corresponding to the determination result is performed.

Next, the main CPU 51 performs initialization processing when one game ends (S2). In this initialization process, the data in the designated storage area in the main RAM 53 is cleared. The designated storage area referred to here is, for example, a storage area such as an internal winning combination storage area or a display combination storage area, the data of which needs to be erased for each game.

Next, the main CPU 51 performs medal acceptance/start check processing (S3). In this process, the inputs of the medal sensor 35S and the start switch 16S are checked.

Specifically, the main CPU 51 counts the number of medals inserted by automatic insertion when a display combination related to a replay (replay combination) is established in the previous game, and counts the number of medals inserted from the medal slot 13. , and counting the number of inserted coins based on the pressing of the BET buttons (MAXBET, 1BET), etc., and when the number of inserted coins has reached the game-startable number, the state of the start switch is determined.

Next, the main CPU 51 extracts a random number value (0 to 65535) from the first random number register (not shown) of the random number generator 56, and stores the extracted random number value in a random number storage area (not shown) provided in the main RAM 53. ) (S4). Next, the main CPU 51 extracts a random number for effect used in controlling reel effects and locks from a second random number register (not shown) of the random number generator 56 , and stores the extracted random number for effect in the main RAM 53 . Stored in the effect random number storage area (not shown) (S5). In this embodiment, the random number for effect is extracted from the range of 0-127.

When the extracted random number values are stored in a predetermined random number storage area, the main CPU 51 performs an internal lottery process (S6). In this process, an internal winning combination is determined by lottery based on the random numbers extracted in S4.

Next, the main CPU 51 performs game lock lottery processing (S7). In the game lock lottery process, the main CPU 51 refers to a game lock lottery table (not shown) corresponding to the game state, and performs a game lock lottery based on the effect random number value.

Next, the main CPU 51 performs reel stop initialization processing (S8). In the reel stop initial setting process, the main CPU 51 acquires various information related to rule stop control from a reel stop initial setting table (not shown) based on the internal winning combination.

Next, the main CPU 51 performs start command transmission processing (S9). Specifically, the main CPU 51 transmits a start command to the sub control circuit 42 . The start command includes a parameter specifying an internal winning combination and the like, a game lock type, a lock time, and the like.

Next, the main CPU 51 performs wait processing (S10). In this process, if a predetermined time (for example, 4.1 seconds) has not passed since the start of the previous game, the main CPU 51 consumes the waiting time until the predetermined time elapses.

Next, the main CPU 51 performs reel rotation start processing (S11). In this process, the main CPU 51 requests the start of rotation of all reels. In the reel rotation start process, the main CPU 51 requests the start of rotation of all reels. When the start of rotation of all reels is requested, the three stepping motors 61L, 61C, 61R are controlled by an interrupt process (see FIG. 20), which will be described later, which is executed at a constant cycle (1.1172 msec). The rotation of the left reel 3L, middle reel 3C and right reel 3R is started.

Next, the main CPU 51 performs attraction priority storage processing (S12). In this process, the main CPU 51 acquires attraction priority data and stores it in an attraction priority data storage area (not shown).

Next, the main CPU 51 performs reel stop control processing (S13). In this process, the rotation of the relevant reel is stopped based on the timing at which the left stop button 17L, the middle stop button 17C and the right stop button 17R are pressed and the internal winning combination. That is, in this embodiment, the main control circuit 41 that executes the reel stop control process constitutes stop control means.

Next, the main CPU 51 performs game lock processing (S14). In this process, the main CPU 51 nullifies or delays the progress of the game. The main CPU 51 sets a value corresponding to the period during which the determined game lock type is executed in the lock timer, and waits until the value of the lock timer becomes "0". During that time, the main CPU 51 does not accept any operation by the player.

Next, the main CPU 51 performs winning search processing (S15). In this process, the main CPU 51 stores the data in the symbol code storage area (not shown) in the display combination storage area (not shown). Also, in this process, after all the left reel 3L, the middle reel 3C and the right reel 3R are stopped, the combination of symbols displayed on the effective line (win determination line) is collated with a symbol combination table (not shown). Then, the main CPU 51 may determine whether or not a display combination is displayed on the activated line, and store the determination result in the display combination storage area.

Next, the main CPU 51 performs medal payout processing (S16). The medal payout process represents a specific example of the game medium provision means according to the present invention. In this process, the hopper 33 is driven and the number of credits is updated based on the number of payouts for the display combination determined in S15, and medals are paid out. At this time, in this embodiment, as shown in the symbol combination table (not shown), the number of inserted medals is 1 to 3, and the number of paid out medals varies depending on the display combination. The payout upper limit) is 15 sheets.

Next, the main CPU 51 performs RT control processing (S17). In this process, the main CPU 51 manages the RT gaming state. The main CPU 51 refers to an RT transition table (not shown), checks the RT game state transition conditions that can be established in the transition source (current) RT game state, and determines that the RT game state transition conditions are satisfied. When it is determined, an RT transition table (not shown) is referred to, and based on the transition conditions, transition is made to the RT game state of the transition destination.

Next, the main CPU 51 performs payout end command transmission processing (S18). Specifically, the main CPU 51 transmits a payout end command to the sub-control circuit 42 .

Next, the main CPU 51 performs bonus end check processing (S19). In this process, the main CPU 51 refers to various counters for managing the trigger for ending the bonus game, and checks whether or not to end the operation of the bonus game.

Next, the main CPU 51 performs bonus activation check processing (S20). In this process, the main CPU 51 checks whether or not to start the operation of the bonus game and whether or not to play again. When the bonus operation check process ends, the main CPU 51 returns the process to S2, and repeats the processes after S2.

[Interrupt processing under control of main CPU (1.1172 msec)]
Next, with reference to FIG. 20, interrupt processing performed at regular intervals (every 1.1172 msec) under the control of a timer (not shown) incorporated in the main CPU 51 will be described.

First, the main CPU 51 saves the register (S351). Next, the main CPU 51 performs input port check processing (S352). In this process, signals input from various switches such as the stop switch 17S are checked.

Next, the main CPU 51 performs timer update processing (S353). In this process, the main CPU 51 performs, for example, a process of subtracting the value of the lock timer for each interrupt process. Next, the main CPU 51 performs communication data transmission processing (S354). In this process, various commands are mainly sent to the main control circuit 41 and the sub-control circuit 42 as appropriate.

Next, the main CPU 51 performs reel control processing (S355). In this process, the main CPU 51 starts rotating the left reel 3L, the middle reel 3C and the right reel 3R when it is requested to start rotating all the reels, and then rotates the reels at a constant speed. It drives and controls the three stepping motors 61L, 61C and 61R. Also, when the number of sliding symbols is determined, the main CPU 51 updates the symbol counter of the corresponding reel by the number of sliding symbols. Then, the main CPU 51 waits for the updated symbol counter to match the value corresponding to the expected stop position (the symbol at the expected stop position reaches the area on the effective line (win determination line) of the display window). , drives and controls the corresponding stepping motor so that the rotation of the relevant reel is decelerated and stopped. In addition, in the present embodiment, in the processing of S355, in addition to the above-described normal acceleration processing, constant speed processing, and stop processing, if a reel performance pattern is set during acceleration processing, it corresponds to the reel performance pattern. It also performs reel performance (reel action) and lock control processing.

Next, the main CPU 51 performs lamp/7 segment drive processing (S356). In this process, the main CPU 51 drives and controls the 7-segment display 6 to display the number of payouts, the number of credits, and the like. Next, the main CPU 51 performs register restoration processing (S357). After that, the main CPU 51 terminates the interrupt process.

<Description of the operation of the sub-control circuit>
Next, contents of various processes (tasks) executed by the sub CPU 81 of the sub control circuit 42 using programs will be described with reference to FIGS. 21 to 32. FIG.

[Power-on processing]
FIG. 21 is a flow chart showing power-on processing of the sub-control circuit 42 executed when the power is turned on.

First, the sub CPU 81 executes initialization processing (S361). In the initialization process, the sub CPU 81 initializes various drivers in addition to error checking of the sub RAM 83 and the like.

The tasks initialized in S361 are the main board communication task (see FIG. 22), which is a task group of command reception interrupt synchronization, and the sound control task (see FIG. 27), which is a task group of timer interrupt synchronization, and the lamp Includes control tasks (see FIG. 30) and the like.

Next, the sub CPU 81 activates the lamp control task (S362). In the lamp control task, the sub CPU 81 waits for reception of a timer interrupt event message transmitted every 2 ms, and turns on various lamps such as the LED group 21 in response to receiving the timer interrupt event message. control the state. Thus, the sub CPU 81 that executes the lamp control task constitutes control means.

Next, the sub CPU 81 activates the sound control task (S363). In the sound control task, the sub CPU 81 controls sound output states of various speakers such as the speakers 20L and 20R, as in the lamp control task.

Next, the sub CPU 81 activates the main board communication task (S364). In the main board communication task, the sub CPU 81 receives and analyzes commands transmitted from the main control circuit 41, and determines an effect based on the analyzed commands (lottery).

Next, the sub CPU 81 acquires date and time data from the RTC 86 and stores it in the date and time storage area (see FIG. 13) allocated to the sub RAM 83 (S365). Thus, the sub CPU 81 constitutes date and time acquisition means.

Next, the sub CPU 81 acquires a count value from a clock counter (not shown) provided in the sub CPU 81 and stores it in the sub RAM 83 as a clock count P (S366). After executing the process of S366, the sub CPU 81 ends the power-on process. The clock counter is a counter circuit that counts a clock of a predetermined frequency oscillated by an oscillation circuit 84 (see FIG. 7) incorporated in the sub CPU 81. The sub CPU 81 having a clock counter that counts the clock of the oscillation circuit 84 is , constitute the counting means.

[Main board communication task]
Next, the main board communication task performed by the sub CPU 81 will be described with reference to FIG.

First, the sub CPU 81 performs reception check of a command transmitted from the main control circuit 41 (S501). Next, the sub CPU 81 determines whether or not the received command is valid based on the reception check result (S502).

For example, the sub CPU 81 determines that the first condition is that the data length of the received command is 8 bytes, and that the received commands are a start command, a reel stop command, a display command, a payout end command, a bonus start command, a bonus end command, and a no-operation command. and the third condition that the sum value stored in the 8th byte of the received command is correct. The command is reflected as valid, and if any condition is not met, the received command is reflected as invalid in the check result of the reception check.

In S502, when the sub CPU 81 determines that the received command is not valid (NO in S502), the sub CPU 81 returns the process to S501 and repeats the processes after S501.

On the other hand, when the sub CPU 81 determines in S502 that the received command is valid (if determined as YES in S502), the sub CPU 81 stores a message in the message queue based on the received command (S503). . A message queue is a mechanism for exchanging information between processes. After the process of S503, the sub CPU 81 returns the process to S501, and repeats the processes after S501.

[Production registration task]
Next, the effect registration task performed by the sub CPU 81 will be described with reference to FIG.

First, the sub CPU 81 retrieves a message from the message queue (S511). Next, the sub CPU 81 determines whether or not there is a message in the message queue (S512). When the sub CPU 81 determines in S512 that there is no message in the message queue (when S512 determines NO), the sub CPU 81 performs the processing of S515, which will be described later.

On the other hand, when the sub CPU 81 determines in S512 that there is a message in the message queue (when S512 determines YES), the sub CPU 81 copies game information from the message (S513). In this process, for example, various data such as the internal winning combination, the type of reel whose rotation has stopped, the display combination, and the game state flag specified by the parameters are copied to a storage area (not shown) provided in the sub-RAM 83. be.

Next, the sub CPU 81 performs effect content determination processing (S514). In this process, the sub CPU 81 determines the contents of the effect, registers the effect data, etc. according to the type of the received command. Details of the effect content determination process will be described later with reference to FIG. 24, which will be described later.

Next, the sub CPU 81 registers sound data (S515). Next, the sub CPU 81 registers the lamp data (S516). These registration processes are performed based on the effect data registered in the effect content determination process of S514. In this embodiment, the sub CPU 81 registers the sound data by storing the sound data request number in the registration area of the sub RAM 83 only when the sound data request number has been determined, and requests the lamp data. The lamp data is registered by storing the request number of the lamp data in the registration area of the sub-RAM 83 only when the number has been determined. After S516, the sub CPU 81 returns the process to S511 and repeats the processes after S511.

[Production content determination process]
Next, with reference to FIG. 24, the effect content determination process performed at S514 in the flow chart of the effect registration task (see FIG. 23) will be described.

First, the sub CPU 81 determines whether or not it is time to receive a start command (S521).

In S521, when the sub CPU 81 determines that it is time to receive the start command (if determined as YES in S521), the sub CPU 81 performs processing when receiving the start command (S522). In this process, the sub CPU 81 extracts a random value for effect, and determines and registers the effect number by lottery based on the internal winning combination and the like. Here, the effect number is data specifying the content of the effect to be executed this time.

Next, the sub CPU 81 registers effect data at the start according to the registered effect number (S523). Effect data is data specifying animation data, sound data, and lamp data. Therefore, when the effect data is registered, the corresponding animation data and the like are determined, and the effect such as display by the display device is executed. After the process of S523, the sub CPU 81 ends the effect content determination process, and shifts the process to S515 of the effect registration task (see FIG. 23).

On the other hand, when the sub CPU 81 determines in S521 that the start command has not been received (NO in S521), the sub CPU 81 determines whether or not the reel stop command has been received (S524).

In S524, when the sub CPU 81 determines that it is time to receive the reel stop command (if determined as YES in S524), the sub CPU 81 determines the time of stopping according to the registered effect number and the type of the operation stop button. Effect data is selected (S525). Thereafter, the sub CPU 81 ends the effect content determination process, and shifts the process to S515 of the effect registration task (see FIG. 23).

On the other hand, when the sub CPU 81 determines in S524 that the reel stop command has not been received (NO in S524), the sub CPU 81 determines whether or not the display command has been received (S526).

When the sub CPU 81 determines in S526 that the display command is being received (if the determination in S526 is YES), the sub CPU 81 performs display command reception processing (S527). In this process, the sub CPU 81 determines and registers the effect number by lottery based on the display combination and the like. Here, the effect number is data specifying the content of the effect to be executed this time. Thereafter, the sub CPU 81 ends the effect content determination process, and shifts the process to S515 of the effect registration task (see FIG. 23).

On the other hand, when it is determined in S526 that the display command is not received (NO determination in S526), the sub CPU 81 determines whether or not the payout end command is received (S528). In S528, when the sub CPU 81 determines that it is time to receive the payout end command (if the determination in S528 is YES), the sub CPU 81 performs payout end command reception processing (S529). Thereafter, the sub CPU 81 ends the effect content determination process, and shifts the process to S515 of the effect registration task (see FIG. 23).

On the other hand, when the sub CPU 81 determines in S528 that the payout end command has not been received (NO in S528), the sub CPU 81 determines whether or not the bonus start command has been received (S530).

In S530, when the sub CPU 81 determines that it is time to receive the bonus start command (if determined as YES in S530), the sub CPU 81 registers effect data for starting the bonus (S531). Thereafter, the sub CPU 81 ends the effect content determination process, and shifts the process to S515 of the effect registration task (see FIG. 23).

On the other hand, when the sub CPU 81 determines in S530 that the bonus start command has not been received (NO in S530), the sub CPU 81 determines whether or not the bonus end command has been received (S532). In S532, when the sub CPU 81 determines that it is time to receive the bonus end command (if determined as YES in S532), the sub CPU 81 registers effect data for bonus end (S533). Thereafter, the sub CPU 81 ends the effect content determination process, and shifts the process to S515 of the effect registration task (see FIG. 23).

When the sub CPU 81 determines in S532 that the bonus end command has not been received (NO in S532), the sub CPU 81 determines whether or not the no-operation command has been received (S534). In S534, when the sub CPU 81 determines that it is not time to receive the no-operation command (when the determination in S534 is NO), the sub CPU 81 ends the effect content determination process, and performs the process as part of the effect registration task (see FIG. 23). Move to S515.

On the other hand, when the sub CPU 81 determines in S534 that it is time to receive a no-operation command (if determined as YES in S534), the sub CPU 81 performs processing when no-operation command is received (S535). The details of the no-operation command reception process will be described later with reference to FIG. 25, which will be described later. After the process of S535, the sub CPU 81 ends the effect content determination process, and shifts the process to S515 of the effect registration task (see FIG. 23).

[Processing when no operation command is received]
Next, with reference to FIG. 25, the no-operation command reception processing performed at S535 in the flowchart of the effect content determination processing (see FIG. 24) will be described.

In the no-operation command reception process, the sub CPU 81 executes the date and time update process shown in FIG. 26 (S540). After executing the process of S540, the sub CPU 81 ends the no-operation command reception process.

The no-operation command is transmitted from the main control circuit 41 at intervals of approximately 10 msec. The date and time update process shown in FIG. 26 is not limited to the no-operation command reception process, and may be executed from other processes or tasks that are periodically executed.

[Date and time update process]
Next, the date/time update process will be described with reference to FIG.

First, the sub CPU 81 acquires a count value from the clock counter and stores it in the sub RAM 83 as a clock count C (S541). Next, the sub CPU 81 calculates a clock count D by subtracting the clock count P from the clock count C (S542). Thus, the sub CPU 81 constitutes elapsed time calculation means.

Next, the sub CPU 81 determines whether or not the clock count D is equal to or greater than the clock count value corresponding to one second (hereinafter simply referred to as "1 second count") (S543). In this embodiment, the sub CPU 81 operates with a clock of 22 MHz, so the one-second count is 22,000,000 (pulses).

If it is determined in S543 that the clock count D is not equal to or greater than the one-second count (NO), the sub CPU 81 terminates the date/time update process. If it is determined in S543 that the clock count D is equal to or greater than the 1 second count (YES), the sub CPU 81 subtracts the 1 second count from the clock count D (S544).

After executing the process of S544, the sub CPU 81 adds a one second count to the clock count P (S545). Next, the sub CPU 81 adds 1 to the date and time storage area (seconds) (S546).

Next, the sub CPU 81 determines whether or not the date and time storage area (seconds) is 60 or more (S547). If it is determined in S547 that the date and time storage area (seconds) is not equal to or greater than 60 (NO), the sub CPU 81 executes the process of S543.

If it is determined in S547 that the date/time storage area (seconds) is 60 or more (YES), the sub CPU 81 updates the date/time storage area (seconds) to 0 and adds 1 to the date/time storage area (minutes). (S548).

After executing the processing of S548, the sub CPU 81 determines whether or not the date and time storage area (minutes) is 60 or more (S549). If it is determined in S549 that the date and time storage area (minutes) is not equal to or greater than 60 (NO), the sub CPU 81 executes the process of S543.

If it is determined in S549 that the date and time storage area (minute) is 60 or more (YES), the sub CPU 81 updates the date and time storage area (minute) to 0 and adds 1 to the date and time storage area (hour). (S550).

After executing the process of S550, the sub CPU 81 determines whether or not the date and time storage area (hour) is 24 or more (S551). If it is determined in S551 that the date and time storage area (hour) is not equal to or greater than 24 (NO), the sub CPU 81 executes the process of S543.

If it is determined in S551 that the date and time storage area (hour) is 24 or more (YES), the sub CPU 81 updates the date and time storage area (hour) to 0, and stores the date and time storage area (day) and the date and time storage area. 1 is added to (day of the week) (S552).

After executing the processing of S552, the sub CPU 81 determines whether or not the date and time storage area (day of the week) is 7 or more (S553). If it is determined in S553 that the date and time storage area (day of the week) is 7 or more (YES), the sub CPU 81 updates the date and time storage area (day of the week) to 0 (S554).

If it is determined in S553 that the date and time storage area (day of the week) is not equal to or greater than 7 (NO), or after executing the process of S554, the sub CPU 81 determines whether the year represented by the date and time storage area (year) is a leap year. is calculated (S555).

Note that leap years are calculated for years with no remainder when the year is divided by "4", "100" and "400" (for example, the year 2000), and when the year is divided by "4" and the remainder is A leap year is a year in which there is no AD and there is a remainder when the year is divided by "100" (for example, the year 2020).

Next, the sub CPU 81 identifies the number of days (hereinafter, also referred to as “the number of months”) associated with the calculation result of S555 and the date and time storage area (month) from the monthly day table (see FIG. 12). , the date and time storage area (day) is greater than or equal to the number of days in a month (S556).

If it is determined in S556 that the date and time storage area (day) is not equal to or greater than the number of days in a month (NO), the sub CPU 81 executes the process of S543. If it is determined in S556 that the date/time storage area (day) is equal to or greater than the number of days in the month (YES), the sub CPU 81 updates the date/time storage area (day) to 1 and adds 1 to the date/time storage area (month). Add (S557).

After executing the process of S557, the sub CPU 81 determines whether or not the date and time storage area (month) is 12 or more (S558). If it is determined in S558 that the date and time storage area (month) is not 12 or more (NO), the sub CPU 81 executes the process of S543.

If it is determined in S558 that the date and time storage area (month) is 12 or more (YES), the sub CPU 81 updates the date and time storage area (month) to 1 and adds 1 to the date and time storage area (year). (S559). After executing the process of S559, the sub CPU 81 executes the process of S543.

In this way, the sub CPU 81 that executes the date/time update process constitutes elapsed time calculation means. The date/time update process updates the date/time data by adding 1 second as a specified time to the date/time data stored in the date/time storage area. Therefore, originally, the date and time data in the date and time storage area is updated by acquiring the date and time data from the RTC 86 and storing the acquired date and time data in the date and time storage area. By updating the date and time data in the date and time storage area without updating, the sub CPU 81 can omit the processing load associated with communication with the RTC 86 .

In general, when calculating the elapsed date and time from the clock count, the clock count is divided by the clock count equivalent to one day, and from the quotient, the number of elapsed years, the number of elapsed months, and the number of elapsed days are calculated, and the remainder is 1. Divide by the clock count equivalent to time to calculate the elapsed time, divide the remainder by the clock count equivalent to 1 minute to calculate the elapsed minutes, divide the remainder by the clock count equivalent to 1 second to calculate the elapsed seconds Calculate

Division processing by the CPU is performed by floating point arithmetic or iterative arithmetic. Therefore, division imposes the highest processing load on the CPU among the four arithmetic operations. The date and time update processing in this embodiment reduces the load on the sub CPU 81 by updating the date and time data stored in the date and time storage area only by addition processing without performing division processing with a high processing load.

Further, in the present embodiment, the date and time data is acquired from the RTC 86 in the power-on process (FIG. 21) and is updated using the clock counter, but the present invention is not limited to this. Alternatively, date and time data may be read from the RTC 86 every hour.

[Sound control task]
Next, the sound control task performed by the sub CPU 81 will be described with reference to FIG.

First, the sub CPU 81 executes sound function RAM transfer processing for transferring a predetermined program among the control programs stored in the sub ROM 82 to the sub RAM 83 (S581). The sound function RAM transfer processing will be described later with reference to FIG.

Next, the sub CPU 81 determines whether or not the sound data registered in the effect registration task (see S515 in FIG. 23) has been updated (S582). This sound data is data for driving and controlling the speakers 20L and 20R (see FIG. 2) during a certain period.

In S582, if the sub CPU 81 determines that the registered sound data has been updated (YES), it executes the process of S583, and if it determines that the registered sound data has not been updated (NO). , S584 are executed.

At S583, the sub CPU 81 acquires the registered sound data (S583). After executing the process of S583, the sub CPU 81 executes the process of S584. In S584, the sub CPU 81 executes sound control data generation processing for generating sound control data according to the sound data and the reproduction position of the sound data.

The sound control data is data for driving and controlling the speakers 20L and 20R for each predetermined cycle. That is, the sub CPU 81 creates sound control data by dividing sound data, which is data for driving and controlling the speakers 20L and 20R in a certain period, for each predetermined period.

After executing the process of S584, the sub CPU 81 executes the process of S585. In S585, the sub CPU 81 registers the sound control data generated in the sound control data generation process (S584) in the sound driver (software).

By registering the sound control data in the sound driver in this manner, the sub CPU 81 that executes the processing of the sound driver transmits the sound control data to the sound IC 88 . Also, when transmitting the sound control data to the sound IC 88, the sub CPU 81 receives information such as the reproduction state of the sound IC.

After executing the process of S585, the sub CPU 81 executes the process of S586. In S586, the sub CPU 81 determines whether or not the sound being played has finished playing. In S586, if the sub CPU 81 determines that the sound being reproduced has finished playing (YES), it executes the process of S587, and if it determines that the sound being played has not finished playing (NO). , S582 are executed.

In S587, the sub CPU 81 determines whether or not the sound being reproduced is loop reproduction. In S587, if the sub CPU 81 determines that the sound being played is for loop playback (YES), it executes the process of S588, and if it determines that the sound being played is not for loop playback (NO). , S582 are executed.

In S588, the sub CPU 81 executes sound data cue processing. In the sound data cue process, the sub CPU 81 returns the sound data reproduction position to the beginning. After executing the process of S588, the sub CPU 81 executes the process of S582.

[Sound function RAM transfer processing]
Next, referring to FIG. 28, sound function RAM transfer processing will be described.

First, the sub CPU 81 transfers a program for executing sound control data generation processing (see S584 in FIG. 27) in the sound control task from the sub ROM 82 to the sub RAM 83 (S591).

Next, the sub CPU 81 transfers the sound driver from the sub ROM 82 to the sub RAM 83 (S592). After executing the process of S592, the sub CPU 81 ends the sound function RAM transfer process.

The sub CPU 81 executes a sound control data generation processing program transferred to the sub RAM 83 from the sound control task program, which is a higher-level program. The sub CPU 81 also executes processing as a sound driver according to the program transferred to the sub RAM 83 .

Thus, in the sound function RAM transfer process, the sub CPU 81 transfers the program for executing the sound data generation process, which is a predetermined program with a relatively high processing load, and the sound driver from the sub ROM 82 to the sub RAM 83. By doing so, the processing speed is improved.

[Specific example of sound control task and sound function RAM transfer processing]
Referring to FIG. 29, the sound control task and sound function RAM transfer processing described with reference to FIGS. 27 and 28 will be specifically described. Note that in FIG. 29, the sound control task and the sound function RAM transfer process are each expressed in C language.

"SoundRamTrans()" is a program for executing the sound function RAM transfer process shown in FIG. A program for executing the processing of step S584 of the sound control task is stored at the location represented by the address “_SoundMakeData” of the sub ROM 82 .

In step S591 of the sound function RAM transfer process, the memory copy function (memcpy) transfers the program size (sizeof(_SoundMakeData)) from the sub-ROM 82 address "_SoundMakeData" to the sub-RAM 83 address "__SoundMakeData". A memory copy is performed.

Thus, the program for executing the process of step S584 of the sound control task is transferred to the sub-RAM83. In the present embodiment, it is assumed that an area for storing the program is secured at the location indicated by the address "__SoundMakeData" of the sub-RAM 83 before executing the sound function RAM transfer process.

A program for executing the processing of step S585 of the sound control task is stored at the location indicated by the address "_SetSoundDriver" of the sub ROM 82 . In step S592 of the sound function RAM transfer process, the memory copy function (memcpy) transfers the program size (sizeof(_SetSoundDriver)) from the sub ROM 82 address "_SetSoundDriver" to the sub RAM 83 address "__SetSoundDriver". A memory copy is performed.

Thus, the program for executing the process of step S585 of the sound control task is transferred to the sub-RAM83. In the present embodiment, it is assumed that an area for storing the program is secured at the location represented by the address "__SetSoundDriver" of the sub-RAM 83 before executing the sound function RAM transfer process.

"SoundTask()" is a program for executing the sound control task shown in FIG. Note that "SoundTask( )" shown in FIG. 29 represents the processing of steps S583 to S585, and the description of other processing is omitted.

In "SoundTask( )", "index" is used as a variable representing the request number for identifying sound data, and "SoundData" is used as a pointer variable representing the address of the sub ROM 82 where the sound data is stored. , “SoundBuf” are used as a pointer variable representing the address of the sub-RAM 83 where the sound control data is stored.

"GetSoundData( )" executes the processing of step S583 of the sound control task and acquires the registered sound data. Specifically, "GetSoundData()" stores the address of the storage destination of the specified sound data in "SoundData" when the request number of the registered sound data is specified by "index".

"SoundMakeData()" is an access function of the program "__SoundMakeData()" transferred to the address "__SoundMakeData" of the sub-RAM 83 in step S591 of the sound function RAM transfer process shown in FIG.

"__SoundMakeData()" generates sound control data in the sub-RAM 83 based on the sound data whose address is specified when the address of the storage destination of the sound data indicated by the argument "dat" is specified, and the generated sound control data is generated. Store the address of the data storage destination in the argument "buf".

Therefore, "SoundMakeData()" in "SoundTask()" executes the processing of step S584 of the sound control task, and by specifying the pointer variable "SoundData" representing the address of the sound data storage destination, the pointer variable The address of the sub-RAM 83 where the sound control data is stored is stored in "SoundBuf".

"SetSoundDriver()" is an access function of the program "__SetSoundDriver()" transferred to the address "__SetSoundDriver" of the sub-RAM 83 in step S591 of the sound function RAM transfer process shown in FIG. "__SetSoundDriver()" registers the specified address in the sound driver when the address of the sub-RAM 83 where the sound control data indicated by the argument "buf" is stored is specified.

Therefore, "SetSoundDriver()" in "SoundTask()" executes the processing of step S585 of the sound control task, and by specifying "SoundBuf" representing the address where the sound control data is stored, the sound control data is registered in the sound driver.

[Lamp control task]
Next, the lamp control task performed by the sub CPU 81 will be described with reference to FIG.

First, the sub CPU 81 executes ramp function RAM transfer processing for transferring a predetermined program among the control programs stored in the sub ROM 82 to the sub RAM 83 (S601). The ramp function RAM transfer process will be described later with reference to FIG.

Next, the sub CPU 81 executes lamp data reading processing for reading the lamp data registered in the effect registration task (see S516 in FIG. 23) and the like into the sub RAM 83 (S602). The lamp data reading process will be described later with reference to FIG.

Next, the sub CPU 81 determines whether or not the lamp data is being reproduced based on the value of the entry part number storage area of the reproduction state management storage area (see FIG. 14) (S603). As described above, when lamp data is being reproduced, a part number for identifying the part data being reproduced is stored in the entry part number storage area of the reproduction state management storage area. On the other hand, as will be described later, when lamp data is not being reproduced, a specific value (for example, "0") is stored in the entry part number storage area of the regeneration state management storage area.

For this reason, the sub CPU 81 in this embodiment determines that the lamp data is being reproduced if the value of the entry part number storage area of the regeneration state management storage area is not a specific value, and If the value in the number storage area is a specific value, it is determined that lamp data is not being reproduced.

In S603, if the sub CPU 81 determines that the lamp data is being reproduced (YES), it executes the process of S604, and if it determines that the lamp data is not being reproduced (NO), it executes the process of S602. to run.

In S604, the sub CPU 81 acquires the attribute data of the part data being reproduced in the lamp data. Next, the sub CPU 81 determines whether or not the luminance pattern at the reproduction position of the part data being reproduced is an end block (for example, "-1") (S605).

In S605, if the sub CPU 81 determines that the luminance pattern at the reproduction position of the part data being reproduced is the end block (YES), it executes the process of S608, and if it determines that it is not the end block ( NO), the process of S606 is executed.

In S606, the sub CPU 81 generates control data (see FIGS. 8 to 10) from the luminance pattern at the reproduction position of the part data being reproduced. As described above, in this embodiment, the control data represents the luminance with 6 bits (range of 0 to 63), and the luminance pattern represents the luminance with 8 bits (range of 0 to 255).

Therefore, the sub CPU 81 converts the luminance value in the luminance pattern into a 6-bit luminance value by bit shifting (shifts the luminance value, which is 8-bit data, by 2 bits in the LSB direction), and serially converts the luminance value based on the converted luminance value. Control data is generated according to the data format of the communication circuit for bus communication. That is, the sub CPU 81 registers the brightness value converted into 6 bits in the corresponding brightness data L of the control data.

In this embodiment, the luminance value of the luminance pattern is represented by 8 bits. This is because the brightness pattern can be diverted simply by changing the processing, and the lamp data can be diverted even if the type of the driver IC is different.

After executing the process of S606, the process of S607 is executed. In S607, the sub CPU 81 registers the control data generated in the lamp control data generation process (S606) in the lamp driver (software).

By registering the control data in the lamp driver in this manner, the sub CPU 81 that executes lamp driver processing transmits the control data to the driver IC. After executing the process of S607, the sub CPU 81 executes the process of S602.

In S608, the sub CPU 81 determines whether or not there is part data next to the part data being reproduced based on the entry part number storage area and the part number storage area of the playback state management storage area (see FIG. 14). do. In S608, if the sub CPU 81 determines that there is next part data (YES), it executes the process of S609, and if it determines that there is no next part data (for example, in the case of FIG. If the part data is part number: 8 or the end code in the end code storage area (see FIG. 14) is detected (NO), the process of S610 is executed.

In S609, the sub CPU 81 updates the entry part number storage area of the playback state management storage area to the value of the next part number storage area, and moves the playback position to the next part data. At S610, the sub CPU 81 determines whether or not the attribute data obtained at S604 is shot+chain.

In S610, when the sub CPU 81 determines that the attribute data is shot+chain (YES), it executes attribute search cue processing (S611). In the attribute search cue process, the sub CPU 81, based on the contents stored in the reproduction state management storage area (see FIGS. 14 to 18), if "TRUE" is stored in the chain/loop setting area, the lamp Part data representing shot + chain attribute data is searched from the beginning of the identification information represented by the data (for example, part number: 1 in the case of FIG. 16) (for example, in the case of FIG. 16, part number: 2) and detected The reproduction position is moved to the beginning of the part data (for example, "2" is set in the entry part number storage area in FIG. 14). After executing the process of S611, the sub CPU 81 executes the process of S602.

If it is determined in S610 that the attribute data is not shot+chain (NO), the sub CPU 81 determines whether or not the attribute data acquired in S604 is a loop (S612). In S612, when it is determined that the attribute data is not a loop (NO), the sub CPU 81 executes the process of S602.

In S612, when it is determined that the attribute data is a loop (YES), the sub CPU 81 executes an in-part cue process (S613). In the attribute search cue process, the sub CPU 81 moves the reproduction position to the beginning of the part data being reproduced. After executing the process of S613, the sub CPU 81 executes the process of S602.

If the attribute data is a loop and the part data changes from "0" to "9" in ascending order, then the part data is cueed to "0" which is the beginning of the part data. It is a repeat function that repeats from "0" to "9".

[Lamp data read processing]
Next, referring to FIG. 31, lamp data reading processing will be described.

First, the sub CPU 81 determines whether or not an error in pachislot 1 is detected (S631). Pachi-slot 1 errors include a hopper empty error indicating that the hopper 33 (see FIG. 5) is empty, and an insertion error indicating that the number of medals stored in the medal auxiliary storage 37 (see FIG. 5) has reached a specified amount. There is an error such as the medal auxiliary storage full error.

The main CPU 51 sends an error command representing these errors to the sub control circuit 42 . The sub CPU 81 determines whether or not an error in pachi-slot 1 is detected based on this error command.

In S631, if the sub CPU 81 determines that an error in Pachi-slot 1 has been detected (YES), it executes the process of S632, and if it determines that an error in Pachi-slot 1 has not been detected (NO), S634. process.

In S632, the sub CPU 81 stores the request number of the lamp data being reproduced in the sub RAM 83 if the lamp data is being reproduced. After executing the process of S632, the sub CPU 81 registers lamp data for errors (S633). After executing the process of S633, the sub CPU 81 executes the process of S638.

At S634, the sub CPU 81 determines whether or not the error of pachi-slot 1 has been resolved (S634). In S634, if the sub CPU 81 determines that the error in pachi-slot 1 has been cleared (YES), it executes the process of S635; if it determines that the error in pachi-slot 1 has not been cleared (NO), The process of S637 is executed.

In S635, the sub CPU 81 identifies the request number of the lamp data for recovery from interruption corresponding to the request number saved in S632. After executing the process of S635, the sub CPU 81 registers the error lamp data of the request number specified in S635 (S636). After executing the process of S636, the sub CPU 81 executes the process of S638.

At S637, the sub CPU 81 determines whether or not the lamp data registered at S516 (see FIG. 23) of the effect registration task has been updated (S637). In S637, if the sub CPU 81 determines that the lamp data has been updated (YES), it executes the process of S638; if it determines that the lamp data has not been updated (NO), it performs a lamp data reading process. exit.

At S638, the sub CPU 81 acquires the lamp data registered at S633, S636 or S516 of the effect registration task. After executing the processing of S638, the sub CPU 81 executes reproduction data generation processing for generating a reproduction state management storage area (see FIG. 14) in the sub RAM 83 based on the lamp data acquired in S638 (S639).

The sub CPU 81 in this embodiment registers blank lamp data in S516 of the effect registration task when ending the reproduction of the lamp data. When blank lamp data is registered, the sub CPU 81 sets a specific value (for example, "0") in the entry part number storage area and generates a reproduction state management storage area that does not include the part number storage area in S639. do. After executing the process of S639, the sub CPU 81 ends the lamp data reading process.

[Ramp function RAM transfer processing]
Next, referring to FIG. 32, ramp function RAM transfer processing will be described.

First, the sub CPU 81 transfers a program for executing the reproduction data generation process (see S639 in FIG. 31) in the lamp data reading process from the sub ROM 82 to the sub RAM 83 (S651).

Next, the sub CPU 81 transfers the program for executing the lamp control data generation process (S606 in FIG. 30) in the lamp control task from the sub ROM 82 to the sub RAM 83 (S652).

Next, the sub CPU 81 transfers the lamp driver from the sub ROM 82 to the sub RAM 83 (S653). After executing the process of S653, the sub CPU 81 ends the ramp function RAM transfer process.

The sub CPU 81 executes a reproduction data generation processing program from a lamp data read processing program, which is a higher-level program, and executes a lamp control data generation processing program from a lamp control task program, which is a higher-level program. The sub CPU 81 also executes processing as a lamp driver according to the program transferred to the sub RAM 83 .

Thus, in the ramp function RAM transfer process, the sub CPU 81 loads the programs for executing the reproduction data generation process and the lamp control data generation process, which are predetermined programs with relatively high processing loads, and the lamp driver from the sub ROM 82. The processing speed is improved by transferring to the sub-RAM 83 and executing.

[Specific Examples of Ramp Control Task, Ramp Data Read Processing, and Ramp Function RAM Transfer Processing]
Referring to FIG. 33, the ramp control task, ramp data read processing, and ramp function RAM transfer processing described with reference to FIGS. 30 to 32 will be specifically described. Note that in FIG. 33, the ramp control task and ramp function RAM transfer processing are each expressed in C language.

"LampRamTrans()" is a program for executing the ramp function RAM transfer process shown in FIG. A program for executing the process of step S639 of the lamp data reading process shown in FIG.

In step S651 of the ramp function RAM transfer process, the memory copy function (memcpy) transfers the program size (sizeof(_LampPlayMake)) from the sub ROM 82 address "_LampPlayMake" to the sub RAM 83 address "__LampPlayMake". A memory copy is performed.

Thus, the program for executing the process of step S639 of the lamp data reading process shown in FIG. In the present embodiment, it is assumed that an area for storing the program is secured at the location represented by the address "__LampPlayMake" of the sub-RAM 83 before execution of the ramp function RAM transfer process.

A program for executing the process of step S606 of the lamp control task shown in FIG. In step S652 of the ramp function RAM transfer process, the memory copy function (memcpy) transfers the program size (sizeof(_LampMakeData)) from the sub-ROM 82 address "_LampMakeData" to the sub-RAM 83 address "__LampMakeData". A memory copy is performed.

Thus, the program for executing the process of step S606 of the lamp control task shown in FIG. 30 is transferred to the sub-RAM 83. FIG. In the present embodiment, it is assumed that an area for storing the program is secured at the location represented by the address "__LampMakeData" of the sub-RAM 83 before execution of the ramp function RAM transfer process.

A program for executing the process of step S607 of the lamp control task shown in FIG. In step S593 of the ramp function RAM transfer process, the memory copy function (memcpy) transfers the program size (sizeof(_SetLampDriver)) from the sub ROM 82 address "_SetLampDriver" to the sub RAM 83 address "__SetLampDriver". A memory copy is performed.

Thus, the program for executing the process of step S607 of the lamp control task shown in FIG. 30 is transferred to the sub-RAM83. In the present embodiment, it is assumed that an area for storing the program is secured at the location indicated by the address "__SetLampDriver" of the sub-RAM 83 before execution of the ramp function RAM transfer process.

"LampTask( )" is a program for executing the lamp control task shown in FIG. Note that "LampTask( )" shown in FIG. 33 represents the processing of steps S605 to S607, and the description of other processing is omitted.

In "LampTask()", "LampData" is used as a pointer variable representing the address of the sub-ROM 82 where the luminance data is stored, and "LampBuf" is used as a pointer variable representing the address of the sub-RAM 83 where the lamp control data is stored. used as The determination statement "if(*LampData!=EndBlock)" represents the processing of step S605.

“LampPlayMake( )” is an access function of the program “__LampPlayMake( )” transferred to the address “__LampPlayMake” of the sub-RAM 83 in step S651 of the ramp function RAM transfer process shown in FIG.

"__LampPlayMake()" reads the specified luminance pattern into the reproduction state management storage area (see FIG. 14) of the sub-RAM 83 when the address of the luminance pattern storage indicated by the argument "dat" is specified. Store the address of the playback status management storage area in the argument "buf".

"LampMakeData()" is an access function of the program "__LampMakeData()" transferred to the address "__LampMakeData" of the sub-RAM 83 in step S652 of the ramp function RAM transfer process shown in FIG.

"__LampMakeData()" generates lamp control data in the sub-RAM 83 based on the luminance pattern whose address is specified when the address of the storage destination of the luminance pattern represented by the argument "dat" is specified, and the generated lamp control data is generated. Store the address of the data storage destination in the argument "buf".

Therefore, 'LampMakeData()' in 'LampTask()' executes the processing of step S606 of the lamp control task shown in FIG. Thus, the address of the sub-RAM 83, which is the storage destination of the lamp control data, is stored in the pointer variable "LampBuf".

"SetLampDriver()" is an access function of the program "__SetLampDriver()" transferred to the address "__SetLampDriver" of the sub-RAM 83 in step S653 of the ramp function RAM transfer process shown in FIG. "__SetLampDriver()" registers the specified address in the lamp driver when the address of the sub-RAM 83, which is the storage destination of the lamp control data indicated by "buf", is specified.

Therefore, "SetLampDriver()" in "LampTask()" executes the process of step S607 of the lamp control task shown in FIG. By doing so, the address of the sub-RAM 83 where the lamp control data is stored is registered in the lamp driver.

[Manufacturing method of program to be executed by sub CPU]
Next, referring to FIG. 34, a method of manufacturing a program to be executed by the sub CPU of the sub control circuit 42 will be described.

In this embodiment, the sub CPU 81 executes while reading the control program stored in the sub ROM 82 . On the other hand, in general, the reading speed of RAM is faster than the reading speed of ROM as a characteristic of semiconductors.

For this reason, the sub CPU 81 transfers some programs with a high processing load (generally called "functions" or "subroutines") to the sub RAM 83, and reads the programs transferred to the sub RAM 83. This improves the execution speed of some programs with a high processing load.

However, if the program stored in the sub-ROM 82 is only transferred to the sub-RAM 83, the address stored in the transferred program points to the address in the sub-ROM 82, so normal operation cannot be performed.

Before storing the program in the sub-ROM 82, it is necessary to change the address in the program to be transferred to the sub-RAM 83 to the address in the sub-RAM 83. In this embodiment, the programs to be transferred to the sub-RAM 83 are the programs stored in the addresses "_SoundMakeData" and "_SoundBuf" of the sub-ROM 82 described with reference to FIG. Programs stored at addresses "_LampPlayMake", "_LampMakeData" and "_LampBuf".

In addition, in the higher-level program that uses the program to be transferred to the sub-RAM 83, it is necessary to change the calling address of the program to be transferred to the sub-RAM 83 to the address within the sub-RAM 83.

In this embodiment, the upper-level programs that use the programs transferred to the sub-RAM 83 are the access functions "SoundMakeData()" and "SetSoundDriver()" shown in FIG. 29, and the access functions shown in FIG. Includes "LampPlayMake()", "LampMakeData()" and "SetLampDriver()".

Therefore, in the program manufacturing method of the present embodiment, the program to be transferred to the sub-RAM 83 and the upper-level program that uses the program to be transferred to the sub-RAM 83 (hereinafter collectively referred to as "address conversion target program") are It is produced by a method different from that for programs other than the conversion target program.

As shown in FIG. 34, in the program manufacturing method of the present embodiment, after executing the step P1 of compiling the target C language source group of the address conversion target program, the assembler source group generated at the step P1 is subjected to the above It has a step P2 of changing the address (specifically, the label) and the instruction (so-called mnemonic).

For example, a jump destination label is changed, and an instruction to jump to the label before change at an absolute address is rewritten as an instruction to jump to a relative address to the label after change. In this case, since the label of the assembler source generated from the original C language source points to the sub-ROM 82, the label is changed so as to jump to the sub-RAM 83, and the relative position (the current address of the instruction plus direction, or a relative number of bytes in the negative direction).

Further, in the program manufacturing method of the present embodiment, a non-target C language source group of a program other than the address conversion target program is compiled to generate an object file (intermediate file), and the address is changed by the step P2 RAM execution Step P3 of assembling the group of prepared assembler sources to generate an object file, linking the object file of the non-target C language source group and the object file of the group of RAM-executable assembler sources to generate a final program. and a step P4 of writing the program generated in the step P3 into the sub-ROM 82 .

[Various effects]
As described above, the pachi-slot machine 1 according to the embodiment of the present invention converts the pattern data corresponding to the effect to be executed according to the data format of the communication circuit for serial bus communication with the driver IC, and converts the converted pattern data. Various lamp groups such as the first lamp group 111, the seventh lamp group 117, the eighth lamp group 118, and the dot matrix section 119 are controlled by transmitting control data based on the data to the driver IC. Various groups of lamps can be controlled by independent pattern data.

In particular, the pachi-slot machine 1 according to the embodiment of the present invention converts the luminance value of the LED included in the pattern data corresponding to the performance to be executed into a luminance value corresponding to the driver IC, and transmits the control data based on the converted luminance value to the driver IC. In order to control various lamp groups such as the first lamp group 111, the seventh lamp group 117, the eighth lamp group 118 and the dot matrix section 119 by transmitting to the IC, various lamps are controlled by pattern data that does not depend on the specification of the driver IC. Groups can be controlled.

In addition, in the pachi-slot machine 1 according to the embodiment of the present invention, by not synchronizing the error detection data E with the data for setting the brightness of the LED in the control data, the sub CPU 81 can be operated without being affected by the data pattern. and an abnormality in serial bus communication between the driver ICs can be detected on the receiving side of the control data.

In addition, the pachislot machine 1 according to the embodiment of the present invention is specified by a first mode for setting the luminance of all LEDs driven by the driver IC, a channel number for specifying the LEDs to be driven by the driver IC, and a channel number. The control data can be sent in either the second mode for setting the brightness of the LEDs or the mode.

Therefore, when controlling the LEDs individually, such as when controlling the dot matrix section 119 arranged in a matrix, the second mode for setting the luminance of a specific LED is more effective than the first mode. The data length of the control data is also shortened.

On the other hand, when controlling the LEDs as a whole, such as when controlling the first lamp group 111, the seventh lamp group 117, and the eighth lamp group 118, the first lamp group 111, the seventh lamp group 117, and the eighth lamp group 118 do not require the channel numbers that specify the LEDs. The data length of the control data is shorter in the mode than in the second mode.

Further, when turning off all the LEDs, the data length is shorter in the third mode, which does not require the specification of the brightness value of each LED or the channel number for specifying the LED, than in the first and second modes. Become.

In this way, the pachi-slot machine 1 according to the embodiment of the present invention selects a control data mode in which the data length is shortened according to the application of the LED driven by the driver IC, thereby enabling transmission between the sub CPU 81 and the driver IC. The load can be reduced and the responsiveness of the LED can be improved.

Further, the pachi-slot machine 1 according to the embodiment of the present invention manages the date and time data by causing the sub CPU 81 to count operating clocks. Therefore, the sub CPU 81 does not need to perform serial communication with the RTC 86 each time it acquires date and time data. Thus, the pachi-slot machine 1 according to the embodiment of the present invention can reduce the load on the sub CPU 81 .

Further, the pachi-slot machine 1 according to the embodiment of the present invention updates the date and time data by referring to a monthly day table in which the number of days in a leap year and the number of days in a non-leap year are associated with each month. Data can be updated without error.

In addition, the pachi-slot 1 according to the embodiment of the present invention keeps the date and time stored in the date and time storage area of the sub RAM 83 until the calculated elapsed time is added to the date and time represented by the date and time data stored in the date and time storage area of the sub RAM 83. By adding the specified time (1 second count) to the data, the date and time data stored in the date and time storage area of the sub RAM 83 is updated only by addition processing without performing division processing with a high processing load. load can be reduced.

In addition, the pachislot machine 1 according to the embodiment of the present invention executes a program for executing sound data generation processing, which is a program with a relatively high processing load, a sound driver, reproduction data generation processing, and lamp control data generation processing. The processing speed of the sub CPU 81 can be improved by transferring the program and the lamp driver to the sub RAM 83 and executing them.

In addition, the pachi-slot machine 1 according to the embodiment of the present invention reduces the storage capacity required for the sub-RAM 83 by executing programs other than programs with a relatively high processing load while being stored in the sub-ROM 82. Cost can be suppressed.

In addition, the pachislot machine 1 according to the embodiment of the present invention can be diversified into various lamp groups such as the first lamp group 111, the seventh lamp group 117, the eighth lamp group 118 and the dot matrix section 119 by combining the parts data. In order to execute such effects, it is possible to check and change the light emission pattern of various lamp groups for each part data. Thus, the pachi-slot machine 1 according to the embodiment of the present invention can reduce the burden of confirming and changing the light emission patterns of various lamp groups.

In addition, the pachislot machine 1 according to the embodiment of the present invention has the first lamp group 111, the seventh lamp group 117, the eighth lamp group 118, the dot matrix section 119, etc., depending on the part data whose attribute data is set to continuous reproduction. Since the various lamp groups are caused to repeatedly execute the performance, even when the performance by the various lamp groups is executed for a long time, the burden of confirming and changing the light emission patterns of the various lamp groups can be reduced.

Also, when the pachislot machine 1 according to the embodiment of the present invention recovers from the error state, the identification information of the part data whose attribute data does not represent shot + chain is removed, and the identification information represented by the new effect data is removed. Therefore, since the pattern data included in the parts data controls the various lamp groups such as the first lamp group 111, the seventh lamp group 117, the eighth lamp group 118 and the dot matrix section 119, the performance data is reproduced from the beginning when the error is recovered. By doing so, it is possible to prevent execution of an effect that is not suitable for the game state.

[Modification]
In the present embodiment, an example has been described in which the sub CPU 81 stores the date and time data acquired from the RTC 86 in the sub RAM 83 when the power is turned on, and updates the date and time data stored in the sub RAM 83 by counting the operating clock.

In addition, the sub CPU 81 may acquire date and time data from the RTC 86 and adjust the date and time data stored in the sub RAM 83 each time a predetermined condition is satisfied. Predetermined conditions include that the counted value exceeds a predetermined value, that a specific command such as a start command has been received, that an error state has been recovered, or that a reset button (not shown) has been pressed. etc.

Further, in the present embodiment, a program for executing sound data generation processing, which is a program with a relatively high processing load, a sound driver, a program for executing reproduction data generation processing and lamp control data generation processing, and a lamp driver at startup (in this embodiment, sound function RAM transfer processing and lamp function RAM transfer processing executed respectively as initialization processing for the sound control task and lamp control task that are started when the power of the sub CPU 81 is turned on). An example in which the data is transferred to the RAM 83 in advance and executed has been described.

On the other hand, the pachi-slot machine 1 according to the embodiment of the present invention may transfer each program to the sub-RAM 83 and execute it upon execution of each program having a relatively high processing load.

Further, when the pachi-slot machine 1 according to the embodiment of the present invention executes each program with a relatively high processing load, if each program has not been transferred to the sub-RAM 83, it transfers each program to the sub-RAM 83 for execution. You may do so.

With this configuration, the pachi-slot machine 1 according to the embodiment of the present invention, when executing each program with a relatively high processing load, if each program has been transferred to the sub-RAM 83, it has already been transferred to the sub-RAM 83. , the processing of the sub CPU 81 for transferring each program to the sub RAM 83 can be omitted.

In the pachi-slot machine 1 according to the embodiment of the present invention, if an area for transferring each program having a relatively high processing load is secured in the sub-RAM 83, the area for transferring each program is transferred to the sub-RAM 83. If not, an area for transferring each program may be secured in the sub-RAM 83, and each program may be transferred to the secured area and executed.

With this configuration, the pachi-slot machine 1 according to the embodiment of the present invention reliably transfers each program with a relatively high processing load to the sub-RAM 83 and executes it, so that the processing speed of the sub-CPU 81 is reliably improved. can be made

Further, the pachi-slot machine 1 according to the embodiment of the present invention transfers some of the programs having a relatively high processing load to the sub-RAM 83 in advance at startup, and transfers other programs to the sub-RAM 83 at the time of execution. You may make it transfer.

For example, the pachislot machine 1 according to the embodiment of the present invention includes a program for executing sound data generation processing, a sound driver, a program for executing reproduction data generation processing and lamp control data generation processing, and a lamp driver. The driver and lamp driver may be transferred to the sub-RAM 83 in advance at startup, and the programs for executing the sound data generation process, reproduction data generation process, and lamp control data generation process may be transferred to the sub-RAM 83 at the time of execution.

Further, in the present embodiment, the sub CPU 81 transmits control data in the second mode from the second port to the driver IC that drives the LEDs of the first light emitter group, and drives the LEDs of the second light emitter group. An example of transmitting control data in the first mode from the first port to the driver IC has been described.

On the other hand, the sub CPU 81 transmits the control data in the first mode from the second port to the driver IC that drives the LEDs of the first light emitter group, and sends the control data to the driver IC that drives the LEDs of the second light emitter group. may transmit the control data from the first port in the second mode.

Further, the sub CPU 81 transmits control data in the first mode from the second port to the driver IC that drives the LEDs of the first light emitter group, and the driver IC that drives the LEDs of the second light emitter group: The control data may be transmitted in the first mode from the first port.

Further, the sub CPU 81 transmits control data in the second mode from the second port to the driver IC that drives the LEDs of the first light emitter group, and the driver IC that drives the LEDs of the second light emitter group: Control data may be transmitted in the second mode from the first port.

Further, the sub CPU 81 may determine in which mode the control data generated from the registered lamp data is to be transmitted when the lamp data is registered by the effect registration task (see S516 in FIG. 23) or the like. .

Alternatively, a mode may be set in advance in the lamp data or parts data stored in the sub ROM 82, and the sub CPU 81 may transmit the control data in the mode set in advance in the lamp data or parts data.

[Other expandability of the gaming machine according to the present invention]
In the pachislot machine 1 of the above embodiment, the player's operation of inserting medals (that is, the operation of inserting the medals on hand into the medal insertion slot 13, or pushing the MAX bet button 14 or the 1 bet button 15 with the credited medals is performed. A game is started by an operation of inserting a coin into the game, and if medals are to be paid out at the end of the game, the hopper 33 is driven to pay out the medals from the medal payout port 18 or credits are given. Although the embodiment has been described, the invention is not so limited.

For example, for all forms in which a player inserts game media necessary for a game, a game is played based on it, and a privilege is awarded (for example, medals are paid out) based on the result of the game, The present invention can be applied. In other words, not only is the game medium inserted (played) and paid out by the physical action of the player, but the main control circuit (main board 31) itself can electromagnetically transfer the game medium held by the player. It may also be a form in which the game is managed systematically and the game can be played without medals. In this case, the game media held by the player may be electromagnetically managed by a game media management device that is mounted (connected) to the main control circuit (main board 31) and that manages the game media. good.

In this case, the game medium management device has ROM and RWM (or RAM), is provided in the game machine, and is capable of two-way communication with an external game medium handling device (not shown) via a predetermined interface. is connected to the game medium lending operation (that is, the action of providing the necessary game medium when the player performs the operation of inserting the game medium) or winning a prize related to the payout of the game medium (the relevant game media payout operation (that is, the operation of acquiring the game media necessary for paying out the game media to the player) in the case where the combination is established), or the game media used for the game are electromagnetically generated. It is sufficient that the operation of recording can be performed in real time. The game medium management device not only manages the actual number of game media, but also displays the number of owned game media (not shown) for displaying the number of game media owned, for example, based on the management result of the number of game media. may be provided on the front surface of the pachi-slot machine 1 to manage the number of game media displayed on the display device for the number of owned game media. In other words, the game media management device may record and display the total number of game media that a player can use for games by an electromagnetic method.

In this case, the game medium management device may have a performance (function) that allows the player to freely transmit a signal indicating the number of recorded game media to an external game medium handling device. desirable. In addition, it is desirable that the game medium management device has a performance that does not allow the number of recorded game mediums to be reduced except when directly operated by the player. Also, if an external connection terminal board (not shown) is provided between the game medium management device and the external game medium handling device, the game medium management device can It is desirable for a player to have the ability to not send a signal indicating the number of game media recorded.

In addition to the above, the game machine is provided with lending operation means, return (settlement) operation means, and an external connection terminal board that can be operated by the player. Slots for recording media (e.g. IC cards), non-contact communication antennas for depositing electronic money, etc., from mobile terminals, various operation means such as lending operation means, return operation means, etc., and external connections on the game media handling device side A terminal board may be provided (neither shown).

As a game flow at that time, for example, the player deposits valuable value into the game medium handling device by any of the above methods, and a predetermined number of valuable values is subtracted, and the game media corresponding to the subtracted valuable value are increased from the game media handling device to the game media management device. Then, the player plays the game, and repeats the above operation when the game medium is required. After that, as a result of the game, a predetermined number of game media are obtained, and when the game is finished, the game media management device sends the game media handling device the number of game media by operating one of the return operation means. , and the game medium handling device ejects the recording medium recording the number of game media. Also, when the game medium management device transmits the number of game media, it clears the number of game media stored in itself. The player takes the ejected recording medium to a prize counter or the like to exchange for prizes, or moves the game machine to play a game on another game machine based on the recorded game medium.

In the above example, the total number of game media was transmitted from the game media management device to the game media handling device. The game media possessed by the player may be divided and processed. Also, in the above example, the game medium handling device ejects the recording medium, but cash or cash equivalents may be ejected, or may be stored in a portable terminal or the like. Further, the game medium handling device may be configured so that the member recording medium of the game parlor can be inserted, the game medium is stored in the member recording medium, and the stored game medium can be used to play again at a later date. .

Also, in the game machine or the game medium handling device, by operating a predetermined operation means (not shown), it is possible to perform a lock operation to lock the game medium or valuable value data communication to the game medium handling device or the game medium management device. may be In this case, information that only the player can know, such as a one-time password, may be set, or the player may be stored by imaging means provided in the game machine or game medium handling device.

As described above, the game medium management device may allow the game to be played only without medals, or the game medium may be inserted (played) by a physical action of the player, and the game medium may be released. The game may be played in both a payout mode and a mode in which the game can be played without medals. In the latter case, the game media management device may adopt a method of directly controlling the selector 35 and the hopper 33 described above, or these may be controlled by the main control circuit (main board 31), and the control thereof may be performed. It is also possible to employ a system that can electromagnetically record and control the display of the total number of game media that a player can use for a game based on the transmission of the results.

Further, in the above example, the game medium management device is applied to pachislot, but for example, a slot machine using game balls or a sealed game machine may be provided with a game medium management device in the same way, and a player can use the game medium management device. of game media can be managed.

When the game medium management device described above is provided, it is possible to reduce the number of devices such as the selector 35 and the hopper 33 inside the game machine, as compared with the case where the game medium is physically provided for the game. Not only can the cost and manufacturing cost be reduced, but also the player can be prevented from directly contacting the game medium, the game environment can be improved, the noise can be reduced, and the reduction in the number of devices can reduce the number of game machines. It is also possible to reduce power consumption. Further, when the above-described game medium management device is provided, it is possible to prevent fraudulent actions through the game medium or the slot for inserting or paying out the game medium. That is, when the game medium management device described above is provided, it is possible to provide a gaming machine capable of improving various environments surrounding the gaming machine.

[Summary of Invention]
<Summary 1>
Japanese Laid-Open Patent Publication No. 2005-323768 proposes a game machine in which LEDs are arranged in a dot matrix to form a display unit.

In order to control the light emission of a light-emitting section composed of a plurality of light-emitting bodies, such as those in which LEDs are arranged in a dot matrix, there is a method in which each light-emitting body is directly controlled, and an LED driver IC or the like is used to transmit control data. There is also a method in which the light emission drive means drives the individual light emitters by transmitting to the light emission drive means.

The specifications of the light emission driving means may differ depending on the manufacturer of the light emission driving means or the series manufactured by the same manufacturer. Therefore, when controlling the individual light emitters through the light emission driving means, it is necessary to recreate the pattern data representing the light emission pattern of the light emitting section according to the light emission driving means.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a game machine capable of controlling a light emitting section by pattern data that does not depend on the specifications of the light emitting driving means.

The game machine according to the present invention is
a light-emitting portion (first lamp group 111, seventh lamp group 117, eighth lamp group 118, dot matrix portion 119) configured by a plurality of light-emitting bodies (LEDs);
light emission driving means (driver IC) for driving the light emitting unit;
a control unit (sub CPU 81) for controlling the light emission pattern of the light emitting unit;
pattern data storage means (sub ROM 82) storing a plurality of pattern data representing the light emission pattern of the light emitting unit;
The control unit
determining pattern data corresponding to the light emission pattern to be executed from a plurality of pattern data stored in the pattern data storage means;
converting the luminance value of the light emitter included in the determined pattern data into a luminance value corresponding to the light emission driving means;
The control data based on the converted brightness value is transmitted to the light emission driving means through serial bus communication.

With this configuration, the gaming machine according to the present invention converts the luminance value of the light emitter included in the pattern data corresponding to the light emission pattern to be executed into the luminance value corresponding to the light emission driving means, and controls the control data based on the converted luminance value. to the light emission drive means, the light emission part can be controlled by the pattern data independent of the specifications of the light emission drive means.

In addition, in the gaming machine according to the present invention,
The control unit inserts error detection data into the control data in a period that is not synchronized with the data for setting the luminance of the light emitter (for example, 9-bit period data for 6-bit period data). You may do so.

With this configuration, the game machine according to the present invention can perform serial bus communication without being affected by the data pattern by not synchronizing the error detection data with the data for setting the luminance of the light emitter in the control data. can be detected on the receiving side of the control data.

According to the present invention, it is possible to provide a game machine capable of controlling the light emitting section by pattern data that does not depend on the specifications of the light emission driving means.

<Summary 2>
In order to solve the same problem as in Summary 1, the gaming machine according to the present invention
a light-emitting portion (first lamp group 111, seventh lamp group 117, eighth lamp group 118, dot matrix portion 119) configured by a plurality of light-emitting bodies (LEDs);
light emission driving means (driver IC) for driving the light emitting unit;
a control unit (sub CPU 81) for controlling the light emission pattern of the light emitting unit;
pattern data storage means (sub ROM 82) storing a plurality of pattern data representing the light emission pattern of the light emitting unit;
The control unit
determining pattern data corresponding to the light emission pattern to be executed from a plurality of pattern data stored in the pattern data storage means;
converting the luminance value of the light emitter included in the determined pattern data into a luminance value corresponding to the light emission driving means;
Transmitting control data based on the converted luminance value to the light emission driving means by serial bus communication;
The control data are
a first mode for setting the brightness of all light emitters driven by the light emission driving means;
It has a configuration in which transmission is possible in any of a channel number specifying the light emitter to be driven by the light emission drive means and a second mode setting the luminance of the light emitter specified by the channel number.

With this configuration, the gaming machine according to the present invention converts the luminance value of the light emitter included in the pattern data corresponding to the light emission pattern to be executed into the luminance value corresponding to the light emission driving means, and controls the control data based on the converted luminance value. to the light emission drive means, the light emission part can be controlled by the pattern data independent of the specifications of the light emission drive means.

Further, the gaming machine according to the present invention is characterized by a first mode for setting the brightness of all the light emitters driven by the light emission drive means, a channel number for specifying the light emitters to be driven by the light emission drive means, and a channel number specified by the channel number. The control data can be sent in either the second mode for setting the brightness of the light emitters.

Therefore, when controlling the light emitters individually, the data length of the control data is shorter in the second mode in which the luminance of a specific light emitter is set than in the first mode, and the light emitters are controlled as a whole. When controlling, the data length of the control data is shorter in the first mode, which does not require the channel number specifying the light emitter, than in the second mode.

Therefore, in the game machine according to the present invention, by selecting a control data mode that shortens the data length according to the application of the light emitter driven by the light emission drive means, transmission between the control unit and the light emission drive means The load can be reduced, and the responsiveness of the light emitter can be improved.

In addition, in the gaming machine according to the present invention,
The control unit inserts error detection data into the control data in a period that is not synchronized with the data for setting the luminance of the light emitter (for example, 9-bit period data for 6-bit period data). You may do so.

With this configuration, the game machine according to the present invention can perform serial bus communication without being affected by the data pattern by not synchronizing the error detection data with the data for setting the luminance of the light emitter in the control data. can be detected on the receiving side of the control data.

According to the present invention, it is possible to provide a game machine capable of controlling the light emitting section by pattern data that does not depend on the specifications of the light emission driving means.

<Summary 3>
In order to solve the same problem as in Summary 1, the gaming machine according to the present invention
a light-emitting portion (first lamp group 111, seventh lamp group 117, eighth lamp group 118, dot matrix portion 119) configured by a plurality of light-emitting bodies (LEDs);
light emission driving means (driver IC) for driving the light emitting unit;
a control unit (sub CPU 81) for controlling the light emission pattern of the light emitting unit;
pattern data storage means (sub ROM 82) storing a plurality of pattern data representing the light emission pattern of the light emitting unit;
The control unit
determining pattern data corresponding to the light emission pattern to be executed from a plurality of pattern data stored in the pattern data storage means;
converting the luminance value of the light emitter included in the determined pattern data into a luminance value corresponding to the light emission driving means;
Transmitting control data based on the converted luminance value to the light emission driving means by serial bus communication;
The control data are
a first mode for setting the brightness of all light emitters driven by the light emission driving means;
can be transmitted in any of a channel number specifying the light emitter to be driven by the light emission driving means and a second mode setting the luminance of the light emitter specified by the channel number,
The plurality of light emitters,
a first light emitter group arranged in a matrix;
and a second light emitter group not included in the first light emitter group,
The control unit
transmitting the control data in the second mode to the light emission driving means for driving the light emitters of the first light emitter group;
The light emission driving means for driving the light emitters of the second light emitter group is configured to transmit the control data in the first mode.

With this configuration, the gaming machine according to the present invention converts the luminance value of the light emitter included in the pattern data corresponding to the light emission pattern to be executed into the luminance value corresponding to the light emission driving means, and controls the control data based on the converted luminance value. to the light emission drive means, the light emission part can be controlled by the pattern data independent of the specifications of the light emission drive means.

Further, the gaming machine according to the present invention is characterized by a first mode for setting the brightness of all the light emitters driven by the light emission drive means, a channel number for specifying the light emitters to be driven by the light emission drive means, and a channel number specified by the channel number. The control data can be sent in either the second mode for setting the brightness of the light emitters.

Therefore, for the first group of light emitters arranged in a matrix, the light emitters are individually controlled, so the second mode for setting the luminance of specific light emitters is more controlled than the first mode. Data length becomes shorter.

On the other hand, for the second light emitter group that is not included in the first light emitter group, the first mode, which does not require the channel numbers for specifying the light emitters, is more suitable for the overall control of the light emitters. The data length of control data is shorter than in 2 modes.

Therefore, in the game machine according to the present invention, by selecting a control data mode that shortens the data length according to the application of the light emitter driven by the light emission drive means, transmission between the control unit and the light emission drive means The load can be reduced, and the responsiveness of the light emitter can be improved.

In addition, in the gaming machine according to the present invention,
The control unit inserts error detection data into the control data in a period that is not synchronized with the data for setting the luminance of the light emitter (for example, 9-bit period data for 6-bit period data). You may do so.

With this configuration, the game machine according to the present invention can perform serial bus communication without being affected by the data pattern by not synchronizing the error detection data with the data for setting the luminance of the light emitter in the control data. can be detected on the receiving side of the control data.

According to the present invention, it is possible to provide a game machine capable of controlling the light emitting section by pattern data that does not depend on the specifications of the light emission driving means.

<Summary 4>
In order to solve the same problem as in Summary 1, the gaming machine according to the present invention
a light-emitting portion (first lamp group 111, seventh lamp group 117, eighth lamp group 118, dot matrix portion 119) configured by a plurality of light-emitting bodies (LEDs);
light emission driving means (driver IC) for driving the light emitting unit;
a control unit (sub CPU 81) for controlling the light emission pattern of the light emitting unit;
pattern data storage means (sub ROM 82) storing a plurality of pattern data representing the light emission pattern of the light emitting unit;
The control unit
determining pattern data corresponding to the light emission pattern to be executed from a plurality of pattern data stored in the pattern data storage means;
converting the determined pattern data according to the light emission driving means;
Control data based on the converted pattern data is transmitted to the light emission driving means by serial bus communication.

With this configuration, the gaming machine according to the present invention converts the pattern data corresponding to the light emission pattern to be executed according to the light emission driving means, and transmits the control data based on the converted pattern data to the light emission driving means. Since the light emitting unit is controlled, the light emitting unit can be controlled by pattern data that does not depend on the specifications of the light emission driving means.

In addition, in the gaming machine according to the present invention,
The control unit inserts error detection data into the control data in a period that is not synchronized with the data for setting the luminance of the light emitter (for example, 9-bit period data for 6-bit period data). You may do so.

With this configuration, the game machine according to the present invention can perform serial bus communication without being affected by the data pattern by not synchronizing the error detection data with the data for setting the luminance of the light emitter in the control data. can be detected on the receiving side of the control data.

According to the present invention, it is possible to provide a game machine capable of controlling the light emitting section by pattern data that does not depend on the specifications of the light emission driving means.

<Summary 5>
In order to solve the same problem as in Summary 1, the gaming machine according to the present invention
a light-emitting portion (first lamp group 111, seventh lamp group 117, eighth lamp group 118, dot matrix portion 119) configured by a plurality of light-emitting bodies (LEDs);
light emission driving means (driver IC) for driving the light emitting unit;
a control unit (sub CPU 81) for controlling the light emission pattern of the light emitting unit;
pattern data storage means (sub ROM 82) storing a plurality of pattern data representing the light emission pattern of the light emitting unit;
The control unit
determining pattern data corresponding to the light emission pattern to be executed from a plurality of pattern data stored in the pattern data storage means;
converting the luminance value of the light emitter included in the determined pattern data into a luminance value corresponding to the light emission driving means;
Transmitting control data based on the converted luminance value to the light emission driving means by serial bus communication;
The control data are
a first mode for setting the brightness of all light emitters driven by the light emission driving means;
a second mode for setting a channel number specifying a light emitter to be driven by the light emission driving means and a luminance of the light emitter specified by the channel number;
The third mode including a command for turning off all the light emitters driven by the light emission drive means can be transmitted in either mode.

With this configuration, the gaming machine according to the present invention converts the luminance value of the light emitter included in the pattern data corresponding to the light emission pattern to be executed into the luminance value corresponding to the light emission driving means, and controls the control data based on the converted luminance value. to the light emission drive means, the light emission part can be controlled by the pattern data independent of the specifications of the light emission drive means.

Further, the gaming machine according to the present invention is characterized by a first mode for setting the brightness of all the light emitters driven by the light emission drive means, a channel number for specifying the light emitters to be driven by the light emission drive means, and a channel number specified by the channel number. The control data can be sent in either the second mode for setting the brightness of the light emitters.

Therefore, when controlling the light emitters individually, the data length of the control data is shorter in the second mode in which the luminance of a specific light emitter is set than in the first mode, and the light emitters are controlled as a whole. When controlling, the data length of the control data is shorter in the first mode, which does not require the channel number specifying the light emitter, than in the second mode.

Further, when all the light emitters are extinguished, the third mode, which does not require the specification of the luminance value of each light emitter or the channel number for specifying the light emitter, is more data efficient than the first and second modes. length becomes shorter.

Therefore, in the game machine according to the present invention, by selecting a control data mode that shortens the data length according to the application of the light emitter driven by the light emission drive means, transmission between the control unit and the light emission drive means The load can be reduced, and the responsiveness of the light emitter can be improved.

In addition, in the gaming machine according to the present invention,
The control unit inserts error detection data into the control data in a period that is not synchronized with the data for setting the luminance of the light emitter (for example, 9-bit period data for 6-bit period data). You may do so.

With this configuration, the game machine according to the present invention can perform serial bus communication without being affected by the data pattern by not synchronizing the error detection data with the data for setting the luminance of the light emitter in the control data. can be detected on the receiving side of the control data.

According to the present invention, it is possible to provide a game machine capable of controlling the light emitting section by pattern data that does not depend on the specifications of the light emission driving means.

<Summary 6>
Japanese Laid-Open Patent Application No. 2017-51385 proposes a gaming machine in which an effect control CPU and an RTC (Real Time Clock) are connected by serial bus communication using an I2C (Inter-Integrated Circuit).

In order to obtain date and time data from the RTC, conventional gaming machines such as those described above need to perform serial communication such as I2C, which may impose a load on arithmetic processing means such as the effect control CPU.

SUMMARY OF THE INVENTION An object of the present invention is to provide a gaming machine capable of reducing the load on the arithmetic processing means.

The game machine according to the present invention is
Arithmetic processing means (sub CPU 81) that performs arithmetic processing;
clock generation means (oscillation circuit 84) for generating a clock for operating the arithmetic processing means;
Arithmetic storage means (sub-RAM 83) capable of storing data to be used by the arithmetic processing means;
A timekeeping means (RTC 86) that is connected to the arithmetic processing means by serial communication and clocks the date and time,
The arithmetic processing means is
date and time acquisition means for acquiring date and time data from the timekeeping means and storing the date and time data in the arithmetic storage means;
counting means (clock counter) for counting the clock generated by the clock generating means;
elapsed time calculation means for calculating the elapsed time based on the value counted by the counting means;
When the elapsed time calculated by the elapsed time calculating means reaches a prescribed elapsed time, the date and time data stored in the arithmetic storage means for the time corresponding to the elapsed time calculated by the elapsed time calculating means. date and time data updating means for updating the

With this configuration, the gaming machine according to the present invention manages date and time data by causing the arithmetic processing means to count operating clocks. Therefore, the arithmetic processing means does not need to perform serial communication with the clock means each time it acquires the date and time data. Thus, the gaming machine according to the present invention can reduce the load on the arithmetic processing means.

In addition, in the gaming machine according to the present invention, the date and time data updating means subtracts a specified elapsed time from the elapsed time, and repeats the process of updating the date and time data until the result of subtraction becomes less than the specified elapsed time. can be

According to the present invention, it is possible to provide a game machine capable of reducing the load on the arithmetic processing means.

<Summary 7>
In order to solve the same problem as in Summary 6, the gaming machine according to the present invention
Arithmetic processing means (sub CPU 81) that performs arithmetic processing;
clock generation means (oscillation circuit 84) for generating a clock for operating the arithmetic processing means;
Arithmetic storage means (sub-RAM 83) capable of storing data to be used by the arithmetic processing means;
clocking means (RTC 86) connected to the arithmetic processing means by serial communication and clocking the date and time;
a monthly day table storage means (sub ROM 82) for storing a monthly day table in which the number of days in a leap year and the number of days in a non-leap year are associated with each month;
The arithmetic processing means is
date and time acquisition means for acquiring date and time data from the timekeeping means and storing the date and time data in the arithmetic storage means;
a counting means for counting the clock generated by the clock generating means;
elapsed time calculation means for calculating the elapsed time based on the value counted by the counting means;
When the elapsed time calculated by the elapsed time calculating means reaches a prescribed elapsed time, the date and time data stored in the arithmetic storage means for the time corresponding to the elapsed time calculated by the elapsed time calculating means. date and time data updating means for updating the
The date and time data update means has a configuration for updating the date and time data with reference to the day of month table.

With this configuration, the gaming machine according to the present invention manages date and time data by causing the arithmetic processing means to count operating clocks. Therefore, the arithmetic processing means does not need to perform serial communication with the clock means each time it acquires the date and time data. Thus, the gaming machine according to the present invention can reduce the load on the arithmetic processing means.

In addition, since the gaming machine according to the present invention updates the date and time data with reference to the monthly day table in which the number of days in a leap year and the number of days in a non-leap year are associated with each month, the date and time data may be incorrect. can be updated without

In addition, in the gaming machine according to the present invention, the date and time data updating means subtracts a specified elapsed time from the elapsed time, and repeats the process of updating the date and time data until the result of subtraction becomes less than the specified elapsed time. can be

According to the present invention, it is possible to provide a game machine capable of reducing the load on the arithmetic processing means.

<Summary 8>
In order to solve the same problem as in Summary 6, the gaming machine according to the present invention
Arithmetic processing means (sub CPU 81) that performs arithmetic processing;
clock generation means (oscillation circuit 84) for generating a clock for operating the arithmetic processing means;
Arithmetic storage means (sub-RAM 83) capable of storing data to be used by the arithmetic processing means;
A timekeeping means (RTC 86) that is connected to the arithmetic processing means by serial communication and clocks the date and time,
The arithmetic processing means is
date and time storage means for acquiring date and time data from the timekeeping means and storing the date and time data in the arithmetic storage means;
a counting means for counting the clock generated by the clock generating means;
elapsed time calculation means for calculating the elapsed time based on the value counted by the counting means;
When the elapsed time calculated by the elapsed time calculating means reaches a prescribed elapsed time, the date and time data stored in the arithmetic storage means for the time corresponding to the elapsed time calculated by the elapsed time calculating means. date and time data updating means for updating the
The date/time data updating means updates the date/time data stored in the calculation/storage means until the elapsed time calculated by the elapsed time calculation means is added to the date/time represented by the date/time data stored in the calculation/storage means. A predetermined time is added to .

With this configuration, the gaming machine according to the present invention manages date and time data by causing the arithmetic processing means to count operating clocks. Therefore, the arithmetic processing means does not need to perform serial communication with the clock means each time it acquires the date and time data. Thus, the gaming machine according to the present invention can reduce the load on the arithmetic processing means.

Further, in the gaming machine according to the present invention, the date and time data stored in the calculation and storage means is kept at a predetermined time until the elapsed time calculated by the elapsed time calculation means is added to the date and time represented by the date and time data stored in the calculation and storage means. By adding the time, the date and time data stored in the arithmetic storage means can be updated only by the addition process without performing the division process with a high processing load, so the load on the arithmetic processing means can be reduced.

In addition, in the gaming machine according to the present invention, the date and time data updating means subtracts a specified elapsed time from the elapsed time, and repeats the process of updating the date and time data until the result of subtraction becomes less than the specified elapsed time. can be

According to the present invention, it is possible to provide a game machine capable of reducing the load on the arithmetic processing means.

<Summary 9>
Japanese Laid-Open Patent Publication No. 2000-296223 proposes a game machine that causes a CPU to execute a program stored in a ROM. Further, Japanese Laid-Open Patent Publication No. 2008-148891 proposes a gaming machine that transfers a program stored in a ROM to a RAM by boot processing at startup and causes a CPU to execute the program transferred to the RAM.

In a conventional game machine in which a program stored in a ROM is executed by an arithmetic processing means such as a CPU, the arithmetic processing means accesses the ROM each time the program is executed. It slowed down the processing speed of On the other hand, a conventional game machine, which causes an arithmetic processing means such as a CPU to execute a program transferred to a RAM, requires an increased RAM capacity, resulting in increased cost.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a game machine capable of improving the processing speed of arithmetic processing means without increasing costs.

The game machine according to the present invention is
Arithmetic processing means (sub CPU 81) that performs arithmetic processing;
a first storage means (sub ROM 82) in which programs and data for operating the arithmetic processing means are stored;
A rewritable second storage means (sub-RAM 83) having a higher access speed than the first storage means,
The arithmetic processing means is
transferring a predetermined program among the programs stored in the first storage means to the second storage means;
It has a configuration for executing the predetermined program transferred to the second storage means from an upper program for the predetermined program.

With this configuration, the gaming machine according to the present invention transfers a program having a relatively high processing load as a predetermined program to the second storage means and executes it, so that the processing speed of the arithmetic processing means can be improved.

Further, the gaming machine according to the present invention reduces the storage capacity required for the second storage means by executing programs other than the predetermined program stored in the first storage means, thereby reducing costs. be able to.

In the gaming machine according to the present invention, when the predetermined program is transferred to the second storage means, the arithmetic processing means transfers the first argument to the predetermined program stored in the first storage means. The first address may be used, the second argument may be the top address of the transfer destination of the second storage means, and the third argument may be the program capacity of the predetermined program stored in the first storage means.

According to the present invention, it is possible to provide a gaming machine capable of improving the processing speed of the arithmetic processing means without incurring costs.

<Summary 10>
In order to solve the same problem as in Summary 9, the gaming machine according to the present invention
Arithmetic processing means (sub CPU 81) that performs arithmetic processing;
a first storage means (sub ROM 82) in which programs and data for operating the arithmetic processing means are stored;
A rewritable second storage means (sub-RAM 83) having a higher access speed than the first storage means,
The arithmetic processing means is
Transferring the predetermined program to the second storage means with the execution of the predetermined program among the programs stored in the first storage means as a trigger,
It has a configuration for executing the predetermined program transferred to the second storage means from an upper program for the predetermined program.

With this configuration, the gaming machine according to the present invention transfers the predetermined program to the second storage means and executes it when the program having a relatively high processing load is executed as the predetermined program. The processing speed of the means can be improved.

Further, the gaming machine according to the present invention reduces the storage capacity required for the second storage means by executing programs other than the predetermined program stored in the first storage means, thereby reducing costs. be able to.

In the gaming machine according to the present invention, when the predetermined program is transferred to the second storage means, the arithmetic processing means transfers the first argument to the predetermined program stored in the first storage means. The first address may be used, the second argument may be the top address of the transfer destination of the second storage means, and the third argument may be the program capacity of the predetermined program stored in the first storage means.

According to the present invention, it is possible to provide a gaming machine capable of improving the processing speed of the arithmetic processing means without incurring costs.

<Summary 11>
In order to solve the same problem as in Summary 9, the gaming machine according to the present invention
Arithmetic processing means (sub CPU 81) that performs arithmetic processing;
a first storage means (sub ROM 82) in which programs and data for operating the arithmetic processing means are stored;
A rewritable second storage means (sub-RAM 83) having a higher access speed than the first storage means,
The arithmetic processing means is
A predetermined program among the programs stored in the first storage means is transferred in advance to the second storage means,
It has a configuration for executing the predetermined program transferred to the second storage means from an upper program for the predetermined program.

With this configuration, the gaming machine according to the present invention transfers a program having a relatively high processing load as a predetermined program to the second storage means in advance and executes the program, thereby improving the processing speed of the arithmetic processing means. be able to.

Further, the gaming machine according to the present invention reduces the storage capacity required for the second storage means by executing programs other than the predetermined program stored in the first storage means, thereby reducing costs. be able to.

In the gaming machine according to the present invention, when the predetermined program is transferred to the second storage means, the arithmetic processing means transfers the first argument to the predetermined program stored in the first storage means. The first address may be used, the second argument may be the top address of the transfer destination of the second storage means, and the third argument may be the program capacity of the predetermined program stored in the first storage means.

According to the present invention, it is possible to provide a gaming machine capable of improving the processing speed of the arithmetic processing means without incurring costs.

<Summary 12>
In order to solve the same problem as in Summary 9, the gaming machine according to the present invention
Arithmetic processing means (sub CPU 81) that performs arithmetic processing;
a first storage means (sub ROM 82) in which programs and data for operating the arithmetic processing means are stored;
A rewritable second storage means (sub-RAM 83) having a higher access speed than the first storage means,
The arithmetic processing means is
When executing a predetermined program among the programs stored in the first storage means, if the predetermined program has not been transferred to the second storage means, the predetermined program is transferred to the second storage means. death,
It has a configuration for executing the predetermined program transferred to the second storage means from an upper program for the predetermined program.

With this configuration, when the gaming machine according to the present invention executes a program with a relatively high processing load as a predetermined program, if the predetermined program has not been transferred to the second storage means, the predetermined program is stored in the second storage means. The processing speed of the arithmetic processing means can be improved by transferring the data to the means for execution.

Further, in the gaming machine according to the present invention, when executing the predetermined program, if the predetermined program has been transferred to the second storage means, the predetermined program transferred to the second storage means is executed. It is possible to omit the processing of the arithmetic processing means for transferring the program of (1) to the second storage means.

Further, the gaming machine according to the present invention reduces the storage capacity required for the second storage means by executing programs other than the predetermined program stored in the first storage means, thereby reducing costs. be able to.

In the gaming machine according to the present invention, when the predetermined program is transferred to the second storage means, the arithmetic processing means transfers the first argument to the predetermined program stored in the first storage means. The first address may be used, the second argument may be the top address of the transfer destination of the second storage means, and the third argument may be the program capacity of the predetermined program stored in the first storage means.

According to the present invention, it is possible to provide a gaming machine capable of improving the processing speed of the arithmetic processing means without incurring costs.

<Summary 13>
In order to solve the same problem as in Summary 9, the gaming machine according to the present invention
Arithmetic processing means (sub CPU 81) that performs arithmetic processing;
a first storage means (sub ROM 82) in which programs and data for operating the arithmetic processing means are stored;
A rewritable second storage means (sub-RAM 83) having a higher access speed than the first storage means,
The arithmetic processing means is
transferring the predetermined program to the second storage means if an area for transferring the predetermined program out of the programs stored in the first storage means is reserved in the second storage means;
if an area for transferring the predetermined program is not secured in the second storage means, securing an area for transferring the predetermined program in the second storage means, and transferring the predetermined program to the secured area;
It has a configuration for executing the predetermined program transferred to the second storage means from an upper program for the predetermined program.

With this configuration, the gaming machine according to the present invention can improve the processing speed of the arithmetic processing means by transferring a program having a relatively high processing load as a predetermined program to the second storage means and executing the program. .

Further, in the gaming machine according to the present invention, if an area for transferring a predetermined program is not reserved in the second storage means, an area for transferring a predetermined program is secured in the second storage means, and a predetermined program is transferred to the secured area. Since the program is transferred and executed, the processing speed of the arithmetic processing means can be reliably improved.

Further, the gaming machine according to the present invention reduces the storage capacity required for the second storage means by executing programs other than the predetermined program stored in the first storage means, thereby reducing costs. be able to.

In the gaming machine according to the present invention, when the predetermined program is transferred to the second storage means, the arithmetic processing means transfers the first argument to the predetermined program stored in the first storage means. The first address may be used, the second argument may be the top address of the transfer destination of the second storage means, and the third argument may be the program capacity of the predetermined program stored in the first storage means.

According to the present invention, it is possible to provide a gaming machine capable of improving the processing speed of the arithmetic processing means without incurring costs.

<Summary 14>
Japanese Laid-Open Patent Publication No. 2005-323768 proposes a game machine in which LEDs are arranged in a dot matrix to form a display unit.

In order to perform light emission control of a light emitting section composed of a plurality of light emitters, such as LEDs arranged in a dot matrix, all light emission patterns are stored in a ROM or the like, and the light emission patterns are updated as appropriate. . For this reason, it is necessary to prepare a large number of light emission patterns according to the contents of the presentation, and confirmation and change of the patterns are a burden on the developer and the confirmation person.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a game machine capable of reducing the burden of confirming and changing the light emission pattern of the light emission unit.

The game machine according to the present invention is
a light-emitting portion (first lamp group 111, seventh lamp group 117, eighth lamp group 118, dot matrix portion 119) configured by a plurality of light-emitting bodies (LEDs);
a control unit (sub CPU 81) for controlling the light emission pattern of the light emitting unit;
pattern data storage means (sub ROM 82) storing a plurality of light emission data and a plurality of parts data for controlling the light emission pattern of the light emitting unit;
The parts data are
identification information for identifying the parts data;
pattern data representing a light emission pattern of the light emitting unit;
attribute data indicating attributes of the parts data,
The light emission data represents the order of identification information of the parts data,
The control unit
determining light emission data from a plurality of light emission data stored in the pattern data storage means, controlling the light emitting unit with pattern data included in the part data according to the order of identification information represented by the determined light emission data;
After controlling the light emitting unit with the pattern data included in the part data corresponding to the last identification information in the light emission data, the attribute data included in the part data corresponding to the last identification information in the light emission data is used for continuous reproduction. part data whose attribute data indicates continuous reproduction from the beginning of the identification information represented by the light emission data, and from the detected parts data to the parts data in accordance with the order of the identification information represented by the light emission data. It has a configuration for controlling the light emitting unit by the included pattern data.

With this configuration, the gaming machine according to the present invention allows the light-emitting unit to perform various effects by combining the parts data, so that the light-emitting pattern of the light-emitting unit can be confirmed and changed for each part data. . Thus, the gaming machine according to the present invention can reduce the burden of checking and changing the light emission pattern of the light emission unit.

Further, in the gaming machine according to the present invention, since the part data whose attribute data is set to continuous reproduction causes the light emitting unit to repeatedly execute the effect, even when the effect by the light emitting unit is executed for a long period of time, the light is emitted. It is possible to reduce the burden of checking and changing the light emission pattern of the part.

According to the present invention, it is possible to provide a game machine capable of reducing the burden of checking and changing the light emission pattern of the light emitting unit.

<Summary 15>
In order to solve the same problem as in Summary 14, the gaming machine according to the present invention
a light-emitting portion (first lamp group 111, seventh lamp group 117, eighth lamp group 118, dot matrix portion 119) configured by a plurality of light-emitting bodies (LEDs);
a control unit (sub CPU 81) for controlling the light emission pattern of the light emitting unit; and light emission data storage means (sub ROM 82) storing a plurality of light emission data and a plurality of parts data for controlling the light emission pattern of the light emitting unit. and a gaming machine comprising
The parts data are
identification information for identifying the parts data;
pattern data representing a light emission pattern of the light emitting unit;
attribute data indicating attributes of the parts data,
The light emission data represents the order of identification information of the parts data,
The control unit
determining light emission data from a plurality of light emission data stored in the light emission data storage means, controlling the light emitting unit with pattern data included in the part data according to the order of identification information represented by the determined light emission data;
After controlling the light emitting unit with the pattern data included in the part data corresponding to the last identification information in the light emission data, the attribute data included in the part data corresponding to the last identification information in the light emission data is used for continuous reproduction. part data whose attribute data indicates continuous reproduction from the beginning of the identification information represented by the light emission data, and from the detected parts data to the parts data in accordance with the order of the identification information represented by the light emission data. controlling the light emitting unit with included pattern data;
When the game machine recovers from the error state, the attribute data represents the continuous reproduction from the order of the identification information of the part data represented by the error state data executed when the game machine entered the error state. The light emitting unit is controlled by the pattern data included in the parts data according to the order of the identification information represented by the light emission data from which the identification information of the missing parts data is removed.

With this configuration, the gaming machine according to the present invention allows the light-emitting unit to perform various effects by combining the parts data, so that the light-emitting pattern of the light-emitting unit can be confirmed and changed for each part data. . Thus, the gaming machine according to the present invention can reduce the burden of checking and changing the light emission pattern of the light emission unit.

Further, in the gaming machine according to the present invention, since the part data whose attribute data is set to continuous reproduction causes the light emitting unit to repeatedly execute the effect, even when the effect by the light emitting unit is executed for a long period of time, the light is emitted. It is possible to reduce the burden of checking and changing the light emission pattern of the part.

Further, in the gaming machine according to the present invention, when the game machine recovers from the error state, the part data is transferred to the part data according to the order of the identification information indicated by the new effect data from which the identification information of the part data whose attribute data does not indicate continuous reproduction is removed. Since the light emitting part is controlled by the included pattern data, it is possible to prevent the execution of the performance unsuitable for the game state by reproducing the performance data from the beginning when the error is recovered.

According to the present invention, it is possible to provide a game machine capable of reducing the burden of checking and changing the light emission pattern of the light emitting unit.

<Summary 16>
In order to solve the same problem as in Summary 14, the gaming machine according to the present invention
a light-emitting portion (first lamp group 111, seventh lamp group 117, eighth lamp group 118, dot matrix portion 119) configured by a plurality of light-emitting bodies (LEDs);
light emission driving means (LED driver IC) for driving the light emitting unit;
a control unit (sub CPU 81) for controlling the light emission pattern of the light emitting unit;
A light emission data storage means (sub ROM 82) storing a plurality of light emission data and a plurality of parts data for controlling the light emission pattern of the light emitting unit,
The parts data are
identification information for identifying the parts data;
pattern data representing a light emission pattern of the light emitting unit;
attribute data indicating attributes of the parts data,
The light emission data represents the order of identification information of the parts data,
The control unit
Light emission data is determined from a plurality of light emission data stored in the light emission data storage means, and luminance values of the light emitters included in the pattern data of the parts data are determined according to the order of identification information represented by the determined light emission data. controlling the light emitting unit by converting into a luminance value corresponding to the light emission driving means and transmitting control data based on the converted luminance value to the light emission driving means by serial bus communication;
After controlling the light emitting unit with the pattern data included in the part data corresponding to the last identification information in the light emission data, the attribute data included in the part data corresponding to the last identification information in the light emission data is used for continuous reproduction. part data whose attribute data indicates continuous reproduction from the beginning of the identification information represented by the light emission data, and from the detected parts data to the parts data in accordance with the order of the identification information represented by the light emission data. It has a configuration for controlling the light emitting unit by the included pattern data.

With this configuration, the gaming machine according to the present invention allows the light-emitting unit to perform various effects by combining the parts data, so that the light-emitting pattern of the light-emitting unit can be confirmed and changed for each part data. . Thus, the gaming machine according to the present invention can reduce the burden of checking and changing the light emission pattern of the light emission unit.

Further, in the gaming machine according to the present invention, since the part data whose attribute data is set to continuous reproduction causes the light emitting unit to repeatedly execute the effect, even when the effect by the light emitting unit is executed for a long period of time, the light is emitted. It is possible to reduce the burden of checking and changing the light emission pattern of the part.

Further, the gaming machine according to the present invention converts the luminance value of the light emitter included in the pattern data into a luminance value corresponding to the light emission driving means, and transmits control data based on the converted luminance value to the light emission driving means. Since the light emitting section is controlled, the light emitting section can be controlled by pattern data that does not depend on the specifications of the light emission driving means.

According to the present invention, it is possible to provide a game machine capable of reducing the burden of checking and changing the light emission pattern of the light emitting section.

1 Pachislot (game machine)
81 sub CPU (control unit, arithmetic processing means, date and time acquisition means, count means, elapsed time calculation means, date and time data update means)
82 sub-ROM (pattern data storage means, monthly day table storage means, first storage means, effect data storage means)
83 sub-RAM 83 (calculation storage means, second storage means)
84 Oscillation circuit (clock generating means)
86 RTC (timekeeping means)
111 First lamp group (light emitting part, second light emitter group)
117 7th lamp group (light emitting part, 2nd light emitter group)
118 Eighth lamp group (light-emitting part, second light-emitting body group)
119 dot matrix section (light emitting section, first light emitter group)
121a to 121b, 127a to 127d, 128a to 128c, 129a to 129g driver IC (light emission driving means)

Claims (2)

Production control means for controlling game production,
A light emitting means for emitting light under the control of the production control means;
and a light emission driving means for driving and controlling the light emitting means,
The production control means is
Arithmetic processing means for performing arithmetic processing;
a first storage means storing a program and data for operating the arithmetic processing means;
a rewritable second storage means having a higher access speed than the first storage means;
The arithmetic processing means has light emission control means for controlling light emission of the light emitting means,
The light emission control means has transfer means for transferring a specific light emission control program among a plurality of light emission control programs related to light emission control stored in the first storage means to the second storage means,
the transfer means transfers the specific light emission control program only once when the initialization process after power-on is completed and the light emission control means is activated;
The specific light emission control program comprises: a process of acquiring lamp data; a process of generating control data based on the acquired lamp data; and a program for executing the
A gaming machine, wherein the light emission control program other than the specific light emission control program is executed while being stored in the first storage means. 2. The game machine according to claim 1, wherein the processing by the specific light emission control program has a relatively higher processing load than the processing by the light emission control programs other than the specific light emission control program.

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