JP2020005948A - Game machine - Google Patents

Abstract

To provide a game machine capable of improving the process speed of arithmetic processing means without increasing costs.SOLUTION: A game machine includes a ROM storing a program and data for operating arithmetic processing means, and a RAM. When a predetermined program (program, LED driver or the like for executing a reproduction data generating process and a lamp control data generating process) out of programs stored in the ROM is executed, a predetermined program is transferred to the RAM, and a predetermined program transferred to the RAM from the host program to a predetermined program is executed.SELECTED DRAWING: Figure 32

Description

  The present invention relates to a gaming machine such as a pachislot machine.

  Conventionally, a plurality of reels having a plurality of symbols arranged on respective surfaces, game medals, coins, and the like (hereinafter, referred to as “game media”) are inserted, and it is detected that a start lever is operated by a player, A start switch for requesting the start of rotation of a plurality of reels and a stop button provided for each of the plurality of reels are detected by a player to be pressed, and a request is made to stop the rotation of the corresponding reel. A stop switch that outputs a signal, a stepping motor that is provided corresponding to each of the plurality of reels, and that transmits a driving force to each of the reels, and a stepping motor based on signals output by the start switch and the stop switch. And a reel control device for controlling the operation of each reel and rotating and stopping each reel, and the start lever is operated when the start lever is operated. When it is detected, the lottery is performed based on the random number value, and the rotation of the reel is stopped based on the result of the lottery (hereinafter referred to as “internal winning combination”) and the timing at which the operation of the stop button is detected. A gaming machine called a pachi-slot is known.

  As this type of gaming machine, Patent Document 1 proposes a gaming machine that causes a CPU to execute a program stored in a ROM. In addition, Japanese Patent Application Laid-Open No. H11-163873 proposes a gaming machine in which a program stored in a ROM is transferred to a RAM by boot processing at the time of startup, and the program transferred to the RAM is executed by a CPU.

JP 2000-296223 A JP 2008-148991 A

  In a conventional gaming machine that causes a processing unit such as a CPU to execute a program stored in a ROM, the processing unit accesses the ROM each time the program is executed. Processing speed was reduced. On the other hand, a conventional gaming machine that causes an arithmetic processing unit such as a CPU to execute a program transferred to a RAM increases the necessary capacity of the RAM, thus increasing costs.

  The present invention has been made to solve such a problem, and an object of the present invention is to provide a gaming machine capable of improving the processing speed of an arithmetic processing unit without increasing costs.

The gaming machine according to the present invention,
Arithmetic processing means (sub CPU 81) for performing arithmetic processing;
First storage means (sub-ROM 82) in which a program and data for operating the arithmetic processing means are stored;
A second storage unit (sub-RAM 83) having a higher access speed than the first storage unit and being rewritable;
The arithmetic processing means,
Executing the predetermined program among the programs stored in the first storage means as an opportunity to transfer the predetermined program to the second storage means;
And executing the predetermined program transferred from the host program corresponding to the predetermined program to the second storage means.

  With this configuration, the gaming machine according to the present invention can execute the predetermined processing by transferring the predetermined program to the second storage means and executing the predetermined program when the relatively high processing load is executed as the predetermined program. The processing speed of the means can be improved.

  Further, the gaming machine according to the present invention executes a program other than the predetermined program in a state stored in the first storage means, thereby suppressing a storage capacity required for the second storage means, thereby reducing costs. be able to.

  Note that, in the gaming machine according to the present invention, when transferring the predetermined program to the second storage means, the arithmetic processing means sets a first argument of the predetermined program stored in the first storage means. The second argument may be a start address of the transfer destination of the second storage means, and the third argument may be a program capacity of a predetermined program stored in the first storage means.

  According to the present invention, it is possible to provide a gaming machine capable of improving the processing speed of the arithmetic processing unit without increasing costs.

It is an explanatory view explaining a functional flow in a game machine of one embodiment of the present invention. It is a perspective view showing an example of appearance composition in a game machine of one embodiment of the present invention. It is a front view in the state where the front panel was removed in the gaming machine of one embodiment of the present invention. It is an LED arrangement port diagram in the game machine of one embodiment of the present invention. 1 is a perspective view showing an internal structure of a gaming machine according to an embodiment of the present invention, with a front door opened. It is a block diagram showing the whole circuit composition provided in the game machine of one embodiment of the present invention. It is a block diagram showing the internal configuration of the sub-control circuit in the gaming machine of one embodiment of the present invention. It is a figure showing the data structure of control data of the 1st mode in the gaming machine of one embodiment of the present invention. It is a figure showing the data structure of the control data of the 2nd mode in the game machine of one embodiment of the present invention. It is a figure showing the data structure of the control data of the 3rd mode in the game machine of one embodiment of the present invention. It is a figure showing an example of the symbol arrangement table in the gaming machine of one embodiment of the present invention. It is a figure showing a monthly table in a game machine of one embodiment of the present invention. It is a figure showing the date storage area in the gaming machine of one embodiment of the present invention. It is a figure showing the reproduction state management storage area in the game machine of one embodiment of the present invention. It is a figure showing the example of the reproduction state management storage area where the ramp data was stored in the game machine of one embodiment of the present invention. It is a figure showing an example of reproduction of ramp data in a game machine of one embodiment of the present invention. It is a figure showing the example of the reproduction state management storage area where the lamp data for interruption return was stored in the game machine of one embodiment of the present invention. It is a figure showing an example of reproduction of lamp data for interruption return in a game machine of one embodiment of the present invention. It is a flowchart which shows the power-on process of the main control circuit in the game machine of one Embodiment of this invention. It is a flow chart which shows the interruption processing of the main CPU in the game machine of one embodiment of the present invention. It is a flowchart which shows the power-on process of the sub control circuit in the gaming machine of one Embodiment of this invention. 9 is a flowchart illustrating a main board communication task performed by a sub CPU according to an embodiment of the present invention. It is a flowchart which shows the effect registration task performed by the sub CPU in one Embodiment of this invention. It is a flow chart which shows production contents decision processing in one embodiment of the present invention. 5 is a flowchart illustrating an example of a no-operation command reception process according to an embodiment of the present invention. It is a flowchart which shows the date and time update process in one Embodiment of this invention. 9 is a flowchart illustrating a sound control task performed by a sub CPU according to an embodiment of the present invention. 9 is a flowchart illustrating a sound function RAM transfer process according to an embodiment of the present invention. FIG. 3 is a schematic diagram illustrating a specific example of a sound control task and a sound function RAM transfer process according to an embodiment of the present invention in source code. 6 is a flowchart illustrating a lamp control task performed by a sub CPU according to an embodiment of the present invention. 5 is a flowchart illustrating a lamp data reading process according to an embodiment of the present invention. 6 is a flowchart illustrating a ramp function RAM transfer process according to an embodiment of the present invention. FIG. 5 is a schematic diagram illustrating a specific example of a lamp control task, a lamp data reading process, and a ramp function RAM transfer process in a source code according to an embodiment of the present invention. FIG. 7 is a conceptual diagram for describing a method of manufacturing a program to be executed by a sub CPU according to an embodiment of the present invention.

Hereinafter, a pachislot which is a game machine according to an embodiment of the present invention will be described with reference to FIGS.
In the present embodiment, a pachislot having a function of activating a replay time (hereinafter, referred to as “RT”) in a game state in which a winning probability of replay is higher than usual when a specific symbol combination is displayed. explain.

<Function flow>
First, a functional flow of a pachislot will be described with reference to FIG.
In the pachislo of the present embodiment, medals are used as game media for performing a game. As the game medium, coins, game balls, point data for games, tokens, and the like can be applied in addition to medals.

  When a medal is inserted by the player and the start lever is operated, one value (hereinafter, random number value) is extracted from a random number within a predetermined numerical value range (for example, 0 to 65535).

  The internal lottery means performs a lottery based on the extracted random number value and determines an internal winning combination. This internal lottery means is carried out by a main control circuit described later. By determining the internal winning combination, a combination of symbols permitted to be displayed along a winning determination line described later is determined. In addition, the types of symbol combinations include those related to “winning” in which a bonus such as payout of medals, activation of replays, activation of bonuses, etc. are given to a player, and those relating to other so-called “losing”. Is provided.

  Further, when the start lever is operated, rotation of the plurality of reels is performed. Thereafter, when the stop button corresponding to the predetermined reel is pressed by the player, the reel stop control means performs control to stop the rotation of the corresponding reel based on the internal winning combination and the timing at which the stop button is pressed. Do. This reel stop control means is carried out by a main control circuit described later.

  In the pachislot, basically, control for stopping the rotation of the relevant reel is performed within a specified time (190 msec or 75 msec) from when the stop button is pressed. In the present embodiment, the number of symbols that move with the rotation of the reel within the specified time is referred to as “the number of sliding pieces”. If the specified period is 190 msec, the maximum number of sliding pieces is determined to be four symbols, and if the specified period is 75 msec, the maximum number of sliding pieces is determined to be one symbol.

  When the internal winning combination that permits the display of the combination of the symbols related to the winning is determined, the reel stop control unit normally changes the combination of the symbols to the winning determination line within a specified time of 190 msec (for four frames of the symbol). The rotation of the reel is stopped so as to be displayed along as much as possible. In addition, for example, during the operation of a challenge bonus (CB), which is a second type special accessory, and a middle bonus (MB) for continuously operating the CB, the reel stop control means controls one or more reels. The rotation of the reel is stopped so that the combination of the symbols is displayed as much as possible along the winning determination line within the time 75 msec (for one frame of the symbol). Further, the reel stop control means uses various specified times corresponding to the gaming state to rotate the reels so that a combination of symbols whose display is not permitted by the internal winning combination is not displayed along the winning determination line. Stop.

  When the rotations of the plurality of reels are all stopped, the winning determination unit determines whether the combination of the symbols displayed along the winning determination line is related to the winning. This winning determination means is carried by a main control circuit described later. When the prize determining means determines that the prize is related to a prize, a privilege such as a medal payout is given to the player. In the pachislot, the above-described series of flows is performed as one game.

  Also, in the pachislot, various effects are performed in the above-described series of flows using the display of an image performed by the display device, the output of light performed by various lamps, the output of sound performed by a speaker, or a combination thereof. Will be

  When the start lever is operated, an effect random number value (hereinafter, effect random number value) is extracted separately from the random number value used for determining the internal winning combination described above. When the effect random number value is extracted, the effect content determination means randomly determines the effect to be executed this time from among a plurality of types of effect contents associated with the internal winning combination. This effect content determination means is carried by a sub-control circuit described later.

  When the content of the effect is determined, the effect executing means executes the effect corresponding to each opportunity such as when the rotation of the reels is started, when the rotation of each reel is stopped, and when the winning is determined. In this way, in the pachislot, by executing the effect contents associated with the internal winning combination, the player has an opportunity to know or predict the determined internal winning combination (in other words, a combination of symbols to be aimed). Provided to improve the interest of the player.

<Pachislot structure>
Next, the structure of the pachislot according to the present embodiment will be described with reference to FIGS.

[Appearance structure]
FIG. 2 is a perspective view showing an external structure of the pachislot 1. FIG. 3 is a front view of the pachislot 1 according to the present embodiment with the front panel 10 removed.

As shown in FIG. 2, the pachislot 1 includes an exterior body 2. The exterior body 2 includes a cabinet 2a that accommodates reels, circuit boards, and the like, and a front door 2b that is attached to the cabinet 2a so as to be openable and closable.
Handles 7 are provided on both side surfaces of the cabinet 2a (only one side handle 7 is shown in FIG. 2). The handle 7 is a concave portion to which a hand is put when carrying the pachislot 1.

  Inside the cabinet 2a, three reels 3L, 3C, 3R are provided side by side. Hereinafter, the respective reels 3L, 3C, 3R are referred to as a left reel 3L, a middle reel 3C, and a right reel 3R, respectively. Each of the reels 3L, 3C, 3R is for a reel body formed in a cylindrical shape, a translucent sheet material mounted on a peripheral surface of the reel body, and a reel for irradiating light to the sheet material from inside the reel body. A light source. On the surface of the sheet material, a plurality (for example, 21) of symbols are drawn at predetermined intervals along the circumferential direction. Here, a part of the red 7 symbol (not shown) is a translucent portion. Red In addition, the reel body is provided with a reel backlight that irradiates light to the back surface of the sheet material. The reel backlight is turned on and off under the control of a sub-control circuit 42 described later.

The front door 2b includes a door body 9, a front panel 10, and a light emitting display device 11.
The door body 9 is attached to the cabinet 2a using a hinge (not shown) so as to be openable and closable. The hinge is provided at the left end of the door body 9 when the door body 9 is viewed from the front of the pachislot 1.

  As shown in FIG. 2, the light emitting display device 11 is provided on an upper part of the door body 9. The light emitting display device 11 includes a dot matrix portion 119 (see FIG. 3) formed by a plurality of light source portions arranged in a matrix, and a portion facing the dot matrix portion 119 of the front panel 10.

  The dot matrix unit 119 illuminates (flashes) the light source unit at an arbitrary location to illuminate an arbitrary location (a firework pattern in the present embodiment) of the design applied to the front panel 10 from the back. Thus, an effect of emitting light at an arbitrary position of the design applied to the front panel 10 is performed.

  Below the light-emitting display device 11, display windows 4L, 4C, 4R for displaying symbols drawn on the three reels 3L, 3C, 3R are provided. Hereinafter, the display windows 4L, 4C, and 4R are referred to as a left display window 4L, a middle display window 4C, and a right display window 4R, respectively.

  The display windows 4L, 4C, 4R are formed of a transparent member such as an acrylic plate. The display windows 4L, 4C, and 4R are provided at positions overlapping with the arrangement areas of the three reels, as viewed from the front (the player side), and are located closer to the three reels (the player side). Is provided. Therefore, the player can visually recognize the three reels provided behind the display windows 4L, 4C, 4R via the display windows 4L, 4C, 4R.

  In the present embodiment, when the rotation of the corresponding reel provided behind the display windows 4L, 4C, and 4R is stopped, the display windows 4L, 4C, and 4R are consecutively arranged among a plurality of types of symbols drawn on each reel. The size is set to display two symbols. That is, the upper, middle, and lower regions are provided for each reel in the frame of the display windows 4L, 4C, 4R, and one symbol is displayed in each region.

  The front panel 10 is attached to an upper part of the door body 9. The front panel 10 has an upper display unit 101, a reel lighting unit 102, reel side effect display units 103A and 103B, edge effect display units 104A and 104B, and a reel lower display unit 105.

  The upper display unit 101 is disposed above the light emitting display device 11, and the reel lighting unit 102 is disposed between the reels 3L, 3C, 3R and the light emitting display device 11. The reel side effect display units 103A and 103B are arranged on the sides of the reels 3L, 3C and 3R, and the edge effect display units 104A and 104B are arranged on the side of the reel side effect display unit 103. The reel lower display unit 105 is arranged below the reels 3L, 3C, 3R.

  The upper display unit 101, the reel illumination unit 102, the reel side effect display units 103A and 103B, the edge effect display units 104A and 104B, and the reel lower display unit 105 are provided with various lamp groups 111 to 117 provided on the door body 9 and described later. Covering. The upper display units 101, 102, 103A, 103B, 104A, 104B, and 105 emit light by being irradiated with light from various lamp groups 111 to 117.

  For example, the reel side effect display unit 103A is provided with three BET light emitting units arranged vertically. The number of lights of the three BET light-emitting units indicates the number of medals used for one game.

  In the present embodiment, the number of medals used for one game is set to one to three. For example, when the number of medals used for one game is set to “1”, one BET light emitting unit (for example, the BET light emitting unit located at the bottom) is turned on, and the other BET light emitting units (one in the middle) The BET light emitting unit located at the top is turned off.

  As shown in FIG. 2, a pedestal portion 12 is formed at the center of the door body 9. The pedestal portion 12 is provided with various devices (medal slot 13, MAX bet button 14, 1 bet button 15, start lever 16, and stop buttons 17L, 17C, 17R) to be operated by the player.

  The medal insertion slot 13 is provided for receiving a medal dropped by the player into the pachislot 1 from outside. The medals received from the medal insertion slot 13 are used in one game with a preset number (for example, 3) as an upper limit, and a portion exceeding the preset number is deposited in the pachislot 1. (So-called credit function).

  The MAX bet button 14 and the 1-bet button 15 are provided for determining the number of medals stored in the pachislot 1 to be used in one game. Although not shown in FIG. 2, the pedestal portion 12 is provided with a settlement button. The settlement button is provided for drawing out (discharging) medals stored in the pachislot 1 to the outside.

  The start lever 16 is provided for starting rotation of all reels (3L, 3C, 3R). The stop buttons 17L, 17C, 17R are provided in association with the left reel 3L, the middle reel 3C, and the right reel 3R, respectively, and each stop button is provided to stop the rotation of the corresponding reel. Hereinafter, the stop buttons 17L, 17C, and 17R are referred to as a left stop button 17L, a middle stop button 17C, and a right stop button 17R, respectively.

  The pedestal portion 12 is provided with a 7-segment display 6 including a 7-segment LED (Light Emitting Diode). The 7-segment display 6 is used for playing a game, the number of medals to be paid out to the player as a privilege (hereinafter, the number of payouts), the number of medals deposited in the pachislot 1 (hereinafter, the number of credits), and the like. The information such as the number of inserted medals (hereinafter referred to as BET number) is digitally displayed.

  A medal payout port 18, a medal tray 19, speakers 20L and 20R, and the like are provided below the door body 9. The medal payout exit 18 guides medals discharged by driving a medal payout device 33 described later to the outside. The medal receiving tray 19 stores medals discharged from the medal payout exit 18. Further, the speakers 20L and 20R output sound such as sound effects and music corresponding to the effect contents.

  Further, a waist panel display unit 106 is provided on the door body 9. The waist panel display unit 106 is disposed above the speakers 20L and 20R. The waist panel display unit 106 covers a light source unit (port No. 53) described later provided on the door body 9. Then, the waist panel display unit 106 emits light by being irradiated with light from the light source unit (port No. 53).

[Various lamp groups]
FIG. 4 is an LED arrangement port diagram in the pachislot 1.

  As shown in FIG. 4, the door body 9 is provided with a 337 port light source unit. At least one LED as a light emitter is arranged in each light source unit. Note that other light emitters such as organic electroluminescence may be arranged in each light source unit.

  The light source units related to the ports No. 0 to No. 30 form a first lamp group 111. The first lamp group 111 irradiates the upper display unit 101 (see FIG. 3) with light. The light source units related to the ports No. 49 to No. 52 form the second lamp group 112. The second lamp group 112 irradiates light to the reel illumination unit 102 (see FIG. 3).

  The light source units related to the ports No. 66 to No. 70 form the third lamp group 113, and the light source units related to the ports No. 71 to No. 75 form the fourth lamp group 114. The third lamp group 113 irradiates the reel side effect display unit 103A (see FIG. 3) with light, and the fourth lamp group 114 irradiates the reel side effect display unit 103B (see FIG. 3) with light. The light source units related to the ports of No. 68 to No. 70 of the third lamp group 113 face the three BET light emitting units described above, and emit light from the BET light emitting units facing each other by turning on.

  The light source units related to the ports No. 54 to No. 59 form a fifth lamp group 115, and the light source units related to the ports No. 60 to No. 65 form a sixth lamp group 116. The fifth lamp group 115 irradiates the edge effect display unit 104A (see FIG. 3) with light, and the sixth lamp group 116 irradiates the edge effect display unit 104B (see FIG. 3) with light.

  The light source units related to the ports No. 108 to No. 156 form a seventh lamp group 117. The seventh lamp group 117 irradiates light to the reel lower display unit 105 (see FIG. 3). The light source units related to the ports No. 108 to No. 121 of the seventh lamp group 117 display, for example, the stored number of medals deposited inside the pachislot 1.

  The light source units related to the ports No. 122 to No. 142 of the seventh lamp group 117 display, for example, the number of acquired medals during the bonus. The light source units related to the ports No. 143 to No. 156 of the seventh lamp group 117 display, for example, the number of payout medals.

  The light source units related to the ports No. 31 to No. 48 and No. 76 to No. 93 form an eighth lamp group 118. The light source units related to the ports No. 31 to No. 36 of the eighth lamp group 118 function as light sources for reels (reel backlight) of the left reel 3L. The light source units related to the ports Nos. 37 to 42 function as light sources (reel backlights) for the reels of the middle reel 3C, and the light source units related to the ports Nos. 43 to 48 correspond to the right reel. It functions as a 3R reel light source (reel backlight).

  The light source unit related to the port of No. 53 irradiates light to the waist panel display unit 106 (see FIG. 3). The light source unit related to the port of No. 157 irradiates the MAXBET button 14 with light. The left stop button 17L is irradiated with light. The light source unit related to the port of No. 158 emits light to the left stop button 17L. The light source unit related to the port of No. 159 emits light to the middle stop button 17C. The light source unit related to the port of No. 160 emits light to the right stop button 17R.

  The light source units related to the ports No. 161 to No. 337 form a dot matrix unit 119. The dot matrix section 119 functions as a light source of the light emitting display device 11. Each port of the dot matrix section 119 is provided with one LED.

[Internal structure]
Next, the internal structure of the pachislot 1 will be described with reference to FIG. FIG. 5 is a perspective view showing the internal structure of the pachislot 1.

  The cabinet 2a is formed in a substantially rectangular parallelepiped shape in which one surface on the front side is opened. A main board 31 constituting a main control circuit 41 (see FIG. 6), which will be described later, is provided in an upper part of the cabinet 2a. The main control circuit 41 is a circuit for controlling main operations of the game in the pachi-slot 1 and a flow between the operations, such as determination of an internal winning combination, rotation and stop of each reel, determination of presence / absence of winning, and the like. The specific configuration of the main control circuit 41 will be described later.

  Three reels (a left reel 3L, a middle reel 3C, and a right reel 3R) are provided in a central portion in the cabinet 2a. Although not shown in FIG. 5, each reel is connected to a corresponding stepping motor (one of the stepping motors 61L, 61C, and 61R in FIG. 6) through gears having a predetermined reduction ratio. .

  A medal dispensing device 33 (hereinafter, referred to as a hopper 33) is provided in a lower portion of the cabinet 2a, and is capable of accommodating a large amount of medals and discharging the medals one by one. A power supply device 34 for supplying necessary power to each device of the pachislot 1 is provided on one side (left side in the example shown in FIG. 5) of the hopper 33 in the cabinet 2a.

  A sub-board 32 that constitutes a sub-control circuit 42 (see FIGS. 6 and 7), which will be described later, is provided above the front door 2b on the back side (the part opposite to the display screen side). The sub control circuit 42 is a circuit that controls execution of an effect by displaying an image or the like. The specific configuration of the sub control circuit 42 will be described later.

  Further, a selector 35 is provided at a substantially central portion on the back surface side of the front door 2b. The selector 35 is a device for selecting whether or not the material and the shape of the medal inserted from the outside via the medal insertion slot 13 (see FIG. 2) are appropriate. To guide. Although not shown in FIG. 5, a medal sensor 35S (see FIG. 6) for detecting that a proper medal has passed is provided on a path through which the medal passes in the selector 35.

<Configuration of circuit included in pachislot>
Next, a configuration of a circuit included in the pachislo 1 will be described with reference to FIGS.
FIG. 6 is a block diagram of the entire circuit included in the pachislo 1. FIG. 7 is a block diagram showing the internal configuration of the sub control circuit.

  The pachislo 1 includes a main control circuit 41, a sub control circuit 42, and a peripheral device (actuator) electrically connected to these circuits.

[Main control circuit]
The main control circuit 41 is mainly constituted by a microcomputer 50 installed on a circuit board (main board 31). As other components, the main control circuit 41 includes a clock pulse generation circuit 54, a frequency divider 55, a random number generator 56, a sampling circuit 57, a display drive circuit 64, a hopper drive circuit 65, and a payout completion signal circuit. 66.

  The microcomputer 50 includes a main CPU 51, a main ROM (Read Only Memory) 52, and a main RAM (Random Access Memory) 53.

  The main ROM 52 stores a control program for various processes executed by the main CPU 51, a data table such as an internal lottery table, data for transmitting various control commands (commands) to the sub-control circuit 42, and the like. . The main RAM 53 is provided with a storage area for storing various data such as an internal winning combination determined by executing the control program.

  The main CPU 51 is connected to a clock pulse generation circuit 54, a frequency divider 55, a random number generator 56, and a sampling circuit 57. The clock pulse generation circuit 54 and the frequency divider 55 generate a clock pulse. The main CPU 51 executes a control program based on the generated clock pulse. Further, the random number generator 56 generates a random number within a predetermined range (for example, 0 to 65535). Then, the sampling circuit 57 extracts one value from the generated random numbers.

  Various switches, sensors, and the like are connected to the input port of the microcomputer 50. The main CPU 51 receives input signals from various switches and controls the operation of peripheral devices such as the stepping motors 61L, 61C and 61R.

  The stop switch 17S is a specific example of the stop operation detecting means according to the present invention, and indicates that each of the left stop button 17L, the middle stop button 17C, and the right stop button 17R has been pressed by the player (stop operation). ) Is detected. The start switch 16S is a specific example of the start operation detecting means according to the present invention, and detects that the start lever 16 has been operated by the player (start operation). The settlement switch 14S detects that the settlement button has been pressed by the player.

  The medal sensor 35S is a specific example of the insertion operation detecting means according to the present invention, and detects that a medal inserted into the medal insertion slot 13 has passed through the selector 35. The bet switch 12S detects that a bet button (the MAX bet button 14 or the 1-bet button 15) has been pressed by the player.

  The peripheral devices whose operations are controlled by the microcomputer 50 include three stepping motors 61L, 61C, 61R, a 7-segment display 6, and a hopper 33. A drive circuit for controlling the operation of each peripheral device is connected to the output port of the microcomputer 50.

  The motor drive circuit 62 controls the drive of three stepping motors 61L, 61C, 61R provided respectively for the left reel 3L, the middle reel 3C, and the right reel 3R. The reel position detection circuit 63 detects, for each reel, a reel index indicating that the reel has made one rotation by an optical sensor having a sensor light emitting unit and a sensor light receiving unit.

  Each of the three stepping motors 61L, 61C, and 61R has a configuration in which the momentum is proportional to the number of pulse outputs, and the rotation axis can be stopped at a specified angle. The driving force of each stepping motor is transmitted to a corresponding reel via a gear having a predetermined reduction ratio. Each time one pulse is output to each stepping motor, the corresponding reel rotates at a fixed angle. The three reels 3L, 3C, 3R and the three stepping motors 61L, 61C, 61R show one specific example of the variable display means according to the present invention.

  The main CPU 51 detects the reel index of each reel, and then counts the number of times a pulse is output to the corresponding stepping motor, thereby determining the rotation angle of each reel (specifically, the number of reel symbols. Just rotated or not).

  Here, the management of the rotation angle of each reel will be specifically described. The number of pulses output to each stepping motor is counted by a pulse counter (not shown) provided in the main RAM 53. Each time a pulse counter outputs a predetermined number of pulses (for example, 16 times) required for rotation of one symbol, the value of a symbol counter (not shown) provided in the main RAM 53 is set to “1”. Is added. The symbol counter is provided for each reel. The value of the symbol counter is cleared when the reel position detection circuit 63 detects the reel index.

  That is, in the present embodiment, by managing the value of the symbol counter, it is managed how many symbols have been rotated since the reel index was detected. Therefore, the position of each symbol on each reel is detected based on the position where the reel index is detected.

  The display drive circuit 64 controls the operation of the 7-segment display 6. The hopper drive circuit 65 controls the operation of the hopper 33. The payout completion signal circuit 66 manages the medal detection performed by the medal detecting unit 33S provided in the hopper 33, and checks whether or not the number of medals discharged from the hopper 33 to the outside reaches a predetermined number of payouts. Further, the external terminal plate 18S is connected to the main control circuit 41. The main control circuit 41 is connected to the hall computer or the calling device 100 via the external terminal board 18S.

[Sub-control circuit]
As shown in FIG. 7, the sub-control circuit 42 is electrically connected to the main control circuit 41 and performs processing such as determination and execution of effect contents based on a command transmitted from the main control circuit 41. The sub control circuit 42 includes a sub CPU 81, a sub ROM 82, a sub RAM 83 (operation storage means), an oscillation circuit 84, a backup RAM 85, an RTC (Real-Time Clock) 86, a battery 87, and a sound IC 88.

  The sub CPU 81 performs sound and light output control in accordance with a control program stored in the sub ROM 82 in response to a command transmitted from the main control circuit 41. The sub CPU 81 forms a control unit and an arithmetic processing unit.

  The sub-ROM 82 is a specific example of a storage unit according to the gaming machine of the present invention, and basically has a program storage area and a data storage area. As described above, the sub-ROM 82 constitutes a first storage unit in which a program and data for operating the sub-CPU 81 are stored.

  Various control programs executed by the sub CPU 81 are stored in the program storage area. The control program stored in the program storage area includes, for example, a main board communication task for controlling communication with the main control circuit 41, the extraction of effect random numbers, determination of effect contents (effect data), and An effect registration task for performing registration, a lamp control task for controlling light output by the dot matrix unit 119 and various lamp groups of the light emitting display device 11 based on the determined effect contents, and sound output by the speakers 20L and 20R. And a program for controlling a sound, such as a sound control task.

  The data storage area includes, for example, a storage area for storing various data tables, a storage area for storing effect data constituting various effect contents, a storage area for storing sound data related to BGM and sound effects, and a pattern for turning on and off light. And various storage areas such as a storage area for storing lamp data related to the lamp data. The lamp data will be described later with reference to FIGS.

  The sub-RAM 83 has a higher access speed than the sub-ROM 82 and constitutes a rewritable second storage unit, and is constituted by, for example, a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory). .

  The sub-RAM 83 has a storage area for registering the determined effect contents and effect data, an effect state storage area for storing various data such as a game state and an internal winning combination transmitted from the main control circuit 41, and the like. The oscillation circuit 84 constitutes a clock generation unit that generates (oscillates) a clock of a predetermined frequency for operating the sub CPU 81, for example, 22 MHz.

  The backup RAM 85 is composed of, for example, an FRAM (Ferroelectric Random Access Memory) (registered trademark) which is a rewritable nonvolatile memory that does not require a power supply. The backup RAM 85 may be configured by connecting a battery 87 for supplying power to the RTC 86 also to the SRAM.

  The backup RAM 85 has a date and time storage area for storing the date and time measured by the RTC 86, a game information area for storing information about the game state of the sub control circuit 42, and information about effects, and a storage area for storing error information history. And a storage area for storing various settings of the pachislot 1 set in the hall menu.

  The game information area of the backup RAM 85 stores the effects of the sub RAM 83 at an arbitrary timing (for example, when the power supply to the sub-control circuit 42 is cut off (when a power cut occurs) or when a start command is received). The state storage area is copied to the game information area of the backup RAM 85, and is copied to the effect state storage area of the sub RAM 83 immediately after the power-on process (see FIG. 19). The pachislot 1 can restart the effect of the game executed before the power is turned on by copying the game information area of the backup RAM 85 to the effect state storage area of the sub RAM 83.

  When the power of the pachislot 1 is turned on, the RTC 86 operates with power supplied from a power supply board (not shown), similarly to the electronic components mounted on the sub-control circuit 42, and operates when the power of the pachislot 1 is turned off. For example, it operates by the electric power supplied from the battery 87, and constitutes a clock unit for clocking the date and time.

  The RTC 86 is connected to the sub CPU 81 by an I2C (Inter-Integrated Circuit), and transmits date and time data indicating the date and time measured in response to a request from the sub CPU 81 to the sub CPU 81. The battery 87 is configured by a primary battery such as a coin-type lithium battery, or a lithium ion secondary battery.

  The speakers 20L and 20R are connected to the sound IC 88. The sound IC 88 outputs audio signals such as BGM from the speakers 20L and 20R according to the sound data transmitted from the sub CPU 81.

  The sub-control circuit 42 includes driver ICs 128a to 128c for driving the eighth lamp group 118, driver ICs 121a to 121b for driving the first lamp group 111, and a driver IC 127a for driving the seventh lamp group 117. To 127d, and driver ICs 129a to 129g for driving the dot matrix section 119.

  These driver ICs and the sub CPU 81 are connected by serial bus communication. The sub CPU 81 includes two communication circuits (not shown) for serial bus communication. The channel 0 is connected to the driver ICs 128a to 128c, the driver ICs 121a to 121b and the driver ICs 127a to 127d, and the channel 1 is connected to the driver ICs 129a to 129a. 129 g are connected.

  In the present embodiment, the first lamp group 111, the seventh lamp group 117, the eighth lamp group 118, and the dot matrix unit 119 constitute a light emitting unit. The driver ICs 128a to 128c, the driver ICs 121a to 121b, the driver ICs 127a to 127d, and the driver ICs 129a to 129g (hereinafter, also simply referred to as “driver ICs”) constitute light emission driving means.

  In the present embodiment, each driver IC has 24 output terminals. Therefore, each driver IC can drive 24 systems of LEDs from channel 0 to channel 23.

  Each driver IC has an output setting terminal. Each driver IC sets the output of the output terminal to one of a constant current output and a sink output in accordance with the state of the output setting terminal (High / Low). Therefore, the output terminal of each driver IC can be set to one of the constant current output and the sink output according to the connection state of the LED.

  Each driver IC has a built-in 6-bit register corresponding to each channel, and outputs a drive signal having a duty ratio according to the value set in the register at a cycle of 63 μs to each channel.

  For example, when the value of the register is 63, a driving signal having a duty ratio of 100% (that is, a pulse width of 63 μs) is output from the driver IC to the corresponding channel, and the LED of the corresponding channel emits light with the highest luminance.

  On the other hand, when the value of the register is 0, a drive signal having a duty ratio of 0% (that is, a pulse width of 0) is output from the driver IC to the corresponding channel, and the LED of the corresponding channel is turned off.

  In the present embodiment, the sub CPU 81 and each driver IC perform communication by a serial bus communication method. Serial bus communication is performed by synchronous serial communication using two data lines / clock lines or three data lines / clock lines / select lines. Each lamp group 111, 117, 118 and dot are provided to each driver IC. Control data for controlling the light emission mode of the LEDs of the matrix unit 119 is transmitted.

  The sub CPU 81 has a plurality of output ports for outputting control data, and can transmit control data from each output port to a plurality of driver ICs. In the present embodiment, the sub CPU 81 has a first port and a second port for outputting control data. Driver ICs 128a to 128c, driver ICs 121a to 121b, and driver ICs 127a to 127d are connected to the first port. Driver ICs 129a to 129g are connected to the second port.

  Each driver IC has a plurality of address terminals, and a unique address is assigned in the output port of the sub CPU 81 according to the level (High / Low) of each address terminal.

  As described with reference to FIGS. 8 to 10, the control data transmitted from each output port of the sub CPU 81 includes a first mode for setting the luminance of the LEDs of all the channels in each driver IC, and a channel for the specified channel. , And a third mode including a command to turn off the LEDs of all channels.

  8 to 10, the first row indicates the bit order in the control data, the second row indicates the type of each parameter included in the control data, and the third row indicates the error detection data described later. E is represented.

  The error detection data E is inserted at a predetermined position in the control data regardless of the position of each parameter in the control data. For this reason, in FIGS. 8 to 10, the type of each parameter included in the control data and the error detection data E are shown in two lines. That is, in FIGS. 8 to 10, each bit indicated by “E” in the third row corresponds to error detection data E, and each bit indicated by “E” in the third row is: This corresponds to the parameter shown in the second line.

  8 to 10, the fourth line represents control data actually transmitted from each output port of the sub CPU 81. In the control data shown in the fourth row, “*” represents a value (“0” or “1”) set according to the control data.

(1st mode)
As shown in FIG. 8, the control data in the first mode includes, as a header, a head detection bit HD, a device identifier DEV, an address ADR, a mode MD, and error detection data E ( For example, a fixed value “0”) is included.

  Specifically, the header of the control data in the first mode has 22 bits. The head detection bit HD is allocated to 9 bits from the first bit to the ninth bit. The head detection bit HD is a fixed value as shown.

  The device identifier DEV is allocated to 4 bits from the 11th bit to the 14th bit. The device identifier DEV indicates the type of each driver IC. Therefore, the same value is used for the same type of driver IC.

  The address ADR is allocated to 5 bits from the 15th bit to the 18th bit and the 20th bit. The address ADR indicates an address for identifying the driver IC. That is, the address ADR indicates the address set in the address terminal of the driver IC to which the control data is transmitted.

  Specifically, each of the driver ICs 128a to 128c has five terminals (not shown) for setting an address. When each of the five terminals is connected to a + 5V power supply side (PullUp) or a ground side (PullDown), the driver IC The address for identifying is set.

  The mode MD is assigned to one bit of the 21st bit. The mode MD indicates whether the control data is the first mode or the second mode. In the present embodiment, the mode MD is set to “0” in the case of the first mode, and is set to “1” in the case of the second mode.

  The error detection data E is assigned to each bit of the 10th, 19th, and 22nd bits. In the present embodiment, the error detection data E is a fixed value, for example, “0”. The error detection data E may be a value based on a predetermined rule (for example, a cyclic value of a predetermined cycle) or a parity bit, other than the fixed value.

  The control data in the first mode includes, as payload, luminance data L of channels 0 to 23 (the suffix of L represents a channel number in the figure), error detection data E, and end bit END. Including.

  Each of the luminance data L0 to L23 of channel 0 to channel 23 is allocated in 6-bit units from the beginning of the payload. The error detection data E is the same as the error detection data E in the header, and is inserted at a 9-bit cycle from the ninth bit of the payload. The end bit END indicates the last bit of the control data. In the present embodiment, the end bit END is a fixed value, for example, “0”.

  As described above, the payload of the control data in the first mode is not affected by the data pattern of the luminance data L by not synchronizing the cycle of the error detection data E with the cycle of the luminance data L. It is defined that an abnormality can be detected on the control data receiving side.

  The driver IC that has received the control data in the first mode corresponds to channels 0 to 23 if the assigned address is equal to the address ADR of the control data and the device identifier DEV registered in advance is equal to the device identifier DEV. The register value is updated to the luminance data L0 to L23.

(2nd mode)
As shown in FIG. 9, the header of the control data in the second mode is the same as the header of the control data in the first mode, and a description thereof will be omitted.

  The control data in the second mode includes, as payloads, the number of channels CHN, the channel number CH (in the figure, the suffix of CH is sequentially assigned from a), and the luminance data L (the suffix of L in the figure). Are sequentially added from a), error detection data E, and end bit END.

  The number of channels CHN is allocated to 5 bits from the beginning of the payload. The channel number CHN indicates the number of channels to be updated. That is, the channel number CHN indicates the number of subsequent pairs of the channel number CH and the luminance data L.

  The channel number CH is represented by 5 bits and represents the number of any one of channels 0 to 23. Each of the luminance data La to Lg is represented by 6 bits following the channel number CH.

  The error detection data E is the same as the error detection data E in the control data in the first mode, and is inserted in a 9-bit cycle from the ninth bit of the payload. The end bit END is the same as the end bit END in the control data of the first mode.

  As described above, the payload of the control data in the second mode does not synchronize the cycle of the error detection data E with the cycle of the luminance data L, so that the payload of the serial bus communication is not affected by the data pattern of the luminance data L. It is defined that an abnormality can be detected on the control data receiving side.

  The driver IC that has received the control data of the second mode, if the assigned address is equal to the address ADR of the control data and the device identifier DEV is equal to the device identifier registered in advance, the register corresponding to each channel number CH Is updated to each luminance data L.

(3rd mode)
As shown in FIG. 10, the control data in the third mode includes a head detection bit HD, a reset command RST, error detection data E, and an end bit END.

  The head detection bit HD is the same as the head detection bit HD in the header of the control data in the first mode, and is assigned to 9 bits from the first bit to the ninth bit. The reset command RST is allocated to 8 bits from the 11th bit to the 18th bit. In the present embodiment, the reset command RST is a fixed value as illustrated.

  The error detection data E is the same as the head detection bit HD in the header of the control data in the first mode, and is assigned to one bit of the tenth bit. The end bit END is the same as the end bit END in the control data of the first mode. The driver IC that has received the control data in the third mode updates the values of the registers corresponding to all the channels to 0.

  As described above, when the channels are individually controlled, by transmitting the control data in the second mode, the data length of the control data can be reduced as compared with the first mode. On the other hand, when controlling the channel as a whole, by transmitting the control data in the first mode that does not require a channel number, the data length of the control data can be made shorter than in the second mode.

  Further, when the LEDs of all the channels are turned off, by transmitting the control data in the third mode, the data length of the control data can be reduced as compared with the first mode and the second mode.

  As described above, the transmission load between the sub CPU 81 and the driver IC can be reduced by selecting the mode in which the data length of the control data is shortened according to the use of the light emitter driven by the driver IC. , The response of the LED can be improved.

  In the present embodiment, the LEDs constituting the dot matrix section 119 constitute a first light emitter group, and the LEDs constituting each of the first lamp group 111, the seventh lamp group 117, and the eighth lamp group 118 are the second lamp groups. A luminous body group is constituted.

  The sub CPU 81 transmits control data in the second mode from the second port to the driver IC that drives the LEDs of the first light emitter group. The sub CPU 81 transmits control data in a first mode from a first port to a driver IC that drives the LEDs of the second light emitting body group. The sub CPU 81 transmits control data from the corresponding port in the third mode when all LEDs are turned off, such as when power is turned on or when effects are switched.

  Note that the second lamp group 112, the third lamp group 113, the fourth lamp group 114, the fifth lamp group 115, the sixth lamp group 116, and the light source units related to the other ports according to the present embodiment are not provided. It is controlled by the sub CPU 81 via the driver IC shown in the figure.

<Configuration of Data Table Stored in Main ROM>
Next, the configuration of various data tables stored in the main ROM 52 will be described.

[Symbol layout table]
First, the symbol arrangement table will be described with reference to FIG. The symbol arrangement table defines the correspondence between the position of each symbol in the rotation direction of each of the left reel 3L, the center reel 3C, and the right reel 3R, and data specifying the type of the symbol arranged at each position.

  In the symbol arrangement table, when the reel index is detected, the position of the symbol of each reel arranged in the middle area in the frame of the display windows 4L, 4C, 4R is defined as “0”. Then, in each reel, "0" to "20" corresponding to the symbol counter are assigned to each symbol as the symbol position in the order of progressing in the reel rotation direction (downward direction in FIG. 11) based on the symbol position "0". Assigned.

  That is, by referring to the symbol counter value ("0" to "20") and the symbol arrangement table, the reels are displayed in the upper, middle, and lower regions of each reel within the frames of the display windows 4L, 4C, and 4R. It is possible to specify the type of the symbol being displayed. For example, when the value of the symbol counter corresponding to the left reel 3L is “7”, the upper, middle, and lower tiers of the left reel 3L within the frame of the display window 4 have the symbol position “8” at the symbol position “8”, respectively. A symbol corresponding to "Don 1", "Bell 2" at symbol position "7", and "Replay" at symbol position "6" is displayed.

<Data table stored in sub-ROM>
[Monthly table]
As shown in FIG. 12, in the monthly day table, the number of days in a leap year and the number of days in a non-leap year are associated with each month. The monthly date table is referred to by the sub CPU 81 that executes a date and time update process (see FIG. 26) described later. As described above, the sub ROM 82 that stores the monthly day table constitutes a monthly day table storage unit.

<Storage area allocated to sub RAM>
[Date and time storage area]
As shown in FIG. 13, the date and time storage area includes sub RAM 83 for storing “year”, “month”, “day”, “day of the week”, “hour”, “minute”, and “second”, respectively. Assigned to. That is, date and time data is stored in the date and time storage area.

  In the following description, the values of the respective areas constituting the date / time storage area will be referred to as date / time storage area (year), date / time storage area (month), date / time storage area (day), date / time storage area (day of the week), date / time storage area (hour). , Date and time storage area (minutes), and date and time storage area (seconds). The date and time storage area is used by the sub CPU 81 that executes a date and time update process (see FIG. 26) described later.

<Lamp data>
In the present embodiment, the sub ROM 82 stores lamp data (also referred to as “light emission data”), which is effect data relating to a pattern of turning off (including increasing and decreasing) light, and a plurality of parts data. Thus, the sub ROM 82 constitutes a light emission data storage unit and a pattern data storage unit.

  Each part data includes identification information for identifying the part data, attribute data indicating the attribute of the part data, and pattern data indicating a light spot (including increase / decrease) light-off pattern. Each lamp data represents the order of the identification information of the parts data.

  The pattern data is composed of a plurality of luminance patterns ordered in the order of reproduction. Each luminance pattern represents the luminance set for each channel of each driver IC to be controlled. In each luminance pattern, the luminance set for the channel of the driver IC is represented by 8 bits in consideration of the versatility of the pattern data.

  Note that the luminance set for the channel of the driver IC may be represented by 16 bits, 32 bits, or 64 bits as long as the versatility of the pattern data is ensured. The last luminance pattern in the pattern data represents an end block.

  The attribute data of the part data includes a shot, a shot + chain, and a loop. The part data whose attribute data is shot is reproduced only once in one lamp data.

  Shot + chain represents continuous playback. Part data whose attribute data is shot + chain is continuously reproduced in one lamp data. Therefore, in the case where one piece of lamp data has continuous shot + chain attribute data, a series of shot + chain attribute data is repeatedly reproduced.

  In other words, after the part data corresponding to the last identification information in the lamp data is reproduced, if the attribute data included in the part data corresponding to the last identification information in the lamp data indicates shot + chain, the lamp data is Part data whose attribute data indicates shot + chain is searched from the head of the identification information to be displayed, and continuous reproduction is started from the detected part data.

  A loop represents repeated playback. Part data whose attribute data is a loop is repeatedly reproduced in one lamp data. In other words, when the attribute data includes the identification information of the part data of the loop, the part data is repeatedly reproduced.

  A specific example of the lamp data according to the present embodiment will be described. The lamp data corresponding to the effect to be executed is selected by the sub CPU 81 and read into the reproduction state management storage area of the sub RAM 83 shown in FIG.

  In FIG. 14, an entry part number storage area for storing a part number for identifying the part data being reproduced and a part number as identification information for identifying the part data are stored in the reproduction state management storage area. The part number storage area, the end code storage area for storing the end code representing the end of the lamp data, and the part data of the identification information represented by the lamp data include part data whose attribute data is shot + chain or loop. And a chain / loop setting area that indicates whether or not there is any data. The number of part number storage areas included in the reproduction state management storage area is equal to the number of part data represented by the lamp data.

  FIG. 15 shows a specific example of the playback state management storage area. In the example shown in FIG. 15, "1" (a number assigned with an intro) is stored as an entry part number in the entry part number storage area, and "1" to "8" is stored as a part number in the part number storage area. Is stored in the end code storage area, and “TRUE” is stored in the chain / loop setting area.

  If the attribute data represented by the lamp data does not include part data whose attribute data is shot + chain or loop, “FALSE” is stored in the chain / loop setting area. . When “FALSE” is stored in the chain / loop setting area, the part data is not repeatedly reproduced without searching for the attribute data. (One-time playback)

  FIG. 16 shows an example of lamp data reproduction based on the reproduction state management storage area shown in FIG. In the part data having the part number “1”, a shot is set in the attribute data, and a luminance pattern representing an intro effect for, for example, 30 seconds is set in the pattern data.

  In each of the part data having the part numbers “2” to “8”, a shot + chain is set in the attribute data, and a luminance pattern representing a continuous effect for, for example, 30 seconds is set in the pattern data. In the illustrated example, the reproduction time of all the part data having the part numbers “1” to “8” is 30 seconds, but the lengths of the part data may be different from each other.

  As shown by the arrow in the figure, when the reproduction of the lamp data is started, the part data with the part number "1" is reproduced for 30 seconds, and then the parts with the part numbers "2" to "8" The data is played over 30 seconds. At this time, the update of the part number from “1” to “2” is managed by updating the value of the entry part number storage area of the playback state management storage area from “1” to “2”. You.

  When the end code is detected based on the value of the entry part number storage area, the attribute data of the part data with the last reproduced part number “8” is shot + chain, so the part which is the head of the lamp data Part data whose attribute data is shot + chain is searched from the part data with the number “1”.

  In the illustrated example, the part data with the part number “2” is detected. Therefore, "2" is set in the entry part number storage area, and as shown by the arrow in the drawing, a series of part data of part numbers "2" to "8" is changed from the part data of part number "2". Plays continuously. Thereafter, unless the lamp data is updated, a series of part data having the part numbers “2” to “8” is repeatedly reproduced.

  If an error of the pachislot 1 is detected during the reproduction of the lamp data, the sub CPU 81 reproduces the error lamp data. Therefore, the reproduction of the lamp data being reproduced at the time of detecting the error is interrupted. At the time of error recovery, the sub CPU 81 reproduces the lamp data that was being reproduced when the error was detected.

  At this time, if the interrupted lamp data is reproduced from the beginning, the effect contents may not match the gaming state. For this reason, the sub-ROM 82 stores the interruption return lamp data corresponding to the lamp data. The interruption return lamp data is obtained by removing the part number of the part data whose attribute data does not represent the shot + chain from the normal lamp data.

  FIG. 17 shows a reproduction state management storage area in which lamp data for suspension return is stored. In the reproduction state management storage area shown in FIG. 17, “2” is stored in the reproduction state management storage area, and the attribute data is shot + chained with respect to the lamp data stored in the reproduction state management storage area shown in FIG. "1" (the number to which the intro is assigned), which is the part number of the part data that does not represent "."

  Therefore, as shown in FIG. 18, the reproduction of the interruption return lamp data is started from the part data whose attribute data indicates the shot + chain and the leading part number is “2”. In this manner, the sub CPU 81 starts reproduction of the interruption return lamp data at the time of error recovery, thereby preventing the effect contents from conforming to the gaming state (reproducing the intro despite the effect of the effect). Preventing.

  Note that the sub CPU 81 uses the playback state management storage area in the attribute search cueing process (to be described later) (step S611 in FIG. 30) to perform cueing for repeated playback. 15 to 18 are also specific examples of the attribute search cueing process.

  Instead of storing the lamp data for interruption return corresponding to the lamp data in the sub ROM 82, the sub CPU 81 converts the lamp data reproduced at the time of error detection into the lamp data for interruption recovery at the time of error recovery. It may be.

  Specifically, the sub CPU 81 converts the lamp data stored in the reproduction state management storage area into the lamp data for interruption recovery by removing the part number of the part data whose attribute data does not represent the shot + chain. You may make it.

<Description of operation of main control circuit>
Next, with reference to FIG. 19, the contents of various processes executed by the main CPU 51 of the main control circuit 41 using a program will be described.

[Power on process]
First, a power-on process of the main control circuit 41 of the pachislo 1 performed under the control of the main CPU 51 will be described with reference to FIG.

  First, when the power is turned on to the pachislot 1, the main CPU 51 performs an initialization process at the time of turning on the power (S1). In this initialization process, it is determined whether the backup has been performed normally, the setting has been changed appropriately, and the like, and initialization corresponding to the determination result is performed.

  Next, the main CPU 51 performs an initialization process at the end of one game (S2). In this initialization process, the data in the designated storage area in the main RAM 53 is cleared. Note that the designated storage area here is a storage area in which data must be deleted for each game, such as an internal winning combination storage area and a display combination storage area.

  Next, the main CPU 51 performs a medal acceptance / start check process (S3). In this process, the input of the medal sensor 35S and the start switch 16S is checked.

  Specifically, the main CPU 51 counts the number of inserted coins by automatic insertion when a display combination relating to a replay (replay combination) is established in the previous game, and counts the number of inserted coins by medals inserted from the medal insertion slot 13. And counting the number of inserted coins based on the pressing of the BET button (MAX BET, 1 BET), and if the inserted coins have reached the number of startable games, the state of the start switch is determined.

  Next, the main CPU 51 extracts a random number value (0 to 65535) from a first random number register (not shown) of the random number generator 56 and stores the extracted random number value in a random number value storage area (not shown) provided in the main RAM 53. ) (S4). Next, the main CPU 51 extracts an effect random number value used for reel effect and lock control from a second random number register (not shown) of the random number generator 56, and the extracted effect random number value is provided in the main RAM 53. It is stored in an effect random number storage area (not shown) (S5). In the present embodiment, the effect random number value is extracted from the range of 0 to 127.

  Then, when the extracted various random numbers are stored in the predetermined random number storage area, the main CPU 51 performs an internal lottery process (S6). In this process, the internal winning combination is determined by lottery based on the random number value extracted in S4.

  Next, the main CPU 51 performs a game lock lottery process (S7). In the game lock lottery process, the main CPU 51 refers to a game lock lottery table (not shown) according to the game state and performs the game lock lottery based on the random number value for effect.

  Next, the main CPU 51 performs a reel stop initialization process (S8). In the reel stop initial setting process, the main CPU 51 acquires various information related to the rule stop control from a reel stop initial setting table (not shown) based on the internal winning combination.

  Next, the main CPU 51 performs a start command transmission process (S9). Specifically, the main CPU 51 transmits a start command to the sub control circuit 42. The start command includes a parameter for specifying an internal winning combination and the like, a game lock type, a lock time, and the like.

  Next, the main CPU 51 performs a wait process (S10). In this process, if a predetermined time (for example, 4.1 seconds) has not elapsed since the previous game started, the main CPU 51 exhausts the waiting time until the predetermined time elapses.

  Next, the main CPU 51 performs a reel rotation start process (S11). In this process, the main CPU 51 requests the start of rotation of all reels. In the reel rotation start processing, the main CPU 51 requests the start of rotation of all reels. When the start of rotation of all reels is requested, the driving of the three stepping motors 61L, 61C, 61R is controlled by an interrupt process (see FIG. 20) described later, which is executed at a constant cycle (1.1172 msec). The rotation of the left reel 3L, the center reel 3C, and the right reel 3R is started.

  Next, the main CPU 51 performs a pull-in priority storing process (S12). In this process, the main CPU 51 acquires the attraction priority data and stores it in the attraction priority data storage area (not shown).

  Next, the main CPU 51 performs a reel stop control process (S13). In this processing, the rotation of the corresponding reel is stopped based on the timing at which the left stop button 17L, the middle stop button 17C, and the right stop button 17R are pressed, and the internal winning combination. That is, in the present embodiment, the main control circuit 41 that executes the reel stop control processing constitutes stop control means.

  Next, the main CPU 51 performs a game lock process (S14). In this process, the main CPU 51 invalidates or delays the progress of the game. The main CPU 51 sets a value corresponding to a period for executing the determined game lock type in the lock timer, and waits until the value of the lock timer becomes “0”. During that time, the main CPU 51 does not accept any operation of the player.

  Next, the main CPU 51 performs a winning search process (S15). In this process, the main CPU 51 stores the data in the symbol code storage area (not shown) in the display combination storage area (not shown). In this process, the combination of symbols displayed on the activated line (winning determination line) after all of the left reel 3L, the middle reel 3C, and the right reel 3R are stopped is compared with a symbol combination table (not shown). Then, the main CPU 51 may determine whether or not the display combination is displayed on the activated line, and store the determination result in the display combination storage area.

  Next, the main CPU 51 performs a medal payout process (S16). The medal payout process is a specific example of the game medium providing means according to the present invention. In this process, the hopper 33 is driven and the number of credits is updated based on the number of payouts of the display combination determined in S15, and the medals are paid out. At this time, in the present embodiment, as shown in a symbol combination table (not shown), the number of inserted medals is 1 to 3, and the number of paid out medals varies depending on the display combination. The payout upper limit is 15 cards.

  Next, the main CPU 51 performs an RT control process (S17). In this process, the main CPU 51 manages the RT gaming state. The main CPU 51 refers to an RT transition table (not shown) to check a transition condition of the RT game state that can be satisfied in the transfer source (current) RT game state, and determines that the transition condition of the RT game state is satisfied. When it is determined, a transition is made to the transition destination RT gaming state based on the transition condition with reference to an RT transition table (not shown).

  Next, the main CPU 51 performs a payout end command transmission process (S18). Specifically, the main CPU 51 transmits a payout end command to the sub control circuit 42.

  Next, the main CPU 51 performs a bonus end check process (S19). In this processing, the main CPU 51 refers to various counters for managing the timing of ending the bonus game, and checks whether or not to end the operation of the bonus game.

  Next, the main CPU 51 performs a bonus operation check process (S20). In this processing, the main CPU 51 checks whether or not to start the operation of the bonus game and whether or not to perform the replay. When the bonus operation check processing is completed, the main CPU 51 returns the processing to S2 and repeats the processing from S2.

[Interrupt processing under control of main CPU (1.1172 msec)]
Next, with reference to FIG. 20, a description will be given of an interrupt process performed at a fixed period (every 1.1172 msec) under the control of a timer (not shown) built in the main CPU 51.

  First, the main CPU 51 saves the register (S351). Next, the main CPU 51 performs an input port check process (S352). In this process, signals input from various switches such as the stop switch 17S are checked.

  Next, the main CPU 51 performs a timer update process (S353). In this process, the main CPU 51 performs, for example, a process of subtracting the value of the lock timer for each interrupt process. Next, the main CPU 51 performs a communication data transmission process (S354). In this processing, various commands are mainly transmitted to the main control circuit 41 and the sub-control circuit 42 as appropriate.

  Next, the main CPU 51 performs a reel control process (S355). In this process, when the start of rotation of all reels is requested, the main CPU 51 starts rotation of the left reel 3L, middle reel 3C, and right reel 3R, and then rotates each reel at a constant speed. The drive of three stepping motors 61L, 61C, 61R is controlled. When the number of sliding pieces is determined, the main CPU 51 updates the symbol counter of the corresponding reel by the number of sliding pieces. Then, the main CPU 51 waits until the updated symbol counter matches the value corresponding to the expected stop position (the symbol at the expected stop position reaches an area on the active line (winning determination line) of the display window). The drive of the corresponding stepping motor is controlled so that the rotation of the corresponding reel is decelerated and stopped. Further, in the present embodiment, in the processing of S355, in addition to the normal acceleration processing, the constant speed processing, and the stop processing described above, when a reel effect pattern is set at the time of the acceleration processing, the processing corresponds to the reel effect pattern. A reel effect (reel action) and lock control processing are also performed.

  Next, the main CPU 51 performs a lamp / 7-seg driving process (S356). In this process, the main CPU 51 controls the drive of the 7-segment display 6 to display the number of payouts, the number of credits, and the like. Next, the main CPU 51 performs a register return process (S357). Then, after that, the main CPU 51 ends the interrupt processing.

<Description of operation of sub-control circuit>
Next, contents of various processes (tasks) executed by the sub CPU 81 of the sub control circuit 42 using a program will be described with reference to FIGS.

[Power on process]
FIG. 21 is a flowchart showing a power-on process of the sub-control circuit 42 executed when the power is turned on.

  First, the sub CPU 81 executes an initialization process (S361). In the initialization processing, the sub CPU 81 initializes various drivers in addition to the error check of the sub RAM 83 and the like.

  The tasks initialized in S361 include a main board communication task (see FIG. 22) which is a task group for command reception interrupt synchronization, a sound control task (see FIG. 27) which is a task group for timer interrupt synchronization, and a lamp. It includes a control task (see FIG. 30) and the like.

  Next, the sub CPU 81 activates a lamp control task (S362). In the lamp control task, the sub CPU 81 waits for reception of a timer interrupt event message transmitted every 2 ms, and turns on various lamps such as the LED group 21 in response to the reception of the timer interrupt event message. Control the state. As described above, the sub CPU 81 that executes the lamp control task constitutes a control unit.

  Next, the sub CPU 81 activates a sound control task (S363). In the sound control task, the sub CPU 81 controls the sound output state of various speakers such as the speakers 20L and 20R, similarly to the lamp control task.

  Next, the sub CPU 81 activates the main board communication task (S364). In the main board communication task, the sub CPU 81 determines (lottery) an effect based on reception and analysis of the command transmitted from the main control circuit 41 and the analyzed command.

  Next, the sub CPU 81 acquires date and time data from the RTC 86 and stores it in the date and time storage area (see FIG. 13) allocated to the sub RAM 83 (S365). Thus, the sub CPU 81 constitutes a date and time obtaining unit.

  Next, the sub CPU 81 acquires a count value from a clock counter (not shown) provided in the sub CPU 81 and stores it as a clock count P in the sub RAM 83 (S366). After executing the processing of S366, the sub CPU 81 ends the power-on processing. Note that the clock counter is a counter circuit built in the sub CPU 81 that counts a clock of a predetermined frequency oscillated by the oscillation circuit 84 (see FIG. 7). The sub CPU 81 including the clock counter that counts the clock of the oscillation circuit 84 , And constitutes counting means.

[Main board communication task]
Next, a main board communication task performed by the sub CPU 81 will be described with reference to FIG.

  First, the sub CPU 81 checks the reception of the command transmitted from the main control circuit 41 (S501). Next, the sub CPU 81 determines whether the received command is valid based on the result of the reception check (S502).

  For example, the sub CPU 81 determines that the first condition that the data length of the received command is 8 bytes, the received command is a start command, a reel stop command, a display command, a payout end command, a bonus start command, a bonus end command, and a no operation command For example, when three conditions, that is, a second condition that is a command registered in advance and a third condition in which the sum value stored in the 8th byte of the received command is correct, the received condition is received as a check result. It is reflected that the command is valid, and if any of the conditions is not satisfied, the result of the reception check is reflected that the received command is not valid.

  When the sub CPU 81 determines in S502 that the received command is not valid (NO in S502), the sub CPU 81 returns the processing to S501 and repeats the processing from S501.

  On the other hand, when the sub CPU 81 determines in S502 that the received command is valid (YES in S502), the sub CPU 81 stores a message in a message queue based on the received command (S503). . The message queue is a mechanism for exchanging information between processes. Then, after the processing in S503, the sub CPU 81 returns the processing to S501, and repeats the processing from S501.

[Direction registration task]
Next, the effect registration task performed by the sub CPU 81 will be described with reference to FIG.

  First, the sub CPU 81 extracts a message from the message queue (S511). Next, the sub CPU 81 determines whether or not there is a message in the message queue (S512). In S512, when the sub CPU 81 determines that there is no message in the message queue (when S512 is NO), the sub CPU 81 performs the process of S515 described later.

  On the other hand, in S512, when the sub CPU 81 determines that there is a message in the message queue (when S512 is YES), the sub CPU 81 copies game information from the message (S513). In this process, for example, various data such as an internal winning combination, a type of reel stopped rotating, a display combination, and a game state flag specified by parameters are copied to a storage area (not shown) provided in the sub RAM 83. You.

  Next, the sub CPU 81 performs an effect content determination process (S514). In this processing, the sub CPU 81 determines the contents of the effect, registers the effect data, and the like according to the type of the received command. Note that details of the effect content determination processing will be described later with reference to FIG. 24 described later.

  Next, the sub CPU 81 registers sound data (S515). Next, the sub CPU 81 registers the lamp data (S516). Note that these registration processes are performed based on the effect data registered in the effect content determination process of S514. Also, in the present embodiment, the sub CPU 81 registers the sound data by storing the request number of the sound data in the registration area of the sub RAM 83 only when the request number of the sound data has been determined. Only when the number has been determined, the lamp data is registered by storing the request number of the lamp data in the registration area of the sub RAM 83. After S516, the sub CPU 81 returns the processing to S511, and repeats the processing from S511.

[Direction content decision processing]
Next, with reference to FIG. 24, the effect content determination processing performed in S514 in the effect registration task flowchart (see FIG. 23) will be described.

  First, the sub CPU 81 determines whether or not a start command has been received (S521).

  In S521, when the sub CPU 81 determines that the start command is received (when S521 is YES), the sub CPU 81 performs a start command receiving process (S522). In this process, the sub CPU 81 extracts a random number for effect, determines the effect number by lottery based on the internal winning combination, and registers the effect number. Here, the effect number is data for specifying the effect content to be executed this time.

  Next, the sub CPU 81 registers the effect data at the time of start according to the registered effect number (S523). The effect data is data that specifies animation data, sound data, and lamp data. Therefore, when the effect data is registered, the corresponding animation data and the like are determined, and an effect such as display on the display device is executed. Then, after the process of S523, the sub CPU 81 ends the effect content determination process, and moves the process to S515 of the effect registration task (see FIG. 23).

  On the other hand, when the sub CPU 81 determines in S521 that the start command has not been received (NO in S521), the sub CPU 81 determines whether or not a reel stop command has been received (S524).

  In S524, when the sub CPU 81 determines that the reel stop command has been received (YES in S524), the sub CPU 81 determines whether or not to stop at the time of stop according to the registered effect number and the type of the operation stop button. The effect data is selected (S525). After that, the sub CPU 81 ends the effect content determination processing, and moves the processing to S515 of the effect registration task (see FIG. 23).

  On the other hand, in S524, when the sub CPU 81 determines that it is not the time to receive the reel stop command (if S524 is NO), the sub CPU 81 determines whether it is the time to receive the display command (S526).

  When the sub CPU 81 determines in S526 that the display command is being received (YES in S526), the sub CPU 81 performs a display command receiving process (S527). In this process, the sub CPU 81 determines and registers the effect number by lottery based on the display combination and the like. Here, the effect number is data for specifying the effect content to be executed this time. After that, the sub CPU 81 ends the effect content determination processing, and moves the processing to S515 of the effect registration task (see FIG. 23).

  On the other hand, if it is determined in S526 that the display command has not been received (NO in S526), the sub CPU 81 determines whether or not the payout end command has been received (S528). In S528, when the sub CPU 81 determines that the payout end command has been received (YES in S528), the sub CPU 81 performs a payout end command reception process (S529). After that, the sub CPU 81 ends the effect content determination processing, and moves the processing to S515 of the effect registration task (see FIG. 23).

  On the other hand, in S528, when the sub CPU 81 determines that the payout end command has not been received (NO in S528), the sub CPU 81 determines whether or not the bonus start command has been received (S530).

  In S530, when the sub CPU 81 determines that the bonus start command has been received (YES in S530), the sub CPU 81 registers the effect data for bonus start (S531). After that, the sub CPU 81 ends the effect content determination processing, and moves the processing to S515 of the effect registration task (see FIG. 23).

  On the other hand, in S530, when the sub CPU 81 determines that the bonus start command has not been received (NO in S530), the sub CPU 81 determines whether a bonus end command has been received (S532). When the sub CPU 81 determines in S532 that the bonus end command has been received (YES in S532), the sub CPU 81 registers effect data for ending the bonus (S533). After that, the sub CPU 81 ends the effect content determination processing, and moves the processing to S515 of the effect registration task (see FIG. 23).

  In S532, when the sub CPU 81 determines that it is not the time when the bonus end command is received (S532 is NO), the sub CPU 81 determines whether it is the time when the no operation command is received (S534). In S534, when the sub CPU 81 determines that it is not the time of receiving the no operation command (when S534 is NO), the sub CPU 81 ends the effect content determination process, and executes the process of the effect registration task (see FIG. 23). Move to S515.

  On the other hand, in S534, when the sub CPU 81 determines that the non-operation command has been received (YES in S534), the sub CPU 81 performs a non-operation command reception process (S535). The details of the non-operation command reception process will be described later with reference to FIG. After the processing of S535, the sub CPU 81 ends the effect content determination processing, and moves the processing to S515 of the effect registration task (see FIG. 23).

[Process when receiving no operation command]
Next, with reference to FIG. 25, a description will be given of the non-operation command reception process performed in S535 in the flowchart of the effect content determination process (see FIG. 24).

  In the no-operation command receiving process, the sub CPU 81 executes the date and time updating process shown in FIG. 26 (S540). After executing the processing of S540, the sub CPU 81 ends the non-operation command reception processing.

  The no-operation command is transmitted from the main control circuit 41 at a cycle of about 10 msec. The date and time updating process shown in FIG. 26 is not limited to the no-operation command receiving process, and may be executed from another process or task that is executed periodically.

[Date and time update process]
Next, the date and time update process will be described with reference to FIG.

  First, the sub CPU 81 acquires a count value from the clock counter and stores it in the sub RAM 83 as the clock count C (S541). Next, the sub CPU 81 calculates a clock count D obtained by subtracting the clock count P from the clock count C (S542). Thus, the sub CPU 81 constitutes an elapsed time calculation unit.

  Next, the sub CPU 81 determines whether or not the clock count D is equal to or more than a clock count value corresponding to one second (hereinafter, simply referred to as “one second count”) (S543). In the present embodiment, since the sub CPU 81 operates with a clock of 22 MHz, the one-second count is 22,000,000 (pulse).

  If it is determined in S543 that the clock count D is not equal to or greater than the one-second count (NO), the sub CPU 81 ends the date and time updating process. If it is determined in S543 that the clock count D is equal to or greater than the one-second count (YES), the sub CPU 81 subtracts the one-second count from the clock count D (S544).

  After executing the processing of S544, the sub CPU 81 adds a one-second count to the clock count P (S545). Next, the sub CPU 81 adds 1 to the date and time storage area (second) (S546).

  Next, the sub CPU 81 determines whether or not the date and time storage area (seconds) is 60 or more (S547). If it is determined in S547 that the date and time storage area (seconds) is not 60 or more (NO), the sub CPU 81 executes the processing of S543.

  If it is determined in S547 that the date / time storage area (seconds) is 60 or more (YES), the sub CPU 81 updates the date / time storage area (seconds) to 0 and adds 1 to the date / time storage area (minutes). (S548).

  After executing the processing of S548, the sub CPU 81 determines whether or not the date and time storage area (minutes) is 60 or more (S549). If it is determined in S549 that the date and time storage area (minutes) is not 60 or more (NO), the sub CPU 81 executes the processing of S543.

  If it is determined in S549 that the date / time storage area (minute) is 60 or more (YES), the sub CPU 81 updates the date / time storage area (minute) to 0 and adds 1 to the date / time storage area (hour). (S550).

  After executing the processing of S550, the sub CPU 81 determines whether or not the date and time storage area (hour) is 24 or more (S551). If it is determined in S551 that the date and time storage area (hour) is not 24 or more (NO), the sub CPU 81 executes the processing of S543.

  If it is determined in S551 that the date and time storage area (hour) is 24 or more (YES), the sub CPU 81 updates the date and time storage area (hour) to 0, and updates the date and time storage area (day) and the date and time storage area. One is added to (day of the week) (S552).

  After executing the processing of S552, the sub CPU 81 determines whether the date and time storage area (day of the week) is 7 or more (S553). If it is determined in S553 that the date and time storage area (day of the week) is 7 or more (YES), the sub CPU 81 updates the date and time storage area (day of the week) to 0 (S554).

  In S553, when it is determined that the date and time storage area (day of the week) is not 7 or more (NO), or after executing the processing of S554, the sub CPU 81 determines whether or not the year represented by the date and time storage area (year) is a leap year. Is calculated (S555).

  The leap year is calculated by dividing the year by "4", "100", and "400" and leaving a remainder (for example, 2000) and the year by dividing the year by "4". There is no year and the year in which the Christian era is divided by "100" and has a surplus (for example, 2020) is a leap year.

  Next, the sub CPU 81 specifies the calculation result of S555 and the number of days (hereinafter, also referred to as “month day number”) associated with the date and time storage area (month) using the monthly day table (see FIG. 12). It is determined whether or not the date and time storage area (day) is equal to or greater than the number of months and days (S556).

  If it is determined in S556 that the date and time storage area (day) is not equal to or greater than the number of months and days (NO), the sub CPU 81 executes the processing of S543. In S556, if it is determined that the date and time storage area (day) is equal to or greater than the number of months and days (YES), the sub CPU 81 updates the date and time storage area (day) to 1 and sets 1 to the date and time storage area (month). It is added (S557).

  After executing the processing of S557, the sub CPU 81 determines whether or not the date and time storage area (month) is 12 or more (S558). If it is determined in S558 that the date and time storage area (month) is not 12 or more (NO), the sub CPU 81 executes the processing of S543.

  If it is determined in S558 that the date and time storage area (month) is 12 or more (YES), the sub CPU 81 updates the date and time storage area (month) to 1 and adds 1 to the date and time storage area (year). (S559). After executing the processing of S559, the sub CPU 81 executes the processing of S543.

  In this way, the sub CPU 81 that executes the date and time update processing constitutes an elapsed time calculation unit. The date and time updating process updates the date and time data by adding one second as a specified time to the date and time data stored in the date and time storage area. Therefore, originally, the date and time data is acquired from the RTC 86, and the acquired date and time data is stored in the date and time storage area, thereby updating the date and time data in the date and time storage area. By updating the date and time data in the date and time storage area without performing the process, the sub CPU 81 can omit the processing load related to communication with the RTC 86.

  In general, when calculating the elapsed date and time from the clock count, the clock count is divided by the clock count equivalent to one day, the elapsed years, the elapsed months and the elapsed days are calculated from the quotient, and the remainder is 1 The elapsed time is calculated by dividing by the clock count equivalent to time, the remainder is divided by the clock count equivalent to 1 minute to calculate the elapsed minutes, and the remainder is divided by the clock count equivalent to 1 second, and the elapsed seconds is calculated. Is calculated.

  The division process by the CPU is executed by a floating-point operation or an iterative operation. For this reason, division has the highest processing load on the CPU among the four arithmetic operations. In the date and time update process in the present embodiment, the load on the sub CPU 81 is reduced by updating the date and time data stored in the date and time storage area only by the addition process without performing the division process with a high processing load.

  Further, in the present embodiment, the description has been given of acquiring the date and time data from the RTC 86 in the power-on process (FIG. 21) and updating the date and time data using the clock counter. However, the present invention is not limited to this. Instead, the date and time data may be read from the RTC 86 every hour.

[Sound control task]
Next, a sound control task performed by the sub CPU 81 will be described with reference to FIG.

  First, the sub CPU 81 executes a sound function RAM transfer process of transferring a predetermined program among the control programs stored in the sub ROM 82 to the sub RAM 83 (S581). The sound function RAM transfer processing will be described later with reference to FIG.

  Next, the sub CPU 81 determines whether or not the sound data registered in the effect registration task (see S515 in FIG. 23) has been updated (S582). This sound data is data for driving and controlling the speakers 20L and 20R (see FIG. 2) during a certain period.

  In S582, when sub CPU 81 determines that the registered sound data has been updated (YES), it executes the process of S583, and when it determines that the registered sound data has not been updated (NO). , S584 are executed.

  In S583, the sub CPU 81 acquires the registered sound data (S583). After executing the processing of S583, the sub CPU 81 executes the processing of S584. In S584, the sub CPU 81 executes sound control data generation processing for generating sound control data according to the sound data and the reproduction position of the sound data.

  The sound control data is data for driving and controlling the speakers 20L and 20R at predetermined intervals. That is, the sub CPU 81 creates sound control data by dividing sound data, which is data for driving and controlling the speakers 20L and 20R during a predetermined period, at predetermined intervals.

  After executing the processing of S584, the sub CPU 81 executes the processing of S585. In S585, the sub CPU 81 registers the sound control data generated in the sound control data generation processing (S584) in the sound driver (software).

  As described above, by registering the sound control data in the sound driver, the sub CPU 81 executing the processing of the sound driver transmits the sound control data to the sound IC 88. When transmitting the sound control data to the sound IC 88, the sub CPU 81 receives a reproduction state of the sound IC and the like.

  After executing the processing of S585, the sub CPU 81 executes the processing of S586. In S586, the sub CPU 81 determines whether or not the sound being played has ended playing. In S586, if the sub CPU 81 determines that the sound being reproduced has ended reproduction (YES), the sub CPU 81 executes the process of S587, and if it determines that the sound being reproduced has not ended reproduction (NO). , S582.

  In S587, the sub CPU 81 determines whether or not the sound being reproduced is a loop reproduction. In S587, if the sub CPU 81 determines that the sound being reproduced is loop reproduction (YES), it executes the process of S588, and if it determines that the sound being reproduced is not loop reproduction (NO). , S582.

  In S588, the sub CPU 81 executes a sound data search process. In the sound data search processing, the sub CPU 81 returns the reproduction position of the sound data to the beginning. After executing the processing of S588, the sub CPU 81 executes the processing of S582.

[Sound function RAM transfer processing]
Next, the sound function RAM transfer processing will be described with reference to FIG.

  First, the sub CPU 81 transfers a program for executing the sound control data generation process (see S584 in FIG. 27) in the sound control task from the sub ROM 82 to the sub RAM 83 (S591).

  Next, the sub CPU 81 transfers the sound driver from the sub ROM 82 to the sub RAM 83 (S592). After performing the processing of S592, the sub CPU 81 ends the sound function RAM transfer processing.

  The sub CPU 81 executes a sound control data generation process program transferred from the sound control task program, which is an upper program, to the sub RAM 83. The sub CPU 81 executes a process as a sound driver according to a program transferred to the sub RAM 83.

  As described above, in the sound function RAM transfer processing, the sub CPU 81 transfers the program for executing the sound data generation processing, which is a predetermined program having a relatively high processing load, and the sound driver from the sub ROM 82 to the sub RAM 83. By executing, the processing speed is improved.

[Specific example of sound control task and sound function RAM transfer processing]
With reference to FIG. 29, the sound control task and the sound function RAM transfer processing described with reference to FIGS. 27 and 28 will be specifically described. In FIG. 29, the sound control task and the sound function RAM transfer process are each expressed in C language.

  "SoundRamTrans ()" is a program for executing the sound function RAM transfer processing shown in FIG. At a position represented by the address “_SoundMakeData” in the sub-ROM 82, a program for executing the process of step S584 of the sound control task is stored.

  In step S591 of the sound function RAM transfer process, the memory copy function (memcpy) is used to transfer the program size (sizeof (_SoundMakeData)) from the address “_SoundMakeData” in the sub ROM 82 to the position indicated by the address “__SoundMakeData” in the sub RAM 83. A memory copy is performed.

  As described above, the program for executing the process of step S584 of the sound control task is transferred to the sub RAM 83. In the present embodiment, it is assumed that an area for storing the program is secured at a position represented by the address “__SoundMakeData” in the sub RAM 83 before executing the sound function RAM transfer processing.

  A program for executing the process of step S585 of the sound control task is stored in the sub-ROM 82 at a position represented by the address “_SetSoundDriver”. In step S592 of the sound function RAM transfer processing, the memory copy function (memcpy) is used to transfer the program size (sizeof (_SetSoundDriver)) from the address “_SetSoundDriver” in the sub ROM 82 to the position indicated by the address “__SetSoundDriver” in the sub RAM 83. A memory copy is performed.

  As described above, the program for executing the process of step S585 of the sound control task is transferred to the sub RAM 83. In the present embodiment, it is assumed that an area for storing the program is secured at a position represented by an address “__SetSoundDriver” in the sub RAM 83 before executing the sound function RAM transfer processing.

  “SoundTask ()” is a program for executing the sound control task shown in FIG. Note that “SoundTask ()” illustrated in FIG. 29 represents the processing of steps S583 to S585, and the description of other processing is omitted.

  In “SoundTask ()”, “index” is used as a variable indicating a request number for identifying sound data, and “SoundData” is used as a pointer variable indicating an address of a storage destination of sound data in the sub ROM 82. , “SoundBuf” are used as pointer variables indicating the address of the storage destination of the sound control data in the sub RAM 83.

  "GetSoundData ()" executes the process of step S583 of the sound control task, and acquires the registered sound data. Specifically, when the request number of the registered sound data is specified by “index”, “GetSoundData ()” stores the storage address of the specified sound data in “SoundData”.

  "SoundMakeData ()" is an access function of the program "__SoundMakeData ()" transferred to the address "__SoundMakeData" of the sub RAM 83 in step S591 of the sound function RAM transfer process shown in FIG.

  “__SoundMakeData ()” generates sound control data in the sub RAM 83 based on the sound data whose address is specified when the address of the storage destination of the sound data represented by the argument “dat” is specified, and generates the generated sound control data. The address of the data storage destination is stored in the argument “buf”.

  Therefore, "SoundMakeData ()" in "SoundTask ()" executes the process of step S584 of the sound control task, and the pointer variable "SoundData" representing the address of the storage destination of the sound data is specified, thereby changing the pointer variable. The address of the sub RAM 83 that is the storage destination of the sound control data is stored in “SoundBuf”.

  "SetSoundDriver ()" is an access function of the program "__SetSoundDriver ()" transferred to the address "__SetSoundDriver" of the sub RAM 83 in step S591 of the sound function RAM transfer process shown in FIG. “__SetSoundDriver ()” registers the specified address in the sound driver when the address of the sub RAM 83 that stores the sound control data indicated by the argument “buf” is specified.

  Therefore, "SetSoundDriver ()" in "SoundTask ()" executes the process of step S585 of the sound control task, and "SoundBuf" representing the address of the storage destination of the sound control data is designated, thereby setting the sound control data. Is registered in the sound driver in the address of the sub RAM 83 in which is stored.

[Lamp control task]
Next, a lamp control task performed by the sub CPU 81 will be described with reference to FIG.

  First, the sub CPU 81 executes a ramp function RAM transfer process of transferring a predetermined program among the control programs stored in the sub ROM 82 to the sub RAM 83 (S601). The ramp function RAM transfer processing will be described later with reference to FIG.

  Next, the sub CPU 81 executes a lamp data reading process of reading the lamp data registered in the effect registration task (see S516 in FIG. 23) into the sub RAM 83 (S602). The lamp data reading process will be described later with reference to FIG.

  Next, the sub CPU 81 determines whether or not the lamp data is being reproduced based on the value of the entry part number storage area of the reproduction state management storage area (see FIG. 14) (S603). As described above, when the lamp data is being reproduced, the part number for identifying the part data being reproduced is stored in the entry part number storage area of the reproduction state management storage area. On the other hand, as described later, when the lamp data is not being reproduced, a specific value (for example, “0”) is stored in the entry part number storage area of the reproduction state management storage area.

  For this reason, if the value of the entry part number storage area of the playback state management storage area is not a specific value, the sub CPU 81 in this embodiment determines that the lamp data is being played back, and If the value of the number storage area is a specific value, it is determined that the lamp data is not being reproduced.

  In S603, if it is determined that the lamp data is being reproduced (YES), the sub CPU 81 executes the processing of S604, and if it is determined that the lamp data is not being reproduced (NO), the processing of S602 is performed. Execute

  In S604, the sub CPU 81 acquires the attribute data of the part data being reproduced in the lamp data. Next, the sub CPU 81 determines whether or not the luminance pattern at the reproduction position of the part data being reproduced is an end block (for example, “−1”) (S605).

  In S605, if the sub CPU 81 determines that the luminance pattern at the reproduction position of the part data being reproduced is an end block (YES), it executes the processing of S608, and if it determines that the luminance pattern is not an end block ( NO), the processing of S606 is executed.

  In S606, the sub CPU 81 generates control data (see FIGS. 8 to 10) from the luminance pattern at the reproduction position of the part data being reproduced. As described above, in the present embodiment, the control data represents luminance with 6 bits (range of 0 to 63), and the luminance pattern represents luminance with 8 bits (range of 0 to 255).

  For this reason, the sub CPU 81 converts the luminance value in the luminance pattern into a 6-bit luminance value by bit-shifting (the luminance value being 8-bit data is shifted by 2 bits in the LSB direction), and performs serial conversion based on the converted luminance value. Control data according to the data format of the communication circuit for bus communication is generated. That is, the sub CPU 81 registers the luminance value converted into 6 bits in the corresponding luminance data L of the control data.

  In the present embodiment, the luminance value of the luminance pattern is represented by 8 bits. However, even when a driver IC corresponding to the luminance value of 8 bits or 7 bits is used, the luminance value is converted. This is because the luminance pattern can be diverted only by changing the processing, and the lamp data can be diverted even if the type of the driver IC is different.

  After executing the processing of S606, the processing of S607 is executed. In S607, the sub CPU 81 registers the control data generated in the lamp control data generation process (S606) in the lamp driver (software).

  By registering the control data in the lamp driver as described above, the sub CPU 81 executing the processing of the lamp driver transmits the control data to the driver IC. After executing the processing of S607, the sub CPU 81 executes the processing of S602.

  In S608, the sub CPU 81 determines whether or not there is part data next to the part data being reproduced based on the entry part number storage area and the part number storage area of the reproduction state management storage area (see FIG. 14). I do. In S608, when the sub CPU 81 determines that there is the next part data (YES), it executes the processing of S609, and when it determines that there is no next part data (for example, in the case of FIG. If the part data is part number: 8 or an end code in the end code storage area (see FIG. 14) is detected (NO), the process of S610 is executed.

  In S609, the sub CPU 81 updates the entry part number storage area of the playback state management storage area to the value of the next part number storage area, and moves the playback position to the next part data. In S610, the sub CPU 81 determines whether or not the attribute data acquired in S604 is shot + chain.

  In S610, when the sub CPU 81 determines that the attribute data is shot + chain (YES), the sub CPU 81 executes an attribute search cueing process (S611). In the attribute search start processing, if “TRUE” is stored in the chain / loop setting area based on the content stored in the reproduction state management storage area (see FIGS. 14 to 18), the sub CPU 81 turns on the lamp. From the head of the identification information represented by the data (for example, part number: 1 in FIG. 16), the attribute data is searched for part data representing shot + chain (for example, part number: 2 in FIG. 16) and detected. The reproduction position is moved to the beginning of the part data (for example, the value of the entry part number storage area in FIG. 14 is set to “2”). After executing the processing of S611, the sub CPU 81 executes the processing of S602.

  If it is determined in S610 that the attribute data is not shot + chain (NO), the sub CPU 81 determines whether or not the attribute data acquired in S604 is a loop (S612). If it is determined in S612 that the attribute data is not a loop (NO), the sub CPU 81 executes the processing of S602.

  If it is determined in S612 that the attribute data is a loop (YES), the sub CPU 81 executes the in-part heading process (S613). In the attribute search start processing, the sub CPU 81 moves the reproduction position to the head of the part data being reproduced. After executing the processing of S613, the sub CPU 81 executes the processing of S602.

  In the part search processing, the attribute data is a loop, and if the part data is data that changes from "0" to "9" in ascending order, the head is searched for "0" which is the head of the part data. This is a repeat function that repeats "0" to "9".

[Lamp data reading process]
Next, the lamp data reading process will be described with reference to FIG.

  First, the sub CPU 81 determines whether or not an error of the pachislot 1 is detected (S631). The error of the pachislot 1 includes a hopper empty error indicating that the hopper 33 (see FIG. 5) is empty, and an insertion indicating that the medal stored in the medal auxiliary storage 37 (see FIG. 5) has reached a specified amount. There is a medal auxiliary storage full error.

  The main CPU 51 sends an error command indicating these errors to the sub control circuit 42. The sub CPU 81 determines whether an error of the pachislo 1 is detected based on the error command.

  In S631, if it is determined that the pachislot 1 error has been detected (YES), the sub CPU 81 executes the process of S632, and if it is determined that the pachislot 1 error has not been detected (NO), S634. Execute the processing of

  In step S632, if the lamp data is being reproduced, the sub CPU 81 stores the request number of the lamp data being reproduced in the sub RAM 83. After executing the processing of S632, the sub CPU 81 registers the lamp data for the error (S633). After executing the processing of S633, the sub CPU 81 executes the processing of S638.

  In S634, the sub CPU 81 determines whether or not the error of the pachislot 1 has been canceled (S634). In S634, if the sub CPU 81 determines that the error of the pachislot 1 has been released (YES), it executes the processing of S635, and if it determines that the error of the pachislot 1 has not been released (NO), The processing of S637 is executed.

  In S635, the sub CPU 81 specifies the request number of the interruption return lamp data corresponding to the request number stored in S632. After executing the process of S635, the sub CPU 81 registers the error lamp data of the request number specified in S635 (S636). After executing the processing of S636, the sub CPU 81 executes the processing of S638.

  In S637, the sub CPU 81 determines whether or not the lamp data registered in S516 (see FIG. 23) of the effect registration task has been updated (S637). In S637, if sub-CPU 81 determines that the lamp data has been updated (YES), it executes the process of S638, and if it determines that the lamp data has not been updated (NO), the lamp-data reading process To end.

  In S638, the sub CPU 81 acquires the lamp data registered in S633, S636 or S516 of the effect registration task. After executing the processing of S638, the sub CPU 81 executes a reproduction data generation processing of generating a reproduction state management storage area (see FIG. 14) in the sub RAM 83 based on the lamp data acquired in S638 (S639).

  When terminating the reproduction of the lamp data, the sub CPU 81 in the present embodiment registers blank lamp data in S516 of the effect registration task. When the blank lamp data is registered, the sub CPU 81 sets a specific value (for example, “0”) in the entry part number storage area and generates a playback state management storage area not including the part number storage area in S639. I do. After executing the processing of S639, the sub CPU 81 ends the lamp data reading processing.

[Ramp function RAM transfer processing]
Next, a ramp function RAM transfer process will be described with reference to FIG.

  First, the sub CPU 81 transfers a program for executing the reproduction data generation process (see S639 in FIG. 31) in the lamp data reading process from the sub ROM 82 to the sub RAM 83 (S651).

  Next, the sub CPU 81 transfers a program for executing the lamp control data generation process (S606 in FIG. 30) in the lamp control task from the sub ROM 82 to the sub RAM 83 (S652).

  Next, the sub CPU 81 transfers the lamp driver from the sub ROM 82 to the sub RAM 83 (S653). After performing the processing of S653, the sub CPU 81 ends the ramp function RAM transfer processing.

  The sub CPU 81 executes a reproduction data generation program from a ramp data reading program as a higher-level program, and executes a lamp control data generation program from a lamp control task program as a higher-level program. Further, the sub CPU 81 executes a process as a lamp driver according to a program transferred to the sub RAM 83.

  As described above, in the ramp function RAM transfer process, the sub CPU 81 stores the program for executing the reproduction data generation process and the lamp control data generation process, which are predetermined programs with relatively high processing loads, and the lamp driver from the sub ROM 82. The processing speed is improved by transferring the data to the sub RAM 83 and executing it.

[Specific examples of lamp control task, lamp data reading processing, and lamp function RAM transfer processing]
With reference to FIG. 33, the ramp control task, the ramp data reading process, and the ramp function RAM transfer process described with reference to FIGS. 30 to 32 will be specifically described. In FIG. 33, the ramp control task and the ramp function RAM transfer process are each expressed in C language.

  "LampRamTrans ()" is a program for executing the ramp function RAM transfer process shown in FIG. At a position represented by the address “_LampPlayMake” of the sub ROM 82, a program for executing the processing of step S639 of the lamp data reading processing shown in FIG. 31 is stored.

  In step S651 of the ramp function RAM transfer processing, the memory copy function (memcpy) is used to transfer the program size (sizeof (_LampPlayMake)) from the address “_LampPlayMake” of the sub ROM 82 to the position indicated by the address “__LampPlayMake” of the sub RAM 83. A memory copy is performed.

  In this way, the program for executing the processing of step S639 of the lamp data reading processing shown in FIG. In the present embodiment, it is assumed that an area for storing the program is secured at a position represented by the address “__LampPlayMake” in the sub RAM 83 before the execution of the ramp function RAM transfer processing.

  A program for executing the process of step S606 of the lamp control task shown in FIG. 30 is stored at a position represented by the address “_LampMakeData” in the sub ROM 82. In step S652 of the ramp function RAM transfer process, the memory copy function (memcpy) is used to transfer the program size (sizeof (_LampMakeData)) from the address “_LampMakeData” of the sub-ROM 82 to the position indicated by the address “__LampMakeData” of the sub-RAM 83. A memory copy is performed.

  In this way, the program for executing the processing of step S606 of the lamp control task shown in FIG. In the present embodiment, it is assumed that an area for storing the program is secured at a position represented by the address “__LampMakeData” in the sub RAM 83 before the execution of the ramp function RAM transfer process.

  A program for executing the process of step S607 of the lamp control task shown in FIG. 30 is stored in the sub-ROM 82 at the position represented by the address “_SetLampDriver”. In step S593 of the ramp function RAM transfer process, the memory copy function (memcpy) is used to transfer the program size (sizeof (_SetLampDriver)) from the address “_SetLampDriver” in the sub ROM 82 to the position indicated by the address “__SetLampDriver” in the sub RAM 83. A memory copy is performed.

  In this way, the program for executing the processing of step S607 of the lamp control task shown in FIG. In the present embodiment, it is assumed that an area for storing the program is secured in the sub RAM 83 at the position represented by the address “__SetLampDriver” before the execution of the ramp function RAM transfer process.

  “LampTask ()” is a program for executing the lamp control task shown in FIG. Note that “LampTask ()” illustrated in FIG. 33 represents the processing of steps S605 to S607, and the description of other processing is omitted.

  In “LampTask ()”, “LampData” is used as a pointer variable indicating the address of the storage location of the brightness data in the sub ROM 82, and “LampBuf” is a pointer variable indicating the address of the storage location of the lamp control data in the sub RAM 83. Used as The determination statement of “if (* LampData! = EndBlock)” indicates the processing of step S605.

  "LampPlayMake ()" is an access function of the program "__LampPlayMake ()" transferred to the address "__LampPlayMake" of the sub RAM 83 in step S651 of the ramp function RAM transfer process shown in FIG.

  “__LampPlayMake ()”, when the address of the storage destination of the luminance pattern represented by the argument “dat” is specified, reads the specified luminance pattern into the reproduction state management storage area (see FIG. 14) of the sub-RAM 83, The address of the playback state management storage area is stored in the argument “buf”.

  "LampMakeData ()" is an access function of the program "__LampMakeData ()" transferred to the address "__LampMakeData" of the sub RAM 83 in step S652 of the ramp function RAM transfer processing shown in FIG.

  “__LampMakeData ()”, when the address of the storage destination of the luminance pattern represented by the argument “dat” is specified, generates lamp control data in the sub RAM 83 based on the specified luminance pattern, and generates the generated lamp control data. The address of the data storage destination is stored in the argument “buf”.

  Therefore, “LampMakeData ()” in “LampTask ()” executes the processing of step S606 of the lamp control task shown in FIG. 30, and the pointer variable “LampData” indicating the address of the storage destination of the luminance pattern is specified. As a result, the address of the sub RAM 83 as the storage destination of the lamp control data is stored in the pointer variable “LampBuf”.

  "SetLampDriver ()" is an access function of the program "__SetLampDriver ()" transferred to the address "__SetLampDriver" of the sub RAM 83 in step S653 of the ramp function RAM transfer process shown in FIG. “__SetLampDriver ()” registers the specified address in the lamp driver when the address of the sub RAM 83 as the storage destination of the lamp control data indicated by “buf” is specified.

  Therefore, "SetLampDriver ()" in "LampTask ()" executes the process of step S607 of the lamp control task shown in FIG. 30, and the pointer variable "LampBuf" indicating the address of the storage destination of the lamp control data is designated. Thus, the address of the sub RAM 83 as the storage destination of the lamp control data is registered in the lamp driver.

[Method of Manufacturing Program Executed by Sub CPU]
Next, a method of manufacturing a program to be executed by the sub CPU of the sub control circuit 42 will be described with reference to FIG.

  In the present embodiment, the sub CPU 81 reads and executes the control program stored in the sub ROM 82. On the other hand, generally, the read speed of the RAM is faster than the read speed of the ROM as a characteristic of the semiconductor.

  For this reason, the sub CPU 81 transfers a part of the program with a high processing load (generally referred to as “function” or “subroutine”) to the sub RAM 83, and reads the program transferred to the sub RAM 83. While executing the program, the execution speed of a program having a partly high processing load is improved.

  However, simply transferring the program stored in the sub-ROM 82 to the sub-RAM 83 cannot operate normally because the address stored in the transferred program points to the address in the sub-ROM 82.

  Before storing the program in the sub-ROM 82, it is necessary to change the address in the program to be transferred to the sub-RAM 83 to the address in the sub-RAM 83. In the present embodiment, the programs transferred to the sub-RAM 83 are the programs stored at the addresses “_SoundMakeData” and “_SoundBuf” of the sub-ROM 82 described with reference to FIG. 29, and the programs stored in the sub-ROM 82 described with reference to FIG. And programs stored at addresses “_LampPlayMake”, “_LampMakeData”, and “_LampBuf”.

  In a higher-level program that uses a program to be transferred to the sub RAM 83, it is necessary to change the call address of the program to be transferred to the sub RAM 83 to an address in the sub RAM 83.

  In the present embodiment, the upper programs using the program transferred to the sub RAM 83 are the access functions "SoundMakeData ()" and "SetSoundDriver ()" shown in FIG. 29 and the access function shown in FIG. "LampPlayMake ()", "LampMakeData ()", and "SetLampDriver ()" are included.

  Therefore, in the method of manufacturing a program according to the present embodiment, the program to be transferred to the sub-RAM 83 and the upper-side program using the program to be transferred to the sub-RAM 83 (hereinafter, also referred to as “address conversion target program”) are addressed. It is manufactured by a method different from the program other than the program to be converted.

  As shown in FIG. 34, in the method for manufacturing a program according to the present embodiment, after executing a step P1 of compiling a target C language source group of an address conversion target program, the assembler source group generated in the step P1 is described above. And a step P2 of changing the address (specifically, the label) and changing the instruction (so-called mnemonic).

  As the contents of the change, for example, the label at the jump destination is changed, and the instruction to jump to the label before the change at the absolute address is rewritten to the instruction to jump to the address relative to the label after the change. In this case, since the label of the assembler source generated from the original C-language source points to the sub-ROM 82, the label is changed so that the sub-RAM 83 can be jumped, and the relative position (plus from the current address where the instruction is present) is increased. (The relative number of bytes in the minus direction or minus direction).

  Further, in the method of manufacturing a program according to the present embodiment, an object file (intermediate file) is generated by compiling a non-target C-language source group of a program other than the address conversion target program, and is executed in the RAM whose address has been changed in step P2 A step P3 of assembling the supported assembler source group to generate an object file, and linking the object file of the non-target C language source group and the object file of the RAM execution supported assembler source group to each other to generate a final program And a step P4 of writing the program generated in the step P3 into the sub-ROM 82.

[Various effects]
As described above, the pachi-slot 1 according to the embodiment of the present invention converts the pattern data according to the effect to be executed according to the data format of the communication circuit for serial bus communication with the driver IC, and converts the converted pattern. By transmitting control data based on the data to the driver IC, various lamp groups such as the first lamp group 111, the seventh lamp group 117, the eighth lamp group 118, and the dot matrix section 119 are controlled. Various lamp groups can be controlled by independent pattern data.

  In particular, the pachislo 1 according to the embodiment of the present invention converts the luminance value of the LED included in the pattern data according to the effect to be executed into a luminance value according to the driver IC, and converts the control data based on the converted luminance value into the driver value. Since various lamp groups such as the first lamp group 111, the seventh lamp group 117, the eighth lamp group 118, and the dot matrix section 119 are controlled by transmitting the data to the IC, various lamps are controlled by pattern data independent of the specifications of the driver IC. Groups can be controlled.

  Further, the pachislo 1 according to the embodiment of the present invention does not synchronize the error detection data E with the data for setting the LED brightness in the control data, so that the sub CPU 81 is not affected by the data pattern. In addition, an abnormality in serial bus communication between the driver ICs can be detected on the control data receiving side.

  Further, the pachislo 1 according to the embodiment of the present invention is specified by a first mode for setting the brightness of all LEDs driven by the driver IC, and a channel number and a channel number for specifying the LEDs to be driven by the driver IC. The control data can be transmitted in any of the second mode for setting the LED brightness.

  For this reason, when controlling the LEDs individually, such as when controlling the dot matrix units 119 arranged in a matrix, the second mode for setting the brightness of a specific LED is better than the first mode. Also, the data length of the control data becomes short.

  On the other hand, when controlling the LEDs as a whole, such as when controlling the first lamp group 111, the seventh lamp group 117, and the eighth lamp group 118, the first lamp which does not need the channel number for specifying the LED is used. The data length of the control data is shorter in the mode than in the second mode.

  When all the LEDs are turned off, the data length of the third mode, which does not require the specification of the luminance value of each LED or the channel number for specifying the LED, is shorter than the first mode and the second mode. Become.

  As described above, the pachi-slot 1 according to the embodiment of the present invention can control the transmission between the sub CPU 81 and the driver IC by selecting the control data mode in which the data length is shortened according to the use of the LED driven by the driver IC. The load can be reduced, and the responsiveness of the LED can be improved.

  Further, the pachislo 1 according to the embodiment of the present invention causes the sub CPU 81 to manage date and time data by counting the operation clock. Therefore, the sub CPU 81 does not need to perform serial communication with the RTC 86 every time the date and time data is acquired. Thus, the pachislo 1 according to the embodiment of the present invention can reduce the load on the sub CPU 81.

  Further, the pachislot 1 according to the embodiment of the present invention updates the date and time data with reference to a monthly date table in which the number of days when the leap year is not and the number of days when the leap year is not present are associated with each month. Data can be updated without errors.

  Further, the pachislot 1 according to the embodiment of the present invention stores the date and time stored in the date and time storage area of the sub RAM 83 until the calculated elapsed time is added to the date and time represented by the date and time data stored in the date and time storage area of the sub RAM 83. By adding the specified time (1 second count) to the data, the date and time data stored in the date and time storage area of the sub RAM 83 is updated only by the addition process without performing the division process with a high processing load. The load can be reduced.

  The pachislo 1 according to the embodiment of the present invention executes a program for executing sound data generation processing, which is a program having a relatively high processing load, a sound driver, a reproduction data generation processing, and a lamp control data generation processing. The processing speed of the sub CPU 81 can be improved by transferring the program and the lamp driver to the sub RAM 83 for execution.

  Further, the pachislo 1 according to the embodiment of the present invention executes programs other than programs having a relatively high processing load in a state stored in the sub ROM 82, thereby suppressing the storage capacity required for the sub RAM 83. Cost can be reduced.

  Further, the pachislot 1 according to the embodiment of the present invention can be diversified into various lamp groups such as a first lamp group 111, a seventh lamp group 117, an eighth lamp group 118, and a dot matrix unit 119 by combining part data. In order to execute such an effect, it is possible to confirm and change the light emission pattern of various lamp groups in units of parts data. As described above, the pachislo 1 according to the embodiment of the present invention can reduce the burden of checking and changing the light emission pattern of various lamp groups.

  Further, the pachislot 1 according to the embodiment of the present invention uses the part data for which the attribute data is set to the continuous reproduction, the first lamp group 111, the seventh lamp group 117, the eighth lamp group 118, the dot matrix section 119, and the like. Since the various lamp groups repeatedly perform the effect, even when the effect of the various lamp groups is performed for a long time, the burden of confirming and changing the light emission pattern of the various lamp groups can be reduced.

  Further, when the pachislot 1 according to the embodiment of the present invention returns from the error state, the order of the identification information represented by the new effect data excluding the identification information of the part data whose attribute data does not represent the shot + chain is removed. Therefore, since the various lamp groups such as the first lamp group 111, the seventh lamp group 117, the eighth lamp group 118, and the dot matrix section 119 are controlled by the pattern data included in the part data, the rendering data is reproduced from the beginning when the error is recovered. By doing so, it is possible to prevent an effect that does not match the game state from being executed.

[Modification]
In the present embodiment, an example has been described in which the sub CPU 81 stores the date and time data acquired from the RTC 86 in the sub RAM 83 when the power is turned on, and updates the date and time data stored in the sub RAM 83 by counting the operation clock.

  In addition, the sub CPU 81 may acquire the date and time data from the RTC 86 and adjust (adjust) the date and time data stored in the sub RAM 83 every time a predetermined condition is satisfied. The predetermined condition may be that the counted value exceeds a predetermined value, that a specific command such as a start command has been received, that an error state has been restored, or that a reset button (not shown) has been pressed. And the like.

  In this embodiment, a program for executing sound data generation processing, which is a program having a relatively high processing load, a sound driver, a program for executing reproduction data generation processing and lamp control data generation processing, and a lamp driver At startup (in the present embodiment, sound function RAM transfer processing and lamp function RAM transfer processing executed as initialization processing of the sound control task and the lamp control task started when the sub CPU 81 is turned on). The example in which the data is transferred to the RAM 83 in advance and executed is described.

  On the other hand, the pachislo 1 according to the embodiment of the present invention may transfer each program to the sub-RAM 83 and execute the program upon execution of each program having a relatively high processing load.

  Further, the pachislot 1 according to the embodiment of the present invention transfers each program to the sub-RAM 83 and executes each program if the respective programs are not transferred to the sub-RAM 83 when each program having a relatively high processing load is executed. You may do so.

  With this configuration, the pachi-slot 1 according to the embodiment of the present invention has already been transferred to the sub-RAM 83 if each program is transferred to the sub-RAM 83 when executing each program having a relatively high processing load. Therefore, the processing of the sub CPU 81 for transferring each program to the sub RAM 83 can be omitted.

  Further, the pachislot 1 according to the embodiment of the present invention transfers the program having a relatively high processing load to the sub RAM 83 if the area for transferring each program is secured in the sub RAM 83, and the area for transferring each program to the sub RAM 83. Otherwise, an area for transferring each program may be secured in the sub RAM 83, and each program may be transferred to the secured area and executed.

  With this configuration, the pachislo 1 according to the embodiment of the present invention reliably transfers each program having a relatively high processing load to the sub RAM 83 and executes the program, so that the processing speed of the sub CPU 81 is reliably improved. Can be done.

  In addition, the pachislot 1 according to the embodiment of the present invention transfers some of the programs having relatively high processing loads to the sub-RAM 83 in advance at the time of startup, and stores the other programs in the sub-RAM 83 at the time of execution. You may make it transfer.

  For example, the pachislo 1 according to the embodiment of the present invention includes a program for executing a sound data generation process, a sound driver, a program for executing a reproduction data generation process and a lamp control data generation process, and a sound driver. The driver and the lamp driver may be transferred to the sub RAM 83 in advance at the time of startup, and a program for executing the sound data generation processing, the reproduction data generation processing, and the lamp control data generation processing may be transferred to the sub RAM 83 at the time of execution.

  Further, in the present embodiment, the sub CPU 81 transmits control data in the second mode from the second port to the driver IC that drives the LEDs of the first light emitter group, and drives the LEDs of the second light emitter group. The example in which the control data is transmitted from the first port to the driver IC in the first mode has been described.

  On the other hand, the sub CPU 81 transmits the control data in the first mode from the second port to the driver IC that drives the LEDs of the first light emitter group, and sends the control data to the driver IC that drives the LEDs of the second light emitter group. May transmit control data in the second mode from the first port.

  The sub CPU 81 transmits control data in the first mode from the second port to the driver IC that drives the LEDs of the first light emitter group, and transmits the control data to the driver IC that drives the LEDs of the second light emitter group. Control data may be transmitted in the first mode from the first port.

  The sub CPU 81 transmits control data in the second mode from the second port to the driver IC that drives the LEDs of the first light emitter group, and transmits the control data to the driver IC that drives the LEDs of the second light emitter group. Control data may be transmitted from the first port in the second mode.

  Further, when the sub CPU 81 registers the lamp data in the effect registration task (see S516 in FIG. 23) or the like, the sub CPU 81 may determine in which mode the control data generated from the registered lamp data is transmitted. .

  Alternatively, the mode may be set in advance to the lamp data or parts data stored in the sub ROM 82, and the sub CPU 81 may transmit the control data in the mode set in advance to the lamp data or parts data.

[Other expandability of the gaming machine according to the present invention]
In the pachislot 1 of the above embodiment, the player inserts a medal into the medal (that is, inserts a medal in the hand into the medal slot 13 or presses the credited medal on the MAX bet button 14 or the 1-bet button 15). When the game is started by the operation of inputting and paying out, and the game is paid out when the game is finished, the hopper 33 is driven to pay out the medal from the medal payout opening 18 or to be credited. Although the embodiment has been described, the present invention is not limited to this.

  For example, a game medium required for a game is inserted by a player, a game is performed based on the medium, and a privilege is given based on a result of the game (for example, a medal is paid out). The present invention can be applied. That is, the main control circuit (main board 31) itself controls the game medium held by the player by not only the form in which the game medium is inserted (hanged) by the action of the physical player and the game medium is paid out, but also the game medium held by the player. It may be a form that manages the game and enables games without a medal. In this case, the game medium held by the player is electromagnetically managed by a game medium management device mounted (connected) to the main control circuit (main board 31) and managing the game medium. Good.

  In this case, the game medium management device has a ROM and RWM (or RAM), is a device provided in the game machine, and is capable of bidirectional communication with an external game medium handling device (not shown) via a predetermined interface. The operation of lending the game media (that is, the operation of providing the required game media when the player performs the operation of inserting the game media) or winning the role related to the payout of the game media ( The payout operation of the game medium when the role is established) (that is, the operation of obtaining the required game medium in paying out the game medium to the player) or the game medium provided for the game What is necessary is just to be able to perform the operation | movement which records in a dynamic way. In addition, the game medium management device not only manages the actual number of game media, but also displays, for example, the number of held game media based on the management result of the number of game media (not shown). May be provided on the front surface of the pachislot 1 to manage the number of game media displayed on the retained game medium number display device. That is, the game medium management device may record and display the total number of game media that the player can use for the game by an electromagnetic method.

  In this case, the game medium management device may have a performance (function) that allows a player to freely transmit a signal indicating the number of recorded game media to an external game medium handling device. desirable. Further, it is desirable that the game medium management device has a performance that cannot reduce the number of recorded game media except when the player directly operates the game medium management device. Also, when an external connection terminal plate (not shown) is provided between the game medium management device and an external game medium handling device, the game medium management device must be connected via the external connection terminal plate. It is desirable for a player to have the ability to not transmit a signal indicating the number of recorded game media.

  In addition to the above, the gaming machine is provided with a lending operation means that can be operated by the player, a return (payment) operation means, an external connection terminal plate, and a gaming medium handling device has an input port of valuables such as bills, Insertion slot of recording medium (for example, IC card), non-contact communication antenna for depositing electronic money and the like from a portable terminal, other various operation means such as lending operation means, return operation means, and external connection on the game medium handling device side A terminal plate may be provided (neither is shown).

  As a flow of the game at that time, for example, a player deposits a valuable value into the game medium handling device by any one of the above methods, and a predetermined number of valuable values based on the operation of any one of the lending operation means. Is subtracted from the game medium handling device to the game medium management device, and the number of game media corresponding to the subtracted value is increased. Then, the player plays the game, and repeats the above operation when a further game medium is required. Thereafter, as a result of the game, a predetermined number of game media is obtained, and when the game is completed, the game medium management device operates the return medium by operating any one of the above-mentioned return operation means to the game medium handling device, And the game medium handling device ejects the recording medium on which the number of game media is recorded. The game medium management device clears the number of game media stored therein when transmitting the number of game media. The player takes the discharged recording medium to a prize counter or the like to exchange prizes, or moves the gaming table to play a game at another gaming table based on the recorded game medium.

  In the above example, the total number of game media is transmitted from the game media management device to the game media handling device, but only the number of game media desired by the player is transmitted from the gaming machine or the game media handling device, and the The game media possessed by the player may be divided and processed. Further, in the above example, the game medium handling device ejects the recording medium, but cash or cash equivalent may be ejected, or may be stored in a portable terminal or the like. In addition, the game medium handling device may be configured to insert a member recording medium in a game arcade, store the game medium in the member recording medium, and enable the game to be played again later using the stored game medium. .

  Further, in a gaming machine or a game medium handling device, a lock operation for locking game medium or valuable data communication can be performed on the game medium handling device or the game medium management device by operating a predetermined operation means (not shown). It may be. At that time, information that can be known only to the player, such as a one-time password, may be set, or the player may be stored by an imaging unit provided in the gaming machine or the game medium handling device.

  As described above, the game medium management device may enable a game only without a medal, or a game medium is inserted (hanged) by an operation of a physical player, and the game medium is The game may be made available in both a paid-out form and a form that enables the game without a medal. In the latter case, a system in which the game medium management device directly controls the selector 35 and the hopper 33 described above may be employed, and these may be controlled by the main control circuit (main board 31). Based on the transmission of the result, it is also possible to adopt a method capable of controlling the recording and displaying of the total number of game media that the player can use for the game by using an electromagnetic method.

  Further, in the above example, the case where the game medium management device is applied to a pachislot is described. For example, a game medium management device is similarly provided in a slot machine using a game ball or an enclosed game machine, Of game media can be managed.

  When the above-described game medium management device is provided, the number of devices such as the selector 35 and the hopper 33 inside the game machine can be reduced as compared with the case where the game medium is physically provided for the game, and Not only can the cost and manufacturing cost be reduced, but also the player can be prevented from directly touching the game media, the gaming environment can be improved, noise can be reduced, and the reduced number of devices reduces the It is also possible to reduce power consumption. In addition, in the case where the above-described game medium management device is provided, it is possible to prevent an illegal act through an insertion port or a payout port of the game medium or the game medium. That is, when the above-described gaming medium management device is provided, it is possible to provide a gaming machine capable of improving various environments surrounding the gaming machine.

[Summary of the Invention]
<Summary 1>
A gaming machine in which LEDs are arranged in a dot matrix to constitute a display unit is proposed in Japanese Patent Application Laid-Open No. 2005-323768.

  In order to control the light emission of a light emitting unit composed of a plurality of light emitters, such as an arrangement in which LEDs are arranged in a dot matrix, a method of directly controlling individual light emitters and a method of controlling data by using an LED driver IC or the like There is a method in which each light-emitting element is driven by the light-emitting drive means by transmitting the light to the light-emitting drive means.

  The specifications of the light emission drive means may differ depending on the manufacturer of the light emission drive means or the series of the same manufacturer. For this reason, when controlling the individual light emitters via the light emission driving means, it is necessary to re-create the pattern data representing the light emission pattern of the light emitting section according to the light emission driving means.

  The present invention has been made in order to solve such a problem, and an object of the present invention is to provide a gaming machine capable of controlling a light-emitting unit by pattern data that does not depend on the specifications of a light-emitting drive unit.

The gaming machine according to the present invention,
A light-emitting section (first lamp group 111, seventh lamp group 117, eighth lamp group 118, dot matrix section 119) composed of a plurality of light-emitting bodies (LEDs);
Light emission driving means (driver IC) for driving the light emitting section;
A control unit (sub CPU 81) for controlling a light emitting pattern of the light emitting unit;
Pattern data storage means (sub-ROM 82) storing a plurality of pattern data representing the light emitting pattern of the light emitting section,
The control unit includes:
From a plurality of pattern data stored in the pattern data storage means, determine pattern data according to the light emitting pattern to be executed,
Convert the luminance value of the luminous body included in the determined pattern data to a luminance value according to the light emission driving means,
It has a configuration in which control data based on the converted luminance value is transmitted to the light emission drive unit through serial bus communication.

  With this configuration, the gaming machine according to the present invention converts the luminance value of the illuminant included in the pattern data corresponding to the light emission pattern to be executed into a luminance value corresponding to the light emission drive unit, and controls the control data based on the converted luminance value. Is transmitted to the light emission driving unit, thereby controlling the light emission unit. Therefore, the light emission unit can be controlled by pattern data independent of the specification of the light emission driving unit.

In the gaming machine according to the present invention,
The control unit inserts error detection data into the control data at a period that is not synchronized with data for setting the luminance of the illuminant (for example, a 9-bit period for a 6-bit period data). You may do so.

  With this configuration, the gaming machine according to the present invention does not synchronize the error detection data with the data for setting the luminance of the illuminant in the control data, thereby preventing the serial bus communication without being affected by the data pattern. Can be detected on the control data receiving side.

  According to the present invention, it is possible to provide a gaming machine that can control a light emitting unit by pattern data that does not depend on the specifications of a light emission driving unit.

<Summary 2>
In order to solve the same problem as in the abstract 1, the gaming machine according to the present invention
A light-emitting section (first lamp group 111, seventh lamp group 117, eighth lamp group 118, dot matrix section 119) composed of a plurality of light-emitting bodies (LEDs);
Light emission driving means (driver IC) for driving the light emitting section;
A control unit (sub CPU 81) for controlling a light emitting pattern of the light emitting unit;
Pattern data storage means (sub-ROM 82) storing a plurality of pattern data representing the light emitting pattern of the light emitting section,
The control unit includes:
From a plurality of pattern data stored in the pattern data storage means, determine pattern data according to the light emitting pattern to be executed,
Convert the luminance value of the luminous body included in the determined pattern data to a luminance value according to the light emission driving means,
Transmitting control data based on the converted luminance value to the light emission driving unit by serial bus communication,
The control data is
A first mode for setting the luminance of all luminous bodies driven by the luminescence driving means;
The transmission can be performed in any one of a channel number for specifying a light emitter to be driven by the light emission drive means and a second mode for setting the luminance of the light emitter specified by the channel number.

  With this configuration, the gaming machine according to the present invention converts the luminance value of the illuminant included in the pattern data corresponding to the light emission pattern to be executed into a luminance value corresponding to the light emission drive unit, and controls the control data based on the converted luminance value. Is transmitted to the light emission driving unit, thereby controlling the light emission unit. Therefore, the light emission unit can be controlled by pattern data independent of the specification of the light emission driving unit.

  Further, the gaming machine according to the present invention is specified by a first mode for setting the luminance of all the luminous bodies driven by the luminescence driving unit, and a channel number and a channel number for specifying the luminous body to be driven by the luminescence driving unit. The control data can be transmitted in any of the second mode for setting the luminance of the illuminant.

  Therefore, when individually controlling the light emitters, the data length of the control data is shorter in the second mode in which the luminance of the specific light emitter is set than in the first mode, and the light emitters are totally controlled. In the case of control, the data length of the control data is shorter in the first mode, which does not require the channel number for specifying the light emitter, than in the second mode.

  Therefore, the gaming machine according to the present invention can control the transmission between the control unit and the light emission driving means by selecting the control data mode in which the data length is shortened according to the use of the light emitter driven by the light emission driving means. The load can be reduced, and the responsiveness of the luminous body can be improved.

In the gaming machine according to the present invention,
The control unit inserts error detection data into the control data at a period that is not synchronized with data for setting the luminance of the illuminant (for example, a 9-bit period for a 6-bit period data). You may do so.

  With this configuration, the gaming machine according to the present invention does not synchronize the error detection data with the data for setting the luminance of the illuminant in the control data, thereby preventing the serial bus communication without being affected by the data pattern. Can be detected on the control data receiving side.

  According to the present invention, it is possible to provide a gaming machine that can control a light emitting unit by pattern data that does not depend on the specifications of a light emission driving unit.

<Summary 3>
In order to solve the same problem as in the abstract 1, the gaming machine according to the present invention
A light-emitting section (first lamp group 111, seventh lamp group 117, eighth lamp group 118, dot matrix section 119) composed of a plurality of light-emitting bodies (LEDs);
Light emission driving means (driver IC) for driving the light emitting section;
A control unit (sub CPU 81) for controlling a light emitting pattern of the light emitting unit;
Pattern data storage means (sub-ROM 82) storing a plurality of pattern data representing the light emitting pattern of the light emitting section,
The control unit includes:
From a plurality of pattern data stored in the pattern data storage means, determine pattern data according to the light emitting pattern to be executed,
Convert the luminance value of the luminous body included in the determined pattern data to a luminance value according to the light emission driving means,
Transmitting control data based on the converted luminance value to the light emission driving unit by serial bus communication,
The control data is
A first mode for setting the luminance of all luminous bodies driven by the luminescence driving means;
It is possible to transmit in any mode of a channel number for specifying the light emitting body to be driven by the light emission driving unit and a second mode for setting the luminance of the light emitting body specified by the channel number,
The plurality of luminous bodies,
A first light emitter group arranged in a matrix;
A second illuminant group that is not included in the first illuminant group;
The control unit includes:
Transmitting the control data in the second mode to light emission driving means for driving the light emitters of the first light emitter group;
The light emission driving means for driving the light emitters of the second light emitter group has a configuration for transmitting the control data in the first mode.

  With this configuration, the gaming machine according to the present invention converts the luminance value of the illuminant included in the pattern data corresponding to the light emission pattern to be executed into a luminance value corresponding to the light emission drive unit, and controls the control data based on the converted luminance value. Is transmitted to the light emission driving unit, thereby controlling the light emission unit. Therefore, the light emission unit can be controlled by pattern data independent of the specification of the light emission driving unit.

  Further, the gaming machine according to the present invention is specified by a first mode for setting the luminance of all the luminous bodies driven by the luminescence driving unit, and a channel number and a channel number for specifying the luminous body to be driven by the luminescence driving unit. The control data can be transmitted in any of the second mode for setting the luminance of the illuminant.

  For this reason, for the first luminous body group arranged in a matrix, the luminous bodies are individually controlled, so that the second mode for setting the luminance of a specific luminous body is more controllable than the first mode. The data length of the data becomes shorter.

  On the other hand, for the second illuminant group that is not included in the first illuminant group, the first mode, which does not require a channel number for specifying the illuminant, is used in order to control the illuminant as a whole. The data length of the control data is shorter than in the two modes.

  Therefore, the gaming machine according to the present invention can control the transmission between the control unit and the light emission driving means by selecting the control data mode in which the data length is shortened according to the use of the light emitter driven by the light emission driving means. The load can be reduced, and the responsiveness of the luminous body can be improved.

In the gaming machine according to the present invention,
The control unit inserts error detection data into the control data at a period that is not synchronized with data for setting the luminance of the illuminant (for example, a 9-bit period for a 6-bit period data). You may do so.

  With this configuration, the gaming machine according to the present invention does not synchronize the error detection data with the data for setting the luminance of the illuminant in the control data, thereby preventing the serial bus communication without being affected by the data pattern. Can be detected on the control data receiving side.

  According to the present invention, it is possible to provide a gaming machine that can control a light emitting unit by pattern data that does not depend on the specifications of a light emission driving unit.

<Summary 4>
In order to solve the same problem as in the abstract 1, the gaming machine according to the present invention
A light-emitting section (first lamp group 111, seventh lamp group 117, eighth lamp group 118, dot matrix section 119) composed of a plurality of light-emitting bodies (LEDs);
Light emission driving means (driver IC) for driving the light emitting section;
A control unit (sub CPU 81) for controlling a light emitting pattern of the light emitting unit;
Pattern data storage means (sub-ROM 82) storing a plurality of pattern data representing the light emitting pattern of the light emitting section,
The control unit includes:
From a plurality of pattern data stored in the pattern data storage means, determine pattern data according to the light emitting pattern to be executed,
Converting the determined pattern data according to the light emission driving means,
A configuration is provided in which control data based on the converted pattern data is transmitted to the light emission driving means by serial bus communication.

  With this configuration, the gaming machine according to the present invention converts the pattern data according to the light emission pattern to be executed according to the light emission drive unit, and transmits control data based on the converted pattern data to the light emission drive unit to emit light. Since the unit is controlled, the light emitting unit can be controlled by pattern data that does not depend on the specification of the light emission driving unit.

In the gaming machine according to the present invention,
The control unit inserts error detection data into the control data at a period that is not synchronized with data for setting the luminance of the illuminant (for example, a 9-bit period for a 6-bit period data). You may do so.

  With this configuration, the gaming machine according to the present invention does not synchronize the error detection data with the data for setting the luminance of the illuminant in the control data, thereby preventing the serial bus communication without being affected by the data pattern. Can be detected on the control data receiving side.

  According to the present invention, it is possible to provide a gaming machine that can control a light emitting unit by pattern data that does not depend on the specifications of a light emission driving unit.

<Summary 5>
In order to solve the same problem as in the abstract 1, the gaming machine according to the present invention
A light-emitting section (first lamp group 111, seventh lamp group 117, eighth lamp group 118, dot matrix section 119) composed of a plurality of light-emitting bodies (LEDs);
Light emission driving means (driver IC) for driving the light emitting section;
A control unit (sub CPU 81) for controlling a light emitting pattern of the light emitting unit;
Pattern data storage means (sub-ROM 82) storing a plurality of pattern data representing the light emitting pattern of the light emitting section,
The control unit includes:
From a plurality of pattern data stored in the pattern data storage means, determine pattern data according to the light emitting pattern to be executed,
Convert the luminance value of the luminous body included in the determined pattern data to a luminance value according to the light emission driving means,
Transmitting control data based on the converted luminance value to the light emission driving unit by serial bus communication,
The control data is
A first mode for setting the luminance of all luminous bodies driven by the luminescence driving means;
A second mode for setting a channel number for specifying a light emitter to be driven by the light emission drive unit and a luminance of the light emitter specified by the channel number;
The transmission is possible in any one of a third mode including a command for turning off all the light emitters driven by the light emission drive unit.

  With this configuration, the gaming machine according to the present invention converts the luminance value of the illuminant included in the pattern data corresponding to the light emission pattern to be executed into a luminance value corresponding to the light emission drive unit, and controls the control data based on the converted luminance value. Is transmitted to the light emission driving unit, thereby controlling the light emission unit. Therefore, the light emission unit can be controlled by pattern data independent of the specification of the light emission driving unit.

  Further, the gaming machine according to the present invention is specified by a first mode for setting the luminance of all the luminous bodies driven by the luminescence driving unit, and a channel number and a channel number for specifying the luminous body to be driven by the luminescence driving unit. The control data can be transmitted in any of the second mode for setting the luminance of the illuminant.

  Therefore, when individually controlling the light emitters, the data length of the control data is shorter in the second mode in which the luminance of the specific light emitter is set than in the first mode, and the light emitters are totally controlled. In the case of control, the data length of the control data is shorter in the first mode, which does not require the channel number for specifying the light emitter, than in the second mode.

  When all the light emitters are turned off, the third mode, which does not require the specification of the luminance value of each light emitter or the channel number for specifying the light emitter, has a higher data rate than the first mode and the second mode. The length becomes shorter.

  Therefore, the gaming machine according to the present invention can control the transmission between the control unit and the light emission driving means by selecting the control data mode in which the data length is shortened according to the use of the light emitter driven by the light emission driving means. The load can be reduced, and the responsiveness of the luminous body can be improved.

In the gaming machine according to the present invention,
The control unit inserts error detection data into the control data at a period that is not synchronized with data for setting the luminance of the illuminant (for example, a 9-bit period for a 6-bit period data). You may do so.

  With this configuration, the gaming machine according to the present invention does not synchronize the error detection data with the data for setting the luminance of the illuminant in the control data, thereby preventing the serial bus communication without being affected by the data pattern. Can be detected on the control data receiving side.

  According to the present invention, it is possible to provide a gaming machine that can control a light emitting unit by pattern data that does not depend on the specifications of a light emission driving unit.

<Summary 6>
A gaming machine in which an effect control CPU and an RTC (Real Time Clock) are connected by serial bus communication using an I2C (Inter-Integrated Circuit) is proposed in JP-A-2017-51385.

  The above-described conventional gaming machine needs to perform serial communication by I2C or the like in order to obtain date and time data from the RTC, and thus a load may be applied to an arithmetic processing unit such as a production control CPU.

  The present invention has been made in order to solve such a problem, and an object of the present invention is to provide a gaming machine capable of reducing a load on an arithmetic processing unit.

The gaming machine according to the present invention,
Arithmetic processing means (sub CPU 81) for performing arithmetic processing;
Clock generation means (oscillation circuit 84) for generating a clock for operating the arithmetic processing means;
Operation storage means (sub-RAM 83) capable of storing data for use by the operation processing means;
A clock means (RTC86) connected to the arithmetic processing means via serial communication for clocking the date and time;
The arithmetic processing means,
Date and time obtaining means for obtaining date and time data from the timing means and storing the data in the arithmetic storage means,
Counting means (clock counter) for counting a clock generated by the clock generating means;
Elapsed time calculation means for calculating an elapsed time based on the value counted by the counting means,
When the elapsed time calculated by the elapsed time calculating means has reached a prescribed elapsed time, the time and date data stored in the arithmetic storage means for a time corresponding to the elapsed time calculated by the elapsed time calculating means. And date and time data updating means for updating the date and time.

  With this configuration, the gaming machine according to the present invention causes the arithmetic processing means to count operation clocks, thereby managing date and time data. Therefore, the arithmetic processing means does not need to perform serial communication with the clock means every time the date and time data is acquired. Thus, the gaming machine according to the present invention can reduce the load on the arithmetic processing means.

  In the gaming machine according to the present invention, the date and time data updating means may repeat a process of subtracting a prescribed elapsed time from the elapsed time and updating the date and time data until the subtraction result is less than a prescribed elapsed time. It may be.

  According to the present invention, it is possible to provide a gaming machine capable of reducing the load on the arithmetic processing means.

<Summary 7>
In order to solve the same problem as in the summary 6, the gaming machine according to the present invention includes:
Arithmetic processing means (sub CPU 81) for performing arithmetic processing;
Clock generation means (oscillation circuit 84) for generating a clock for operating the arithmetic processing means;
Operation storage means (sub-RAM 83) capable of storing data for use by the operation processing means;
A clock means (RTC86) connected to the arithmetic processing means via serial communication for clocking the date and time;
Monthly day table storage means (sub-ROM 82) for storing a monthly day table in which the number of days in a leap year and the number of days in a non-leap year are associated for each month,
The arithmetic processing means,
Date and time obtaining means for obtaining date and time data from the timing means and storing the data in the arithmetic storage means,
Counting means for counting the clock generated by the clock generating means,
Elapsed time calculation means for calculating an elapsed time based on the value counted by the counting means,
When the elapsed time calculated by the elapsed time calculating means has reached a prescribed elapsed time, the time and date data stored in the arithmetic storage means for a time corresponding to the elapsed time calculated by the elapsed time calculating means. Date and time data updating means for updating
The date and time data updating means updates the date and time data with reference to the monthly date table.

  With this configuration, the gaming machine according to the present invention causes the arithmetic processing means to count operation clocks, thereby managing date and time data. Therefore, the arithmetic processing means does not need to perform serial communication with the clock means every time the date and time data is acquired. Thus, the gaming machine according to the present invention can reduce the load on the arithmetic processing means.

  Further, the gaming machine according to the present invention updates the date and time data by referring to the monthly date table in which the number of days when the leap year is not and the number of days when the leap year is not associated with each month. Can be updated without.

  In the gaming machine according to the present invention, the date and time data updating means may repeat a process of subtracting a prescribed elapsed time from the elapsed time and updating the date and time data until the subtraction result is less than a prescribed elapsed time. It may be.

  According to the present invention, it is possible to provide a gaming machine capable of reducing the load on the arithmetic processing means.

<Summary 8>
In order to solve the same problem as in the summary 6, the gaming machine according to the present invention includes:
Arithmetic processing means (sub CPU 81) for performing arithmetic processing;
Clock generation means (oscillation circuit 84) for generating a clock for operating the arithmetic processing means;
Operation storage means (sub-RAM 83) capable of storing data for use by the operation processing means;
A clock means (RTC86) connected to the arithmetic processing means via serial communication for clocking the date and time;
The arithmetic processing means,
Date and time storage means for obtaining date and time data from the clocking means and storing the data in the arithmetic and storage means;
Counting means for counting the clock generated by the clock generating means,
Elapsed time calculation means for calculating an elapsed time based on the value counted by the counting means,
When the elapsed time calculated by the elapsed time calculating means has reached a prescribed elapsed time, the time and date data stored in the arithmetic storage means for a time corresponding to the elapsed time calculated by the elapsed time calculating means. Date and time data updating means for updating
The date and time data updating unit is configured to store the date and time data stored in the arithmetic storage unit until the elapsed time calculated by the elapsed time calculation unit is added to the date and time represented by the date and time data stored in the arithmetic storage unit. A predetermined time is added to the data.

  With this configuration, the gaming machine according to the present invention causes the arithmetic processing means to count operation clocks, thereby managing date and time data. Therefore, the arithmetic processing means does not need to perform serial communication with the clock means every time the date and time data is acquired. Thus, the gaming machine according to the present invention can reduce the load on the arithmetic processing means.

  Further, the gaming machine according to the present invention may be configured such that the predetermined date and time data stored in the arithmetic storage means is added until the elapsed time calculated by the elapsed time calculation means is added to the date and time represented by the date and time data stored in the arithmetic storage means. By adding the time, the date and time data stored in the arithmetic storage unit is updated only by the addition process without performing the division process with a high processing load, so that the load on the arithmetic processing unit can be reduced.

  In the gaming machine according to the present invention, the date and time data updating means may repeat a process of subtracting a prescribed elapsed time from the elapsed time and updating the date and time data until the subtraction result is less than a prescribed elapsed time. It may be.

  According to the present invention, it is possible to provide a gaming machine capable of reducing the load on the arithmetic processing means.

<Summary 9>
A gaming machine that causes a CPU to execute a program stored in a ROM has been proposed in Japanese Patent Application Laid-Open No. 2000-296223. Japanese Patent Application Laid-Open No. 2008-148891 proposes a gaming machine in which a program stored in a ROM is transferred to a RAM by boot processing at the time of startup, and the program transferred to the RAM is executed by a CPU.

  In a conventional gaming machine that causes a processing unit such as a CPU to execute a program stored in a ROM, the processing unit accesses the ROM each time the program is executed. Processing speed was reduced. On the other hand, a conventional gaming machine that causes an arithmetic processing unit such as a CPU to execute a program transferred to a RAM increases the necessary capacity of the RAM, thus increasing costs.

  The present invention has been made to solve such a problem, and an object of the present invention is to provide a gaming machine capable of improving the processing speed of an arithmetic processing unit without increasing costs.

The gaming machine according to the present invention,
Arithmetic processing means (sub CPU 81) for performing arithmetic processing;
First storage means (sub-ROM 82) in which a program and data for operating the arithmetic processing means are stored;
A second storage unit (sub-RAM 83) having a higher access speed than the first storage unit and being rewritable;
The arithmetic processing means,
Transferring a predetermined program among the programs stored in the first storage means to the second storage means,
And executing the predetermined program transferred from the host program corresponding to the predetermined program to the second storage means.

  With this configuration, the gaming machine according to the present invention transfers a program having a relatively high processing load as the predetermined program to the second storage unit and executes the program, so that the processing speed of the arithmetic processing unit can be improved.

  Further, the gaming machine according to the present invention executes a program other than the predetermined program in a state stored in the first storage means, thereby suppressing a storage capacity required for the second storage means, thereby reducing costs. be able to.

  Note that, in the gaming machine according to the present invention, when transferring the predetermined program to the second storage means, the arithmetic processing means sets a first argument of the predetermined program stored in the first storage means. The second argument may be a start address of the transfer destination of the second storage means, and the third argument may be a program capacity of a predetermined program stored in the first storage means.

  According to the present invention, it is possible to provide a gaming machine capable of improving the processing speed of the arithmetic processing unit without increasing costs.

<Summary 10>
In order to solve the same problem as in the summary 9, the gaming machine according to the present invention
Arithmetic processing means (sub CPU 81) for performing arithmetic processing;
First storage means (sub-ROM 82) in which a program and data for operating the arithmetic processing means are stored;
A second storage unit (sub-RAM 83) having a higher access speed than the first storage unit and being rewritable;
The arithmetic processing means,
Executing the predetermined program among the programs stored in the first storage means as an opportunity to transfer the predetermined program to the second storage means;
And executing the predetermined program transferred from the host program corresponding to the predetermined program to the second storage means.

  With this configuration, the gaming machine according to the present invention can execute the predetermined processing by transferring the predetermined program to the second storage means and executing the predetermined program when the relatively high processing load is executed as the predetermined program. The processing speed of the means can be improved.

  Further, the gaming machine according to the present invention executes a program other than the predetermined program in a state stored in the first storage means, thereby suppressing a storage capacity required for the second storage means, thereby reducing costs. be able to.

  Note that, in the gaming machine according to the present invention, when transferring the predetermined program to the second storage means, the arithmetic processing means sets a first argument of the predetermined program stored in the first storage means. The second argument may be a start address of the transfer destination of the second storage means, and the third argument may be a program capacity of a predetermined program stored in the first storage means.

  According to the present invention, it is possible to provide a gaming machine capable of improving the processing speed of the arithmetic processing unit without increasing costs.

<Summary 11>
In order to solve the same problem as in the summary 9, the gaming machine according to the present invention
Arithmetic processing means (sub CPU 81) for performing arithmetic processing;
First storage means (sub-ROM 82) in which a program and data for operating the arithmetic processing means are stored;
A second storage unit (sub-RAM 83) having a higher access speed than the first storage unit and being rewritable;
The arithmetic processing means,
A predetermined program among the programs stored in the first storage means is previously transferred to the second storage means,
And executing the predetermined program transferred from the host program corresponding to the predetermined program to the second storage means.

  With this configuration, the gaming machine according to the present invention improves the processing speed of the arithmetic processing unit by transferring a program having a relatively high processing load as the predetermined program in advance to the second storage unit and executing the program. be able to.

  Further, the gaming machine according to the present invention executes a program other than the predetermined program in a state stored in the first storage means, thereby suppressing a storage capacity required for the second storage means, thereby reducing costs. be able to.

  Note that, in the gaming machine according to the present invention, when transferring the predetermined program to the second storage means, the arithmetic processing means sets a first argument of the predetermined program stored in the first storage means. The second argument may be a start address of the transfer destination of the second storage means, and the third argument may be a program capacity of a predetermined program stored in the first storage means.

  According to the present invention, it is possible to provide a gaming machine capable of improving the processing speed of the arithmetic processing unit without increasing costs.

<Summary 12>
In order to solve the same problem as in the summary 9, the gaming machine according to the present invention
Arithmetic processing means (sub CPU 81) for performing arithmetic processing;
First storage means (sub-ROM 82) in which a program and data for operating the arithmetic processing means are stored;
A second storage unit (sub-RAM 83) having a higher access speed than the first storage unit and being rewritable;
The arithmetic processing means,
When executing a predetermined program among the programs stored in the first storage means, if the predetermined program has not been transferred to the second storage means, the predetermined program is transferred to the second storage means. And
And executing the predetermined program transferred from the host program corresponding to the predetermined program to the second storage means.

  With this configuration, the gaming machine according to the present invention stores the predetermined program in the second storage device when the predetermined program is not transferred to the second storage means when executing the program having a relatively high processing load as the predetermined program. The processing speed of the arithmetic processing means can be improved by transferring the data to the means and executing it.

  Further, when executing the predetermined program, the gaming machine according to the present invention executes the predetermined program which has been transferred to the second storage means if the predetermined program has been transferred to the second storage means. The processing of the arithmetic processing means for transferring the program to the second storage means can be omitted.

  Further, the gaming machine according to the present invention executes a program other than the predetermined program in a state stored in the first storage means, thereby suppressing a storage capacity required for the second storage means, thereby reducing costs. be able to.

  Note that, in the gaming machine according to the present invention, when transferring the predetermined program to the second storage means, the arithmetic processing means sets a first argument of the predetermined program stored in the first storage means. The second argument may be a start address of the transfer destination of the second storage means, and the third argument may be a program capacity of a predetermined program stored in the first storage means.

  According to the present invention, it is possible to provide a gaming machine capable of improving the processing speed of the arithmetic processing unit without increasing costs.

<Summary 13>
In order to solve the same problem as in the summary 9, the gaming machine according to the present invention
Arithmetic processing means (sub CPU 81) for performing arithmetic processing;
First storage means (sub-ROM 82) in which a program and data for operating the arithmetic processing means are stored;
A second storage unit (sub-RAM 83) having a higher access speed than the first storage unit and being rewritable;
The arithmetic processing means,
If an area for transferring a predetermined program among the programs stored in the first storage means is secured in the second storage means, transfer the predetermined program to the second storage means;
If an area for transferring the predetermined program is not secured in the second storage means, an area for transferring the predetermined program is secured in the second storage means, and the predetermined program is transferred to the secured area.
And executing the predetermined program transferred from the host program corresponding to the predetermined program to the second storage means.

  With this configuration, the gaming machine according to the present invention can improve the processing speed of the arithmetic processing unit by transferring a program having a relatively high processing load as the predetermined program to the second storage unit and executing the program. .

  Further, the gaming machine according to the present invention secures an area for transferring a predetermined program in the second storage means if an area for transferring the predetermined program is not secured in the second storage means, and stores a predetermined area in the secured area. Since the program is transferred and executed, the processing speed of the arithmetic processing means can be reliably improved.

  Further, the gaming machine according to the present invention executes a program other than the predetermined program in a state stored in the first storage means, thereby suppressing a storage capacity required for the second storage means, thereby reducing costs. be able to.

  Note that, in the gaming machine according to the present invention, when transferring the predetermined program to the second storage means, the arithmetic processing means sets a first argument of the predetermined program stored in the first storage means. The second argument may be a start address of the transfer destination of the second storage means, and the third argument may be a program capacity of a predetermined program stored in the first storage means.

  According to the present invention, it is possible to provide a gaming machine capable of improving the processing speed of the arithmetic processing unit without increasing costs.

<Summary 14>
A gaming machine in which LEDs are arranged in a dot matrix to constitute a display unit is proposed in Japanese Patent Application Laid-Open No. 2005-323768.

  In order to control the light emission of a light emitting unit composed of a plurality of light emitters, such as an LED arranged in a dot matrix, all light emission patterns are stored in a ROM or the like, and the light emission patterns are appropriately updated. . For this reason, it is necessary to prepare a large amount of light emission patterns in accordance with the contents of the effect, and the confirmation and change thereof are burdened on the developer and the confirmer.

  The present invention has been made in order to solve such a problem, and an object of the present invention is to provide a gaming machine capable of reducing a burden of checking and changing a light emitting pattern of a light emitting unit.

The gaming machine according to the present invention,
A light-emitting section (first lamp group 111, seventh lamp group 117, eighth lamp group 118, dot matrix section 119) composed of a plurality of light-emitting bodies (LEDs);
A control unit (sub CPU 81) for controlling a light emitting pattern of the light emitting unit;
Pattern data storage means (sub-ROM 82) storing a plurality of light emission data and a plurality of part data for controlling the light emission pattern of the light emitting section,
The part data is
Identification information for identifying the part data;
Pattern data representing a light emitting pattern of the light emitting section;
Attribute data indicating the attribute of the part data,
The light emission data represents the order of the identification information of the part data,
The control unit includes:
From a plurality of light emission data stored in the pattern data storage means, determine light emission data, control the light emitting unit with pattern data included in the part data according to the order of identification information represented by the determined light emission data,
After controlling the light emitting unit with the pattern data included in the part data corresponding to the last identification information in the light emission data, the attribute data included in the part data corresponding to the last identification information in the light emission data performs continuous reproduction. The attribute data is searched for part data indicating continuous reproduction from the head of the identification information represented by the light emission data, and the part data is converted from the detected part data to the part data in accordance with the order of the identification information represented by the light emission data. The light emitting section is controlled by the included pattern data.

  With this configuration, the gaming machine according to the present invention can cause the light emitting unit to execute various effects by combining the part data, so that the light emitting pattern of the light emitting unit can be confirmed and changed in parts data units. . Thus, the gaming machine according to the present invention can reduce the burden of checking and changing the light emission pattern of the light emitting unit.

  Further, the gaming machine according to the present invention causes the light emitting unit to repeatedly execute the effect by the part data whose attribute data is set to the continuous reproduction. The burden on checking and changing the light emission pattern of the unit can be reduced.

  According to the present invention, it is possible to provide a gaming machine capable of reducing the burden of checking and changing the light emitting pattern of the light emitting unit.

<Summary 15>
In order to solve the same problem as in the summary 14, the gaming machine according to the present invention
A light-emitting section (first lamp group 111, seventh lamp group 117, eighth lamp group 118, dot matrix section 119) composed of a plurality of light-emitting bodies (LEDs);
A control unit (sub-CPU 81) for controlling the light-emitting pattern of the light-emitting unit; and a light-emitting data storage unit (sub-ROM 82) storing a plurality of light-emitting data and a plurality of part data for controlling the light-emitting pattern of the light-emitting unit. And a gaming machine having
The part data is
Identification information for identifying the part data;
Pattern data representing a light emitting pattern of the light emitting section;
Attribute data indicating the attribute of the part data,
The light emission data represents the order of the identification information of the part data,
The control unit includes:
From a plurality of light emission data stored in the light emission data storage means, determine the light emission data, control the light emitting unit with the pattern data included in the part data according to the order of the identification information represented by the determined light emission data,
After controlling the light emitting unit with the pattern data included in the part data corresponding to the last identification information in the light emission data, the attribute data included in the part data corresponding to the last identification information in the light emission data performs continuous reproduction. On condition that the part data is represented, the attribute data is searched from the beginning of the identification information represented by the light emission data for part data representing continuous reproduction, and the detected part data is converted to the part data according to the order of the identification information represented by the light emission data. Controlling the light emitting unit with the included pattern data,
When the gaming machine returns from the error state, the attribute data indicates the continuous reproduction from the order of the identification information of the parts data represented by the error state data being executed when the gaming machine enters the error state. The light emitting unit is controlled by the pattern data included in the part data in accordance with the order of the identification information represented by the light emission data from which the identification information of the part data is removed.

  With this configuration, the gaming machine according to the present invention can cause the light emitting unit to execute various effects by combining the part data, so that the light emitting pattern of the light emitting unit can be confirmed and changed in parts data units. . Thus, the gaming machine according to the present invention can reduce the burden of checking and changing the light emission pattern of the light emitting unit.

  Further, the gaming machine according to the present invention causes the light emitting unit to repeatedly execute the effect by the part data whose attribute data is set to the continuous reproduction. The burden on checking and changing the light emission pattern of the unit can be reduced.

  Further, when the gaming machine according to the present invention returns from the error state, the attribute data is converted to the part data according to the order of the identification information represented by the new effect data excluding the identification information of the part data in which the attribute data does not represent the continuous reproduction. Since the light-emitting unit is controlled by the included pattern data, it is possible to prevent an effect that does not fit the game state from being executed by reproducing the effect data from the beginning at the time of error recovery.

  According to the present invention, it is possible to provide a gaming machine capable of reducing the burden of checking and changing the light emitting pattern of the light emitting unit.

<Summary 16>
In order to solve the same problem as in the summary 14, the gaming machine according to the present invention
A light-emitting section (first lamp group 111, seventh lamp group 117, eighth lamp group 118, dot matrix section 119) composed of a plurality of light-emitting bodies (LEDs);
Light emission driving means (LED driver IC) for driving the light emitting unit;
A control unit (sub CPU 81) for controlling a light emitting pattern of the light emitting unit;
Light emission data storage means (sub-ROM 82) storing a plurality of light emission data and a plurality of part data for controlling the light emission pattern of the light emitting section;
The part data is
Identification information for identifying the part data;
Pattern data representing a light emitting pattern of the light emitting section;
Attribute data indicating the attribute of the part data,
The light emission data represents the order of the identification information of the part data,
The control unit includes:
From the plurality of luminescence data stored in the luminescence data storage means, determine the luminescence data, the luminance value of the luminous body included in the pattern data of the part data according to the order of the identification information represented by the determined luminescence data, The light emitting unit is converted to a luminance value according to the light emission driving unit, and the light emitting unit is controlled by transmitting control data based on the converted luminance value to the light emission driving unit by serial bus communication,
After controlling the light emitting unit with the pattern data included in the part data corresponding to the last identification information in the light emission data, the attribute data included in the part data corresponding to the last identification information in the light emission data performs continuous reproduction. The attribute data is searched for part data indicating continuous reproduction from the head of the identification information represented by the light emission data, and the part data is converted from the detected part data to the part data in accordance with the order of the identification information represented by the light emission data. The light emitting section is controlled by the included pattern data.

  With this configuration, the gaming machine according to the present invention can cause the light emitting unit to execute various effects by combining the part data, so that the light emitting pattern of the light emitting unit can be confirmed and changed in parts data units. . Thus, the gaming machine according to the present invention can reduce the burden of checking and changing the light emission pattern of the light emitting unit.

  Further, the gaming machine according to the present invention causes the light emitting unit to repeatedly execute the effect by the part data whose attribute data is set to the continuous reproduction. The burden on checking and changing the light emission pattern of the unit can be reduced.

  Further, the gaming machine according to the present invention converts the luminance value of the illuminant included in the pattern data into a luminance value corresponding to the light emission driving unit, and transmits control data based on the converted luminance value to the light emission driving unit. Since the light emitting unit is controlled, the light emitting unit can be controlled by pattern data that does not depend on the specification of the light emission driving unit.

  According to the present invention, it is possible to provide a gaming machine capable of reducing the burden of checking and changing the light emitting pattern of the light emitting unit.

1 Pachislot (game machine)
81 Sub CPU (control unit, arithmetic processing unit, date and time obtaining unit, counting unit, elapsed time calculating unit, date and time data updating unit)
82 Sub ROM (pattern data storage means, monthly table storage means, first storage means, effect data storage means)
83 Sub RAM 83 (operation storage means, second storage means)
84 Oscillation circuit (clock generation means)
86 RTC (measuring means)
111 First lamp group (light-emitting unit, second light-emitting body group)
117 Seventh Lamp Group (Light Emitting Unit, Second Light Emitting Body Group)
118 eighth lamp group (light-emitting unit, second light-emitting body group)
119 dot matrix section (light-emitting section, first light-emitting body group)
121a to 121b, 127a to 127d, 128a to 128c, 129a to 129g Driver IC (light emission driving means)

Claims (2)

Arithmetic processing means for performing arithmetic processing;
First storage means for storing a program and data for operating the arithmetic processing means,
An access speed higher than the first storage means, and rewritable second storage means,
The arithmetic processing means,
Executing the predetermined program among the programs stored in the first storage means as an opportunity to transfer the predetermined program to the second storage means;
A gaming machine which executes the predetermined program transferred from a higher-level program corresponding to the predetermined program to the second storage means. The arithmetic processing means, when transferring a predetermined program to the second storage means, sets a first argument as a start address of the predetermined program stored in the first storage means, and sets a second argument as the 2. The gaming machine according to claim 1, wherein a transfer destination start address of the second storage means is set, and a third argument is a program capacity of a predetermined program stored in the first storage means.

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