JP2023046287A - Surface-mounted piezoelectric oscillator - Google Patents

Abstract

To improve electrical characteristics by reducing adverse influences of floating capacitance caused by a wiring pattern of a surface-mounted piezoelectric oscillator.SOLUTION: The present invention relates to a surface-mounted piezoelectric oscillator comprising: an integrated circuit element 2 incorporating an amplifier for oscillation; a piezoelectric vibration element 3 connected to an input side and an output side of the integrated circuit element; and a base 1 of which the storage part consists of a ceramic substrate. A pair of wiring patterns for piezoelectric vibration element connecting the integrated circuit element and the piezoelectric vibration element is included in the storage part, and a wiring pattern for power supply and a wiring pattern for grounding are included in an intermediate layer between the storage part, and a bottom face of a sheath part. A superposing part superposing the wiring pattern for power supply and the wiring pattern for grounding with the pair of wiring patterns for piezoelectric vibration element entirely or partially in a planar view is included.SELECTED DRAWING: Figure 8

Description

The present invention relates to a surface mount piezoelectric oscillator.

2. Description of the Related Art Piezoelectric oscillators using a piezoelectric vibrating element such as a crystal diaphragm can stably obtain an oscillation frequency with high precision, and are therefore used in various fields as a reference frequency source for electronic equipment and the like. A surface-mounted piezoelectric oscillator uses a ceramic multilayer substrate as an insulating base, and an integrated circuit element for an oscillator circuit is placed in the housing of the base, and a crystal diaphragm is supported and fixed above the integrated circuit element. , and hermetically sealed with a lid. Such a configuration has a relatively small number of parts due to the customization of the integrated circuit element, is a simple configuration, and contributes to cost reduction.

In such a piezoelectric oscillator, after the package is hermetically sealed, the input/output electrodes of the piezoelectric vibrating element are directly packaged in the ceramic base, as shown in Patent Document 1, in order to measure the characteristics of the piezoelectric vibrating element alone from the outside. A configuration for deriving to the outside is considered. In other words, a metallized wiring pattern is formed on the ceramic base so as to be connected to the input/output electrodes of the single piezoelectric vibrating element, and the metallized wiring pattern is led out to the castellation part formed on a part of the side end of the ceramic base for measurement. make up the terminal. By measuring in a state in which the measurement terminal of the piezoelectric oscillator configured in this way and the contact probe of the piezoelectric vibration element characteristic measuring device are in contact with each other, it is possible to measure the piezoelectric vibration rather than the characteristics of the entire oscillation circuit without other circuit parts intervening. Device properties can be measured.

By the way, as shown in Patent Document 1, recent surface-mounted piezoelectric oscillators are equipped with a one-chip integrated circuit element with a built-in oscillation amplifier and a piezoelectric vibrating element as an oscillation reference source in a housing portion of a ceramic base. It is common to construct an oscillation circuit by For example, as an oscillation circuit configuration of an oscillation amplifier, as disclosed in Patent Document 1, capacitive elements (divided capacitors C1 and C2) are provided on the input side (gate side) and the output side (drain side) of the oscillation amplifier, respectively. are connected in series, and a piezoelectric vibration element and a feedback resistor R1 are connected in parallel between the oscillation amplifier and the capacitive element.

Actual Kaihei 5-65110

In the oscillation circuit configuration with such a built-in oscillation amplifier, due to the design of the wiring pattern of the external circuit in which the surface-mounted piezoelectric oscillator is mounted later, the wiring pattern of the surface-mounted piezoelectric oscillator is arranged in close proximity to the wiring pattern. As a result, an unintended new stray capacitance may be formed. In particular, when new stray capacitance is formed in the wiring pattern that connects the piezoelectric vibrating element and the oscillation amplifier, it directly affects the characteristics of the oscillation circuit, causing variations in the design of the oscillation circuit due to frequency determination. There are concerns that it will become easier.

To address this problem, in the wiring pattern structure of the surface-mounted piezoelectric oscillator as described above, no consideration is given to reducing, as much as possible, the adverse effects of stray capacitance on the oscillation circuit configuration that incorporates the oscillation amplifier. is common. In other words, the stray capacitance may change greatly depending on the connection arrangement between the terminals of the surface-mounted piezoelectric oscillator.

In order to solve the above-mentioned problems, the present invention reduces the adverse effects of stray capacitance caused by the wiring pattern of a surface-mounted piezoelectric oscillator having an oscillation circuit configuration that incorporates an oscillation amplifier. It is an object of the present invention to provide a highly reliable surface-mounted piezoelectric oscillator capable of eliminating variations in the electrical characteristics of the oscillator and improving its electrical characteristics.

In order to achieve the above object, the present invention
An integrated circuit element having a built-in oscillation amplifier, a piezoelectric vibrating element having a pair of excitation electrodes connected to the integrated circuit element, and a ceramic substrate are laminated to form a storage section and an exterior section. and an insulative base having a plurality of wiring patterns formed on the bottom surface of the exterior and external terminals connected to a part of the wiring patterns. a wiring pattern surface, the first wiring pattern surface having at least a pair of piezoelectric vibrating element wiring patterns for connecting terminals of an oscillation amplifier of the integrated circuit element and excitation electrodes of the piezoelectric vibrating element; A second wiring pattern surface is provided between the first wiring pattern surface and the bottom surface of the exterior part, and the second wiring pattern surface has at least two DC wiring patterns having different functions, It is characterized by having an overlapping portion in which the two DC wiring patterns and all or part of the pair of wiring patterns for the piezoelectric vibrating element are superimposed in plan view.

With the above configuration, all or part of the pair of piezoelectric vibrating element wiring patterns connected to the oscillation amplifier of the integrated circuit element constitutes a superimposed portion in which at least two DC wiring patterns having different functions are superimposed. Thus, it is possible to form a structurally stable capacitance forming region having a predetermined gap dimension through the laminated surfaces of the ceramic substrates. This capacitance formation region does not cause new stray capacitance to increase when wiring patterns such as external circuits are placed in unintended positions later, so the stray capacitance does not change and is electrically stable. can be a region.

In addition, in the present invention, the wiring pattern on the second wiring pattern surface that overlaps all or part of the wiring pattern for the piezoelectric vibrating element on the first wiring pattern surface is divided into at least two DC wiring patterns having different functions. Therefore, it is possible to easily form a structurally stable capacitor forming region in a wider range without forming a complicated wiring pattern. In particular, regarding the wiring pattern on the second wiring pattern surface, compared to the case where the capacitance forming region is configured with only one DC wiring pattern, the routing of the two DC wiring patterns using the second wiring pattern surface, the wiring pattern shape, etc. By dramatically improving the degree of design freedom, it becomes easier to design connections to wiring patterns on the upper layer and external terminal pads for mounting on the lower layer, and connections can be made over shorter distances. You can also reduce the impedance of the wiring associated with power and ground.

That is, by using at least two DC wiring patterns having different functions, it is possible to construct a capacitance forming region with a wider range and a higher degree of freedom in design, and the oscillation circuit as a whole can be formed more efficiently without forming a complicated wiring pattern. Stabilization of circuit characteristics can be realized. In addition, variations in design associated with determining the frequency of the oscillation circuit of the surface-mounted piezoelectric oscillator can be suppressed. By forming a new stray capacitance, the voltage-controlled piezoelectric oscillator does not lower the frequency variable amount and the frequency variable sensitivity, and the frequency variable balance can be improved.

Also, the two DC wiring patterns may be composed of a wiring pattern for power supply and a wiring pattern for grounding. The wiring pattern for power supply and the wiring pattern for grounding are indispensable wiring patterns for the piezoelectric oscillator, and in order to lower the impedance of the wiring, the characteristics are stabilized by forming a relatively large exclusive area on the insulating base. is common. In the present configuration, by effectively utilizing such a wiring pattern, it is possible to form a capacitor forming region that is structurally stable and advantageous for miniaturization without unnecessarily increasing the area of the wiring pattern. can.

According to the above invention, for a surface-mounted piezoelectric oscillator having an oscillation circuit configuration incorporating an oscillation amplifier, the adverse effects of stray capacitance caused by its wiring pattern are reduced, variations in the oscillation circuit design are eliminated, and electrical It is possible to provide a more reliable surface-mounted piezoelectric oscillator with improved characteristics.

1 is a diagram showing an oscillator circuit applied to the present invention; FIG. 1 is a plan view of a base before mounting a piezoelectric vibrating element and sealing a lid, showing an embodiment of the present invention; FIG. FIG. 3 is a plan view of the base before mounting the integrated circuit element and the piezoelectric vibrating element in FIG. 2 ; FIG. 3 is a plan view of a first intermediate substrate having a piezoelectric vibrating element mounting surface excluding the upper substrate of the base in FIG. 2 ; FIG. 3 is a plan view of a second intermediate substrate having an integrated circuit element mounting surface excluding the upper substrate and the first intermediate substrate of the base in FIG. 2; FIG. 3 is a plan view of a lower substrate having a second wiring pattern surface excluding the upper substrate, the first intermediate substrate, and the second intermediate substrate of the base of FIG. 2; Bottom view of Figure 2 1 is a schematic cross-sectional view showing a state in which a piezoelectric vibrating element is mounted and a lid is sealed, showing an embodiment of the present invention; FIG. FIG. 2 is a bottom view of an integrated circuit device applied to the present invention; FIG. 11 is a plan view of a lower substrate having a second wiring pattern surface excluding the upper substrate, the first intermediate substrate, and the second intermediate substrate, showing a modified example of the embodiment of the present invention;

DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will now be described with reference to the drawings, taking as an example a surface-mounted crystal oscillator (surface-mounted piezoelectric oscillator) using a ceramic multilayer substrate base. FIG. 1 is a diagram showing an oscillation circuit applied to a surface-mounted crystal oscillator of the present invention, and FIG. 2 is a plane of a base before mounting a piezoelectric vibrating element and sealing a lid showing an embodiment of the present invention. 3 is a plan view of the base before mounting the integrated circuit element and the piezoelectric vibration element in FIG. 2, and FIG. 4 is the first intermediate substrate having the piezoelectric vibration element mounting surface excluding the upper substrate of the base in FIG. FIG. 5 is a plan view of a second middle substrate having an integrated circuit element mounting surface excluding the upper substrate and the first middle substrate of the base in FIG. 2, and FIG. 6 is the upper substrate and the first middle substrate of the base in FIG. FIG. 7 is a bottom view of FIG. 2, FIG. 8 is a plan view of the lower substrate having the second wiring pattern surface excluding the substrate and the second middle substrate, and FIG. FIG. 9 is a schematic cross-sectional view in a stopped state, and FIG. 9 is a bottom view showing an integrated circuit element applied to the surface-mounted crystal oscillator of the present invention.

In this embodiment, for example, the surface-mounted crystal oscillator 6 has an outer size in plan view (the outer dimensions of the base 1 in plan view) of about 3.2 mm (long side)×2.5 mm (short side). A base 1 (hereinafter referred to as a base) made of an insulating ceramic multilayer substrate having a concave portion with an upper opening, an integrated circuit element 2 housed in the base, and an upper portion in the base. and a lid 4 joined to the opening of the base.

In this surface-mounted crystal oscillator, a base 1 and a lid 4 are heat-melted and hermetically sealed using a sealing material 5, which will be described later, to form a surface-mounted crystal oscillator 6. FIG. It should be noted that the outer size of the surface-mounted crystal oscillator in a plan view described above is merely an example, and the present invention can be applied to a package size other than the outer size. An outline of each member constituting the surface-mounted crystal oscillator 6 will be described in detail below.

The base 1 of the ceramic multilayer substrate is a rectangular parallelepiped as a whole, and the bottom substrate 11 is a single plate made of a ceramic material such as alumina, which is rectangular in plan view. A single rectangular second middle substrate 12, a frame-shaped first middle substrate 13 made of a ceramic material laminated on the second middle substrate 12, and a frame-shaped uppermost ceramic material. It is formed into a box-like body having a recessed housing portion 10 and an exterior portion covering them when viewed in cross section. The first intermediate substrate 13 and the upper substrate 14, which constitute the storage area for the integrated circuit element 2 and the piezoelectric vibrating element 3, which will be described later, have a thickness of about 200 μm to 300 μm with a margin for the thickness of each element. More specifically, it has a thickness of 250 μm. On the other hand, since the lower substrate 11 and the second middle substrate 12 are regions in which only the second wiring pattern described later is formed in the interlayer portion, they are made thinner than the first middle substrate 13 and the like. It has a thickness of about 100 μm to 150 μm, which is about half the thickness of the first intermediate substrate 13, and more specifically, a thickness of 125 μm.

A first intermediate substrate 13 and an upper substrate 14 are formed around the storage portion 10, and the upper surface (end surface) of the upper substrate 14 is formed flat. The storage portion 10 is composed of a lower storage portion 10a and an upper storage portion 10b, which accommodate the integrated circuit element 2 and the piezoelectric vibrating element 3, respectively. The ceramic multilayer substrate is not limited to the base having a four-layer structure as in the present embodiment, and may have a three-layer structure or four or more layers depending on the structure of the storage portion of the base.

The top surface (end surface) of the upper substrate 14, which is the uppermost layer of the base 1 of the ceramic multilayer substrate, is flat and serves as a bonding area (metal film) 14a with the lid 4, which will be described later. The junction region 14a is composed of a metallized layer made of a metallized material such as tungsten or molybdenum, a nickel layer laminated on the metallized layer, and a gold layer laminated on the nickel layer. Tungsten or molybdenum is integrally formed during firing of the ceramic by metallization technology utilizing thick film printing technology, and a nickel layer and a gold layer are plated on the metallization layer in this order.

A plurality of vertically extending castellations C1 are formed on the square of the outer peripheral wall of the base 1, and two vertically extending castellations C2 are formed on a part of the side of the outer peripheral wall of the base 1. . The castellation has a configuration in which arc-shaped or semi-elliptical notches are formed in the outer peripheral wall of the base in the vertical direction. The bonding region 14a is formed by at least one of a conductive via V1 vertically penetrating the first middle substrate 13 and the upper substrate 14 of the base and a wiring pattern (not shown) formed on the castellation C1. are electrically led out to mounting external terminal pads GT2 formed in the later described. By connecting the external terminal pad GT2 for grounding, a metal lid, which will be described later, is grounded via a bonding region 14a, a conductive via, a wiring pattern on the upper part of the castellation, and the like, and the surface mount type crystal oscillator is electromagnetically connected. You can get a shield effect.

Inside the base 1, a lower housing portion 10a is formed on the lower surface of the base 1 and is composed of the first intermediate substrate 13. The lower housing portion 10a for housing the integrated circuit element 2 is formed. and a pillow portion 10d facing the holding table through the lower storage portion. An upper storage portion 10b composed of the upper substrate 14 is formed above the lower storage portion 10a.

Wiring patterns formed on the upper surface of each substrate arranged below the upper substrate 14 will be described below with reference to the drawings.

The mounting surface of the piezoelectric vibrating element 3 is constituted by the upper surface portion of the first intermediate substrate 13, as shown in FIGS. A holding base 10c for mounting a piezoelectric vibrating element 3 described later is formed on the upper surface of the first intermediate substrate 13 (bottom surface of the upper storage portion 10b), and the piezoelectric vibrating element 3 described later is connected to the upper surface thereof. A pair of internal terminal pads NT and a wiring pattern H are formed. The holding table 10c is formed by protruding a part of the second middle substrate 14 toward the housing portion 10. As shown in FIG. The dashed line in FIG. 4 is obtained through the sealing material 5 arranged on the upper part of the upper substrate 14 .

A first measuring pad connected to the first internal terminal pad NT1 is provided on the upper surface of the castellation C2 formed on a part of the outer peripheral side of the first intermediate substrate 13, which is the intermediate layer of the base 1 of the ceramic multilayer substrate. An external terminal pad for measurement GT5 and a second external terminal pad for measurement GT6 connected to the second internal terminal pad NT2 are formed. In the present embodiment, the castellation C2 and the first external terminal pad GT5 for measurement, and the castellation C2 and the second external terminal pad GT6 for measurement are formed in the central portion of the long side wall portion (long side wall portion) of the base 1. are formed facing each other in the example, but it is not limited to this location.

Specifically, as shown in FIG. 4, a first internal terminal pad NT1 connected to one excitation electrode 31 of the piezoelectric vibrating element 3, which will be described later, penetrates the input-side wiring pattern H1 and the first intermediate substrate 13. It is electrically led to the wiring pattern on the upper surface of the second intermediate substrate 12 in the lower layer by the conductive via V2, and is led out by the first external terminal pad GT5 for measurement and the input side wiring pattern H1. A second internal terminal pad NT2 connected to the other excitation electrode 32 of the piezoelectric vibrating element 3, which will be described later, is connected to the lower second intermediate substrate by a conductive via V3 that penetrates and connects the output-side wiring pattern H2 and the first intermediate substrate 13. 12, and is led out by the second external terminal pad GT6 for measurement and the output-side wiring pattern H2. A contact probe of a piezoelectric vibration element characteristic device is brought into contact with the pair of first external terminal pad GT5 for measurement and second external terminal pad GT6 for measurement to measure the characteristic of the piezoelectric vibration element 3 alone, which will be described later. can do.

In the present invention, the mounting surface connected to the integrated circuit element 2 is defined as the first wiring pattern surface, which is constituted by the upper surface portion of the second intermediate substrate 12, as shown in FIGS. A plurality of internal terminal pads MT and wiring patterns I connected to an integrated circuit element 2, which will be described later, are formed side by side on the upper surface of the second intermediate substrate 12 (the bottom surface of the lower housing portion 10a). Specifically, as shown in FIG. 5, the internal terminal pads MT of the base include input-side internal terminal pads MT1 connected to input-side pads 21 (input-side terminals) of the integrated circuit element 2, which will be described later, and input-side internal terminal pads MT1, which will be described later. an output-side internal terminal pad MT2 connected to the output-side pad 22 (output-side terminal) of the integrated circuit element 2, and an internal terminal pad MT3 for other functions connected to another function pad 23 of the integrated circuit element 2, which will be described later. , an internal grounding terminal pad MT4 connected to a grounding pad 24 of the integrated circuit element 2 to be described later, an internal output terminal pad MT5 connected to an output pad 25 of the integrated circuit element 2 to be described later, and an integrated terminal pad MT5 to be described later. A power supply internal terminal pad MT6 connected to the power supply pad 26 of the circuit element 2 is formed. The dotted line in FIG. 5 shows the end portion of the inner peripheral frame of the first middle substrate 13 forming the boundary with the storage portion 10a.

The wiring pattern I of the base includes an input wiring pattern I1 (piezoelectric vibrating element wiring pattern) connecting the input side internal terminal pad MT1 and the first internal terminal pad NT1 together with the conductive via V2, and an output side internal wiring pattern I1. An output side wiring pattern I2 (wiring pattern for piezoelectric vibrating element) connecting the terminal pad MT2 and the second internal terminal pad NT2 together with the conductive via V3, and an internal terminal pad MT3 for other functions and mounting for other functions to be described later. Other function wiring pattern I3 connecting external terminal pad GT3, first grounding wiring pattern I4 connecting internal grounding terminal pad MT4 and mounting external terminal pad GT2 for grounding described later, internal output An output wiring pattern I5 for connecting the terminal pad MT5 and an output mounting external terminal pad GT1, which will be described later, and a first wiring pattern I5 for connecting the power supply internal terminal pad MT6 and a power supply mounting external terminal pad GT4, which will be described later. A wiring pattern I6 for power supply is formed.

The mounting surface of the integrated circuit element 2 and the bottom surface of the base 1 (bottom surface of the exterior part) are composed of the plane side and the bottom side of the laminate of the lower substrate 11 and the second middle substrate 12 . has an interlayer portion between In the present invention, a portion of the surface corresponding to this interlayer portion is defined as a second wiring pattern surface corresponding to the first wiring pattern surface, and as shown in FIG. be done. In the present invention, on the upper surface of the lower substrate 11, two wiring patterns J for grounding and power supply, which are connected to an integrated circuit element 2, which will be described later, with a DC component, occupy most of the area of the upper surface of the lower substrate 11. It is characterized by being formed like this. In the wiring pattern J composed of such a DC component, there is an area where the input side internal terminal pad and the input side wiring pattern are combined (hereinafter referred to as an input side wiring portion), and an output side internal terminal pad and the output side wiring pattern are combined. By facing the region (hereinafter referred to as the output-side wiring portion), it is possible to form a stable capacitance forming region without imparting unnecessary noise to these regions.

Specifically, as shown in FIG. 6, a second grounding wiring pattern J1 connected to a first grounding wiring pattern I4 and a mounting external terminal pad GT2 for grounding described later, and a first power supply wiring are connected to each other. A pattern I6 and a second power supply wiring pattern J2 connected to a mounting external terminal pad GT4 for power supply, which will be described later, are formed. As in the present embodiment, the wiring pattern J composed of the direct-current component to face the input side wiring portion and the output side wiring portion is divided into the second grounding wiring pattern J1 and the second power supply wiring pattern J2. As a result, it is possible to easily form a structurally stable capacitance forming region without forming a complicated wiring pattern. In particular, compared to the case where only the second ground wiring pattern J1 or the second power supply wiring pattern J2 is formed, the degree of freedom in designing the routing of the two DC wiring patterns and the wiring pattern shape using the second wiring pattern surface. With the dramatic improvement in , it becomes easier to design connections to wiring patterns in upper layers and external terminal pads for mounting in lower layers, and connections can be made over shorter distances. You can also reduce the impedance of the wiring associated with power and ground.

The second ground wiring pattern J1 is formed to have a larger planar area than the first ground wiring pattern I4, and the second power supply wiring pattern J2 is formed to have a larger planar area than the first power supply wiring pattern I6. Dotted lines in FIG. 6 show internal terminal pads MT1 to MT6 and wiring patterns I1 to I6 formed on the upper surface of the upper second intermediate substrate 12. FIG. In this embodiment, the DC wiring pattern is composed of two wiring patterns J for grounding and power supply, but may be composed of only one for grounding or only for power supply. Also, DC wiring patterns for other functions may be combined or additionally arranged.

A plurality of mounting external terminal pads GT connected to external components and external equipment are formed on the lower surface (bottom surface) of the lower substrate 11, which is the lowest layer of the base 1 of the ceramic multilayer substrate. Specifically, as shown in FIG. 7, mounting external terminal pads GT1, GT2, GT3, and GT4 are formed, and a castellation C1 (not shown) formed on the base above the mounting external terminal pads GT1 to GT4 is formed. The external wiring patterns are electrically led to the wiring patterns I3 to I6, the second grounding wiring pattern J1, and the second power supply wiring pattern J2. The external mounting terminal pad GT1 is used as an external terminal for oscillation output, the external mounting terminal pad GT2 is used as an external terminal for grounding, and the external mounting terminal pad GT3 is used as a DC terminal such as an OE terminal (Output Enable) and a control voltage terminal (VCONT). are used as external terminals for other functions, and the mounting external terminal pad GT4 functions as an external terminal for power supply.

The base having the structure described above is formed using a well-known ceramic lamination technique or metallization technique, and the internal terminal pads, the external terminal pads, and the wiring pattern are made of tungsten, molybdenum, or the like, similar to the formation of the bonding regions 13a described above. A nickel plated layer and a gold plated layer are formed on the upper surface of the metallized layer.

In the present invention, the input-side internal terminal pad MT1 and the input-side wiring pattern I1 formed on the first wiring pattern surface and the output-side internal terminal pad MT2 and the output-side wiring pattern I2 are formed on the second wiring pattern surface. There is a characteristic point in the overlapping relation between the second ground wiring pattern J1 and the second power supply wiring pattern J2 in plan view. More specifically, as shown in solid areas in FIG. 6, the overlapping portions of these wiring patterns in plan view include the input-side internal terminal pad MT1, the input-side wiring pattern I1, and the second power supply wiring pattern J2. , a first output-side superimposed portion K2 in which the output-side wiring pattern I2 and the second power supply wiring pattern J2 are superimposed in a plan view, an output-side internal terminal pad MT2, and an output-side internal terminal pad MT2. There are three second output-side overlapping portions K3 in which the wiring pattern I2 and the second grounding wiring pattern J1 are superimposed in plan view. Among these, it is more desirable to form the input side superimposed portion K1 in a state where the plan view area is larger than the plan view area of the output side superimposed portions K2 and K3 combined.

In this configuration, the planar view area of the input-side superimposed portion K1 is formed to be larger than the combined area of the output-side superimposed portion K2 and the output-side superimposed portion K3, thereby providing an electrically stable region in which the stray capacitance does not change afterwards. Therefore, in the input side internal terminal pad MT1 and the input side wiring pattern I1 connected to the input side (gate side) of the oscillation amplifier of the integrated circuit element 2, a new stray capacitance is formed and is less likely to increase. The stray capacitance can be made less likely to change more effectively.

In this embodiment, by covering 100% of the planar view area of the input-side wiring portion including the input-side internal terminal pad MT1 and the input-side wiring pattern I1 with the second power supply wiring pattern J2 or the like, the input-side internal The terminal pad MT1 and the input-side wiring pattern I1 are the most preferable form in which the new stray capacitance does not affect them at all. However, even if such a configuration is difficult due to the wiring design of the base, if the ratio of the plane area of the input-side overlapping portion to the plane area of all the input-side wiring portions can be secured at 50% or more, a new The effect of stray capacitance can be effectively eliminated.

Similarly, it is desirable to eliminate the influence of stray capacitance by ensuring that the ratio of the plane area of the output-side overlapping portion to the plane area of all the output-side wiring portions is 50% or more.

In addition to the above embodiment, as shown in the modification of FIG. 10, the input-side internal terminal pad MT1 and the input-side wiring pattern I1 formed on the first wiring pattern surface, the output-side internal terminal pad MT2 and The output-side wiring pattern I2 may be formed by superimposing the second grounding wiring pattern J3 and the second power supply wiring pattern J4 formed on the second wiring pattern surface in plan view. That is, all of the pair of wiring patterns for piezoelectric vibrating elements may have an input side superimposed portion K4 and an output side superimposed portion K5 that are superimposed in plan view. Such a variant is desirable to further eliminate the effects of stray capacitance.

The integrated circuit element 2 mounted on the inner bottom surface of the lower housing portion 10a is a one-chip integrated circuit element containing an oscillation amplifier, and together with the piezoelectric vibrating element 3 constitutes an oscillation circuit. As shown in FIG. 9, on the bottom side thereof, an input side pad 21 connected to the input side of the oscillation amplifier, an output side pad 22 connected to the output side of the oscillation amplifier, and other pads 23 to 26 are formed. In the integrated circuit element 2, a plurality of pads 21 to 26 of the integrated circuit element 2 and internal terminal pads MT1 to MT6 formed on the base 1 are connected by FCB, for example, via metal bumps C such as gold. . In addition, in this embodiment, a configuration in which metal bumps are used for bonding is used as an example, but metal wires may be used.

The integrated circuit element 2 used in the present embodiment is not limited to a so-called SPXO integrated circuit element having only an oscillation circuit section for amplifying the frequency signal of the piezoelectric vibrating element 3, and may be equipped with a frequency adjustment circuit as an additional function. Alternatively, it may be a so-called VCXO integrated circuit element, or a so-called TCXO integrated circuit element having an additional function such as a temperature compensation function. Also, an integrated circuit element in which these are combined may be used. The integrated circuit element 2 may be bipolar or bi-CMOS other than CMOS.

Above the integrated circuit element 2, the piezoelectric vibrating element 3 is mounted with a predetermined interval in the upper storage portion 10b which is the same space as the storage portion 10. As shown in FIG. The piezoelectric vibrating element 3 is, for example, a rectangular AT-cut crystal vibrating plate, and a pair of rectangular excitation electrodes 31 and 32 and their extraction electrodes are formed facing each other on the front and rear surfaces of the piezoelectric vibrating element 3 . These electrodes are, for example, laminated thin films composed of a base electrode layer of chromium or nickel, an intermediate electrode layer of silver or gold, and an upper electrode layer of chromium or nickel, a base electrode layer of chromium or nickel, and a silver electrode layer. Alternatively, it is a laminated thin film composed of a gold upper electrode layer. Each of these electrodes can be formed by a thin film forming means such as a vacuum deposition method or a sputtering method.

The piezoelectric vibrating element 3 and the base 1 are joined together by using, for example, a paste-like silicone-based conductive resin adhesive (conductive joining material) S containing metal micro-pieces such as silver filler. As shown in FIG. 2, the conductive resin adhesive S is applied to the upper surfaces of the first internal terminal pad NT1 and the second internal terminal pad NT2, and the conductive resin adhesive S is applied to the piezoelectric vibration. By interposing between the element 3 and the holding table 10c and hardening, they are electrically and mechanically joined to each other. As described above, while providing a gap between one end of the piezoelectric vibration element 3 and the bottom surface of the lower housing portion 10a of the base 1, the opposite end of the piezoelectric vibration element 3 is joined to the holding table 10c of the base. Cantilevered. In this embodiment, a configuration in which silicone-based conductive resin adhesive is used for bonding is used as an example. may

A lid 4 for airtightly sealing the base 1 has, for example, a structure in which a metal brazing material (sealing material) is formed on a core material made of kovar or the like. It is configured to be bonded to the bonding region (metal film) 13a. The plan view outline of the metal lid is substantially the same as or slightly smaller than the outline of the ceramic base.

The joint region 13a of the base 1, in which the integrated circuit element 2 and the piezoelectric vibration element 3 are stored in the storage portion 10, is covered with the metal lid 4, and the sealing material 5 of the metal lid 4 and the base are separated. The surface-mounted crystal oscillator 6 is completed by melting and hardening the bonding region 13a and hermetically sealing it.

FIG. 1 shows the oscillating circuit configuration of the C-MOS inverter in the surface-mounted crystal oscillator 6 configured as described above. That is, capacitive elements (divided capacitors C1 and C2) are connected in series to the input side (gate side G) and output side (drain side D) of the C-MOS inverter, respectively. Between them, the piezoelectric vibrating element 3 and the feedback resistor R are connected in parallel. In this oscillation circuit, the measurement external terminals X1 and X2 for measuring the electrical characteristics of the piezoelectric vibrating element 3 alone and the mounted external terminal OUT for oscillation output are disclosed. Terminals (power supply, etc.) are not shown.

According to the above-described embodiment, the input side internal terminal pad MT1 and the input side wiring pattern I1 connected to the input side of the oscillation amplifier of the integrated circuit element 2 have an input side wiring pattern superimposed on the second power supply wiring pattern J2 in plan view. A superimposition unit K1 is configured. The output side internal terminal pad MT2 connected to the output side of the oscillation amplifier of the integrated circuit element 2 and the output side wiring pattern I2 are provided with a first output side superimposed portion superimposed on the second power supply wiring pattern J2 in plan view. K2 is configured, and a second output side overlapping portion K3 that overlaps the second grounding wiring pattern J1 in plan view is configured in the output side internal terminal pad MT2 and the output side wiring pattern I2. These superimposed portions can form a structurally stable capacitance forming region constituted by a gap dimension of 125 μm in thickness of the second intermediate substrate 12 through the laminated surface of the ceramic substrate.

These capacitance formation areas are electrically stable areas where the stray capacitance does not change after the fact because new stray capacitance will not be formed when wiring patterns such as external circuits are placed opposite each other later. can be In addition, since the gap dimension is equal to or larger than the thickness of the single plate of the ceramic laminated substrate, the capacitance forming region can be configured with a distance larger than 50 μm with a constant thickness. Therefore, the capacitance can be kept to a relatively small value, and the electrical characteristics of the oscillation circuit can be less affected.

Then, on the first wiring pattern surface, the input side internal terminal pad MT1 and the input side wiring pattern I1 (wiring pattern for piezoelectric vibrating element), the output side internal terminal pad MT2 and the output side wiring pattern I2 (wiring pattern for piezoelectric vibrating element), and Since the wiring pattern on the second wiring pattern surface to be superimposed is divided into the second grounding wiring pattern J1 and the second power supply wiring pattern J2, it is not necessary to form a complicated wiring pattern. , it is possible to easily form a structurally stable capacitor forming region in a wider range.

In other words, the two DC wiring patterns of the second ground wiring pattern J1 and the second power supply wiring pattern J2 can form a capacitance forming region with a wider range and a higher degree of freedom in design, thus forming a complicated wiring pattern. Therefore, it is possible to more efficiently stabilize the circuit characteristics of the oscillation circuit as a whole. In addition, variations in design associated with determining the frequency of the oscillation circuit of the surface-mounted piezoelectric oscillator 6 can be suppressed. By forming a new stray capacitance, the voltage-controlled piezoelectric oscillator does not lower the frequency variable amount and the frequency variable sensitivity, and the frequency variable balance can be improved.

In this embodiment, a single-structure package in which an oscillation amplifier and a piezoelectric vibration element are housed in one housing space is taken as an example. In such a single structure package, the side wiring pattern that connects the oscillation amplifier and the excitation electrode of the piezoelectric vibration element tends to be arranged relatively close to the external circuit board, and is easily affected by stray capacitance. Become. However, by combining the characteristic configuration of the present invention with a single-structure package, these adverse effects can be eliminated, and the benefits of the effects of the present invention can be easily received.

In the present embodiment described above, an AT-cut crystal diaphragm is used as the piezoelectric vibration element, but the present invention is not limited to this, and a tuning-fork type crystal diaphragm may be used. In addition, although crystal is used as the material for the piezoelectric vibrating element, the material is not limited to this, and piezoelectric ceramics or a piezoelectric single crystal material such as LiNbO ₃ may be used. That is, any piezoelectric vibrating element can be applied. Moreover, although the piezoelectric vibrating element is held in a cantilever manner, the piezoelectric vibrating element may be held at both ends. As the conductive bonding material, a silicone-based conductive resin adhesive is used as an example, but other conductive resin adhesives may be used, such as metal bumps, metal-plated bumps, brazing materials, and the like.

Also, in this embodiment, the electrical connection between the integrated circuit element and the base is disclosed as being joined by the flip chip bonding method, but it is not limited to this, and a wire bonding method or the like may be employed. may Although an oscillator circuit configuration using a one-chip integrated circuit element with a built-in oscillator amplifier is used as an example, an oscillator circuit configuration including other oscillator amplifiers may be used.

In addition, in this embodiment, sealing with a metal brazing material was used as an example, but it is not limited to this, and seam sealing, beam sealing (for example, laser beam, electron beam), glass sealing, etc. can also be used. can be applied.

In addition, in this embodiment, a single-structure package using a base having a concave portion that is open only at the top is used as an example, but the present invention can also be applied to a package having an H-shaped cross-section structure having concave portions on the upper and lower surfaces of the base. .

However, the present invention may be embodied in many other forms without departing from its spirit or essential characteristics. Therefore, the above-described embodiments are merely illustrative in all respects and should not be construed in a restrictive manner. The scope of the present invention is indicated by the claims, and is not restricted by the text of the specification. Furthermore, all modifications and changes within the equivalent range of claims are within the scope of the present invention.

INDUSTRIAL APPLICABILITY The present invention can be applied to surface-mounted piezoelectric vibration oscillators.

REFERENCE SIGNS LIST 1 base 2 integrated circuit element 3 piezoelectric vibrating element 4 lid 5 sealing material 6 surface mount crystal oscillator S conductive resin adhesive (conductive bonding material)
C Metal bump

Claims (2)

an integrated circuit element containing an oscillation amplifier;
a piezoelectric vibration element having a pair of excitation electrodes connected to the integrated circuit element;
The storage part and the exterior part are configured by laminating ceramic substrates,
an insulating base having a plurality of wiring patterns formed in the housing and external terminals formed on the bottom surface of the exterior and connected to a part of the wiring patterns,
The upper surface of the storage portion of the base is defined as a first wiring pattern surface,
On the first wiring pattern surface,
at least a pair of piezoelectric vibrating element wiring patterns for connecting terminals of an oscillation amplifier of the integrated circuit element and excitation electrodes of the piezoelectric vibrating element,
A second wiring pattern surface is provided between the first wiring pattern surface and the bottom surface of the exterior part,
On the second wiring pattern surface,
Having at least two DC wiring patterns with different functions,
A surface-mounted piezoelectric oscillator, wherein the two DC wiring patterns and all or part of the pair of wiring patterns for the piezoelectric vibrating element have overlapping portions in a plan view. 2. A surface-mounted piezoelectric oscillator according to claim 1, wherein said two DC wiring patterns comprise a wiring pattern for power supply and a wiring pattern for grounding.

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