JP2023046274A - Support-equipped board and semiconductor device - Google Patents

Abstract

To provide a support-equipped board and a semiconductor device in which stress in a wiring layer is mitigated to reduce susceptibility to the formation of cracks originating from a location where stress is concentrated.SOLUTION: Provided is a support-equipped board including a support and a wiring board provided over the support. An insulating film in the wiring board is composed of a first organic insulating resin. A first surface and a second surface of the wiring board have electrodes that can be bonded to a semiconductor element or the like. An insulating film on at least one surface layer on the top and the bottom of the wiring board is composed of a second organic insulating resin. The coefficient of thermal expansion (CTE) of the second organic insulating resin is smaller than the CTE of the first organic insulating resin.SELECTED DRAWING: Figure 3A

Description

The present invention relates to a substrate with support and a semiconductor device.

When a semiconductor element having a fine wiring circuit is mounted on a mother board, the semiconductor element and the mother board do not match in electrode spacing and size, which serve as connection terminals. For this reason, an intermediate substrate called FC-BGA (Flip Chip-Ball Grid Array) substrate is generally used between the semiconductor element and the motherboard. By using such an intermediate substrate, it becomes possible to change the electrode spacing and size for connection.

However, as semiconductor devices become faster and more highly integrated, the FC-BGA substrate on which semiconductor elements are mounted is also required to have a narrower pitch of junction terminals and finer wiring in the substrate.
On the other hand, there is a demand for bonding by connecting terminals at a pitch that is almost the same as the conventional interval between the connecting terminals of the FC-BGA substrate and the mother board.

In order to cope with the narrowing of the pitch of the junction terminals of such semiconductor elements and the accompanying miniaturization of the wiring in the FC-BGA substrate, an interposer is used as a further intermediate substrate between the FC-BGA substrate and the semiconductor element. A multi-layer wiring board including fine wiring, also called a multi-layer wiring board, is used.
A technology has emerged to mount a plurality of semiconductor elements on an FC-BGA substrate via such an interposer.

Early interposers were manufactured using a semiconductor element manufacturing process technology, which is a silicon wafer processing technology. However, there is a problem that the manufacturing cost increases when using the semiconductor device manufacturing process technology. In addition, an interposer using a silicon wafer has been pointed out to have a problem of transmission characteristics as a problem in terms of the electrical characteristics of silicon itself.
On the other hand, a glass interposer using glass has also been proposed, but there is a problem with the workability of the glass.

Therefore, as a technique for compensating for the defects of the glass interposer, there is a technique for forming the interposer using an organic insulating resin.
In an interposer using an organic insulating resin, a wiring board is formed by using an organic insulating resin and a wiring material on a support that is also called a carrier. A semiconductor device can be manufactured by mounting a semiconductor element on a wiring board, sealing with resin, peeling off the support, and attaching it to an FC-BGA board (Patent Document 1).

U.S. Patent Application Publication No. 2021/0050298

However, when the interposer is formed using an organic insulating resin, the CTE (coefficient of thermal expansion) of the organic insulating resin is larger than that of FC-BGA. detachment and cracks in the organic insulating resin.
In other words, if the ambient temperature changes significantly after the interposer is attached to the FC-BGA, only the organic insulating resin in the wiring board is greatly deformed, causing warping of the wiring board and stress generated inside the wiring board. Become. As a result, peeling of fine wiring layers and the like, and cracks originating from peeled portions and stress-concentrated portions occur.

SUMMARY OF THE INVENTION Accordingly, the present invention has been made in view of the above problems, and provides a wiring board, a support-attached substrate, and a semiconductor device, in which the stress inside the wiring board is relieved and cracks are less likely to occur starting from places where stress concentrates. for the purpose.

In order to solve the above problems, one typical substrate with a support of the present invention is a substrate with a support comprising a support and a wiring board provided above the support,
the insulating film inside the wiring substrate is made of a first organic insulating resin,
The insulating film of the surface layer of the wiring substrate is composed of a second organic insulating resin having a CTE smaller than that of the first organic insulating resin.

According to the present invention, it is possible to provide a support-equipped substrate and a semiconductor device in which the stress inside the wiring substrate is relieved, and cracks starting from places where stress is concentrated are less likely to occur.
Problems, configurations, and effects other than those described above will be clarified by the following description of the mode for carrying out the invention.

FIG. 1A is a diagram for explaining an outline of a semiconductor element and the like. FIG. 1B is a diagram illustrating an outline of a substrate with a support. FIG. 1C is a schematic diagram of a wiring board, a substrate with a support, and a semiconductor device. FIG. 1D is a schematic diagram of a wiring board, a substrate with a support, and a semiconductor device. FIG. 2A is a diagram illustrating a mode of a wiring board from which a support has been removed. FIG. 2B is a diagram illustrating a mode of the wiring board from which the support has been removed. FIG. 2C is a diagram illustrating a mode of a substrate wiring board with a support. FIG. 2D is a diagram illustrating a mode in which the substrate with support is connected to another wiring substrate. FIG. 3A is a cross-sectional view of the substrate with support according to the first embodiment. FIG. 3B is a cross-sectional view of the support-attached substrate of the first embodiment. FIG. 3C is a cross-sectional view of a substrate with support according to the second embodiment. FIG. 3D is a cross-sectional view of the substrate with support of the second embodiment. FIG. 4A is a cross-sectional view of a substrate with support according to the third embodiment. FIG. 4B is a cross-sectional view of a substrate with support according to the fourth embodiment. FIG. 4C is a cross-sectional view of a substrate with support according to the fourth embodiment. FIG. 5 is a diagram for explaining the manufacturing method of the first embodiment. FIG. 6 is a diagram for explaining the manufacturing method of the first embodiment. FIG. 7 is a diagram for explaining the manufacturing method of the first embodiment. FIG. 8 is a diagram for explaining the manufacturing method of the first embodiment. FIG. 9 is a cross-sectional view when electrodes are formed on the substrate with support. FIG. 10A is a cross-sectional view illustrating a method of manufacturing copper posts on a substrate with a support. FIG. 10B is a cross-sectional view explaining a method of manufacturing copper posts on a substrate with a support. FIG. 10C is a cross-sectional view explaining a method of manufacturing copper posts on a substrate with a support. FIG. 10D is a cross-sectional view explaining a method of manufacturing copper posts on a substrate with a support. FIG. 11A is a cross-sectional view explaining a method of manufacturing copper posts on a substrate with a support. FIG. 11B is a cross-sectional view illustrating a method of manufacturing copper posts on a substrate with a support. FIG. 11C is a cross-sectional view illustrating a method of manufacturing copper posts on a substrate with a support. FIG. 11D is a cross-sectional view illustrating a method of manufacturing copper posts on a substrate with a support. FIG. 12 is a cross-sectional view showing a case where a semiconductor device or the like is mounted on a support-attached substrate in which the second insulating resin does not partially cover the first surface of the support-attached substrate.

An embodiment of the present invention will be described below with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimension, the ratio of thickness of each layer, and the like are different from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. In addition, it is a matter of course that there are portions with different dimensional relationships and ratios between the drawings.

Further, the embodiments shown below are examples of devices and methods for embodying the technical idea of the present invention. etc. are not specified below. Various modifications can be made to the technical idea of the present invention within the technical scope defined by the claims.

In the present disclosure, the term “surface” may refer not only to the surface of the plate-like member, but also to the interface between the layers included in the plate-like member that is substantially parallel to the surface of the plate-like member. In addition, the terms "upper surface" and "lower surface" refer to the upper or lower surface of the drawing when a plate-like member or a layer included in the plate-like member is illustrated. The "upper surface" and "lower surface" may also be referred to as "first surface" and "second surface".

In addition, the “side surface” means a surface of a plate-like member or a layer included in the plate-like member or a portion of the thickness of the layer. Furthermore, a part of a surface and a side surface may be collectively referred to as an "end".
Further, "upward" means the vertically upward direction when the plate-like member or layer is placed horizontally. Further, "upward" and "downward" opposite to this are sometimes referred to as "Z-axis positive direction" and "Z-axis negative direction", and horizontal directions are referred to as "X-axis direction" and "Y-axis direction". It is sometimes called "direction".

Further, "planar shape" and "planar view" mean the shape when a surface or layer is viewed from above. Furthermore, the terms "cross-sectional shape" and "cross-sectional view" mean the shape of a plate-like member or layer cut in a specific direction and viewed from the horizontal direction.
The term "semiconductor element or the like" means a semiconductor element, an electronic component having a size approximately equal to that of the semiconductor element, and a wiring board.

<Wiring substrate, substrate with support, semiconductor device>
First, with reference to FIGS. 1A to 2D, the wiring substrate, the substrate with support member, and the outline of the configuration and manufacturing process of the semiconductor device will be described.
FIG. 1A is a schematic cross-sectional view of a semiconductor element or the like 55 connected above a substrate 54 with a support shown in FIG. 1B. FIG. 1B is a schematic cross-sectional view of a support-attached substrate 54 in which a wiring board 52 is formed above a support 51 with a peeling layer 53 interposed therebetween.
The support 51 is mainly made of glass, and the wiring board 52 is made of organic insulating resin. 1A to 2D, the wiring board 52, the semiconductor element or the like 55, and the other wiring board 61 are shown with their internal structures omitted.

Since the wiring substrate 52 is formed above the support 51, the support-attached substrate 54 shown in FIG. 1B is sometimes referred to as a carrier-attached RDL (Re Distribution Layer). Moreover, the upper surface 56 of the wiring board 52 is called a first surface, and the lower surface 57 of the wiring board 52 is called a second surface.
The upper surface 56 of the wiring board 52 is provided with solder 58 for electrical connection with a semiconductor element 55 or the like. Solder 58 is also provided on the side where the semiconductor element or the like 55 in FIG. 1A is connected to the substrate 54 with the support.

FIG. 1C is a schematic cross-sectional view showing a state in which a semiconductor element or the like 55 is mounted on the first surface, which is the upper surface 56 of the wiring substrate 52 of the substrate with support shown in FIG. 1B, and fixed with an underfill 59.

FIG. 1D is a schematic cross-sectional view showing a state in which the support-attached substrate 54 on which the semiconductor element or the like 55 of FIG. 1C is mounted is further fixed with a mold resin 60 .

Next, with reference to FIGS. 2A to 2D, a description will be given of a process of connecting the substrate with the supporting body to which the semiconductor element 55 is fixed by the molding resin 60 shown in FIG. 1D to another wiring substrate 61. FIG. Note that the other wiring board 61 includes, for example, an FC-BGA board.
First, a substrate with a support to which a semiconductor element or the like 55 is fixed by a mold resin 60 shown in FIG. 1D is irradiated with ultraviolet rays from the side of the support 51 made of glass. As a result, the peeling layer 53, which is a functional layer, exhibits a peeling function, and the wiring substrate 52 and the support 51 are peeled off.
Next, as shown in FIG. 2A, solder or copper posts 62 for electrical connection with another wiring board 61 are formed on the lower surface 57 (second surface) of the wiring board 52 .
In addition to solder or copper posts 62, a semiconductor element or the like may be formed on the lower surface 57 of the wiring board 52, as shown in FIG. 2B.

FIG. 2C is a schematic cross-sectional view of another wiring board 61 to which the wiring board 52 from which the support 51 has been removed is connected. Solder or copper posts 62 are also formed on the surface of the other wiring board 61 to which the wiring board 52 is connected.

Next, as shown in FIG. 2D, the fixed semiconductor element 55 and wiring board 52 shown in FIG. 2A or 2B are connected to another wiring board 61 and underfilled 59 to , becomes a semiconductor device.
FIG. 2D shows only the form in which FIGS. 2A and 2C are connected. It is also possible to connect to the wiring board 61 .

Through the configuration and manufacturing process described above, it is possible to mount a semiconductor element with a narrower pitch on another wiring board such as an FC-BGA board.
In the above example, after the semiconductor element is mounted on the substrate with support 54, it is connected to another wiring substrate 61 such as an FC-BGA substrate.
However, before the semiconductor element is mounted on the board 54 with the support, the support 51 is removed, the wiring board 61 such as the FC-BGA board is connected, and the wiring board 61 such as the FC-BGA board is connected. A semiconductor element or the like may be mounted after the connection is made.

[First embodiment]
<Example using the damascene method>
Next, the support-attached substrate 54 of the first embodiment of the present disclosure will be described with reference to FIG. 3A.
The support-attached substrate 54 includes a wiring substrate 52 above a support 51 that is a glass substrate, and a release layer 53 is provided between the support 51 and the wiring substrate 52 .
The wiring board 52 has multiple layers of wiring 64 formed therein by using the damascene method, and the wiring 64 has vias for connecting the wiring portion and the wiring formed in the XY plane direction to each other in the Z-axis direction. included. (Formation of multilayer wiring by the damascene method will be described later.)
Furthermore, the wiring board 52 is formed with a reinforcing layer 68 as a surface layer insulating film and an internal insulating film 67 .
The inner insulating film is made of a first organic insulating resin, and the reinforcing layer is made of a second organic insulating resin. The CTE of the second organic insulating resin is set smaller than the CTE of the first organic insulating resin, and the CTE of the second organic insulating resin is desirably 40 ppm/K or less. Also, the second organic insulating film may contain a filler, and the filler may contain silicon or a silicon compound.
In addition, the wiring and the vias for joining the wiring in the wiring board are made of copper or an alloy containing copper, and a barrier metal layer is provided on a part of the surface that contacts the first or second organic insulating resin. can be done. The barrier metal layer may contain titanium or tantalum, or compounds thereof.

In FIG. 3A, all reinforcing layers 68 of the wiring board 52 are formed using the second organic insulating resin. However, as shown in FIG. 3B, the uppermost reinforcing layer 68 in the Z-axis direction may be formed using the first organic insulating resin.

[Second embodiment]
Next, a second embodiment in which the intermediate layer 50 is provided between the release layer 53 and the reinforcing layer 68 in the first embodiment will be described with reference to FIGS. 3C and 3D.
The second embodiment differs from the first embodiment in that an intermediate layer 50 is provided between the peeling layer 53 and the reinforcing layer 68 . In the following description, the same reference numerals are given to the same or equivalent components as in the first embodiment described above, and the description thereof will be simplified or omitted.
In the second embodiment, intermediate layer 50 is provided between release layer 53 and reinforcing layer 68 of FIGS. 3A and 3B in the first embodiment. The intermediate layer 50 is formed by, for example, a sputtering method or a vapor deposition method, and includes Cu, Ni, Al, Ti, Cr, Mo, W, Ta, Au, Ir, Ru, Pd, Pt, AlSi, AlSiCu, AlCu, NiFe, ITO, IZO, AZO, ZnO, PZT, TiN, Cu ₃ N ₄ , Cu alloys, and combinations of these can be applied. The intermediate layer 50 may be a single layer, or may be multiple layers.

In the second embodiment of the present disclosure, a titanium layer and then a copper layer are sequentially formed by sputtering as the intermediate layer 50 in consideration of electrical properties, ease of manufacture, and cost. When the intermediate layer 50 is also used as a power supply layer for electroplating, the total thickness of the titanium and copper layers is preferably 1 μm or less. In one embodiment of the present disclosure, Ti: 50 nm and Cu: 300 nm are formed.
By providing such an intermediate layer 50, the adhesion between the release layer 53 and the reinforcing layer 68 can be improved, and the support 51 can be prevented from being easily separated.
In addition, it plays a role of preventing mixing of the peeling layer 53 and the reinforcing layer 68 made of the photosensitive insulating resin film, and the peeling between the peeling layer 53 and the intermediate layer 50 can be reliably performed.

<Functions and effects in the first embodiment and the second embodiment>
Conventionally, the insulating film that forms the wiring board 52 is formed of substantially the same material, and as the insulating film that is generally employed, a photosensitive insulating resin has been adopted because pattern formation is easy. The CTE of the photosensitive resin was generally in the range of 50-80 ppm/K.
On the other hand, when the wiring board 52 is joined as part of a semiconductor device, its outer peripheral portion is often covered with a resin layer containing a filler such as a solder resist or underfill. In this case, due to the difference in elastic modulus due to the presence or absence of the filler and the difference in deformation amount due to the difference in CTE, the wiring substrate 52 may warp, peel off, or crack under conditions where the temperature changes.

In order to match the physical properties such as CTE of the wiring board 52 with the material of the outer peripheral portion, it is conceivable to use an insulating resin containing a filler as the photosensitive insulating resin used for the wiring board 52 as well. However, if a filler is included in the insulating resin of the wiring substrate 52 on which fine wiring is formed, the size of the filler determines the limits of thinning and miniaturization, and the necessary miniaturization cannot be achieved. . Further, when a CMP (Chemical Mechanical Polishing) process is included in the manufacturing process of the wiring board, polishing the insulating film containing the filler exposes a part of the filler in a polished state, which causes a problem. Due to the falling off, the surface becomes uneven, making it difficult to form fine wiring. For this reason, filler-containing resin cannot be used for all insulating resins of the wiring board 52 on which fine wiring is formed.

Therefore, in the first embodiment and the second embodiment of the present disclosure, in order to match the physical property values of the wiring board 52 and the material of the outer peripheral portion, the wiring board 52 has physical properties from the surface layer to the inner layer. It is decided to gradually change the difference between That is, for the surface layer, a material having physical properties close to those of the material for the outer peripheral portion is selected, and for the inside of the wiring board 52, a material having conventional physical properties is used. Cracks are suppressed by matching physical property values such as
That is, the CTE of the second organic insulating resin, which is the material of the reinforcing layer 68 of the wiring board 52, is made smaller than the CTE of the first organic insulating resin, which is the material of the insulating film 67 inside the wiring board 52. there is This makes it possible to suppress cracks and lamination inside the wiring board 52 .

There are various methods for reducing the CTE of the insulating resin. For example, it is relatively easy to incorporate a filler into the insulating resin. Even if a filler is mixed in the insulating resin, if the place where the insulating resin mixed with the filler is arranged is a place such as the reinforcing layer 68 where electrodes are mainly formed and where fine wiring is not required, the filler is used. There is no big problem even if the material of is used.

[Third Embodiment]
<Example using SAP method>
Next, a substrate with support according to a third embodiment of the present disclosure will be described with reference to FIG. 4A.
The third embodiment is different from the first and second embodiments in that the wiring board 52 uses a known semi-additive method (SAP method). In the following description, the same reference numerals are given to the same or equivalent components as in the first embodiment described above, and the description thereof will be simplified or omitted.
In the third embodiment as well, although the wiring forming method is different from the damascene method, there is no great difference in effects such as crack resistance. This will be described later in the description of the embodiment.
In addition, in FIG. 4A for explaining the third embodiment, the intermediate layer 50 disclosed in the second embodiment is not shown. , an intermediate layer 50 may be provided on top of the release layer 53 .

[Fourth Embodiment]
<Example in which the second insulating resin does not cover a part of the wiring board>
Next, a substrate with support according to a fourth embodiment of the present disclosure will be described with reference to FIG. 4B.
In the fourth embodiment, the reinforcing layer 68 covers only a part of the upper surface of the wiring board 52, and the first insulating resin of the inner insulating film 67 is exposed in the uncovered part. It differs from the second and third embodiments. This can also be implemented for the first embodiment.

Alternatively, as shown in FIG. 4C, a plating resist 69, for example, is placed on a portion of the lower surface of the wiring board 52 instead of the reinforcing layer 68, and the plating resist 69 is removed after the support 51 is peeled off. Also, a structure in which only a portion of the lower surface of the wiring board 52 is covered with the reinforcing layer 68 can be employed. The structure in which the reinforcing layer 68 partially covers the wiring board 52 may be on one side or both sides. It can also be implemented for the first embodiment.

<Action/effect>
If the reinforcement layer 68 containing filler is used, especially when the diameter of the filler is large, the filler may hinder the formation of fine wiring, for example, resist patterning in the damascene method. Moreover, in the SAP method, there is a possibility that the filler cannot be sufficiently coated, for example, the filling of the gaps between the insulating resins is inhibited.

There is a possibility that these problems may occur particularly in a portion where solder 58, which is a fine electrode for mounting a semiconductor element or the like 55, is formed. Therefore, it is possible to take a means of not covering the reinforcement layer 68 around the area where the electrodes of the solder 58 for mounting the semiconductor element 55 are arranged.
In addition, when some patterning is performed in a region where the reinforcement layer 68 containing filler is not used, the patterning is performed using a photosensitive resin. , there is also an advantage that the patterning accuracy is improved.
On the other hand, as shown in FIG. 12, the reduction in strength caused by not using the reinforcing layer 68 containing the filler can be dealt with by using an underfill 59 for fixing a semiconductor element or the like 55 in a later step after mounting it. It is also possible to fill the portion not covered with the reinforcing layer 68 to suppress cracks and the like.

[Manufacturing method of the first embodiment]
Next, the manufacturing method of the first embodiment using the damascene method will be described with reference to FIGS.
As shown in FIG. 5, a release layer 53 is formed above a support 51 made of a glass substrate.
<Release layer>
Examples of materials for the release layer 53 include organic resins such as epoxy resin, polyimide resin, polyurethane resin, silicone resin, polyester resin, oxetane resin, maleimide resin, and acrylic resin, amorphous silicon, gallium nitride, and metal oxides. It can be selected from inorganic layers such as layers. Furthermore, the release layer 53 may contain additives such as photodecomposition accelerators, light absorbers, sensitizers, fillers, and the like.

Next, in the manufacturing method of the first embodiment, a second organic insulating resin containing a filler is applied as a reinforcing layer to become the reinforcing layer 68 on the release layer 53 . The second organic insulating resin can be formed of a resin having a filler regardless of whether it is photosensitive or non-photosensitive. Examples of the filler-containing resin include insulating resins such as photosensitive epoxy resins and acrylic resins, and insulating resins such as non-photosensitive epoxy resins. As a method for forming the reinforcing layer, when a liquid photosensitive resin is used, slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen printing, gravure offset printing, spin coating, Can be selected from doctor coat. When using a film-like photosensitive resin, lamination, vacuum lamination, vacuum press, etc. can be applied.

In the case of the second embodiment, after the release layer 53 is formed, the intermediate layer 50 is formed in order to improve the adhesion between the release layer 53 and the reinforcing layer and to prevent kneading. As the material of the intermediate layer 50, for example, nickel, copper, titanium alloys thereof, or a multilayer using a plurality of these can be selected. It is not limited to this. If intermediate layer 50 is provided, reinforcing layer 68 is formed over intermediate layer 50 .

By using the insulating resin as the reinforcing layer for the wiring substrate 52 in this way, the workability is excellent, and the entire surface of the substrate excluding the electrical connection portions such as the electrodes can be covered with the reinforcing layer without gaps. Become. Therefore, the reinforcing layer can effectively suppress the generation of strain stress in the substrate.

Next, as shown in FIG. 6, the reinforcement layer 68 made of the second organic insulating resin is patterned to form connection holes in the reinforcement layer 68 . When a photosensitive resin is used for patterning, photolithography can be used, and laser trimming can also be performed.

Next, a barrier metal layer 63 is formed on the patterned second organic insulating resin. The barrier metal layer 63 can be made of titanium, copper, or multiple layers thereof.
Then, after forming a seed layer of copper above the barrier metal layer 63 by sputtering, a wiring 64 is formed by electrolytic copper plating. The wiring formation method is not limited to this, and various known methods can be adopted.

Next, as shown in FIG. 7, CMP is performed to remove the unnecessary barrier metal layer 63 and wiring 64 deposited on the upper portion of the second organic insulating resin, and the wiring layer is planarized.

Next, as shown in FIG. 8, a first organic insulating resin is applied as an internal insulating film 67 to the surface after CMP. In FIG. 8, the inner insulating film 67 does not contain a filler, and is formed by spin-coating a photosensitive epoxy resin, for example. A photosensitive epoxy resin can be cured at a relatively low temperature, and shrinkage due to curing after formation is small, so that it is excellent for subsequent fine pattern formation.
As a method for forming the photosensitive resin, when using a liquid photosensitive resin as in the case of the filler-containing organic insulating resin, slit coating, curtain coating, die coating, spray coating, electrostatic coating, inkjet coating, gravure coating, screen coating, etc. It can be selected from methods such as printing, gravure offset printing, spin coating and doctor coating.
When a film-like photosensitive resin is used, methods such as lamination, vacuum lamination, and vacuum pressing can be selected. As the photosensitive organic insulating resin, for example, photosensitive polyimide resin, photosensitive benzocyclobutene resin, photosensitive epoxy resin and modified products thereof can be used as the insulating resin.

in subsequent processes. The wiring board 52 can be formed by repeating the steps described with reference to FIGS. Then, when forming the reinforcing layer 68, a second organic insulating resin containing a filler can be used as necessary in the same manner as in FIG. 5 to complete the substrate 54 with the support shown in FIG. 3A. On the other hand, if the first organic insulating resin containing no filler is used, the substrate with support 54 shown in FIG. 3B can be completed.
Although the damascene method is used to form the multilayer wiring described above, the method is not limited to this, and may be formed using the SAP method.

[Manufacturing method of the fourth embodiment]
A manufacturing method in which the second insulating resin does not partially cover the wiring board, that is, the reinforcement layer 68 is partially opened and the entire wiring board is not covered will be described.
For example, as shown in FIG. 4B, in the case of adopting the damascene method, after forming an internal insulating film, a photosensitive resist that does not contain a filler, such as a plating resist, is applied to the entire surface, and photolithography is performed to After leaving the plating resist patterning only on the portions not covered with the reinforcement layer 68, the reinforcement layer 68 is applied to the entire surface of the substrate 54 with support. Next, the reinforcement layer 68 is patterned using a photolithography method, a laser processing method, or the like, followed by plating and CMP steps in that order. 54 can be formed.
Further, in the case of the SAP method, after the reinforcing layer 68 is applied, the unnecessary portion of the reinforcing layer 68 may be removed.

12 is obtained by mounting a semiconductor element or the like 55 on the substrate 54 with the supporting member shown in FIG. 4B and filling the underfill 59 .

Furthermore, in the example shown in FIG. 4C, after forming the reinforcing layer 68 in contact with the peeling layer 53, the portion not covered with the reinforcing layer 68 is filled in advance with a filling material that can be easily removed after plating resist 69, for example. It should be kept. After that, the substrate with support 54 is formed by the same method as described above, and after the support 51 is removed, the plating resist 69 is peeled off to provide an opening in the wiring substrate 52 where the reinforcing layer 68 does not exist. can also

FIG. 4C shows a method of forming an opening in which no reinforcing layer 68 exists on the lower surface of the wiring board 52 in advance. After forming and peeling off the support 51, the unnecessary reinforcing layer 68 may be removed by laser, trimming, or the like to provide an opening where the reinforcing layer 68 does not exist.

Furthermore, an example of another manufacturing method for obtaining a structure in which a part of the reinforcement layer 68 is opened and the entirety is not covered with the reinforcement layer 68 will be described.
In this method, before forming the reinforcement layer 68 on the outermost layer of the wiring board 52, the semiconductor elements 55 are mounted and the underfill 59 is filled. After that, the reinforcing layer 68 may be applied by, for example, a spin coating method or a die coating method, and the reinforcing layer 68 may be removed from the semiconductor elements 55 and electrode portions by photolithography. At this time, as shown in FIG. 12, it is also possible to leave the reinforcing layer 68 on the semiconductor element or the like 55 .

Although not shown, it is also possible to mount a semiconductor element or the like on the lower surface of the wiring board 52 after removing the support 51 and cover the surface of the semiconductor element or the like with the reinforcing layer 68 in the same procedure.

[Manufacturing method after solder mounting process]
Next, as shown in FIG. 9, solder is mounted on the electrodes exposed on the first surface of the substrate 54 with support. This completes the support-attached substrate 54 shown in FIG. 1B. Methods for forming such electrodes include methods such as solder mounting, copper posts, and gold bumps.
Further, copper post electrodes may be formed on the electrodes exposed on the first surface of the substrate with support 54, and solder may be deposited thereon. Soldering can be done by known methods such as by printing solder paste or by depositing tin by plating. (The formation of the copper post electrodes will be described later.)
Further, the electrodes exposed on the first surface of the support-attached substrate 54 may be left with surface treatment only on the copper electrodes without forming solder electrodes. As the surface treatment, for example, surface treatment such as nickel-gold plating or OSP treatment can be adopted.

Next, a method of manufacturing a copper post will be described with reference to FIG. FIG. 10 shows a method for forming copper post electrodes on the first surface 71 of the wiring board 52 . 10, the illustration of the second surface 72 of the wiring board 52 is omitted.
First, as shown in FIG. 10A, a barrier metal layer 63 is formed on an insulating resin containing a filler, a plating resist 69 is adhered thereon, and only post electrode portions are opened. Photolithography can be used as an opening method.
Next, as shown in FIG. 10B, electrolytic copper plating is performed using the barrier metal layer 63 as a seed layer, and solder electrodes are formed on the electrode portions by a printing method or a plating method.
Next, as shown in FIG. 10C, the plating resist 69 is peeled off to remove unnecessary barrier metal, thereby completing copper posts on the first surface 71 of the wiring board 52 as shown in FIG. 10D. be able to.

Next, referring to FIG. 11, a method of manufacturing copper posts on the second surface 72 of the wiring board 52 will be described. Note that the first surface 71 of the wiring substrate 52 is omitted in FIG. 11 .
When manufacturing copper posts on the second surface 72 of the wiring board 52, as shown in FIG. 11A, first, a pattern that will become the copper posts is formed above the release layer 53 using a plating resist 69. Then, as shown in FIG. Keep Next, a second organic insulating resin containing a filler is applied as a reinforcing layer to form the reinforcing layer 68 . Thereafter, lamination is repeated according to the required number in the same manner as described with reference to FIGS. Then, as shown in FIG. 11A, the peeling layer 53 and the support 51 are peeled off by irradiation with ultraviolet rays. If the intermediate layer 50 is formed on the separation layer 53, the intermediate layer 50 exposed on the surface is removed by etching, CMP, or the like. After that, as shown in FIG. 11B, the barrier metal layer 63 exposed on the electrode surface is removed. Then, as shown in FIG. 11C, solder 58 is formed using a printing method or a plating method. Then, as shown in FIG. 11D, the plating resist 69 is removed to complete the copper pillar electrode.

The method of mounting a semiconductor element on the substrate with supporting member 54 and the wiring substrate 52 thus completed is as described with reference to FIGS.

Next, the semiconductor device shown in FIG. 2D was fabricated and evaluated for the structure of the manufacturing method as described above and the effect of using the manufacturing method. As the internal structure of the wiring board used for the evaluation, the structure shown in FIG. 3 in which the reinforcing layer was provided on both sides (FIG. 3A and the structure provided on one side (FIG. 3B)) was used.

In the examples and comparative examples, a wide conductor pattern of 1000 μm was formed in the outermost layer (X in FIGS. 3A and 3B) so as to facilitate the generation of cracks in order to observe the crack improvement effect of the reinforcing layer.

The conditions of the reinforcing layer of Example 1 are as follows.
Thickness of reinforcing layer (Z in FIG. 3A): 45 μm
CTE of reinforcing layer: 9 ppm/K

In Example 1, the conditions of the reinforcing layer were changed as follows.
Thickness of reinforcing layer (Z in FIG. 3A): 45 μm
CTE of reinforcing layer: 19 ppm/K

In Example 1, the conditions of the reinforcing layer were changed as follows.
Thickness of reinforcing layer (Z in FIG. 3A): 45 μm
CTE of reinforcing layer: 28 ppm/K

In Example 1, the conditions of the reinforcing layer were changed as follows.
Thickness of reinforcing layer (Z in FIG. 3A): 45 μm
CTE of reinforcing layer: 39 ppm/K

In Example 1, the wiring method for the fine wiring layer was changed from the damascene method to the SAP method shown in FIG. 3B.

The conditions of the reinforcing layer of Example 1 are as follows.
Thickness of reinforcing layer: 30 μm
CTE of reinforcing layer: 9 ppm/K

In Example 1, the conditions of the reinforcing layer were changed as follows.
Thickness of reinforcing layer: 30 μm
CTE of reinforcing layer: 19 ppm/K

In Example 1, the conditions of the reinforcing layer were changed as follows.
Thickness of reinforcing layer: 30 μm
CTE of reinforcing layer: 28 ppm/K

In Example 1, the conditions of the reinforcing layer were changed as follows.
Thickness of reinforcing layer: 30 μm
CTE of reinforcing layer: 39 ppm/K

The conditions of the reinforcing layer of Example 1 are as follows.
Thickness of reinforcing layer: 15 μm
CTE of reinforcing layer: 9 ppm/K

In Example 1, the conditions of the reinforcing layer were changed as follows.
Thickness of reinforcing layer: 15 μm
CTE of reinforcing layer: 19 ppm/K

In Example 1, the conditions of the reinforcing layer were changed as follows.
Thickness of reinforcing layer: 15 μm
CTE of reinforcing layer: 28 ppm/K

In Example 1, the conditions of the reinforcing layer were changed as follows.
Thickness of reinforcing layer: 15 μm
CTE of reinforcing layer: 39 ppm/K

The conditions of the reinforcing layer of Example 1 are as follows.
Thickness of reinforcing layer: 60 μm
CTE of reinforcing layer: 9 ppm/K

In Example 1, the conditions of the reinforcing layer were changed as follows.
Thickness of reinforcing layer: 60 μm
CTE of reinforcing layer: 19 ppm/K

In Example 1, the conditions of the reinforcing layer were changed as follows.
Thickness of reinforcing layer: 60 μm
CTE of reinforcing layer: 28 ppm/K

In Example 1, the conditions of the reinforcing layer were changed as follows.
Thickness of reinforcing layer: 60 μm
CTE of reinforcing layer: 39 ppm/K
<Comparative example>

As a comparative example, an organic insulating resin without a filler, which is the first organic insulating resin, was used for each insulating film of the surface layer.

A via connection reliability test was conducted on the configurations of Examples 1 to 5 and Comparative Example. In addition, via connection reliability was evaluated according to the following conditions, and criteria for acceptance were that the rate of change in resistance value was within ±3% and that there were no cracks or delamination.
Standard: JESD22-A106B (Condition D)
Temperature: -65°C/5min ⇒ normal temperature/1min → 150°C/5min

<Confirmation of action effect>
In Examples 1 to 17, it took 1000 to 2000 cycles until the via connection reliability test failed, but in the comparative example it took 300 to 500 cycles. According to the present invention, by forming layers of organic insulating resin containing fillers above and below the fine wiring layer, the stress inside the wiring layer is relieved, and cracks originating from places where stress is concentrated are less likely to occur, and via connection is possible. The effect on reliability was shown.

Since the CTE of the photosensitive insulating resin capable of forming fine wiring was within the range of about 50 to 80 ppm/K, the CTE of the reinforcing layer was about 40 ppm/K or less, which is smaller than the CTE of the photosensitive insulating resin, and the effect was obtained. I can say there is.

By increasing the thickness of the reinforcing layer to more than 45 μm, the volume of the reinforcing layer having a CTE smaller than that of the photosensitive insulating resin is increased, so that the stress strain of the insulating resin is further reduced and the crack resistance is further improved. Also, it is thought that if the thickness of the reinforcing layer is less than 45 μm, the crack resistance is improved compared to the comparative example without the reinforcing layer, although the effect is reduced.

From the fact that Example 5 obtained the same results as the other examples, it can be said that there is no great difference in crack resistance between the damascene method and the SAP method, although the method of forming wiring is different.

Furthermore, in all examples, the same results were obtained whether the reinforcing layer was provided on both sides or on one side, so that there was no significant difference in crack resistance even with the difference between the reinforcing layers on one side and both sides. I can say no.

The above-described embodiment is an example, and it goes without saying that other specific details such as the structure can be changed as appropriate.
For example, in the above-described embodiments, the second organic insulating resin is formed only on the surface layer, but the effect of the second organic insulating resin is not limited to being present only on the surface layer. That is, the second organic insulating resin can be formed in a layer adjacent to or close to the surface layer.
In addition, in the above-described embodiments, the second organic insulating resin uses a resin containing a filler, but the composition of the second organic insulating resin is not limited to this. As the material of the second organic insulating resin, various materials can be used as long as they have a CTE of 40 or less.

The present disclosure also includes the following aspects.

(Aspect 1)
A support-equipped substrate comprising a support and a wiring board provided above the support,
the insulating film inside the wiring substrate is made of a first organic insulating resin,
Electrodes that can be bonded to a semiconductor element or the like are provided on the first surface and the second surface of the wiring substrate,
the insulating film of at least one surface layer above or below the wiring substrate is made of a second organic insulating resin,
The substrate with support, wherein the CTE of the second organic insulating resin is smaller than the CTE of the first organic insulating resin.

(Aspect 2)
In the support-attached substrate according to aspect 1,
CTE of the second organic insulating resin is 40 ppm/K or less,
A substrate with a support, characterized by:

(Aspect 3)
In the support-attached substrate according to aspect 1 or 2,
The second organic insulating resin contains a filler,
A substrate with a support, characterized by:

(Aspect 4)
In the substrate with support according to aspect 3,
The filler comprises silicon or a compound of silicon,
A substrate with a support, characterized by:

(Aspect 5)
In the support-attached substrate according to any one of aspects 1 to 4,
The support is a glass substrate,
A substrate with a support, characterized by:

(Aspect 6)
In the support-attached substrate according to any one of aspects 1 to 5,
The wiring in the wiring board and the via that joins the wiring are made of copper or an alloy containing copper,
A barrier metal layer is provided on part of the surface where the wiring or the via is in contact with the first or second organic insulating resin,
A substrate with a support, characterized by:

(Aspect 7)
In the support-attached substrate according to aspect 6,
A substrate with a support, wherein the barrier metal layer contains titanium, tantalum, or a compound thereof.

(Aspect 8)
In the support-attached substrate according to any one of aspects 1 to 7,
A part of the electrode that can be bonded to the semiconductor element or the like penetrates the outermost second organic insulating layer,
A substrate with a support, characterized by:

(Aspect 9)
In the support-attached substrate according to any one of aspects 1 to 8,
A release layer is arranged between the support and the wiring board,
An intermediate layer is arranged between the wiring board and the release layer.
A substrate with a support, characterized by:

(Mode 10)
In the support-attached substrate according to aspect 9,
The intermediate layer is composed of nickel, copper, titanium alloys thereof, or multiple layers using a plurality of these materials,
A substrate with a support, characterized by:

(Aspect 11)
In the support-attached substrate according to any one of aspects 1 to 10,
In the first surface and the second surface of the wiring board, an organic insulating resin containing a filler is not provided in a region where an electrode to be bonded to a semiconductor element or the like is provided.
A substrate with a support, characterized by:

(Aspect 12)
The semiconductor element or another wiring board is bonded to the first surface of the substrate with support according to any one of aspects 1 to 11,
the support is peeled off;
A semiconductor device characterized by:

(Aspect 13)
The semiconductor device of aspect 12, comprising:
The semiconductor element or the like is bonded to the second surface of the wiring substrate,
A semiconductor device characterized by:

(Aspect 14)
A method for manufacturing a support-attached substrate according to aspect 11, comprising:
a first step of forming a release layer over the support;
a second step of forming a reinforcing layer above the release layer;
a third step of forming connection holes in the reinforcing layer;
a fourth step of forming a photosensitive resin layer above the reinforcing layer in which the connection hole is formed;
a fifth step of patterning the photosensitive resin layer to form wiring;
A sixth step of repeating the fifth step any number of times;
A seventh step of forming a reinforcing layer having an opening above the wiring formed in the sixth step;
a sixth step of embedding a conductive material in the partial connection hole of the reinforcing layer having the opening formed in the seventh step;
A method for manufacturing a substrate with a support.

(Aspect 15)
A method for manufacturing a support-attached substrate according to aspect 14, comprising:
After the second step or the third step, a step of removing a portion of the reinforcing layer above the release layer and filling a portion of the removed portion of the reinforcing layer with a filling substance;
A method for manufacturing a substrate with a support.

(Aspect 16)
The semiconductor element or another wiring board is bonded to the first surface of the substrate with support according to any one of aspects 1 to 11,
The support is separated and removed,
A semiconductor device characterized by:

(Aspect 17)
15. The semiconductor device according to any one of aspects 12, 13 or 14,
The semiconductor element or another wiring board is bonded to the second surface of the wiring board,
A semiconductor device characterized by:

(Aspect 18)
A first step of bonding a semiconductor element or the like to the first surface of the wiring substrate in the substrate with support according to any one of aspects 1 to 11;
a second step of peeling off the support from the support-attached substrate;
A method of manufacturing a semiconductor device, comprising a third step of bonding the wiring board from which the support has been removed to another wiring board.

(Aspect 19)
A first step of bonding a semiconductor element or the like to the first surface of the wiring substrate of the substrate with support according to any one of aspects 1 to 11;
a second step of peeling off the support from the support-attached substrate;
a third step of bonding a semiconductor element or the like to the second surface of the wiring board from which the support has been peeled off; a fourth step of bonding to
A method of manufacturing a semiconductor device comprising:

50: Intermediate layer 51: Support 52: Wiring board 53: Peeling layer 54: Substrate with support 55: Semiconductor element, etc. 56: Upper surface of wiring board 52 57: Lower surface of wiring board 52 58: Solder 59: Underfill 60: Mold resin 61: Other wiring board 62: Solder or copper post 63: Barrier metal layer 64: Wiring 67: Internal insulating film 68: Reinforcement layer 69: Plating resist 70: Copper plating 71: First surface 72: Second surface the side of

Claims (18)

A support-equipped substrate comprising a support and a wiring board provided above the support,
the insulating film inside the wiring substrate is made of a first organic insulating resin,
Electrodes that can be bonded to a semiconductor element or the like are provided on the first surface and the second surface of the wiring substrate,
the insulating film of at least one surface layer above or below the wiring substrate is made of a second organic insulating resin,
the CTE of the second organic insulating resin is less than the CTE of the first organic insulating resin;
A substrate with a support, characterized by: In the substrate with support according to claim 1,
CTE of the second organic insulating resin is 40 ppm/K or less,
A substrate with a support, characterized by: The substrate with support according to claim 1 or 2,
The second organic insulating resin contains a filler,
A substrate with a support, characterized by: In the substrate with support according to claim 3,
The filler comprises silicon or a compound of silicon,
A substrate with a support, characterized by: The substrate with support according to claim 1 or 2,
The support is a glass substrate,
A substrate with a support, characterized by: The substrate with support according to claim 1 or 2,
The wiring in the wiring board and the via that joins the wiring are made of copper or an alloy containing copper,
A barrier metal layer is provided on part of the surface where the wiring or the via is in contact with the first or second organic insulating resin,
A substrate with a support, characterized by: In the substrate with support according to claim 6,
the barrier metal layer contains titanium or tantalum, or a compound thereof;
A substrate with a support, characterized by: The substrate with support according to claim 1 or 2,
A part of the electrode that can be bonded to the semiconductor element or the like penetrates the outermost second organic insulating layer,
A substrate with a support, characterized by: The substrate with support according to claim 1 or 2,
A release layer is arranged between the support and the wiring board,
An intermediate layer is arranged between the wiring board and the release layer.
A substrate with a support, characterized by: In the substrate with support according to claim 9,
The intermediate layer is composed of nickel, copper, titanium alloys thereof, or multiple layers using a plurality of these materials,
A substrate with a support, characterized by: The substrate with support according to claim 1 or 2,
In the first surface and the second surface of the wiring board, an organic insulating resin containing a filler is not provided in a region where an electrode to be bonded to a semiconductor element or the like is provided.
A substrate with a support, characterized by: The semiconductor element or another wiring board is bonded to the first surface of the substrate with support according to claim 1 or 2,
the support is peeled off;
A semiconductor device characterized by: 13. The semiconductor device of claim 12,
The semiconductor element or the like is bonded to the second surface of the wiring substrate,
A semiconductor device characterized by: A method for manufacturing a substrate with a support according to claim 11,
a first step of forming a release layer over the support;
a second step of forming a reinforcing layer above the release layer;
a third step of forming connection holes in the reinforcing layer;
a fourth step of forming a photosensitive resin layer above the reinforcing layer in which the connection hole is formed;
a fifth step of patterning the photosensitive resin layer to form wiring;
A sixth step of repeating the fifth step any number of times;
A seventh step of forming a reinforcing layer having an opening above the wiring formed in the sixth step;
a sixth step of embedding a conductive material in the partial connection hole of the reinforcing layer having the opening formed in the seventh step;
A method for manufacturing a substrate with a support. A method for manufacturing a substrate with a support according to claim 14,
After the second step or the third step, a step of removing a portion of the reinforcing layer above the release layer and filling a portion of the removed portion of the reinforcing layer with a filling substance;
A method for manufacturing a substrate with a support. A first step of bonding a semiconductor element or the like to the first surface of the wiring substrate in the substrate with support according to claim 1 or 2,
a second step of peeling off the support from the support-attached substrate;
a third step of bonding the wiring board from which the support has been removed to another wiring board;
A method of manufacturing a semiconductor device comprising: A first step of bonding a semiconductor element or the like to the first surface of the wiring substrate of the substrate with support according to claim 1 or 2,
a second step of peeling off the support from the support-attached substrate;
a third step of bonding a semiconductor element or the like to the second surface of the wiring board from which the support has been removed;
a fourth step of bonding the wiring substrate having the semiconductor element or the like bonded to the first surface and the second surface to another wiring substrate;
A method of manufacturing a semiconductor device comprising: In the method for manufacturing a semiconductor device according to claim 17,
After the second step, a step of removing a portion of the reinforcing layer on the second surface of the wiring board to form an opening in the reinforcing layer;
A method of manufacturing a semiconductor device comprising:

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