JP2023037783A - Inertial sensor, method for manufacturing inertial sensor, and inertial measuring device - Google Patents

Abstract

To provide an inertial sensor that has good bias characteristics.SOLUTION: An acceleration sensor 1 comprises: first and second semiconductor layers 41, 42 that are formed on a third surface F3 being a top face of an insulating film 5; a first side wall oxide film 21 that is formed on a first side face W1 of the first semiconductor layer 41 facing the second semiconductor layer 42; and a second side wall oxide film 22 that is formed on a second side face W2 of the second semiconductor layer 42 facing the first semiconductor layer 41. The first side face W1 has a convex first curved face part R1 facing the second semiconductor layer 42 at an end facing the insulating film 5, and a convex second curved face part R2 facing the second semiconductor layer 42 at an end on the opposite side of the insulating film 5. The second side face W2 has a convex third curved face part R3 facing the first semiconductor layer 41 at an end facing the insulating film 5, and a convex fourth curved face part R4 facing the first semiconductor layer 41 at an end on the opposite side of the insulating film 5. The first side wall oxide film 21 and the second side wall oxide film 22 are in physical contact with each other.SELECTED DRAWING: Figure 3

Description

The present invention relates to an inertial sensor, an inertial sensor manufacturing method, and an inertial measurement device.

In Patent Document 1, an insulator-filled trench groove is formed in a silicon substrate, which is a semiconductor substrate, and an insulator filled in the insulator-filled trench groove forms, for example, a fixed electrode and an outer peripheral portion at its base. and are electrically decoupled from each other. Further, in Patent Document 2, an isolation trench is formed in a silicon substrate, a sidewall insulating film is formed on the sidewall of the isolation trench, and a conductive material is embedded in the isolation trench in which the sidewall insulating film is formed. A semiconductor device filled with polysilicon is described.

JP-A-11-248733 JP-A-2003-45988

However, when the technique described in Patent Document 2 is applied to the angular velocity sensor described in Patent Document 1, between the fixed electrode and the outer peripheral portion at the root thereof, that is, between the semiconductors separated by the trench Since a conductive material is inserted into the trench, the parasitic capacitance between the semiconductors separated by the trench increases, and there is concern that the bias characteristics of the angular velocity sensor will deteriorate. The bias characteristic means the magnitude and stability of the bias, which is an output component unrelated to the input component in an inertial sensor such as an angular velocity sensor.

The inertial sensor includes a substrate, an insulating film formed on a main surface of the substrate, first and second semiconductor layers formed on a surface of the insulating film opposite to the substrate, and the first semiconductor layer. a first sidewall oxide film formed on a first side surface of a semiconductor layer on the second semiconductor layer side; and a second sidewall oxide film formed on a second side surface of the second semiconductor layer on the first semiconductor layer side. , the first side surface has a first curved surface portion protruding toward the second semiconductor layer at an end portion on the insulating film side, and the first curved surface portion at an end portion opposite to the insulating film side. a second curved surface portion protruding toward the second semiconductor layer, the second side surface having a third curved surface portion protruding toward the first semiconductor layer at an end portion on the insulating film side; The end portion opposite to the film side has a convex fourth curved surface portion on the first semiconductor layer side, and the first sidewall oxide film and the second sidewall oxide film are in physical contact. .

A method for manufacturing an inertial sensor includes a step of preparing a base body having a substrate, an insulating film formed on a main surface of the substrate, and a semiconductor layer formed on a surface of the insulating film opposite to the substrate. forming a trench portion and a first semiconductor layer and a second semiconductor layer facing each other across the trench portion by removing a portion of the semiconductor layer; oxidizing the second semiconductor layer at the same time to form a first sidewall oxide film on the first side surface of the first semiconductor layer on the second semiconductor layer side; forming a second sidewall oxide film on a side surface, and filling the trench by bringing the first sidewall oxide film and the second sidewall oxide film into physical contact with each other.

An inertial measurement device includes the inertial sensor described above and a control unit that controls the inertial sensor.

2 is a plan view showing the inertial sensor according to the first embodiment; FIG. FIG. 2 is a cross-sectional view along the line AA in FIG. 1; Sectional drawing corresponding to the position of the D1 part in FIG. Sectional drawing corresponding to the position of the D1 part in FIG. 4A and 4B are diagrams showing a manufacturing process of the inertial sensor according to the first embodiment; FIG. Sectional drawing for demonstrating the manufacturing method of an inertial sensor. Sectional drawing for demonstrating the manufacturing method of an inertial sensor. Sectional drawing corresponding to the position of the D2 part in FIG. Sectional drawing for demonstrating the manufacturing method of an inertial sensor. Sectional drawing corresponding to the position of the D3 part of FIG. Sectional drawing for demonstrating the manufacturing method of an inertial sensor. Sectional drawing corresponding to the position of the D4 part in FIG. Sectional drawing for demonstrating the manufacturing method of an inertial sensor. FIG. 8 is a cross-sectional view corresponding to the position of D1 of the inertial sensor according to the second embodiment; FIG. 11 is a cross-sectional view corresponding to the position of the D1 portion of the inertial sensor according to the third embodiment; FIG. 11 is an exploded perspective view showing a schematic configuration of an inertial measurement device according to Embodiment 4; FIG. 17 is a perspective view of the substrate in FIG. 16;

Next, embodiments of the present invention will be described with reference to the drawings.
For convenience of explanation, the following figures except FIG. 5 show the X-axis, Y-axis, and Z-axis as three mutually orthogonal axes. The direction along the X axis is called the "X direction", the direction along the Y axis is called the "Y direction", and the direction along the Z axis is called the "Z direction". In addition, the tip side of the arrow in each axial direction is also called the "plus side", and the base side of the arrow is called the "minus side". That is, for example, the Y direction refers to both the Y direction plus side and the Y direction minus side. The positive side in the Z direction is also called "upper", and the negative side in the Z direction is also called "lower". In addition, in the following figures, there are cases where dimensions and scales are different from the actual ones in order to make the description easier to understand.

1. Embodiment 1
An acceleration sensor 1 as an example of an inertial sensor according to Embodiment 1 will be described with reference to FIGS. 1 to 4. FIG.
The acceleration sensor 1 is a capacitive acceleration sensor that detects acceleration using variations in capacitance that depend on the distance between the movable portion 2 and the fixed electrode portion 3 .

As shown in FIGS. 1 and 2, the acceleration sensor 1 is configured using a base 7 in which a substrate 4, an insulating film 5, and a semiconductor layer 6 are laminated in this order along the Z direction.

The substrate 4 has a first surface F1, which is the principal surface of the substrate 4, and a second surface F2, which is opposite to the first surface F1. In the present embodiment, the first surface F<b>1 is the surface of the substrate 4 on the positive side in the Z direction, and is also referred to as the top surface of the substrate 4 . The second surface F<b>2 is the surface of the substrate 4 on the negative side in the Z direction, and is also called the lower surface of the substrate 4 . A recess 8 with a bottom is formed in the central portion of the substrate 4 when viewed from above in the Z direction. The recess 8 has an opening on the first surface F1 of the substrate 4 and has a shape that is recessed from the first surface F1 toward the second surface F2. The concave portion 8 is also called a cavity. In this embodiment, the substrate 4 is a semiconductor substrate, specifically a single crystal silicon substrate.

An insulating film 5 is formed on the first surface F<b>1 that is the upper surface of the substrate 4 . In this embodiment, the insulating film 5 is made of silicon oxide. In this embodiment, the insulating film 5 is also formed on the side and bottom surfaces of the recess 8 . In this embodiment, the insulating film 5 may be formed on the first surface F1, and the insulating film 5 on the side and bottom surfaces of the recess 8 may be removed. Further, in the present embodiment, an insulating film is not formed on the second surface F2, which is the lower surface of the substrate 4, but an insulating film may be formed on the second surface F2.

A semiconductor layer 6 is formed on the opposite side of the substrate 4 with the insulating film 5 interposed therebetween. The semiconductor layer 6 is joined to the third surface F3 of the insulating film 5 opposite to the substrate 4 at the periphery of the recess 8 . The third surface F3 of the insulating film 5 is also called the upper surface of the insulating film 5 .

The semiconductor layer 6 has a fourth surface F<b>5 opposite to the insulating film 5 . The fourth surface F5 of the semiconductor layer 6 is also called the upper surface of the semiconductor layer 6 . The semiconductor layer 6 is made of a semiconductor such as silicon, germanium, or silicon germanium. The semiconductor layer 6 is preferably made of a single crystal semiconductor doped with impurities such as boron (B) and phosphorus (P). By doping the semiconductor layer 6 with impurities, carriers can be generated in the semiconductor layer 6 and the resistivity can be lowered. In this embodiment, the semiconductor layer 6 is made of single crystal silicon doped with boron to have a resistivity of 0.001 to 100 Ωcm. Further, in this embodiment, the substrate 7 is an SOI (Silicon On Insulator) substrate having a concave portion 8 which is a cavity.

The semiconductor layer 6 is used to form the movable portion 2 , the fixed electrode portion 3 , the outer frame portion 9 and the elastic portion 13 . In the present embodiment, the movable portion 2 is formed inside the concave portion 8 in plan view in the Z direction. A plurality of fixed electrode portions 3 are formed on both sides of the movable portion 2 in the X direction with the movable portion 2 interposed therebetween. The outer frame portion 9 has a substantially rectangular frame shape surrounding the movable portion 2 and the fixed electrode portion 3 . The outer frame portion 9 is formed on the third surface F<b>3 that is the upper surface of the insulating film 5 in the peripheral portion of the recess 8 . The movable portion 2 and the outer frame portion 9 are connected via the elastic portion 13 .

The movable portion 2 has a movable electrode support portion 10 and a plurality of movable electrode fingers 11 supported by the movable electrode support portion 10 . In this embodiment, the movable part 2 is a vibrator that can be displaced in the Y direction. The movable electrode support portion 10 has a rectangular shape with long sides in the Y direction. Elastic portions 13 are formed at both ends of the movable electrode support portion 10 in the Y direction. Movable electrode fingers 11 are formed on both side surfaces of the movable electrode supporting portion 10 in the X direction. The movable electrode finger 11 has a cantilever shape with a free end extending from the movable electrode support portion 10 toward the fixed electrode portion 3 .

The fixed electrode section 3 has a fixed electrode support section 15 and fixed electrode fingers 16 . The fixed electrode supporting portion 15 is formed on the third surface F<b>3 that is the upper surface of the insulating film 5 in the peripheral portion of the recess 8 . The fixed electrode finger 16 has a cantilever shape with a free end extending from the fixed electrode support portion 15 toward the movable portion 2 .

The movable electrode fingers 11 extending to the positive side in the X direction and the fixed electrode fingers 16 extending to the negative side in the X direction are arranged to face each other with a space therebetween. Similarly, the movable electrode fingers 11 extending to the negative side in the X direction and the fixed electrode fingers 16 extending to the positive side in the X direction are arranged to face each other with a space therebetween. In the state where the movable part 2 is stationary, the side surfaces of the movable electrode fingers 11 and the side surfaces of the fixed electrode fingers 16 are separated by a predetermined distance.

An insulating isolation region 20 is formed between the fixed electrode portion 3 and the outer frame portion 9 . Specifically, the insulating isolation region 20 is formed between the fixed electrode support portion 15 of the fixed electrode portion 3 and the outer frame portion 9 . The fixed electrode portion 3 and the outer frame portion 9 are electrically separated by the insulating isolation region 20 and the insulating film 5 . The isolation region 20 has a first sidewall oxide film 21 and a second sidewall oxide film 22 which will be described later.

An interlayer insulating film 24 is formed on the upper surface of the insulating separation region 20 and the upper surfaces of the outer frame portion 9 and the fixed electrode support portion 15 in the fourth surface F5 that is the upper surface of the semiconductor layer 6 . The interlayer insulating film 24 is preferably a silicon oxide film formed of silicon oxide by a thermal CVD (Chemical Vapor Deposition) method. In this embodiment, the interlayer insulating film 24 is formed of high temperature silicon oxide HTO (High Temperature Oxide) by low pressure thermal CVD.

A contact 26 is formed in the interlayer insulating film 24 at a position corresponding to the fixed electrode supporting portion 15 . Further, electrode pads 27 and 28 and wiring 29 are arranged on the upper surface of the interlayer insulating film 24 . One end of the wiring 29 is electrically connected to the fixed electrode support portion 15 via the contact 26 . The other end of wiring 29 is electrically connected to electrode pad 27 . That is, the fixed electrode portion 3 and the electrode pad 27 are electrically connected via the wiring 29 . The electrode pads 28 are electrically connected to the movable portion 2 by wiring (not shown). In this embodiment, the electrode pads 27 and 28 and the wiring 29 are formed of a metal multilayer film. This metal multilayer film is preferably formed of a material that can ensure adhesion with the interlayer insulating film 24 . Specifically, electrode pads 27 and 28 and wiring 29 are formed of a metal multilayer film made of titanium nitride, aluminum, copper, or the like.

Further, in this embodiment, the outer frame portion 9 is electrically grounded, for example, by wiring (not shown), and a potential difference is generated between the outer frame portion 9 and the fixed electrode portion 3 .

Such an acceleration sensor 1 can detect acceleration as follows. In this embodiment, the acceleration sensor 1 detects acceleration in the Y direction.
When acceleration in the Y direction is applied, the movable portion 2 is displaced in the Y direction with respect to the base 7 . Therefore, the capacitance between the movable electrode fingers 11 of the movable portion 2 and the fixed electrode fingers 16 of the fixed electrode portion 3 changes. Acceleration in the Y direction can be detected based on this change in capacitance.

Next, the insulating isolation region 20 formed between the fixed electrode support portion 15 and the outer frame portion 9 will be described in detail.

As described above, the outer frame portion 9 and the fixed electrode portion 3 having the fixed electrode support portion 15 and the fixed electrode fingers 16 are formed of the semiconductor layer 6 . Further, the outer frame portion 9 and the fixed electrode support portion 15 are formed on the third surface F3, which is the upper surface of the insulating film 5, in the peripheral portion of the recess 8. As shown in FIG.

That is, the outer frame portion 9 formed by the semiconductor layer 6 corresponds to the first semiconductor layer 41 in the present disclosure. Also, the fixed electrode portion 3 formed of the semiconductor layer 6 corresponds to the second semiconductor layer 42 in the present disclosure.
In the following description, the outer frame portion 9 and the fixed electrode support portion 15 are replaced with the first semiconductor layer 41 and the second semiconductor layer 42, respectively.

As shown in FIGS. 2, 3 and 4, the first semiconductor layer 41 (outer frame portion 9) and the second semiconductor layer 42 (fixed electrode support portion 15) form the upper surface of the insulating film 5, which is the third layer. It is formed on the surface F3. A trench portion 40 that is a bottomed groove is formed between the first semiconductor layer 41 and the second semiconductor layer 42 . The bottom surface of the trench portion 40 is the third surface F3 that is the top surface of the insulating film 5 . The first semiconductor layer 41 and the second semiconductor layer 42 are separated with the trench portion 40 interposed therebetween.

The first semiconductor layer 41 has a first side surface W1. The first side surface W1 is a surface of the first semiconductor layer 41 on the second semiconductor layer 42 side. The second semiconductor layer 42 has a second side surface W2. The second side surface W2 is a surface of the second semiconductor layer 42 on the first semiconductor layer 41 side.

A first sidewall oxide film 21 is formed on the first side surface W1 of the first semiconductor layer 41 on the second semiconductor layer 42 side. A second sidewall oxide film 22 is formed on the second side surface W2 of the second semiconductor layer 42 on the side of the first semiconductor layer 41 . The first sidewall oxide film 21 and the second sidewall oxide film 22 are in physical contact. FIG. 3 shows a contact region C1 where the first sidewall oxide film 21 and the second sidewall oxide film 22 are in physical contact. In this embodiment, the contact area C1 extends substantially parallel to the Z direction. In addition, "substantially parallel" and "substantially equal" in the present disclosure mean "parallel" and "equal" including manufacturing variations.

The trench portion 40 is filled by bringing the first sidewall oxide film 21 and the second sidewall oxide film 22 into physical contact with each other. As a result, the insulating isolation region 20 having the first sidewall oxide film 21 and the second sidewall oxide film 22 is formed in the trench portion 40 .

In this embodiment, the first and second sidewall oxide films 21 and 22 are formed by thermally oxidizing the first and second semiconductor layers 41 and 42, respectively. In this embodiment, the first and second sidewall oxide films 21 and 22 are formed of silicon oxide obtained by thermally oxidizing the single crystal silicon forming the first and second semiconductor layers 41 and 42 . Silicon oxide formed by oxidizing silicon by a thermal oxidation method is also called thermally oxidized silicon.

A first side surface W1 of the first semiconductor layer 41 on the side of the second semiconductor layer 42 has a first curved surface portion R1 that protrudes toward the second semiconductor layer 42 at the end on the side of the insulating film 5, and It has a convex second curved surface portion R2 on the second semiconductor layer 42 side at the end portion on the opposite side. Further, in the present embodiment, the first curved surface portion R1 and the second curved surface portion R2 are connected by the flat surface portion L1 on the first side surface W1. The flat portion L1 extends substantially parallel to the Z direction.

Similarly, the second side surface W2 of the second semiconductor layer 42 on the side of the first semiconductor layer 41 has a third curved surface portion R3 that protrudes toward the first semiconductor layer 41 at the end portion on the side of the insulating film 5 to provide insulation. The end portion on the side opposite to the film 5 side has a convex fourth curved surface portion R4 toward the first semiconductor layer 41 side. Further, in the present embodiment, on the second side surface W2, the third curved surface portion R3 and the fourth curved surface portion R4 are connected by the flat surface portion L2. The flat portion L2 extends substantially parallel to the Z direction.

Thus, the first side surface W1 of the first semiconductor layer 41 has the first curved surface portion R1 that protrudes toward the second semiconductor layer 42 at the end on the insulating film 5 side and is opposite to the insulating film 5 side. It has a convex second curved surface portion R2 on the second semiconductor layer 42 side at the side end portion. A second side surface W2 of the second semiconductor layer 42 on the side of the first semiconductor layer 41 has a third curved surface portion R3 protruding toward the first semiconductor layer 41 at the end on the side of the insulating film 5, and the insulating film It has a convex fourth curved surface portion R4 on the first semiconductor layer 41 side at the end portion opposite to the 5 side. As a result, parasitic capacitance such as fringe capacitance between the first semiconductor layer 41 and the second semiconductor layer 42 can be reduced, so the acceleration sensor 1 with good bias characteristics can be provided. Here, the bias characteristic of the acceleration sensor 1 of this embodiment refers to the deviation or offset characteristic from the zero point in the stationary state. This low bias and stable acceleration sensor 1 can be said to be a good inertial sensor.

Moreover, as shown in FIGS. 3 and 4, when both the plane portion L1 and the plane portion L2 are substantially parallel to the Z direction, the curvature of the first curved surface portion R1, the curvature of the second curved surface portion R2, and the curvature of the third curved surface The curvature of the portion R3 and the curvature of the fourth curved surface portion R4 are substantially equal. This increases the symmetry of the parasitic capacitance such as the fringe capacitance, so that the acceleration sensor 1 with good bias characteristics can be provided.

Also, in the first semiconductor layer 41 , an impurity concentration low region 45 is formed in the vicinity of the surface of the first semiconductor layer 41 . Similarly, in the second semiconductor layer 42 , an impurity concentration low region 46 is formed in the vicinity of the surface of the second semiconductor layer 42 . The surface of the first semiconductor layer 41 includes the first side surface W1, the upper surface of the first semiconductor layer 41, and the lower surface of the first semiconductor layer 41. As shown in FIG. The surface of the second semiconductor layer 42 includes the second side surface W2, the upper surface of the second semiconductor layer 42, and the lower surface of the second semiconductor layer 42. The upper surface of the first semiconductor layer 41 and the second semiconductor layer 42 is the fourth surface F5 that is the upper surface of the semiconductor layer 6 . The lower surfaces of the first semiconductor layer 41 and the second semiconductor layer 42 are the surfaces of the first semiconductor layer 41 and the second semiconductor layer 42 that face the third surface F3 of the insulating film 5 .

The low-impurity-concentration regions 45 and 46 are regions where the concentration of impurities such as boron and phosphorus pre-doped in the first and second semiconductor layers 41 and 42 is low. This is because out-diffusion of impurities occurs when the first and second semiconductor layers 41 and 42 are oxidized by the thermal oxidation method. Out-diffusion is a phenomenon in which an impurity previously doped into a semiconductor layer evaporates and diffuses from the semiconductor layer. The out-diffusion of impurities is significant, especially when the impurities are boron. The lower impurity concentration regions 45 and 46 have a higher electric resistance than the insides of the first and second semiconductor layers 41 and 42 . Therefore, by forming the impurity concentration low regions 45 and 46, the insulation resistance between the first semiconductor layer 41 and the second semiconductor layer 42 can be further increased. A sensor 1 can be provided.

Further, in the present embodiment, the film thickness of the insulating film 5 in the region contacting the trench portion 40 is thicker than the film thickness of the insulating film 5 in the region contacting the first and second semiconductor layers 41 and 42 . The region of the insulating film 5 in contact with the trench portion 40 is a region of the insulating film 5 corresponding to the bottom surface of the trench portion 40 . The reason why the insulating film 5 in this region is thicker is that when the first and second semiconductor layers 41 and 42 are oxidized by thermal oxidation, oxygen atoms enter and diffuse into the insulating film 5 and react with the substrate 4 . This is because a thermal oxide film is formed. By making the thickness of the region of the insulating film 5 contacting the trench portion 40 thicker than the film thickness of the region of the insulating film 5 contacting the first and second semiconductor layers 41 and 42, the first semiconductor layer 41 and the second Since the parasitic capacitance between the two semiconductor layers 42 can be further reduced, the acceleration sensor 1 with even better bias characteristics can be provided.

In the region of the insulating film 5 in contact with the trench portion 40 , the third surface F<b>3 that is the upper surface of the insulating film 5 has a convex curved surface toward the trench portion 40 , and the lower surface of the insulating film 5 is the third surface of the substrate 4 that is the lower surface of the insulating film 5 . A surface facing the first surface F<b>1 has a convex curved surface facing the substrate 4 .

Further, in the present embodiment, in the isolation region 20, the contact region C1 where the first sidewall oxide film 21 and the second sidewall oxide film 22 physically contact, the first sidewall oxide film 21 and the second sidewall oxide film and a void 50 that does not make physical contact with 22 . The gap 50 is formed between the insulating film 5 side end of the contact region C<b>1 and the third surface F<b>3 that is the upper surface of the insulating film 5 . The end of the contact region C1 on the insulating film 5 side is also referred to as the lower end of the contact region C1. The void 50 is formed by being surrounded by the insulating film 5 , the first sidewall oxide film 21 and the second sidewall oxide film 22 . When the air gap 50 is formed, the dielectric constant of the air gap 50 becomes the vacuum dielectric constant ε ₀ . Dielectric constant ε ₀ of vacuum is 8.85×10 ⁻¹² [F/m]. Generally, the relative dielectric constant of an oxide film is 3.8 to 3.9 with respect to the vacuum dielectric constant ε ₀ , so the presence of the void 50 with a relative dielectric constant of 1 reduces the fringe capacitance. That is, since the parasitic capacitance between the first semiconductor layer 41 and the second semiconductor layer 42 can be further reduced, the acceleration sensor 1 with even better bias characteristics can be provided.

In the first sidewall oxide film 21, a surface between the lower end of the contact region C1 and the third surface F3, which is the upper surface of the insulating film 5, is a curved surface protruding toward the second semiconductor layer . In other words, the boundary surface between the air gap 50 and the first sidewall oxide film 21 is a curved surface. Similarly, in the second sidewall oxide film 22, the surface between the lower end of the contact region C1 and the third surface F3, which is the upper surface of the insulating film 5, is a curved surface protruding toward the first semiconductor layer 41. be. In other words, the boundary surface between the air gap 50 and the second sidewall oxide film 22 is a curved surface. Further, as described above, in the region where the insulating film 5 contacts the trench portion 40 , the third surface F<b>3 that is the upper surface of the insulating film 5 has a convex curved surface toward the trench portion 40 . In other words, the boundary surface between the air gap 50 and the insulating film 5 is a curved surface.

Thus, the interface between the gap 50 and the insulating film 5, the interface between the gap 50 and the first sidewall oxide film 21, and the interface between the gap 50 and the second sidewall oxide film 22 are curved surfaces. be. Due to the existence of such a curved surface, the electric field between the first semiconductor layer 41 and the second semiconductor layer 42 is relaxed without being concentrated. Therefore, it is possible to provide the acceleration sensor 1 with more stable bias characteristics.

Further, as described above, in the present embodiment, the first semiconductor layer 41 and the second semiconductor layer 42 are monocrystalline silicon doped with impurities, and the first sidewall oxide film 21 and the second sidewall oxide film 22 are It is silicon oxide. Since silicon oxide is a good insulator, the insulation properties of the isolation region 20 having the first semiconductor layer 41 and the second semiconductor layer 42 are improved. As a result, the parasitic capacitance between the first semiconductor layer 41 and the second semiconductor layer 42 can be further reduced, so that the acceleration sensor 1 with even better bias characteristics can be provided.

In this embodiment, the first and second sidewall oxide films 21 and 22 are thermally oxidized silicon obtained by oxidizing the first and second semiconductor layers 41 and 42 made of single crystal silicon by thermal oxidation. Thermally oxidized silicon is, for example, a high-quality insulator with a high withstand voltage compared to silicon oxide produced by a CVD method. This further improves the insulating properties of the isolation region 20 .

Also, let H1 be the height of the first and second side surfaces W1 and W2, and H2 be the height of the contact region C1 where the first sidewall oxide film 21 and the second sidewall oxide film 22 physically contact each other. Then, in this embodiment, H2/H1 is 0.905. A height H1 of the first and second side surfaces W1 and W2 corresponds to the height of the isolation region 20, and in this embodiment is the length of the first and second side surfaces W1 and W2 in the Z direction. The height H2 of the contact area C1 is the length from the top end to the bottom end of the contact area C1, and in this embodiment, it is the length of the contact area C1 in the Z direction. That is, H2/H1 corresponds to the contact ratio of the contact region C1 in the isolation region 20. FIG. In this embodiment, the range of H2/H1 is preferably 0.905 or more and 1 or less, more preferably 0.946 or more and 1 or less.

By setting H2/H1 to 0.905 or more and 1 or less, the height H2 of the contact region C1 where the first sidewall oxide film 21 and the second sidewall oxide film 22 are physically in contact with each other increases, and the first sidewall increases. A gap 50, which is a region where the oxide film 21 and the second sidewall oxide film 22 do not physically contact each other, becomes smaller. As a result, it is possible to suppress the deterioration of the mechanical characteristics and temperature characteristics of the acceleration sensor 1 due to external forces such as vibrations and impacts and environmental changes such as temperature, thereby providing the acceleration sensor 1 with high reliability.

By setting H2/H1 to 0.946 or more and 1 or less, it is possible to further suppress deterioration of the mechanical characteristics and temperature characteristics of the acceleration sensor 1 due to environmental changes such as temperature, and the acceleration sensor 1 has even higher reliability. can be provided.

Next, a method for manufacturing the acceleration sensor 1 as an example of the inertial sensor according to this embodiment will be described with reference to FIGS. 5 to 13. FIG.
As shown in FIG. 5, the method of manufacturing the acceleration sensor 1 comprises: a substrate 4; A substrate forming step of preparing a substrate 7 having a semiconductor layer 6 formed on a third surface F3, which is a surface, and removing a part of the semiconductor layer 6 to form a trench portion 40 and a The first semiconductor layer 41 and the second semiconductor layer 42 are simultaneously oxidized to form the first semiconductor layer 41 and the second semiconductor layer 42 facing each other, and the first semiconductor layer 41 and the second semiconductor layer 42 are simultaneously oxidized to form the second A first sidewall oxide film 21 is formed on the first side surface W1 on the second semiconductor layer 42 side, and a second sidewall oxide film 22 is formed on the second side surface W2 of the second semiconductor layer 42 on the first semiconductor layer 41 side. and a trench portion filling step of filling the trench portion 40 by bringing the first sidewall oxide film 21 and the second sidewall oxide film 22 into physical contact with each other. Further, the method of manufacturing the acceleration sensor 1 includes wiring (not shown) electrically connected to the movable section 2, wiring 29 electrically connected to the fixed electrode section 3, wiring forming the electrode pads 27 and 28, and the like. and a movable portion forming step of forming the outlines of the movable portion 2, the fixed electrode portion 3, the outer frame portion 9, and the like.

1.1 Substrate Forming Step In step S1, a substrate 7 is prepared as shown in FIG.
In this embodiment, as described above, the substrate 7 is an SOI substrate having the recess 8 which is a cavity.

The substrate 7 can be manufactured as follows.
First, the substrate 4 and the structure substrate corresponding to the semiconductor layer 6 are prepared. The structure substrate is also called an active substrate or an active layer substrate. A concave portion 8 is formed in the substrate 4 and an insulating film is formed on the surface of the substrate 4 . As described above, in the present embodiment, the insulating film 5 is formed on the first surface F<b>1 , which is the main surface of the substrate 4 , and the side and bottom surfaces of the recess 8 . In this embodiment, the insulating film 5 may be formed on the first surface F1, and the insulating film 5 on the side and bottom surfaces of the recess 8 may be removed. In addition, although an insulating film is not formed on the second surface F2 of the substrate 4, an insulating film may be formed thereon. The substrate 4 on which the insulating film 5 is formed is also called a support substrate.
Subsequently, by bonding the substrate 4 and a structure substrate corresponding to the semiconductor layer 6 with the insulating film 5 interposed therebetween, the semiconductor layer 6 is formed on the opposite side of the substrate 4 with the insulating film 5 interposed therebetween. 7 can be produced.

1.2 Trench Portion Forming Step Next, in step S2, as shown in FIGS. 7 and 8, the trench portion 40 is formed by removing part of the semiconductor layer 6. As shown in FIGS. The trench portion 40 is a bottomed groove that penetrates the semiconductor layer 6 and has a bottom surface that is the third surface F3 that is the upper surface of the insulating film 5 . In this embodiment, the trench portion 40 is formed using a dry etching method. For example, the Bosch process can be used as the dry etching method. The shape of the trench portion 40 is, for example, 3 μm in width and 30 μm in depth. The width of the trench portion 40 is the length of the trench portion 40 in the X direction. The depth of the trench portion 40 is the length of the trench portion 40 in the Z direction.

Further, by forming the trench portion 40, the semiconductor layer 6 is physically separated into the first semiconductor layer 41 and the second semiconductor layer 42 facing the first semiconductor layer 41 through the trench portion 40. be done. By removing part of the semiconductor layer 6 in this manner, the trench portion 40 and the first semiconductor layer 41 and the second semiconductor layer 42 facing each other with the trench portion 40 therebetween are formed. In the present embodiment, the external shapes of the outer frame portion 9 and the fixed electrode portion 3 are formed in the movable portion forming step, which will be described later. The outer frame portion 9 formed in the movable portion forming step corresponds to the first semiconductor layer 41 , and the fixed electrode support portion 15 of the fixed electrode portion 3 corresponds to the second semiconductor layer 42 .

1.3 Trench Portion Filling Step Next, in step S3, as shown in FIGS. 9 and 10, the first semiconductor layer 41 and the second semiconductor layer 42 are simultaneously oxidized, and the A first sidewall oxide film 21 is formed on the first side surface W1 on the second semiconductor layer 42 side, and a second sidewall oxide film 22 is formed on the second side surface W2 of the second semiconductor layer 42 on the first semiconductor layer 41 side. The first sidewall oxide film 21 and the second sidewall oxide film 22 are brought into physical contact to fill the trench portion 40 .

In this embodiment, in step S2, the substrate 7 having the trench portion 40 formed thereon is put into an oxidation furnace, and the substrate 7 is oxidized in the oxidation furnace using a thermal oxidation method. Thereby, the first semiconductor layer 41 and the second semiconductor layer 42 can be oxidized at the same time. As the thermal oxidation method, for example, a pyrogenic oxidation method can be used. In order to shorten the oxidation treatment time, the oxidation treatment may be performed in a state of increased pressure. In addition, "simultaneously" in the present disclosure means performing processing in the same process or in the same device.

By oxidizing the first semiconductor layer 41 and the second semiconductor layer 42 at the same time, oxide films are simultaneously formed on the respective surfaces of the first and second semiconductor layers 41 and 42 . For convenience of explanation, among the oxide films formed on the surface of the first semiconductor layer 41, the oxide film formed on the first side surface W1 of the first semiconductor layer 41 is referred to as the first sidewall oxide film 21, and the first semiconductor layer 41 The oxide film formed on the upper surface of is referred to as a first upper surface oxide film 61 . Similarly, of the oxide films formed on the surface of the second semiconductor layer 42 , the oxide film formed on the second side surface W2 of the second semiconductor layer 42 is referred to as a second sidewall oxide film 22 . The oxide film formed on the upper surface is referred to as a second upper surface oxide film 62 . The upper surface of the first and second semiconductor layers 41 and 42 is the fourth surface F5 of the semiconductor layer 6. As shown in FIG.

In this embodiment, for example, a pyrogenic oxidation method is used to perform oxidation treatment at 1100° C. for 30 hours or more, so that each surface of the first semiconductor layer 41 and the second semiconductor layer 42 has a thickness of 3 μm or more. oxide film.

The first and second side wall oxide films 21 and 22 extend from the first side surface W1 of the first semiconductor layer 41 and the second side surface W2 of the second semiconductor layer 42 to the trench portion 40 as time elapses during the oxidation process. grow inward. As the thicknesses of the first and second sidewall oxide films 21 and 22 gradually increase, the first sidewall oxide film 21 and the second sidewall oxide film 22 come into physical contact, filling the trench portion 40. be

When the first sidewall oxide film 21 and the second sidewall oxide film 22 are in physical contact, the depth of the trench portion 40 is higher than the position where the first sidewall oxide film 21 and the second sidewall oxide film 22 are in physical contact. It is difficult to supply oxygen to the region near the bottom. Therefore, the first and second sidewall oxide films 21 and 22 grow in a region closer to the bottom surface of the trench portion 40 than the position where the first sidewall oxide film 21 and the second sidewall oxide film 22 physically contact each other. slows down or stops, and voids 50 tend to occur. Therefore, in step S3, an oxidation treatment is performed so that the thickness of the oxide films formed on the surfaces of the first and second semiconductor layers 41 and 42 is equal to or greater than the width of the trench portion 40 in step S2. can be sufficiently small.

Further, by sufficiently lengthening the oxidation treatment time, the upper and lower ends of the first and second side surfaces W1 and W2 of the first and second semiconductor layers 41 and 42 are rounded. The upper ends of the first and second side surfaces W1 and W2 are the ends of the first and second side surfaces W1 and W2 on the insulating film 5 side. The lower ends of the first and second side surfaces W1 and W2 are the ends of the first and second side surfaces W1 and W2 on the side opposite to the insulating film 5 side.

That is, the first side surface W1 of the first semiconductor layer 41 has a first curved surface portion R1 that protrudes toward the second semiconductor layer 42 at the end on the insulating film 5 side, and the first curved surface portion R1 on the side opposite to the insulating film 5 side. It has a convex second curved surface portion R2 on the second semiconductor layer 42 side at the end portion. The second side surface W2 of the second semiconductor layer 42 has a third curved surface portion R3 protruding toward the first semiconductor layer 41 at the end on the insulating film 5 side, and the end on the opposite side to the insulating film 5 side. has a convex fourth curved surface portion R4 on the first semiconductor layer 41 side.

In step S3, the first curved surface portion R1, the second curved surface portion R2, the third curved surface portion R3, and the fourth curved surface portion R4 are formed at the same time. As described above, "simultaneously" in the present disclosure means performing processing in the same process or in the same device. Therefore, the first curved surface portion R1, the second curved surface portion R2, the third curved surface portion R3, and the fourth curved surface portion R4 have approximately the same curvature. This increases the symmetry of parasitic capacitance such as fringe capacitance, making it possible to provide the acceleration sensor 1 with good bias characteristics.

Further, in the present embodiment, since the oxidation treatment is performed using the thermal oxidation method, impurities such as boron and phosphorus pre-doped in the first and second semiconductor layers 41 and 42 are diffused outward by heat. becomes easier. Therefore, in step S3, the low impurity concentration regions 45 and 46 can be formed in the vicinity of the surfaces of the first and second semiconductor layers 41 and 42, respectively.

Further, in step S3, the substrate 4 is partially oxidized by the oxygen that has diffused and migrated through the insulating film 5 through the bottom surface of the trench portion 40 . As a result, the film thickness of the region of the insulating film 5 contacting the trench portion 40 becomes thicker than the film thickness of the region of the insulating film 5 contacting the first and second semiconductor layers 41 and 42 . Further, in the region of the insulating film 5 in contact with the trench portion 40, the third surface F3, which is the upper surface of the insulating film 5, has a convex curved surface toward the trench portion 40, and the substrate 4, which is the lower surface of the insulating film 5, has a convex curved surface facing the substrate 4 .

1.4 Wiring Step Next, in step S4, wiring (not shown) electrically connected to the movable portion 2, wiring 29 electrically connected to the fixed electrode portion 3, electrode pads 27 and 28, and the like are formed. do.
As shown in FIGS. 11 and 12, in this embodiment, prior to forming the wiring 29 electrically connected to the fixed electrode portion 3, the wiring 29 is formed on the upper surfaces of the first and second semiconductor layers 41 and 42. First and second top oxide films 61 and 62, which are oxide films, are removed. That is, by removing the first and second upper surface oxide films 61 and 62, the upper surfaces of the first and second semiconductor layers 41 and 42 and the upper surfaces of the first and second sidewall oxide films 21 and 22 are smoothed. has been made

After smoothing the upper surfaces of the first and second semiconductor layers 41 and 42 and the upper surfaces of the first and second sidewall oxide films 21 and 22, the upper surfaces of the first and second semiconductor layers 41 and 42 and the An interlayer insulating film 24 is formed on the upper surfaces of 1 and second sidewall oxide films 21 and 22 .

As described above, the interlayer insulating film 24 is preferably a silicon oxide film formed of silicon oxide by thermal CVD. A silicon oxide film formed by a thermal CVD method has excellent step coverage. Therefore, by forming the interlayer insulating film 24 with silicon oxide by the thermal CVD method, the upper surfaces of the first and second semiconductor layers 41 and 42 and the upper surfaces of the first and second sidewall oxide films 21 and 22 are uneven. The interlayer insulating film 24 can be stably formed even when the insulating film 24 is formed. In addition, unevenness generated on the upper surfaces of the first and second semiconductor layers 41 and 42 and the upper surfaces of the first and second side wall oxide films 21 and 22 is eliminated by the interlayer insulating film 24 formed of silicon oxide by the thermal CVD method. Since it is absorbed, the electrode pads 27 and 28 and the wiring 29 can be stably formed on the upper surface of the interlayer insulating film 24 . In this embodiment, the interlayer insulating film 24 is formed of high-temperature silicon oxide HTO by low-pressure thermal CVD.

The interlayer insulating film 24 is patterned into a desired shape using a photolithographic technique. A wiring 29 is formed on the upper surface of the interlayer insulating film 24 . Although not shown in FIGS. 11 and 12, electrode pads 27 and 28 are also formed on the upper surface of interlayer insulating film 24 in the same manner as wiring 29 .

In this embodiment, by removing the first and second upper surface oxide films 61 and 62, the upper surfaces of the first and second semiconductor layers 41 and 42 and the first and second sidewall oxide films 21 and 22 are removed. Although the upper surface and , are smoothed, the first and second upper surface oxide films 61 and 62 do not have to be removed. For example, the upper surfaces of the first and second top oxide films 61 and 62 may be smoothed by chemical mechanical polishing (CMP) or etch back. Alternatively, the first and second top surface oxide films 61 and 62 may be used as the interlayer insulating film 24 without removing the first and second top surface oxide films 61 and 62 .

1.5 Movable Part Forming Step Next, in step S5, as shown in FIG. 13, the outlines of the movable part 2, the fixed electrode part 3, the outer frame part 9, and the like are formed. As described above, the movable portion 2 , the fixed electrode portion 3 , the outer frame portion 9 and the like are formed using the semiconductor layer 6 . In this embodiment, the unnecessary portions of the semiconductor layer 6 are removed by dry etching or the like depending on the shape of each portion such as the movable portion 2, the fixed electrode portion 3 and the outer frame portion 9. FIG. As a result, the external shapes of the movable portion 2, the fixed electrode portion 3, the outer frame portion 9, and the like are formed to form the acceleration sensor 1 shown in FIG.

As described above, according to this embodiment, the following effects can be obtained.
An acceleration sensor 1 as an example of an inertial sensor includes a substrate 4, an insulating film 5 formed on a first surface F1 that is the main surface of the substrate 4, and a surface of the insulating film 5 that is opposite to the substrate 4. The first and second semiconductor layers 41 and 42 formed on the third surface F3, the first sidewall oxide film 21 formed on the first side surface W1 of the first semiconductor layer 41 on the side of the second semiconductor layer 42, and the second a second sidewall oxide film 22 formed on a second side surface W2 of the semiconductor layer 42 on the side of the first semiconductor layer 41, the first side surface W1 being on the side of the second semiconductor layer 42 at the end portion on the side of the insulating film 5; has a convex first curved surface portion R1 on the opposite side to the insulating film 5 side, and has a convex second curved surface portion R2 on the second semiconductor layer 42 side at the end opposite to the insulating film 5 side; The end on the insulating film 5 side has a third curved surface portion R3 that protrudes toward the first semiconductor layer 41 side, and the end portion opposite to the insulating film 5 has a fourth curved surface portion R3 that protrudes toward the first semiconductor layer 41 side. Having a curved surface portion R4, the first sidewall oxide film 21 and the second sidewall oxide film 22 are in physical contact.
As a result, parasitic capacitance such as fringe capacitance between the first semiconductor layer 41 and the second semiconductor layer 42 can be reduced, so the acceleration sensor 1 with good bias characteristics can be provided.

A method of manufacturing an acceleration sensor 1 as an example of an inertial sensor comprises: a substrate 4; an insulating film 5 formed on a first surface F1 of the substrate 4; a semiconductor layer 6 formed on a third surface F3 of the insulating film 5; , and removing part of the semiconductor layer 6 to form a trench portion 40 and a first semiconductor layer 41 and a second semiconductor layer 42 facing each other via the trench portion 40. and simultaneously oxidizing the first semiconductor layer 41 and the second semiconductor layer 42 to form the first sidewall oxide film 21 on the first side surface W1 of the first semiconductor layer 41 and the second oxide film 21 of the second semiconductor layer 42 . forming a second sidewall oxide film 22 on the side surface W2, and burying the trench portion 40 by bringing the first sidewall oxide film 21 and the second sidewall oxide film 22 into physical contact with each other.
Thus, it is possible to provide a method for manufacturing the acceleration sensor 1 with good bias characteristics.

In this embodiment, the outer frame portion 9 corresponds to the first semiconductor layer 41 , the fixed electrode support portion 15 corresponds to the second semiconductor layer 42 , and between the outer frame portion 9 and the fixed electrode support portion 15 Although the insulating isolation region 20 having the first and second side wall oxide films 21 and 22 is formed, the first and second semiconductor layers 41 and 42 do not need to be the outer frame portion 9 or the fixed electrode support portion 15. I do not care. For example, assuming that the insulating separation region 20 is formed between the movable portion 2 and the outer frame portion 9, the movable portion 2 corresponds to the first semiconductor layer 41, and the outer frame portion 9 corresponds to the second semiconductor layer 42. , an isolation region 20 having first and second sidewall oxide films 21 and 22 may be formed between the movable portion 2 and the outer frame portion 9 .

In the present embodiment, a sensor that detects acceleration in the Y direction has been exemplified as the acceleration sensor 1, but the acceleration sensor 1 may be a sensor that detects acceleration in the X or Z direction, for example. . Although the acceleration sensor 1 has been described as an example of the inertial sensor in the present embodiment, the inertial sensor may be, for example, an angular velocity sensor.

2. Embodiment 2
Next, an acceleration sensor 1a as an example of an inertial sensor according to Embodiment 2 will be described with reference to FIG. FIG. 14 corresponds to a cross-sectional view at the position of D1 in FIG. In addition, the same code|symbol is attached|subjected about the structure same as Embodiment 1, and the overlapping description is abbreviate|omitted.

The acceleration sensor 1a according to the second embodiment differs from that of the first embodiment except that the shapes of the first and second side surfaces W1a and W2a of the first and second semiconductor layers 41 and 42 are different. It is the same.

As shown in FIG. 14, on the first side surface W1a of the first semiconductor layer 41 on the side of the second semiconductor layer 42, the first curved surface portion R1 and the second curved surface portion R2 are formed by a flat surface portion L1a and a flat surface portion L3a. Concatenated. The plane portion L3a is arranged on the insulating film 5 side below the plane portion L1a. The upper end of the flat portion L1a is connected to the second curved surface portion R2. The lower end of the plane portion L1a is connected to the upper end of the plane portion L3a. A lower end of the flat portion L3a is connected to the first curved portion R1. The upper ends of the plane portions L1a and L3a are the ends of the plane portions L1a and L3a opposite to the insulating film 5 side. The lower ends of the plane portions L1a and L3a are the ends of the plane portions L1a and L3a on the insulating film 5 side.

The flat portion L1a extends substantially parallel to the Z direction.
The flat portion L3a extends so as to intersect the Z direction. Specifically, the planar portion L3a is inclined so as to approach the second semiconductor layer 42 toward the insulating film 5 . In other words, the plane portion L3a corresponds to a first slope portion that slopes toward the second semiconductor layer 42 toward the insulating film 5 .

Similarly, on the second side surface W2a of the second semiconductor layer 42 on the side of the first semiconductor layer 41, the third curved surface portion R3 and the fourth curved surface portion R4 are connected by a flat surface portion L2a and a flat surface portion L4a. . The plane portion L4a is arranged on the insulating film 5 side below the plane portion L2a. The upper end of the flat portion L2a is connected to the fourth curved surface portion R4. The lower end of the plane portion L2a is connected to the upper end of the plane portion L4a. A lower end of the flat portion L4a is connected to the third curved surface portion R3. The upper ends of the planar portion L2a and the planar portion L4a are the ends of the planar portion L2a and the planar portion L4a on the side opposite to the insulating film 5 side. The lower ends of the plane portion L2a and the plane portion L4a are the ends of the plane portion L2a and the plane portion L4a on the insulating film 5 side.

The flat portion L2a extends substantially parallel to the Z direction.
The plane portion L4a extends so as to intersect the Z direction. Specifically, the plane portion L4a is inclined so as to approach the first semiconductor layer 41 toward the insulating film 5 . In other words, the plane portion L4a corresponds to a second slope portion that slopes toward the first semiconductor layer 41 toward the insulating film 5 .

As described above, in the present embodiment, the first side surface W1a has the plane portion L3a as the first slope portion that inclines so as to approach the second semiconductor layer 42 toward the insulating film 5, and the second side surface W2a has the plane portion L3a. , and a plane portion L4a as a second slope portion that slopes toward the first semiconductor layer 41 toward the insulating film 5 . Thereby, the gap 50 can be made even smaller. In other words, the height H2 of the contact region C1 where the first sidewall oxide film 21 and the second sidewall oxide film 22 physically contact can be further increased.

According to this embodiment, in addition to the effects of the first embodiment, the following effects can be obtained.
The first side surface W1a has a plane portion L3a as a first slope portion, and the second side surface W2a has a plane portion L4a as a second slope portion. As a result, the gap 50 can be further reduced and the height H2 of the contact area C1 can be further increased, so that the mechanical characteristics and temperature characteristics of the acceleration sensor 1 may change due to external forces such as vibrations and impacts, and environmental changes such as temperature. It is possible to further suppress deterioration and provide an acceleration sensor 1a having higher reliability.

3. Embodiment 3
Next, an acceleration sensor 1b as an example of an inertial sensor according to Embodiment 3 will be described with reference to FIG. FIG. 15 corresponds to a cross-sectional view at the position of D1 in FIG. In addition, the same code|symbol is attached|subjected about the structure same as Embodiment 1, and the overlapping description is abbreviate|omitted.

The acceleration sensor 1b according to the third embodiment is different from that of the first embodiment except that the shapes of the first and second side surfaces W1b and W2b of the first and second semiconductor layers 41 and 42 are different. It is the same.

As shown in FIG. 15, on the first side surface W1b of the first semiconductor layer 41 on the second semiconductor layer 42 side, the first curved surface portion R1 and the second curved surface portion R2 are connected by a plane portion L3b.

The plane portion L3b extends so as to intersect the Z direction. Specifically, the plane portion L3b is inclined so as to approach the second semiconductor layer 42 toward the insulating film 5 . In other words, the plane portion L3b corresponds to a first slope portion that slopes toward the second semiconductor layer 42 toward the insulating film 5 .

Similarly, on the second side surface W2b of the second semiconductor layer 42 on the first semiconductor layer 41 side, the third curved surface portion R3 and the fourth curved surface portion R4 are connected by a flat surface portion L4b.

The plane portion L4b extends so as to intersect the Z direction. Specifically, the plane portion L4b is inclined so as to approach the first semiconductor layer 41 toward the insulating film 5 . In other words, the plane portion L4b corresponds to a second slope portion that slopes toward the first semiconductor layer 41 toward the insulating film 5 .

As described above, in the present embodiment, the first side surface W1b has the plane portion L3b as the first slope portion that inclines so as to approach the second semiconductor layer 42 toward the insulating film 5, and the second side surface W2b has the plane portion L3b. , and a plane portion L4b as a second slope portion that slopes toward the first semiconductor layer 41 toward the insulating film 5 .

To reduce the gap 50 by increasing the angle at which the Z axis intersects the plane portion L3b as the first slope portion and the angle at which the Z axis intersects the plane portion L4b as the second slope portion. can be done. In other words, by increasing the angle at which the Z-axis intersects the plane portion L3b as the first slope portion and the angle at which the Z-axis intersects the plane portion L4b as the second slope portion, the first sidewall The height H2 of the contact region C1 where the oxide film 21 and the second sidewall oxide film 22 physically contact can be increased.

Here, LD is the distance between the plane portion L3b and the plane portion L4b. A distance LD between the plane portion L3b and the plane portion L4b has a maximum value LDmax and a minimum value LDmin. A distance LD between the plane portion L3b and the plane portion L4b decreases from the positive side in the Z direction toward the negative side in the Z direction. In other words, the distance LD between the plane portion L3b and the plane portion L4b increases toward the fourth surface F5 of the semiconductor layer 6 and decreases toward the insulating film 5 side. That is, the maximum value LDmax is near the fourth surface F5 of the semiconductor layer 6, and the minimum value LDmin is near the third surface F3, which is the upper surface of the insulating film 5. FIG.

The gap 50 can be made smaller by increasing the difference between the maximum value LDmax and the minimum value LDmin of the distance LD between the plane portion L3b and the plane portion L4b. In other words, by increasing the difference between the maximum value LDmax and the minimum value LDmin, the height H2 of the contact region C1 where the first sidewall oxide film 21 and the second sidewall oxide film 22 physically contact can be increased. can do.

In addition, in the present embodiment, the angle at which the Z axis intersects with the plane portion L3b as the first slope portion and the angle at which the Z axis and the plane portion L4b as the second slope portion intersect are sufficiently large. Thus, the void 50 can be prevented from being generated. Alternatively, by sufficiently increasing the difference between the maximum value LDmax and the minimum value LDmin of the distance LD between the plane portion L3b and the plane portion L4b, the air gap 50 can be prevented from occurring. Note that FIG. 15 shows, as an example of the state of the void 50, a state in which the void 50 is not generated. Therefore, the air gap 50 is not shown in FIG.

Table 1 shows the distance LD between the flat portion L3b and the flat portion L4b and H2/H1, which is the ratio of the height H2 of the contact area C1 to the height H1 of the first and second side surfaces W1 and W2. The results calculated by thermal oxidation simulation are shown. In Table 1, the ratio of the difference (LDmax −LDmin)/LDmax are shown in percentage.

When the difference between the maximum value LDmax and the minimum value LDmin of the distance LD between the plane portions L3b and L4b is 0 (zero), the plane portions L3b and L4b are parallel to the Z axis. H2/H1 at this time was 0.905. When the difference between the maximum value LDmax and the minimum value LDmin is 33.3% with respect to the maximum value LDmax, that is, when the ratio of the difference between the maximum value LDmax and the minimum value LDmin to the maximum value LDmax is 1/3, this H2/H1 at that time was 0.946. Furthermore, H2/H1 was 1.000 when the difference between the maximum value LDmax and the minimum value LDmin was 93.3% with respect to the maximum value LDmax. That is, the first sidewall oxide film 21 and the second sidewall oxide film 22 were all in contact.

In this embodiment, H2/H1 is 0.961 when the difference between the maximum value LDmax and the minimum value LDmin of the distance LD between the plane portion L3b and the plane portion L4b is 50% of the maximum value LDmax. Met.

The preferred range of H2/H1 in the present invention is 0.905 or more and 1 or less, more preferably 0.946 or more and 1 or less. Therefore, the range of the difference between the maximum value LDmax and the minimum value LDmin of the distance LD between the plane portion L3b and the plane portion L4b is preferably 0% or more and 100% or less of the maximum value LDmax. More preferably, it is 33.3% or more and 100% or less. As a result, it is possible to suppress the deterioration of the mechanical characteristics and temperature characteristics of the acceleration sensor 1 due to external forces such as vibrations and impacts and environmental changes such as temperature, thereby providing the acceleration sensor 1 with high reliability.

According to this embodiment, in addition to the effects of the first embodiment, the following effects can be obtained.
The first side surface W1b has a plane portion L3b as a first slope portion, and the second side surface W2b has a plane portion L4b as a second slope portion. As a result, the gap 50 can be further reduced and the height H2 of the contact area C1 can be further increased, so that the mechanical characteristics and temperature characteristics of the acceleration sensor 1 may change due to external forces such as vibrations and impacts, and environmental changes such as temperature. It is possible to further suppress deterioration and provide the acceleration sensor 1b having higher reliability.

4. Embodiment 4
Next, an inertial measurement unit 2000 (IMU: Inertial Measurement Unit) including acceleration sensors 1, 1a and 1b according to Embodiment 4 will be described with reference to FIGS. 16 and 17. FIG. In the following description, a configuration to which the acceleration sensor 1 is applied will be described as an example.

The inertial measurement device 2000 is a device that detects inertial momentum such as the posture and behavior of a moving body such as an automobile or a robot. The inertial measurement device 2000 includes inertial sensors such as an acceleration sensor and an angular velocity sensor, and functions as a so-called motion sensor.

As shown in FIG. 16, the inertial measurement device 2000 is a cuboid with a substantially square planar shape. The inertial measurement device 2000 has an outer case 301, a joint member 310, and a sensor module 325 on which an inertial sensor is mounted.

The external shape of the outer case 301 is a rectangular parallelepiped with a substantially square planar shape, similar to the overall shape of the inertial measurement device 2000, and screw holes 302 are formed in the vicinity of two vertices located in the diagonal direction of the square. there is By passing two screws through the two screw holes 302, the inertial measurement device 2000 can be fixed to a mounting surface of a mounting body such as an automobile.

Further, the outer case 301 is box-shaped, and the sensor module 325 is housed inside. Specifically, the sensor module 325 is inserted inside the outer case 301 with the joint member 310 interposed therebetween.

Sensor module 325 has inner case 320 and substrate 315 .

The inner case 320 is a member that supports the substrate 315, and the substrate 315 is bonded to the lower surface of the inner case 320 via an adhesive.

Further, the inner case 320 has a shape that fits inside the outer case 301 . The inner case 320 is formed with a recess 331 for preventing contact with the substrate 315 and an opening 321 for exposing a connector 316, which will be described later. Inner case 320 is joined to outer case 301 via joining member 310 .

Next, the board 315 on which the inertial sensor is mounted will be described.
As shown in FIG. 17, an acceleration sensor 1, a connector 316, an angular velocity sensor 317z for detecting an angular velocity about the Z-axis, and the like are mounted on the inner case 320 side surface of the substrate 315. As shown in FIG. On the side surface of the substrate 315, an angular velocity sensor 317x for detecting angular velocity around the X axis and an angular velocity sensor 317y for detecting angular velocity around the Y axis are mounted.

Note that the acceleration sensor 1 may be, for example, an acceleration sensor capable of detecting acceleration in two directions, the X direction and the Y direction, or an acceleration sensor capable of detecting acceleration in three directions, the X direction, the Y direction, and the Z direction. It can also be used as a sensor.

A control IC 319 as a control unit is mounted on the surface of the substrate 315 on the outer case 301 side, which is the lower surface of the substrate 315 . The control IC 319 is an MCU (Micro Controller Unit), incorporates a storage section including a nonvolatile memory, an A/D converter, and the like, and controls each section of the inertial measurement device 2000 . The storage unit stores a program that defines the order and contents for detecting acceleration and angular velocity, a program that digitizes detected data and incorporates it into packet data, accompanying data, and the like. A plurality of other electronic components are also mounted on the substrate 315 .

Since the inertial measurement device 2000 uses the acceleration sensor 1 as an example of the inertial sensor described above, the inertial measurement device 2000 that enjoys the effects of the acceleration sensor 1 can be provided.

DESCRIPTION OF SYMBOLS 1, 1a, 1b... Acceleration sensor 2... Movable part 3... Fixed electrode part 4... Substrate 5... Insulating film 6... Semiconductor layer 7... Substrate 8... Concave part 9... Outer frame part 10... Movable electrode supporting portion 11 Movable electrode finger 15 Fixed electrode supporting portion 16 Fixed electrode finger 20 Insulating isolation region 21 First side wall oxide film 22 Second side wall oxide film 40 Trench portion , 41... First semiconductor layer, 42... Second semiconductor layer, 50... Gap, 2000... Inertial measurement device, 319... Control IC, F1... First surface, F3... Third surface, R1... First curved surface portion, R2 2nd curved surface portion, R3 3rd curved surface portion, R4 4th curved surface portion, W1, W1a, W1b 1st side surface, W2, W2a, W2b 2nd side surface.

Claims (6)

a substrate;
an insulating film formed on the main surface of the substrate;
a first semiconductor layer and a second semiconductor layer formed on a surface of the insulating film opposite to the substrate;
a first sidewall oxide film formed on a first side surface of the first semiconductor layer on the second semiconductor layer side;
a second sidewall oxide film formed on a second side surface of the second semiconductor layer on the side of the first semiconductor layer;
The first side surface has a convex first curved surface portion on the second semiconductor layer side at an end portion on the insulating film side, and an end portion on the side opposite to the insulating film side on the second semiconductor layer side. has a convex second curved surface portion,
The second side surface has a third curved surface portion protruding toward the first semiconductor layer at an end portion on the insulating film side, and an end portion opposite to the insulating film side on the first semiconductor layer side. has a convex fourth curved surface portion,
the first sidewall oxide and the second sidewall oxide are in physical contact;
inertial sensor. a gap surrounded by the insulating film, the first sidewall oxide film, and the second sidewall oxide film;
The inertial sensor of Claim 1. the first side surface has a first slope portion that slopes toward the second semiconductor layer toward the insulating film;
The second side surface has a second slope portion that slopes toward the first semiconductor layer toward the insulating film,
The inertial sensor of Claim 1. the first semiconductor layer and the second semiconductor layer are single crystal silicon;
wherein the first sidewall oxide film and the second sidewall oxide film are silicon oxide;
The inertial sensor according to any one of claims 1 to 3. preparing a base having a substrate, an insulating film formed on a main surface of the substrate, and a semiconductor layer formed on a surface of the insulating film opposite to the substrate;
forming a trench portion and a first semiconductor layer and a second semiconductor layer facing each other through the trench portion by removing a portion of the semiconductor layer;
The first semiconductor layer and the second semiconductor layer are simultaneously oxidized to form a first sidewall oxide film on the first side surface of the first semiconductor layer on the side of the second semiconductor layer and the second oxide film on the second semiconductor layer. forming a second sidewall oxide film on a second side surface of one semiconductor layer, and burying the trench portion by bringing the first sidewall oxide film and the second sidewall oxide film into physical contact;
A method for manufacturing an inertial sensor having an inertial sensor according to any one of claims 1 to 4;
a control unit that controls the inertial sensor;
inertial measurement device.

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