JP2023027421A - Timing controller, display system, and automobile - Google Patents

Abstract

To provide a display system with a simplified system structure.SOLUTION: A display unit 110 has a display panel 112 and a panel driver 300. A controller unit 130 has a graphic controller 132 and a timing controller IC 200. The graphic controller 132 generates plural pieces of individual image data IMG to display in a plurality of display units 110, and generates one synthesis image data IMGc formed by combining the image data. The timing controller IC 200 receives the synthesis image data IMGc from the graphic controller 132, and divides the synthesis image data into a plurality of individual image data IMG1 to IMG3. The timing controller IC 200 generates a control signal CNTi for controlling a panel driver 300_i of each display unit 110, and sends a control signal CNTi corresponding to a specific individual image data IMGi.SELECTED DRAWING: Figure 2

Description

The present invention relates to timing controllers and display systems.

2. Description of the Related Art In recent years, automobiles are becoming more sophisticated, and a plurality of display units are provided in the vehicle interior. FIG. 1 is a diagram showing a conventional display system 1100. As shown in FIG. The display system 1100 comprises a plurality (three in this example) of display units 1110_1-1110_3, a plurality of interface units 1120_1-1120_3, and a control unit 1130. FIG.

Each display unit 1110 comprises a display panel 1112 , a panel driver 1114 and a timing controller 1116 . A display panel 1112 is a liquid crystal display panel, an organic EL panel, or a micro LED panel. The panel driver 1114 includes a source driver (data driver) and a gate driver (scan driver), and is configured to be able to drive the display panel 1112 .

The timing controller 1116 controls the panel driver 1114 based on the input image data to appropriately display the image data on the display panel 1112 . Specifically, timing controller 1116 generates various driver control signals (timing signals) for controlling panel driver 1114 . Note that the panel driver 1114 and the timing controller 1116 may be integrated into one chip.

Control unit 1130 includes graphics controller 1132 . The graphic controller 1132 generates three image data to be displayed on the display units 1110_1 to 1110_3 and outputs them from three output ports.

If the distance between the control unit 1130 and the display units 1110_1 to 1110_3 is as long as several meters, the image data cannot be transmitted directly from the output port of the graphics controller 1132 to the timing controller 1116. FIG. Therefore, the control unit 1130 is provided with a plurality of serializer/driver ICs 1134 , and each display unit 1110 side is provided with an interface unit 1120 .

Interface unit 1120 includes a receiver deserializer IC 1122 and a microcontroller 1124 . The serializer/driver IC 1134_i (i=1, 2, . . . ) and the receiver/deserializer IC 1122 are configured to enable long-distance high-speed serial transmission.

Microcontroller 1124 monitors each circuit block of display unit 1110 to detect anomalies. Anomalies detected by the microcontroller 1124 are notified to the graphics controller 1132 .

JP 2018-031926 A

The display system 1100 of FIG. 1 has the problem that an interface unit 1120 is required for each display unit 1110, complicating the system.

The present invention has been made in view of such problems, and one exemplary object of certain aspects thereof is to provide a display system with a simplified system configuration.

One aspect of the invention relates to a timing controller for a display system having multiple display units. Each display unit includes a display panel and a panel driver. a timing controller, an interface circuit for receiving, from the graphic controller, one composite image data obtained by combining a plurality of individual image data to be displayed on a plurality of display units; A signal processing unit that generates a plurality of driver control signals for controlling the panel drivers of each of the plurality of display units, and a plurality of serializers that correspond to the plurality of display units, each of which has corresponding individual image data and corresponding a plurality of serializers for converting the driver control signals to serial data; and a plurality of transmitters corresponding to the plurality of display units, each transmitting the output of the corresponding serializer to the corresponding display unit. And prepare.

Another aspect of the invention is a display system. The display system comprises a plurality of display units each having a display panel and a panel driver, and a control unit connected with the plurality of display units. A control unit generates a plurality of individual image data to be displayed on a plurality of display units, and receives and synthesizes the composite image data from the graphic controller, which generates a single composite image data by combining them, and the graphic controller. dividing the image data into a plurality of individual image data, generating a plurality of driver control signals for controlling panel drivers for each of the plurality of display units; a timing controller for transmitting a control signal.

Arbitrary combinations of the above constituent elements, or conversions of the expressions of the present invention between methods, apparatuses, and the like are also effective as embodiments of the present invention.

According to an aspect of the invention, a display system with multiple display units can be simplified and/or reduced in cost.

1 illustrates a conventional display system; FIG. 1 is a block diagram of a display system according to an embodiment; FIG. FIG. 4 is a diagram for explaining composite image data IMGc; It is a figure explaining the reassignment of the display at the time of abnormality. 1 is a block diagram of a timing controller IC according to one embodiment; FIG. 1 is a block diagram of a panel driver IC according to one embodiment; FIG. FIG. 10 is a diagram showing a modified example of the synthetic image IMGc; FIG. 11 is a block diagram of a display unit according to Modification 2; 14 is a block diagram of a display unit according to Modification 3. FIG. FIG. 12 is a block diagram of a display unit according to Modification 4; 1 shows the interior of a motor vehicle with a display system; FIG.

(Overview of Embodiment)
A timing controller is disclosed herein. A timing controller is used in a display system having multiple display units. Each display unit includes a display panel and a panel driver. a timing controller, an interface circuit for receiving, from the graphic controller, one composite image data obtained by combining a plurality of individual image data to be displayed on a plurality of display units; A signal processing unit that generates a plurality of driver control signals for controlling the panel drivers of each of the plurality of display units, and a plurality of serializers that correspond to the plurality of display units, each of which has corresponding individual image data and corresponding a plurality of serializers for converting the driver control signals to serial data; and a plurality of transmitters corresponding to the plurality of display units, each transmitting the output of the corresponding serializer to the corresponding display unit. And prepare.

This configuration eliminates the need to provide a timing controller for each display unit, thereby simplifying the system. Also, since the graphic controller only needs to output one piece of composite image data to one timing controller, the number of output ports can be reduced, or the remaining output ports can be used for other purposes.

The distance between the transmitter and the corresponding panel driver may be 1-10 meters.

The signal processing section may be configured to be able to display individual image data corresponding to the abnormal display unit on a normal display unit when an abnormality occurs in one of the plurality of display units. As a result, the graphic controller only needs to generate the same image in both normal and abnormal conditions, eliminating the need for special image processing for abnormality protection in the graphic controller.

The signal processor may have an OSD (On Screen Display) function.

Another aspect of the invention is a display system. The display system comprises a plurality of display units each having a display panel and a panel driver, and a control unit connected with the plurality of display units. A control unit generates a plurality of individual image data to be displayed on a plurality of display units, and receives and synthesizes the composite image data from the graphic controller, which generates a single composite image data by combining them, and the graphic controller. dividing the image data into a plurality of individual image data, generating a plurality of driver control signals for controlling panel drivers for each of the plurality of display units; a timing controller for transmitting a control signal.

The distance between the timing controller and the multiple panel drivers may be 1-10 meters.

The timing controller may be configured so that, when an abnormality occurs in one of the plurality of display units, individual image data corresponding to the abnormal display unit can be displayed on a normal display unit.

The timing controller may have an OSD (On Screen Display) function. The timing controller may be configured to display OSD characters to be displayed on the abnormal display unit on the normal display unit when an abnormality occurs in one of the plurality of display units.

The control unit may be provided with a microcontroller and the plurality of display units may be free of microcontrollers.

(Embodiment)
BEST MODE FOR CARRYING OUT THE INVENTION The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent constituent elements, members, and processes shown in each drawing are denoted by the same reference numerals, and duplication of description will be omitted as appropriate. Moreover, the embodiments are illustrative rather than limiting the invention, and not all features and combinations thereof described in the embodiments are necessarily essential to the invention.

In this specification, "a state in which member A is connected to member B" refers to a case in which member A and member B are physically directly connected, or a case in which member A and member B are electrically connected to each other. It also includes the case of being indirectly connected via other members that do not substantially affect the connected state or impair the functions and effects achieved by their combination.

Similarly, "the state in which member C is provided between member A and member B" refers to the case where member A and member C or member B and member C are directly connected, as well as the case where they are electrically connected. It also includes the case of being indirectly connected through other members that do not substantially affect the physical connection state or impair the functions and effects achieved by their combination.

FIG. 2 is a block diagram of display system 100 according to an embodiment. The display system 100 includes a plurality (three in this example) of display units 110_1 to 110_3 and a control unit .

Each display unit 110_i and the control unit 130 are placed about 1 m to 10 m apart, and the display unit 110_i and the control unit 130 are connected via a panel interface 150 capable of long-distance transmission. The panel interface 150 is physically composed of differential wiring formed on an FPC (Flexible Printed Circuit) board or housed in a cable. The control unit 130 centrally controls the plurality of display units 110_1 to 110_3. The panel interface 150 includes transmission channels (image transmission channels) 152_1 to 152_3 for transmitting image data and control signals corresponding to the plurality of display units 110. FIG.

Display unit 110_i (i=1, 2, 3) includes display panel 112_i and panel driver IC 300_i. The display panel 112 is typically a liquid crystal (LCD) panel, but may also be an organic EL panel or a micro LED panel. Further, the resolution and aspect ratio of the display panels 112_1 to 112_3 do not need to be the same, and can be determined individually according to the information to be displayed on each of the display panels 112_1 to 112_3.

Panel driver IC 300_i receives individual image data IMGi and a driver control signal (timing signal) for display from control unit 130 via image transmission channel 152_i, and controls display panel 112_i. Although details will be described later, the panel driver IC 300 includes a source driver (also called a data driver), a gate driver (also called a scan driver), a receiver circuit for long-distance transmission, and a deserializer.

Control unit 130 comprises graphics controller 132 , microcontroller 134 and timing controller IC 200 . The graphic controller 132 is an SOC (System On Chip) including a graphic processor, and generates individual image data IMG1-IMG3 to be displayed on the plurality of display panels 112_1-112_3. The graphic controller 132 combines a plurality of individual image data IMG1 to IMG3 to generate a single combined image data IMGc. The graphic controller 132 transmits the RGB value of each pixel of the combined image data IMGc from its output port to the timing controller IC 200 along with control signals such as the pixel clock CLK, vertical synchronization signal Vsync, horizontal synchronization signal Hsync, and data enable signal DE. and send.

FIG. 3 is a diagram for explaining the composite image data IMGc. In this example, a plurality of individual image data IMG1-IMG3 are combined in the horizontal direction. The horizontal resolution x _c of the combined image data IMGc is greater than the sum of the horizontal resolutions x ₁ , x ₂ and x ₃ of the individual image data IMG1 to IMG3. The vertical resolution _yc of the combined image data IMGc is greater than the maximum value ( _y1 in this example) of the vertical resolutions _y1 , _y2 , and _y3 of the individual image data IMG1 to IMG3. The composite image data IMGc can include a blank area (blank period), and this blank area may be used to transmit control signals other than image data. In FIG. 3, a plurality of pieces of individual image data IMG1 to IMG3 are adjacent without gaps, but blank intervals may be inserted between them.

Return to FIG. The timing controller IC 200 receives composite image data IMGc from the graphics controller 132 . The timing controller IC200 divides the combined image data IMGc into a plurality of individual image data IMG1 to IMG3.

The timing controller IC200 generates a driver control signal (timing signal) CNTi for controlling the panel driver IC300_i of the corresponding display unit 110_i for each individual image data IMGi. The generation of the driver control signal CNTi in the timing controller IC 200 is the same as the well-known technique, so the explanation is omitted. Driver control signal CNTi includes a plurality of timing signals. Those skilled in the art will appreciate that the name and symbol for each driver control signal may vary from manufacturer to manufacturer.

1. Driver Control Signals for Source Driver 1.1 Start Pulse (STH)
A plurality of source drivers or gate drivers may be cascade-connected depending on the panel size (resolution) of the display panel. Image data and driver control signals output from the timing controller pass through the plurality of source drivers in order. A plurality of source drivers sequentially advance the start pulse STH like a shift register. A source driver to which a start pulse STH is input takes in image data.

1.2 Latch pulse (LOAD)
The latch pulse LOAD is asserted every scan line. The source driver takes in image data for one scanning line when the latch pulse LOAD is asserted.

1.3 Alternating signal (POL)
The source driver drives the display panel while alternately inverting its polarity. The polarity of the source driver is determined by the alternating signal POL.

2. 2. Driver control signals for gate drivers 2.1 Vertical shift direction input/output signal (STV)
Used when multiple gate drivers are cascaded. The vertical shift direction input/output signal STV is sequentially shifted by a plurality of gate drivers.

2.2 Vertical transfer clock (CPV)
Each gate driver takes in the input vertical shift direction input/output signal STV at the timing of the positive edge of this vertical transfer clock CPV.

2.3 Output Enable (OE)
Data that controls the state of the output terminal of the gate driver. When the output enable OE is asserted, a drive voltage is applied to the gate line (scanning line) GL, and when negated, the potential of the gate line GL is fixed.

The types and number of driver control signals CNT are not limited to those exemplified here.

A microcontroller 134 is provided for functional safety. The microcontroller 134 and the timing controller IC 200 are connected via an interface such as I ² C (Inter IC). Status information (for example, error information) of the display units 110_1 to 110_3 is collected in the timing controller IC200 and written to registers within the timing controller IC200.

The means for collecting the status information of the display units 110_1 to 110_3 in the timing controller IC 200 is not limited. For example, in addition to the image transmission channel 152, an auxiliary channel may be added to the panel interface 150, and the status information of each display unit may be transmitted to the timing controller via this auxiliary channel. The auxiliary channel may employ a bi-directional serial interface, and communications over the auxiliary channel may utilize an ^I2C (Inter IC) compatible protocol.

Microcontroller 134 can detect anomalies occurring in display units 110_1-110_3 by accessing registers in timing controller IC200.

The above is the overall configuration of the display system 100 . The advantages are then described in contrast to the display system 1100 of FIG.

In the display system 1100 of FIG. 1, a timing controller 1116 was implemented for each display unit 1110, requiring three timing controllers for the entire system. On the other hand, according to the display system 100 of FIG. 2, only a single timing controller IC 200 needs to be provided on the control unit 130 side, so the system can be simplified.

In display system 1100 of FIG. 1, graphics controller 1132 has at least three output ports dedicated to outputting image data. On the other hand, in the display system 100 of FIG. 2, the image output port of the graphic controller 132 can be reduced to one, and the remaining output port can be used for other purposes and functions. .

Further, in the display system 1100 of FIG. 1, it was necessary to provide a plurality of serializer/driver ICs 1134 in the control unit 1130 . On the other hand, in the display system 100 of FIG. 2, the functions corresponding to the serializer/driver IC are integrated into the timing controller IC 200, so that the number of parts can be reduced and the system can be further simplified.

Also, in the display system 1100 of FIG. 1, a microcontroller 1124 is provided for each display unit 1110 . On the other hand, in the display system 100 of FIG. 2, status information (for example, error information) of a plurality of display units 110 is collected in the timing controller IC 200, and a single microcontroller 134 is provided in the control unit 130. . This can further simplify the system.

Additional functions and processes of the display system 100 will now be described.

(Reassignment of display when an error occurs)
The timing controller 200 is configured to be able to detect an abnormality occurring in each of the plurality of display units 110_1-110_3. The type of abnormality is not limited, but examples include an abnormality in panel driver IC 300, an abnormality in display panel 112, an abnormality in communication between panel driver IC 300 and timing controller IC 200, and an abnormality in a power supply circuit (not shown).

When an abnormality occurs in one of the display units 110_j (j=1 to 3), the timing controller IC 200 transfers individual image data IMGj corresponding to the display unit 110_j in which the abnormality has occurred to another normal display unit 110_k(k = 1 to 3, k≠j) (reassignment). FIG. 4 is a diagram for explaining reassignment of displays in the event of an abnormality. Here, an abnormality has occurred in the display unit 110_3, and the individual image data IMG3 is reassigned and displayed on the display panel 112_1.

For example, the timing controller IC 200 transfers part or all of the individual image data IMGj to be displayed on the abnormal display unit 110_j to part or all of the display panel 112_k of the normal display unit 110_k in a picture-in-picture format. , may be overlaid and drawn. When overlaying, the individual image data IMGj may be reduced.

Note that the reassignment of individual image data can be performed under the control of the microcontroller 134 . That is, the microcontroller 134 is notified of the status information of the plurality of display units 110_1 to 110_3 integrated in the timing controller IC200. In response to this notification, microcontroller 134 may instruct timing controller IC 200 to reassign. For example, the microcontroller 134 may specify the individual image data to be reassigned, the display panel number of the reassignment destination, the display position, the display size, and the like.

Alternatively, the timing controller IC 200 may autonomously perform abnormal reassignment according to predetermined rules without requiring control from the microcontroller 134 .

If the same function is to be implemented in the display system 1100 of FIG. 1, the graphics controller 1132 needs to perform overlay processing, which increases the load on the graphics controller 1132 . In contrast, in the display system 100 of FIG. 2, the reassignment can be accomplished without the intervention of the graphics controller 132 .

(OSD function at abnormal time)
The timing controller IC 200 may have an OSD (On Screen Display) function. The timing controller IC 200 may be configured so that when an abnormality occurs in one of the plurality of display units 110_1 to 110_3, the OSD characters to be displayed on the abnormal display unit 110_j can be displayed on the normal display unit 110_k. .

(Configuration of timing controller IC)
Next, the configuration of the timing controller IC 200 will be described. FIG. 5 is a block diagram of a timing controller IC 200 according to one embodiment. The timing controller IC 200 includes an image input interface circuit 202, an MPU interface circuit 204, a register 206, a signal processing section 210, a plurality of serializers 220_1-220_3, and a plurality of drivers (transmitters) 230_1-230_3.

The image input interface circuit 202 receives from the graphic controller 132, a single combined image data IMGc obtained by combining a plurality of individual image data IMG1 to IMG3 as a pixel clock CLK, a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, and a data enable signal DE. It is received together with a control signal such as Known techniques can be used for the type of interface between the image input interface circuit 202 and the graphic controller 132 . For example, LVDS (Low Voltage Differential Signaling) is used as the physical layer.

MPU interface circuit 204 is, for example, an I ² C interface and is connected to microcontroller 134 . Status information collected by the timing controller IC 200 from the plurality of display units 110_1 to 110_3 is stored in the register 206 of the timing controller IC 200. FIG. The microcontroller 134 can obtain the status of the display units 110_1-110_3 by accessing the registers 206 through the MPU interface circuit 204. FIG.

The signal processing unit 210 divides the composite image data IMGc into a plurality of individual image data IMG1 to IMG3. Driver control signals CNT1 to CNT3 for controlling the plurality of panel drivers 300_1 to 300_3 are generated for each of the plurality of individual image data IMG1 to IMG3.

The signal processing section 210 includes a division processing section (division processing function) 212 and timing control units (timing control functions) 214_1 to 214_3. The division processing unit 212 divides the composite image data IMGc into a plurality of individual image data IMG1 to IMG3. Although the method of division processing is not limited, for example, the graphic controller 132 transmits a synchronization signal indicating the division of individual image data along with a horizontal synchronization signal and a vertical synchronization signal to the timing controller IC 200, and uses this synchronization signal. may be divided into a plurality of individual image data IMG1 to IMG3. Alternatively, the signal processing unit 210 may have information about the configuration (pixel layout) of the composite image data IMGc in FIG. 3, and may be divided into a plurality of individual image data IMG1 to IMG3 based on this information.

The reassignment processing and OSD functionality described above may be implemented in the signal processing section 210 .

The timing control unit 214_i generates the accompanying driver control signal CNTi based on the corresponding individual image data IMGi. The processing of the timing control unit 214_i is similar to that of a conventional timing controller.

The plurality of serializers 220_1-220_3 and the plurality of transmitters 230_1-230_3 are provided corresponding to the plurality of panel driver ICs 300_1-300_3. The serializer 220_i converts the pixel values of the individual image data IMGc and the driver control signal CNTi into serial data. Conversion to serial data is not particularly limited, but for example, 8b10b encoding or 9b10b encoding proposed by the present applicant in Japanese Patent Application No. 2019-066764 can be adopted.

A transmitter (also referred to as a driver) 230 — i performs differential serial transmission of the output of the corresponding serializer 220 — i to the corresponding display unit 110 . Although the configuration of transmitter 230 is not particularly limited, for example, mini-LVDS, RSDS (Reduced Swing Differential Signaling), etc. can be adopted. The transmitter 230_i and the corresponding panel driver IC 300 may be connected by a plurality of lanes, and the number of lanes may be determined according to the size of image data to be transmitted. The above is the configuration of the timing controller IC 200 .

(Structure of panel driver IC)
FIG. 6 is a block diagram of a panel driver IC300_i according to one embodiment. Panel driver IC 300 — i includes receiver 310 , deserializer 320 and driver 330 . Receiver 310 receives differential serial signals including individual image data IMGi and driver control signals CNTi from corresponding transmitters 230_i. The deserializer 320 converts (deserializes) the differential serial signal received by the receiver 310 into parallel data.

The driving section 330 includes a source driver (data driver) 332 and a gate driver (scan driver) 334 . The source driver 332 is connected to a plurality of source lines (data lines) SL of the display panel 112 — i, and applies drive signals corresponding to pixel values to each source line SL according to the output of the deserializer 320 . The gate driver 334 is connected to the plurality of gate lines GL of the display panel 112 and sequentially selects the plurality of gate lines GL at timing according to the output of the deserializer 320 . The above is the configuration of the panel driver IC 300 .

The present invention has been described above based on the embodiments. It should be understood by those skilled in the art that this embodiment is merely an example, and that various modifications can be made to the combination of each component and each treatment process, and that such modifications are within the scope of the present invention. be. Such modifications will be described below.

(Modification 1)
FIG. 7 is a diagram showing a modified example of the synthesized image IMGc. The layout of the multiple individual images IMG1 to IMG3 in the composite image IMGc is not limited to that shown in FIG. 3, and can be arranged arbitrarily.

(Modification 2)
FIG. 8 is a block diagram of a display unit 110A according to Modification 2. As shown in FIG. In Modification 2, only the source driver 332 is integrated in the panel driver IC 300A_i, and the gate driver 334 is integrated in the external gate driver IC 400 separate from the panel driver IC 300A. The panel driver IC 300A_i extracts part of the driver control signal CNTi received from the transmitter 230_i and transmits it to the gate driver IC400.

(Modification 3)
FIG. 9 is a block diagram of a display unit 110B according to Modification 3. As shown in FIG. The horizontal resolution of the display unit 110 — i may be higher than the resolution of the source driver 332 incorporated in the panel driver IC 300B. To support such a wide panel, the display unit 110B includes a plurality of panel driver ICs 300B_i. The configuration of the panel driver IC 300B is similar to that of the panel driver IC 300A in FIG. A plurality of panel driver ICs 300B and transmitters 230_i are connected in a PtoP (Point to Point) format. Note that in another modification they may be connected in a multi-drop fashion.

(Modification 4)
FIG. 10 is a block diagram of a display unit 110C according to Modification 4. As shown in FIG. In this modification, the receiver 310 and deserializer 320 portions of the panel driver IC 300 — i in FIG. 6 are independently integrated into the receiver/deserializer IC 350 .

(Application)
Finally, the application of display system 100 will be described. FIG. 11 is a diagram showing the interior of an automobile 500 equipped with the display system 100. As shown in FIG. An automobile 500 includes a cluster panel 502, a center information display 504, an electronic rearview mirror 506, side mirrors 508L and 508R, and the like. According to the display system 100 according to the embodiment, these multiple display panels can be collectively controlled by a control unit (ECU (Electronic Control Unit) for display) 130 .

Applications of the display system 100 are not limited to in-vehicle use, and can also be applied to applications that require high reliability, such as industrial machinery.

Although the present invention has been described using specific terms based on the embodiments, the embodiments merely show the principles and applications of the present invention, and the embodiments are defined in the scope of claims. Many modifications and changes in arrangement are permitted without departing from the spirit of the present invention.

100 Display System 110 Display Unit 112 Display Panel 130 Control Unit 132 Graphics Controller 134 Microcontroller 150 Panel Interface 152 Image Transmission Channel 200 Timing Controller IC
202 image input interface circuit 204 MPU interface circuit 206 register 210 signal processing unit 212 division processing unit 214 timing control unit 220 serializer 230 transmitter 300 panel driver IC
310 receiver 320 deserializer 330 driver 332 source driver 334 gate driver

Claims (10)

A timing controller for a display system having multiple display units, comprising:
Each display unit includes a display panel and a panel driver,
The timing controller
an interface circuit for receiving, from a graphics controller, one composite image data obtained by combining a plurality of individual image data to be displayed on the plurality of display units;
a signal processing unit that divides the composite image data into the plurality of individual image data and generates a plurality of control signals for controlling the panel drivers of the plurality of display units;
a plurality of serializers corresponding to the plurality of display units, each serializer converting corresponding individual image data and corresponding control signals into serial data;
a plurality of transmitters corresponding to the plurality of display units, each transmitting a corresponding serializer output to a corresponding display unit;
A timing controller comprising: 2. The timing controller as claimed in claim 1, wherein the distance between the transmitter and the corresponding panel driver is 1-10 m. The signal processing unit is configured to display individual image data corresponding to the abnormal display unit on a normal display unit when an abnormality occurs in one of the plurality of display units. 3. The timing controller according to claim 1 or 2. 4. The timing controller according to claim 1, wherein the signal processing section has an OSD (On Screen Display) function. a plurality of display units each having a display panel and a panel driver;
a control unit connected to the plurality of display units;
with
The control unit is
a graphic controller for generating a plurality of individual image data to be displayed on the plurality of display units and for generating one composite image data by combining them;
receiving the composite image data from the graphics controller, dividing the composite image data into the plurality of individual image data, and generating a plurality of control signals for controlling the panel drivers of each of the plurality of display units; , a timing controller for transmitting corresponding individual image data and corresponding control signals to each of the plurality of display units;
A display system comprising: 6. The display system as claimed in claim 5, wherein the distance between the timing controller and each of the plurality of panel drivers is 1-10m. The timing controller is configured to display individual image data corresponding to the abnormal display unit on a normal display unit when an abnormality occurs in one of the plurality of display units. 7. A display system according to Item 5 or 6. The timing controller has an OSD (On Screen Display) function,
The timing controller is configured to display OSD characters to be displayed on the abnormal display unit on a normal display unit when an abnormality occurs in one of the plurality of display units. Item 8. The display system according to any one of Items 5 to 7. 9. A display system according to any one of claims 5 to 8, wherein the control unit is provided with a microcontroller and the plurality of display units are microcontroller-free. A motor vehicle comprising a display system according to any one of claims 5 to 9.

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