JP2016035488A - Timing controller and display device using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To share a plurality of control parameters between two timing controllers while suppressing an increase in circuit area.SOLUTION: A master timing controller 100a controls a source driver group 4_1 allocated to a first region of an LCD panel 2, and a slave timing controller 100b controls a source driver group 4_2 allocated to a second region of the LCD panel 2. A control parameter generator 120 generates N (N≥2) control parameters PRM. An encoder 122 encodes and converts the N control parameters PRM into a command CMD. A transmitter 124 outputs the command CMD to the slave timing controller 100b via a single common signal line 127. A receiver 130 receives the command CMD in time sharing via the signal line 127. A decoder 132 decodes the command CMD received by the receiver 130 to restore the original N control parameters PRM.SELECTED DRAWING: Figure 2

Description

  The present invention relates to a display panel driving technique, and more particularly to a timing controller (LCD controller) for supplying signals to a scan driver (gate driver) and a data driver (source driver).

  FIG. 1 is a block diagram of a liquid crystal display device (hereinafter simply referred to as a display device) 300 examined by the present inventors. The display apparatus 300 includes an LCD panel 302, a source driver 304, a gate driver 306, and a timing controller 200. The LCD panel 302 includes a plurality of data lines DL, a plurality of scanning lines SL arranged so as to be orthogonal to the data lines DL, and a plurality of TFTs arranged in a matrix at intersections of the data lines DL and the scanning lines SL ( Thin Film Transistor). The source driver 304 applies a voltage corresponding to the luminance to the plurality of data lines DL. The gate driver 306 selects a plurality of scanning lines SL in order.

  The timing controller 200 receives image data to be displayed on the LCD panel 302 from the image source 308. A driver control signal (timing signal) corresponding to the panel resolution is generated and supplied to the source driver 304 and the gate driver 306 together with the image data.

Examples of driver control signals include the following.
・ Start pulse (STH)
・ Latch pulse (LOAD)
・ AC signal (POL)
・ Vertical shift direction input / output signal (STV)
・ Vertical transfer clock (CPV)
・ Output enable (OE)

  With the recent increase in size and resolution of the LCD panel 302, the number of source drivers 304 has increased, making it difficult for one timing controller 200 to control all the source drivers 304. Therefore, the plurality of source drivers 304 are divided into a source driver group 304_1 assigned to the first area of the LCD panel 302 and a source driver group 304_2 assigned to the second area of the LCD panel 302, and the source driver group 304_1, Timing controllers 200_1 and 200_2 are provided for each 304_2. The timing controller 200_1 controls the gate driver 306 in addition to the source driver group 304_1.

JP 2007-206231 A JP 2000-314868 A

  The inventor considered sharing a plurality of control parameters between the two timing controllers 200_1 and 200_2 in the display device 300 as described above. The plurality of control parameters are signals different from the driver control signal described above.

  In the first approach, the two timing controllers 200_1 and 200_2 each independently generate a plurality of control parameters using the same method using a common input signal. For example, when RGB data and data enable DE are input from the image source 308 to the timing controllers 200_1 and 200_2, each timing controller 200 generates a plurality of control parameters based on the RGB data or the data enable DE. Yes.

  In the first approach, since the two timing controllers 200_1 and 200_2 operate asynchronously, there is a possibility that the timings at which the corresponding control parameters are updated are not aligned between the two timing controllers 200_1 and 200_2, or the same control. Regarding parameters, different values may be generated between the two timing controllers 200_1 and 200_2.

  In the second approach, one timing controller 200_1 generates a plurality of control parameters and transmits them to the other timing controller 200_2. However, this method requires a plurality of wirings 310 for transmitting each of a plurality of control parameters, and increases the number of pins (number of terminals) of the timing controller 200, resulting in an increase in circuit area and cost. .

  SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and one exemplary object of one aspect thereof is that a plurality of control parameters can be shared between two timing controllers while suppressing an increase in circuit area. Providing a simple display device.

  One embodiment of the present invention relates to a display device. A display device receives data from a display panel, a gate driver that drives scanning lines of the display panel, a plurality of source drivers that drive data lines of the display panel, and an image source, and the display panel among the plurality of source drivers A master timing controller that controls the first source driver group assigned to the first area and the gate driver, and data from the image source are received and assigned to the second area of the display panel among the plurality of source drivers. And a slave timing controller for controlling the second source driver group. The master timing controller includes a control parameter generator that generates N control parameters (N ≧ 2), an encoder that encodes the N control parameters and converts them into commands, and a command with a single common signal line. And a transmitter for outputting to the slave timing controller. The slave timing controller includes a receiver that receives commands in a time division manner from the master timing controller via a signal line, and a decoder that decodes the commands received by the receiver and restores the original N control parameters. .

  According to this aspect, it is possible to share a plurality of control parameters between the master timing controller and the slave timing controller using a single signal line, and update them at substantially the same timing. it can.

The control parameter generator may be configured to update each of the N control parameters at a predetermined different timing within one frame or within one line. When the i-th (1 ≦ i ≦ N) control parameter is updated, the encoder encodes it to generate a command, and the transmitter may transmit the command every time the command is generated.
By making the update timings of the N control parameters different, it becomes easy to transmit with a single signal line.

The decoder knows the timing at which each of the N control parameters should be updated, and may determine what control parameter the command includes according to the timing at which the receiver receives the command.
This eliminates the need to embed an identifier indicating what control parameter is in the command, thereby reducing the number of bits of the command.

  The decoder may include a selector controller that generates N selection signals that are asserted at a reception timing corresponding to a timing at which each of the N control parameters is to be updated. The decoder may associate a command input during a period in which the i-th selection signal is asserted with the i-th control parameter.

The command may be encoded in a format including an identifier indicating what number the control parameter is and data indicating the value of the control parameter.
Based on the identifier included in the command, the decoder may determine what control parameter value the accompanying data indicates.
Thereby, although the command length becomes long, it is possible to easily determine what control parameter the command received by the slave timing controller corresponds to.

  At least one of the N control parameters may be data to be transmitted to the source driver. At least one of the N control parameters may be data to be used in the timing controller.

  Another aspect of the present invention relates to a timing controller used in a display device. The display device is assigned to the first area of the display panel among the display panel, the gate driver that drives the scanning lines of the display panel, the plurality of source drivers that drive the data lines of the display panel, and the plurality of source drivers. A first timing controller connected to the first source driver group, a gate driver, and a second source driver group assigned to the second region of the display panel among the plurality of source drivers. A timing controller. The first and second timing controllers have the same configuration. The timing controller includes (i) a master mode that receives data from the image source and controls the gate driver and the first source driver group, and (ii) a slave that receives data from the image source and controls the second source driver group. The mode can be switched. The timing controller is active when set to the master mode, and is active when set to the master mode and encodes the N control parameters. An encoder that converts to a command, a transmitter that is active when set to master mode, and outputs a command to a timing controller set to slave mode via a single common signal line, and a slave mode It becomes active when set, and it becomes active when it is set to slave mode and a receiver that receives commands in time division from the timing controller set to master mode via the signal line, and it decodes commands received by the receiver. ,Original Comprising a decoder for restoring the number of control parameters, the. The timing controller (i) sends the N control parameters generated by the control parameter generator to the source driver when set to the master mode, and (ii) restored by the decoder when set to the slave mode. Send N control parameters to the source driver.

  Note that any combination of the above-described constituent elements and the constituent elements and expressions of the present invention replaced with each other among methods, apparatuses, systems, and the like are also effective as an aspect of the present invention.

  According to an aspect of the present invention, it is possible to share a plurality of control parameters between two timing controllers while suppressing an increase in circuit area.

It is a block diagram of the liquid crystal display device which this inventor examined. It is a block diagram of the display apparatus which concerns on embodiment. It is a circuit diagram which shows the specific structural example of a master timing controller and a slave timing controller. It is an operation | movement waveform diagram of a master timing controller and a slave timing controller. It is a block diagram of the timing controller which concerns on embodiment. FIG. 6 is a circuit diagram illustrating a specific configuration example of the timing controller of FIG. 5.

  The present invention will be described below based on preferred embodiments with reference to the drawings. The same or equivalent components, members, and processes shown in the drawings are denoted by the same reference numerals, and repeated descriptions are omitted as appropriate. The embodiments do not limit the invention but are exemplifications, and all features and combinations thereof described in the embodiments are not necessarily essential to the invention.

  In this specification, “the state in which the member A is connected to the member B” means that the member A and the member B are physically directly connected, or the member A and the member B are electrically connected. The case where it is indirectly connected through another member that does not affect the state is also included. Similarly, “the state in which the member C is provided between the member A and the member B” refers to the case where the member A and the member C or the member B and the member C are directly connected, as well as an electrical condition. It includes the case of being indirectly connected through another member that does not affect the connection state.

  FIG. 2 is a block diagram of the display device 1 according to the embodiment. The display device 1 includes an LCD panel 2, a plurality of source drivers 4, a gate driver 6, an image source 8, and two timing controllers 100a and 100b.

  The LCD panel 2 includes a plurality of data lines DL, a plurality of scanning lines SL arranged so as to be orthogonal to the data lines DL, and a plurality of TFTs arranged in a matrix at intersections of the data lines DL and the scanning lines SL ( Thin Film Transistor). The source driver 4 applies a voltage corresponding to the luminance to the plurality of data lines DL. The gate driver 6 selects a plurality of scanning lines in order.

  The display device 1 is connected to an image source 8 including a graphics processor of a personal computer and a tuner unit of a television receiver via a digital interface such as an HDMI (registered trademark) standard, a DVI standard, and a DisplayPort standard. Yes. Then, image data to be displayed on the LCD panel 2 is transmitted from the image source 8 to the display device 1 via the digital interface.

  The timing controller 100 of the display device 1 receives image data to be displayed on the LCD panel 2 from the image source 8. The timing controller 100 generates a driver control signal (collectively referred to as a timing signal TMG) according to the resolution of the LCD panel 2 and supplies it to the gate driver 6 and the source driver 4 together with the image data.

  The LCD panel 2 is divided into two areas. The plurality of source drivers 4 include a first source driver group 4_1 assigned to the first area of the LCD panel 2 and a second source driver group 4_2 assigned to the second area of the LCD panel 2.

  The first timing controller 100a receives the image data from the image source 8 and controls the first source driver group 4_1 and the gate driver 6. The second timing controller 100b receives the image data from the image source 8 and controls the second source driver group 4_2. Each of the first source driver group 4_1 and the second source driver group 4_2 may include one or a plurality of source drivers.

  The first timing controller 100a is also referred to as a master timing controller, and the second timing controller 100b is also referred to as a slave timing controller.

  First, a configuration common to the timing controllers 100a and 100b will be described. The timing controller 100 includes an input I / F (interface) 102, a logic unit 104, a timing signal generator 106, an output interface 108 for timing signals, and an output interface 110 for images.

  The input interface 102 receives image data from the image source 8, acquires RGB image data RGB, a pixel clock CLK, a data enable signal DE, and the like, and outputs them to the logic unit 104. The logic unit 104 performs necessary signal processing on the image data RGB and outputs it to the output interface 110.

  The image output interface 110 is connected to the source driver 4 via a bus such as RSDS standard (Reduced Swing Differential Signaling) or LVDS standard (Low Voltage Differential Signaling), and receives image data (RGB data) for each pixel. Output in order.

  Based on the input signal, the logic unit 104 generates a reference signal REF that is asserted at a predetermined timing of each frame, and outputs the reference signal REF to a timing signal generator 106 and a control parameter generator 120 described later.

  The timing signal generator 106 generates the following driver control signals. Those skilled in the art understand that the names and symbols of each driver control signal may vary from manufacturer to manufacturer.

1. Driver control signal for source driver 1.1 Start pulse (STH)
A plurality of source drivers 4 and gate drivers 6 are cascade-connected in accordance with the panel size (resolution) of the LCD panel 2. The image data and the driver control signal output from the timing controller 100 sequentially pass through the plurality of source drivers 4. The plurality of source drivers 4 sequentially advance the start pulse STH like a shift register. The source driver 4 to which the start pulse STH is input takes in the image data.

1.2 Latch pulse (LOAD)
The latch pulse LOAD is asserted for each scanning line. When the latch pulse LOAD is asserted, the source driver 4 captures image data for one scanning line.

1.3 AC signal (POL)
The source driver 4 drives the LCD panel 2 while inverting the polarity alternately. The polarity of the source driver 4 is determined by the AC signal POL.

2. Driver control signal for gate driver 2.1 Vertical shift direction input / output signal (STV)
It is supplied to a plurality of gate drivers 6 connected in cascade. The vertical shift direction input / output signal STV is sequentially shifted by the plurality of gate drivers 6.

2.2 Vertical transfer clock (CPV)
Each gate driver 6 takes in the inputted vertical shift direction input / output signal STV at the timing of the positive edge of the vertical transfer clock CPV.

2.3 Output enable (OE)
Data for controlling the state of the output terminal of the gate driver 6. When the output enable OE is asserted, a driving voltage is applied to the scanning line SL, and when negated, the potential of the scanning line SL is fixed.

  The pulse width and generation timing of the driver control signal are set to specific values according to the resolution of the panel. The driver control signal is supplied to the source driver 4 and the gate driver 6 through the output interface 108.

  The master timing controller 100a and the slave timing controller 100b share N control parameters (N ≧ 2). One or more of the N control parameters may be data transmitted to the source driver 4 and used in the source driver 4. Another one or plural of the N control parameters may be data used in the timing controllers 100a and 100b themselves.

  For example, when the source driver 4 performs inversion driving to invert the polarity of the driving voltage to be applied to the data line DL every certain time, the data indicating the polarity can be one of the control parameters. When a plurality of modes of the source driver 4 can be selected, a signal that triggers mode switching or a signal that indicates a mode can be one of the control parameters. Alternatively, when the operation mode of the timing controller 100 can be selected from a plurality of modes, a signal that triggers mode switching or a signal that indicates the mode can be one of the control parameters. Some of the control parameters PRM are transmitted from the output I / F 108 to the first source driver group 4_1.

  The master timing controller 100a includes a control parameter generator 120, an encoder 122, a transmitter 124, and a communication terminal 126.

  The communication terminal 126 is connected to the communication terminal 128 on the timing controller 100b side via a single signal line 127. A “single signal line” can be understood as a single bus. Thus, a single signal line may be (i) a single-ended data line and clock line pair and include two wires, or (ii) a differential data line and clock line pair. 3 wirings may be included, or (iii) a clock embedded type (also referred to as CDR system) single-ended data line and may include one wiring, or (iv) a clock embedded type differential. The data line may include two wirings.

  The control parameter generator 120 generates N control parameters PRM1 to PRMN. Each of the N control parameters PRM1 to PRMN is updated at a predetermined different timing within one frame or one line.

  The encoder 122 encodes the N control parameters PRM1 to PRMN and converts them into a command CMD. The transmitter 124 outputs the command CMD to the slave timing controller 100b via a single common signal line 127.

  The slave timing controller 100b includes a receiver 130 and a decoder 132.

  The receiver 130 receives the command CMD from the master timing controller 100a via the signal line 127 in a time division manner. The decoder 132 decodes the command CMD received by the receiver 130 and restores the original N control parameters PRM1 to PRMN. Some of the restored control parameters PRM are transmitted from the output I / F 108 to the second source driver group 4_2.

  The above is the overall configuration of the display device 1.

  FIG. 3 is a circuit diagram showing a specific configuration example of the master timing controller 100a and the slave timing controller 100b.

  The control parameter generator 120 updates each of the N control parameters PRM1 to PRMN at predetermined different timings within one frame or within one line.

  When the i-th (1 ≦ i ≦ N) control parameter PRMi is updated, the encoder 122 encodes it to generate a command CMD. The transmitter 124 transmits the command CMD to the receiver 130 every time the command CMD is generated by the encoder 122.

  The decoder 132 knows the timing at which each of the N control parameters PRM1 to PRMN should be updated within one frame or one line. Then, the decoder 132 determines what control parameter PRMi the command CMD includes according to the timing at which the receiver 130 receives the command CMD.

  For example, the encoder 122 includes a command conversion unit 140, a multiplexer 142, and a selector controller 144. The command conversion unit 140 receives the control parameters PRM1 to PRMN and converts them into commands CMD1 to CMDN in a predetermined format. The format of the command CMD is not particularly limited.

For example, the command CMD may conform to the following format.
In the header part of the command CMD, a symbol indicating the type of instruction is inserted, and subsequently, data to be transmitted is inserted.

  For example, assume that a read command and a write command are supported between the timing controller 100a and the timing controller 100b. Transmission of the control parameters PRM1 to PRMN from the timing controller 100a to the timing controller 100b is supported by a write command. Therefore, the command conversion unit 140 adds a symbol indicating a write command to the head of the command CMD.

  Then, the command conversion unit 140 encodes the control parameter PRM to be transmitted in a predetermined format and / or inserts a bit string to which a parity bit is added into the data portion of the command CMD.

  When a certain command CMDi is updated, the multiplexer 142 selects it and outputs it to the transmitter 124. The selector controller 144 knows when each control parameter PRM is updated, and causes the multiplexer 142 to select a command CMD corresponding to the updated control parameter PRM at an appropriate timing and period.

  When the conversion process in the command conversion unit 140 is common to all the control parameters PRM1 to PRMN, the command conversion unit 140 and the multiplexer 142 may be interchanged.

  The transmitter 124 transmits the command CMD selected by the multiplexer 142 to the receiver 130. The transmitter 124 may be a parallel-serial converter.

  The receiver 130 receives the command CMD transmitted from the transmitter 124 and outputs it to the demultiplexer 150. The receiver 130 may be a serial-parallel converter that converts a serial-format command CMD into a parallel format.

  The decoder 132 includes a demultiplexer 150, a command inverse conversion unit 152, and a selector controller 154.

  The selector controller 154 generates N selection signals SEL1 to SELN that are asserted at a reception timing corresponding to a timing at which each of the N control parameters PRM1 to PRMN is to be updated. The decoder 132 associates the command input during the period when the i-th selection signal is asserted with the i-th control parameter.

  Specifically, selection signals SEL <b> 1 to SELN generated by the selector controller 154 are input to the control terminal of the demultiplexer 150. When the i-th selection signal SELi is asserted, the demultiplexer 150 outputs the input command as CMDi from the i-th output terminal.

  The command reverse conversion unit 152 receives commands CMD1 to CMDN from the demultiplexer 150. The command reverse conversion unit 152 decodes the commands CMD1 to CMDN, and acquires control parameters PRM1 to PRMN.

  For example, the command reverse conversion unit 152 extracts a symbol included in the header of the command CMD, and determines whether the command is a write command or a read command. When a command CMDi is a write command and is received when the i-th selection signal SELi is asserted, a data portion included in the command CMDi is reversed to the command conversion unit 140. Decoding is performed in the procedure, and the control parameter PRMi is extracted.

The above is the configuration of the timing controller 100. Next, the operation will be described.
FIG. 4 is an operation waveform diagram of the master timing controller 100a and the slave timing controller 100b.

  In FIG. 4, in order from the top, vblank, which is one of the driver control signals, control parameters PRM1 to PRM3 (here, N = 3) generated by the master timing controller 100a, selection signals SEL1 to SEL3 in the timing controller 100a, and signal lines Command CMD transmitted via 127, selection signals SEL1 to SEL3 in slave timing controller 100b, and control parameters PRM1 to PRM3 reproduced in slave timing controller 100b are shown.

  The vblank signal is asserted (high level) over the upper and lower scanning lines where no image data exists in one frame. The timing signal generator 106 in each of the master timing controller 100a and the slave timing controller 100b. Generated.

First, the operation of the master timing controller 100a will be described.
For example, the control parameter PRM1 is updated at predetermined time intervals in a period during which the vblank signal is at a low level (negated), that is, a period in which valid image data is included. The control parameter PRM2 is also updated at a timing different from the control parameter PRM1 at a predetermined time interval during a period in which the vblank signal is at a low level (negated). The control parameter PRM3 is updated at a predetermined timing during a period when the vblank signal is at a high level (asserted). Note that the update timings of the control parameters PRM1 to PRM3 are merely examples, and are not particularly limited in the present invention.

  The command conversion unit 140 converts the control parameters PRM1 to PRM3 into commands CMD1 to CMD3. The selector controller 144 of the master timing controller 100a generates selection signals SEL1 to SEL3 that are asserted (high level) at timings when the control parameters PRM1 to PRM3 are updated. When the i-th selection signal SELi is asserted, the control parameter PRMi corresponding thereto is selected by the multiplexer 142 and transmitted from the transmitter 124.

Next, the operation of the slave timing controller 100b will be described.
The receiver 130 receives the command CMD from the transmitter 124. The selector controller 154 generates selection signals SEL1 to SEL3 that are asserted at the same timing as the selection signals SEL1 to SEL3 of the master timing controller 100a in synchronization with the image data input to the slave timing controller 100b. Since the same image data is input to the master timing controller 100a and the slave timing controller 100b, the selection signals SEL1 to SEL3 generated in the master timing controller 100a and the slave timing controller 100b can have the same waveform.

  The demultiplexer 150 assigns and outputs the command CMD received during the period when the i-th selection signal SELi is asserted to the i-th command CMDi. The command reverse conversion unit 152 decodes the i-th command CMDi and outputs it as the control parameter PRMi.

The above is the operation of the display device 1.
According to the display device 1, the master timing controller 100a and the slave timing controller 100b can share a plurality of control parameters PRM1 to PRMN with the same value, and can update them at the same timing. . Since it is only necessary to connect the master timing controller 100a and the timing controller 100b with a single signal line 127, an increase in circuit area can be suppressed as compared with the configuration of FIG.

  Further, in the slave timing controller 100b, it is necessary to embed an identifier indicating the control parameter in the command CMD transmitted through the signal line 127 by predicting the timing at which the master timing controller 100a updates the control parameter PRM. Therefore, the data length of the command CMD can be shortened.

  For chip vendors designing and manufacturing the master timing controller 100a and the slave timing controller 100b, it is useless to line up the master timing controller 100a and the slave timing controller 100b as different products. Also, for the users of the master timing controller 100a and the slave timing controller 100b, if the single timing controller 100 can be switched between the master timing controller 100a and the slave timing controller 100b, it is convenient from the viewpoint of design and manufacturing. It is.

  The timing controller 100 that can switch the functions of the master timing controller 100a and the slave timing controller 100b will be described below.

FIG. 5 is a block diagram of the timing controller 100 according to the embodiment.
The timing controller 100 is configured to be able to switch between a master mode that operates as the master timing controller 100a in FIG. 2 and a slave mode that operates as the slave timing controller 100b in FIG.

  For example, the timing controller 100 may include a mode control pin MODE, and the mode may be selectable according to an electrical state (high level, low level, high impedance, etc.) that can be controlled from the outside. Alternatively, the mode may be selectable according to a command from an external processor.

  The timing controller 100 includes an input I / F 102, a logic unit 104, a timing signal generator 106, an output I / F 108, an output I / F 110, a control parameter generator 120, an encoder 122, a transmitter 124, a receiver 130, and a decoder 132. Each basic operation is as described with reference to FIG. The communication terminal 129 also functions as the communication terminals 126 and 127 in FIG.

  The control parameter generator 120, the encoder 122, and the transmitter 124 become active when set to the master mode, and become inactive when set to the slave mode.

  The receiver 130 and the decoder 132 become active when set to the slave mode, and become inactive when set to the master mode.

  The timing controller 100 operates based on the control parameters PRM1 to PRMN generated by the control parameter generator 120 when set to the master mode, and the control parameters PRM1 to PRMN generated by the decoder 132 when set to the slave mode. Works based on. When the output I / F 108 is set to the master mode, a part of the control parameters PRM1 to PRMN generated by the control parameter generator 120 may be transmitted to the first source driver group 4_1 or set to the slave mode. When this is done, some of the control parameters PRM1 to PRMN generated by the decoder 132 may be transmitted to the second source driver group 4_2.

FIG. 6 is a circuit diagram showing a specific configuration example of the timing controller 100 of FIG.
In this configuration example, the selector controller 144 of the encoder 122 and the selector controller 154 of the encoder 122 are shared. Thereby, the circuit area can be reduced. Further, the multiplexer 142 and the demultiplexer 150 may be shared by configuring them using bidirectional switches.

  The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are within the scope of the present invention. is there. Hereinafter, such modifications will be described.

(First modification)
The encoder 122 encodes a certain control parameter PRMi in a format including an identifier indicating what control parameter PRMi is (that is, i) and data indicating the value of the control parameter PRMi, and generates a code CODE. May be. On the other hand, based on the identifier included in the command CMD, the decoder 132 may determine what control parameter value the accompanying data indicates.

  According to this modification, the data length of the code CODE is increased by the number of bits of the identifier, but the circuit area can be reduced because the multiplexer 142 and the selector controller 144 in the master timing controller 100a and the slave timing controller 100b are not necessary. There is a case.

(Second modification)
Although the liquid crystal display has been described in the embodiment, the present invention can be widely applied to similar matrix type displays. The types of driver control signals are not limited to those described above. The type of driver control signal to be supplied differs depending on the type of data driver and scan driver, but these are naturally included in the scope of the present invention.

(Use)
Display device 100 may be mounted on a television receiver or a monitor attached to a computer. Or you may mount in electronic devices, such as a notebook computer, a tablet terminal, a mobile telephone terminal, and a car navigation system, and the form is not specifically limited.

  Although the present invention has been described above based on the embodiments, it should be understood that the embodiments merely illustrate the principles and applications of the present invention, and the embodiments are within the scope of the claims. It goes without saying that many variations and changes in arrangement are possible without departing from the spirit of the present invention as defined.

DESCRIPTION OF SYMBOLS 1 ... Display apparatus, 2 ... LCD panel, 4 ... Source driver, 6 ... Gate driver, 8 ... Image source, 100 ... Timing controller, 100a ... Master timing controller, 100b ... Slave timing controller, 102 ... Input I / F, 104 ... logic unit 106 ... timing signal generator 108, 110 ... output I / F, 120 ... control parameter generator 122 ... encoder 124 124 transmitter 126 communication terminal 127 127 signal line 128 129 communication Terminal, 130 ... Receiver, 132 ... Decoder, 140 ... Command converter, 142 ... Multiplexer, 144 ... Selector controller, 150 ... Demultiplexer, 152 ... Command reverse converter, 154 ... Selector controller, PRM ... Control parameter.

Claims (14)

A display device,
A display panel;
A gate driver for driving scanning lines of the display panel;
A plurality of source drivers for driving data lines of the display panel;
A master timing controller that receives data from an image source and controls a first source driver group assigned to a first region of the display panel among the plurality of source drivers, and the gate driver;
A slave timing controller that receives data from the image source and controls a second source driver group assigned to a second area of the display panel among the plurality of source drivers;
With
The master timing controller is
A control parameter generator for generating N (N ≧ 2) control parameters;
An encoder that encodes the N control parameters and converts them into commands;
A transmitter for outputting the command to the slave timing controller via a single common signal line;
Including
The slave timing controller is
A receiver that receives the command in a time division manner from the master timing controller via the signal line;
A decoder that decodes the command received by the receiver and restores the original N control parameters;
A display device comprising: The control parameter generator is configured to update each of the N control parameters at a predetermined different timing within one frame or within one line;
When the i-th (1 ≦ i ≦ N) control parameter is updated, the encoder encodes it to generate the command, and the transmitter transmits the command every time the command is generated. The display device according to claim 1, wherein:   The decoder knows when each of the N control parameters should be updated, and determines what control parameter the command includes according to the timing when the receiver receives the command. The display device according to claim 1, wherein:   The decoder includes a selector controller that generates N selection signals that are asserted at a reception timing corresponding to a timing at which each of the N control parameters is to be updated, and in a period in which the i-th selection signal is asserted. The display apparatus according to claim 3, wherein the input command is associated with the i-th control parameter.   The display apparatus according to claim 1, wherein the command is encoded in a format including an identifier indicating a control parameter number and data indicating a value of the control parameter.   The display device according to claim 5, wherein the decoder determines, based on the identifier included in the command, what control parameter value the associated data indicates.   The display device according to claim 1, wherein at least one of the N control parameters is data to be transmitted to the source driver. A timing controller used in a display device,
The display device includes:
A display panel;
A gate driver for driving scanning lines of the display panel;
A plurality of source drivers for driving data lines of the display panel;
A first source driver group assigned to a first region of the display panel among the plurality of source drivers; a first timing controller connected to the gate driver;
A second timing controller connected to a second source driver group assigned to the second region of the display panel among the plurality of source drivers;
With
The first and second timing controllers have the same configuration,
And (ii) a master mode for receiving data from an image source and controlling the gate driver and the first source driver group; and (ii) receiving data from the image source and receiving the second source driver. It is configured to switch between the slave mode that controls the group,
The timing controller is
A control parameter generator that is active when set to the master mode and generates N (N ≧ 2) control parameters;
An encoder that is active when set to the master mode, encodes the N control parameters, and converts them into commands;
A transmitter that is active when set to the master mode and outputs the command to a timing controller set to the slave mode via a single common signal line;
A receiver that is active when set to the slave mode, and receives the command in a time-sharing manner from the timing controller set to the master mode via the signal line;
A decoder that is active when set to the slave mode, decodes the command received by the receiver, and restores the original N control parameters;
With
(I) operates based on the N control parameters generated by the control parameter generator when set to the master mode, and (ii) restored by the decoder when set to the slave mode A timing controller which operates based on the N control parameters. The control parameter generator is configured to update each of the N control parameters at a predetermined different timing within one frame or within one line;
When the i-th (1 ≦ i ≦ N) control parameter is updated, the encoder encodes it to generate the command, and the transmitter transmits the command every time the command is generated. The timing controller according to claim 8, wherein:   The decoder knows when each of the N control parameters should be updated, and determines what control parameter the command includes according to the timing when the receiver receives the command. 10. The timing controller according to claim 8 or 9, wherein:     The decoder includes a selector controller that generates N selection signals that are asserted at a reception timing corresponding to a timing at which each of the N control parameters is to be updated. The timing controller according to claim 10, wherein the input command is associated with the i-th control parameter.   9. The timing controller according to claim 8, wherein the command is encoded in a format including an identifier indicating what number the control parameter is and data indicating a value of the control parameter.   The timing controller according to claim 12, wherein the decoder determines, based on the identifier included in the command, what value of the control parameter the associated data indicates.   14. The timing controller according to claim 8, wherein at least one of the N control parameters is data to be transmitted to the source driver.

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