JP2023009973A - Arithmetic circuit, arithmetic device, method, and program - Google Patents

Abstract

To provide an arithmetic circuit, an arithmetic device, a method, and a program capable of shortening processing time when using a result of first arithmetic processing in second arithmetic processing.SOLUTION: An arithmetic circuit 12 according to the present disclosure includes: a DMA read control unit 121 that reads, from an external memory, second data obtained as a result of arithmetic processing of first data by another arithmetic circuit 11 and stored in the external memory and transfers the second data to an arithmetic processing unit 122; the arithmetic processing unit 122 that performs arithmetic processing on the second data to output third data; a DMA write control unit 123 that writes the third data in the external memory; and a DMA transfer control unit 124 that controls the DMA read control unit 121 to read the second data from the external memory after acquiring a write completion notification indicating that the writing of the second data is completed from the other arithmetic circuit 11.SELECTED DRAWING: Figure 1

Description

TECHNICAL FIELD The present disclosure relates to an arithmetic circuit, an arithmetic device, a method, and a program, and particularly an arithmetic circuit, an arithmetic device, and a method capable of reducing processing time when using the result of a first arithmetic processing in a second arithmetic processing. , and programs.

An FPGA (Field Programmable Gate Array) is known as a circuit that executes arithmetic processing. Some FPGAs include a plurality of arithmetic circuits, and a plurality of arithmetic circuits and a single external memory are connected. A method of arithmetic processing is known in which the result of the first arithmetic processing among the plurality of arithmetic circuits is used in the second arithmetic processing, and the result of the second arithmetic processing is used in the third arithmetic processing. . That is, there is known a method of arithmetic processing in which a series of sequential processing is performed.

In paragraph 0026 of Patent Document 1, "ASIC includes Ethernet I/F and USB I/F that perform I/F (interface) for connection with external devices, read DMAC (Direct Memory Access Controller) for Ethernet I/F. : DMA controller) and write DMAC, two read DMAC and write DMAC for USB I/F, an arbiter and a PCIe endpoint that is a PCIe interface, etc., and perform interface processing with external devices." ing. In addition, in paragraph 0028 of Patent Document 1, it is stated that "output data stored in the main memory is read and transferred from the PCIe endpoint to the USB I/F via the arbiter by the DMAC, and the data is transferred to the USB I/F. When data is received from the USB, the data received by the USB I/F is written to the main memory by the write DMAC via the arbiter." Japanese Patent Application Laid-Open No. 2002-200003 does not describe shortening the processing time in the arithmetic processing that is performed sequentially in series.

JP 2010-211349 A

As described above, Patent Literature 1 does not describe shortening the processing time in arithmetic processing that is performed sequentially in series, and a circuit or the like that shortens the processing time has been desired.

An object of the present disclosure is to provide an arithmetic circuit, an arithmetic device, a method, and a program that solve the above problems.

The arithmetic circuit according to the present disclosure is
The second data obtained as a result of arithmetic processing of the first data by another arithmetic circuit and stored in the external memory is read from the external memory, and the second data is transferred to the arithmetic processing unit. a DMA read controller;
the arithmetic processing unit that performs arithmetic processing on the second data and outputs third data;
a DMA write controller that writes the third data to the external memory;
DMA transfer for controlling the DMA read control unit to read the second data from the external memory after obtaining a write completion notification indicating completion of writing of the second data from the other arithmetic circuit. a control unit;
Prepare.

The computing device according to the present disclosure is
a first arithmetic circuit that performs arithmetic processing on first data and outputs second data after the arithmetic processing;
a second arithmetic circuit that performs arithmetic processing on the second data and outputs third data after the arithmetic processing;
with
The first arithmetic circuit is
a first DMA read control unit that reads the first data from an external memory and transfers the first data to a first arithmetic processing unit;
a first arithmetic processing unit that arithmetically processes the first data and outputs the second data;
a first DMA write controller that writes the second data to the external memory;
a first DMA transfer control unit that controls read timing of the first data;
The second arithmetic circuit is
a second DMA read control unit that reads the second data from the external memory and transfers the second data to a second arithmetic processing unit;
a second arithmetic processing unit that arithmetically processes the second data and outputs the third data;
a second DMA write controller that writes the third data to the external memory;
controlling the second DMA read control unit to read the second data from the external memory after obtaining from the first DMA write control unit a write completion notification indicating that the writing of the second data is completed; and a second DMA transfer control unit.

A method according to the present disclosure includes:
The second data obtained as a result of arithmetic processing of the first data by another arithmetic circuit and stored in the external memory is read from the external memory, and the second data is transferred to the arithmetic processing unit. and
Arithmetic processing of the second data to output third data;
writing the third data to the external memory;
reading the second data from the external memory after obtaining a write completion notification indicating that the writing of the second data has been completed from the other arithmetic circuit;
Prepare.

The program according to the present disclosure is
The second data obtained as a result of arithmetic processing of the first data by another arithmetic circuit and stored in the external memory is read from the external memory, and the second data is transferred to the arithmetic processing unit. and
Arithmetic processing of the second data to output third data;
writing the third data to the external memory;
reading the second data from the external memory after obtaining a write completion notification indicating that the writing of the second data has been completed from the other arithmetic circuit;
run on the computer.

According to the present disclosure, it is possible to provide an arithmetic circuit, an arithmetic device, a method, and a program capable of shortening the processing time when using the result of the first arithmetic processing in the second arithmetic processing.

1 is a block diagram illustrating an arithmetic circuit according to Embodiment 1; FIG. 1 is a block diagram illustrating an arithmetic device according to Embodiment 1; FIG. 4 is a flowchart illustrating the operation of the arithmetic device according to Embodiment 1; FIG. 11 is a block diagram illustrating an arithmetic device according to a second embodiment; FIG. FIG. 11 is a block diagram illustrating an arithmetic device according to a comparative example of the second embodiment; FIG. 10 is a flowchart illustrating the operation of an arithmetic device according to a comparative example of the second embodiment;

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each drawing, the same reference numerals are given to the same or corresponding elements, and redundant description will be omitted as necessary for clarity of description.

[Embodiment 1]
<Configuration>
FIG. 1 is a block diagram illustrating an arithmetic circuit according to Embodiment 1. FIG.
FIG. 1 shows, for example, an arithmetic circuit implemented inside an FPGA (Field Programmable Gate Array).

As shown in FIG. 1, the arithmetic circuit 12 according to the first embodiment is connected to a single external memory. Another arithmetic circuit 11 is also connected to the single external memory. The arithmetic circuit 12 and the further arithmetic circuit 11 are, for example, one arithmetic circuit each in an FPGA. Since the arithmetic circuit 12 and the other arithmetic circuit 11 have the same configuration, the arithmetic circuit 12 will be explained here, and the explanation of the other arithmetic circuit 11 will be omitted.

The arithmetic circuit 12 includes a DMA read control section 121 , an arithmetic processing section 122 , a DMA write control section 123 and a DMA transfer control section 124 . DMA (Direct Memory Access) is an abbreviation for direct memory access. Note that another arithmetic circuit may be called a first arithmetic circuit, and the arithmetic circuit may be called a second arithmetic circuit. Also, the DMA read controller is sometimes called a direct memory read controller, and the DMA write controller is sometimes called a direct memory write controller.

DMA read control unit 121 reads from the external memory the second data that is the second data obtained as a result of arithmetic processing of the first data by another arithmetic circuit 11 and that is stored in the external memory. The DMA read control unit 121 transfers the read second data to the arithmetic processing unit 122 .

The arithmetic processing unit 122 arithmetically processes the second data read from the external memory and outputs the third data.

The DMA write control unit 123 writes the third data output by the arithmetic processing unit 122 to the external memory.

Here, in Embodiment 1, the result of the arithmetic processing of another arithmetic circuit 11 is used in the arithmetic processing of the arithmetic circuit 12 . Specifically, the arithmetic processing unit 122 of the arithmetic circuit 12 stores (writes) the result of arithmetic processing by the arithmetic processing unit 112 of the other arithmetic circuit 11 in a single external memory. Compute data. Therefore, when the DMA read controller 121 reads the second data, the second data must already be stored in the external memory by the DMA write controller 113 of another arithmetic circuit 11 . Generally, the DMA read control unit 121 of the arithmetic circuit 12 needs to wait for the transfer to the external memory and write processing by the DMA write control unit 113 of another arithmetic circuit 11 in order to perform such operations. For this reason, in a method different from that of the first embodiment, for example, an arbitrary wait (time) is inserted to read out the second data in anticipation of the completion of the transfer processing and write processing of the second data to the external memory. A method of adjusting the start timing is adopted. However, in such a method, there is a waiting time between the writing completion time of the second data and the reading start time of the second data, resulting in an increase in processing time.

Therefore, in the first embodiment, another arithmetic circuit 11 is configured to output a write completion notification indicating that writing of the second data to the external memory is completed to the DMA transfer control unit 124 of the arithmetic circuit 12. and As a result, the DMA transfer control unit 124 of the arithmetic circuit 12 according to the first embodiment obtains from another arithmetic circuit 11 the write completion notification indicating that the writing of the second data to the external memory is completed. , controls the DMA read controller 121 to immediately read the second data from the external memory.

That is, after receiving the write completion notification, DMA transfer control unit 124 controls DMA read control unit 121 to read the second data from the external memory within a predetermined period.

<effect>
Arithmetic circuit 12 according to the first embodiment can read the second data from the external memory immediately after obtaining the write completion notification of the second data. This eliminates the extra waiting time between the time when the writing of the second data is completed and the time when the reading of the second data is started.

As a result, it is possible to provide an arithmetic circuit, an arithmetic device, a method, and a program capable of shortening the processing time when using the result of the first arithmetic processing in the second arithmetic processing.

<Detailed configuration>
A detailed configuration of the first embodiment will be described.
In this example, the first arithmetic circuit 11 and the second arithmetic circuit 12 are connected to a single external memory, and the second arithmetic circuit uses the arithmetic result of the first arithmetic circuit.

2 is a block diagram illustrating an arithmetic device according to Embodiment 1. FIG.
FIG. 2 shows a detailed configuration of an arithmetic device having a first arithmetic circuit and a second arithmetic circuit.
The first arithmetic circuit and the second arithmetic circuit are, for example, circuits forming an FPGA. That is, FIG. 2 is a block of an arithmetic circuit inside the FPGA.

"Arb" shown in FIG. 2 indicates an arbiter, "M" shown in FIG. 2 indicates a master, and "S" shown in FIG. 2 indicates a slave. Masters include read masters and write masters, and slaves include read slaves and write slaves.

As shown in FIG. 2, the arithmetic device 10 according to the first embodiment includes a first arithmetic circuit 11 for arithmetically processing first data and outputting second data after the arithmetic processing, and a first arithmetic circuit 11 for arithmetically processing the second data. and a second arithmetic circuit 12 for outputting third data after arithmetic processing. The first arithmetic circuit 11 and the second arithmetic circuit 12 have similar functions and can perform similar operations.

The first arithmetic circuit shown in FIG. 2 corresponds to another arithmetic circuit shown in FIG. 1, and the second arithmetic circuit shown in FIG. 2 corresponds to the arithmetic circuit shown in FIG. Further, for example, an FPGA is configured by a plurality of arithmetic circuits. Therefore, the arithmetic device 10 is, for example, a device equipped with an FPGA having a plurality of arithmetic circuits.

The first arithmetic circuit 11 has a first DMA read control section 111 , a first arithmetic processing section 112 , a first DMA write control section 113 and a first DMA transfer control section 114 .

First DMA read control section 111 reads the first data from the external memory and transfers the first data to first arithmetic processing section 112 . The first arithmetic processing unit 112 arithmetically processes the first data and outputs the second data. First DMA write controller 113 writes the second data to the external memory.

The first DMA transfer control unit 114 controls the read timing of the first data by controlling the first DMA read control unit 111 . Also, the first DMA transfer control unit 114 controls the write timing of the second data by controlling the first DMA write control unit 113 .

The second arithmetic circuit 12 has a second DMA read controller 121 , a second arithmetic processor 122 , a second DMA write controller 123 and a second DMA transfer controller 124 .

Second DMA read control section 121 reads the second data from the external memory and transfers the second data to second arithmetic processing section 122 . The second arithmetic processing unit 122 arithmetically processes the second data and outputs the third data. Second DMA write controller 123 writes the third data to the external memory.

The second DMA transfer control unit 124 controls read timing so that the processing time when the second DMA read control unit 121 reads the second data from the external memory does not increase. Specifically, after the second DMA transfer control unit 124 acquires a write completion notification indicating that the writing of the second data has been completed from the first DMA write control unit 113 of the first arithmetic circuit 11, the second DMA transfer control unit 124 transfers the It controls the second DMA read controller 121 to read 2 data. Also, the second DMA transfer control unit 124 controls the write timing of the third data by controlling the second DMA write control unit 123 .

The second DMA transfer control unit 124 temporarily stops the read processing of reading the second data from the external memory, and when receiving the write completion notification, controls the second DMA read control unit 121 to restart the read processing. may

Further, the second DMA transfer control unit 124 may not return Ack or Ready for access to the second DMA read control unit 121 in order to stop the read processing. By not returning Ack or Ready, the read process stops. After that, the second DMA transfer control unit 124 may return Ack or Ready in response to the access to the second DMA read control unit 121 in order to restart the read processing when the write completion notification is acquired.

The second DMA read control unit 121 may control read processing (transfer processing) of the second data from the external memory according to the read operation pointer information. The second DMA write control unit 123 may control write processing (transfer processing) of the third data to the external memory according to the write operation pointer information.

The second arithmetic circuit 12 has a second read descriptor memory 125 for storing pointer information for read operations and a second write descriptor memory 126 for storing pointer information for write operations so as to operate according to the pointer information. You may have more. At this time, the second DMA read control unit 121 operates based on the read operation pointer information, and the second DMA write control unit 123 operates based on the write operation pointer information.

The first arithmetic circuit 11 has functions similar to those of the second arithmetic circuit 12 . Therefore, the first arithmetic circuit 11 may further include a first read descriptor memory 115 that stores read operation pointer information and a first write descriptor memory 116 that stores write operation pointer information. At this time, the first DMA read control unit 111 operates based on the read operation pointer information, and the first DMA write control unit 113 operates based on the write operation pointer information.

Storing (storing) of the read operation pointer information in the first read descriptor memory 115 and the second read descriptor memory 125 may be performed by software (S/W). Also, storing (storing) the write operation pointer information in the first write descriptor memory 116 and the second write descriptor memory 126 may be executed by software (S/W).

The software registers (saves or stores) pointer information to the external memory in the first write descriptor memory 116 of the first arithmetic circuit 11, then registers pointer information to the first DMA transfer control unit 114, and registers the pointer information to the first DMA transfer control unit 114. Pointer information to the second DMA transfer control unit 124 is registered in the second read descriptor memory 125 of the arithmetic circuit 12, and then pointer information to the external memory is registered. The procedure for registering the software as shown above will be referred to as Procedure 1.

In the first embodiment, pointer information is registered in each descriptor memory in procedure 1 above. As a result, even if the pointer information is stored in the second read descriptor memory 125 of the second arithmetic circuit 12 earlier than the first write descriptor memory 116 of the first arithmetic circuit 11, the second DMA of the second arithmetic circuit 12 is stored. The read control unit 121 is in a stopped state until the transfer processing of the first DMA write control unit 113 of the first arithmetic circuit 11 is completed. Therefore, the second DMA read control unit 121 of the second arithmetic circuit 12 can start read processing immediately after the transfer processing is completed.

Note that the software (S/W) stores pointer information for the operation of the first DMA read control unit 111 in advance in the first read descriptor memory 115 . Also, the software (S/W) stores pointer information for the operation of the first DMA write controller 113 in the first write descriptor memory 116 in advance.

Various connections between the external memory, the first DMA read control unit 111, the first DMA write control unit 113, the first arithmetic processing unit 112, and the software (S/W) are based on AXI4 (Advanced eXtensible Interface 4) or the like. It is desirable to use an interface (I/F) that operates under master-slave control.

Arithmetic device 10 according to the first embodiment can immediately read the second data from the external memory after acquiring the second data write completion notification. This eliminates the extra waiting time between the time when the writing of the second data is completed and the time when the reading of the second data is started.

<Action>
The operation of the arithmetic device according to the first embodiment will be described by taking as an example the case where the second arithmetic circuit 12 uses the arithmetic result of the first arithmetic circuit 11 (the result written in the external memory).
3 is a flowchart illustrating the operation of the arithmetic device according to Embodiment 1. FIG.
Steps S101 to S105 shown in FIG. 3 indicate the operation of the software. Steps S201 to S208 shown in FIG. 3 indicate hardware operations.

The operation of the software will be explained.
As shown in FIG. 3, first, pointer information to the first DMA transfer control unit 114 of the first arithmetic circuit 11 is stored in the second read descriptor memory 125 of the second arithmetic circuit 12 (step S101).

Pointer information to the external memory is stored in the first read descriptor memory 115 of the first arithmetic circuit 11 (step S102).

Pointer information to the second DMA transfer control unit 124 of the second arithmetic circuit 12 is stored in the first write descriptor memory 116 of the first arithmetic circuit 11 (step S103).

The pointer information to the external memory is stored in the second read descriptor memory 125 of the second arithmetic circuit 12 (step S104).

The pointer information to the external memory is stored in the second write descriptor memory 126 of the second arithmetic circuit 12 (step S105).

The operation of the hardware will be explained.
As shown in FIG. 3, first, the second arithmetic circuit 12 stops read processing (step S201). Specifically, the read master M of the second DMA read controller 121 of the second arithmetic circuit 12 accesses the read slave S of the second DMA transfer controller 124 of the second arithmetic circuit 12 . Thereby, the read processing of the second arithmetic circuit 12 is stopped.

Based on step S102, the first arithmetic circuit 11 executes the reading process of the first data from the external memory (step S202).

The first arithmetic circuit 11 executes arithmetic processing using the first data (step S203).

The first arithmetic circuit 11 writes the arithmetic result (second data) to the external memory (step S204).

Based on step S104, the second arithmetic circuit 12 resumes the reading process that was stopped in step S201 (step S205). Specifically, by accessing the write slave S of the second DMA transfer control unit 124 of the second arithmetic circuit 12, the second arithmetic circuit 12 resumes the read processing that was stopped in step S201.

The second arithmetic circuit 12 executes read processing of the second data from the external memory (step S206).

The second arithmetic circuit 12 executes arithmetic processing using the second data (step S207).

The second arithmetic circuit 12 writes the arithmetic result (third data) to the external memory (step S208).

In the first embodiment, in step S201, the read master M of the second DMA read control unit 121 of the second arithmetic circuit 12 accesses the read slave S of the second DMA transfer control unit 124 of the second arithmetic circuit 12 to perform read processing. be stopped. After that, in step S204, immediately after the writing (Write) of the calculation result of the first arithmetic circuit 11 to the external memory is completed, in step S205, the slave S for writing of the second DMA transfer control unit 124 of the second arithmetic circuit 12 , the second arithmetic circuit 12 resumes the read processing that was stopped in step S201. With such an operation, the processing of the first arithmetic circuit 11 and the processing of the second arithmetic circuit 12 can be performed continuously without waiting.

As a result, it is possible to provide an arithmetic circuit, an arithmetic device, a method, and a program capable of shortening the processing time when using the result of the first arithmetic processing in the second arithmetic processing.

[Embodiment 2]
FIG. 4 is a block diagram illustrating an arithmetic device according to a second embodiment;
As shown in FIG. 4, the arithmetic device 20 according to the second embodiment differs from the arithmetic device 10 according to the first embodiment in that it has three or more arithmetic circuits. That is, the arithmetic device 20 has a first arithmetic circuit 11, a second arithmetic circuit 12, . . . , an Nth arithmetic circuit. However, N is an integer of 3 or more.

As shown in FIG. 4, the first DMA transfer control unit 114 has two slaves S, and the first slave S is connected to the read master M of the first DMA read control unit in the first arithmetic circuit 11. . The write master M of the first DMA write control unit 113 of the first arithmetic circuit 11 and the write master M of the second DMA write control unit 123 of the second arithmetic circuit 12 are used as the second slave S of the first DMA transfer control unit 114 . , and the write master M of the DMA write controller in the Nth arithmetic circuit are connected. The first slave S of each DMA transfer control unit in the arithmetic unit 20 is connected to the read master M of the DMA readout control unit in the same arithmetic circuit, and the second slave S is connected to the read master M in the same arithmetic circuit. and write masters M of DMA write control units in other arithmetic circuits are connected.

In normal master and slave operations, one operation (process) is completed when the slave returns Ack or Ready in response to a command from the master.

In Embodiments 1 and 2, when the DMA read slave S of the DMA transfer control unit is accessed, the DMA write slave S is accessed without returning Ack or Ready after the read processing is completed. In that case, Ack or Ready should be returned.

Further, in Embodiments 1 and 2, pointer information addressed to the DMA transfer controller is registered in the read descriptor memory and the write descriptor memory in addition to the pointer information addressed to the external memory. As a result, the software (S/W) can store the pointer information without executing wait processing for adjusting the processing timing, and the entire processing time can be shortened.

As a result, it is possible to provide an arithmetic circuit, an arithmetic device, a method, and a program capable of shortening the processing time when using the result of the first arithmetic processing in the second arithmetic processing.

[Comparative example]
<Configuration>
FIG. 5 is a block diagram illustrating an arithmetic device according to a comparative example of the second embodiment;

As shown in FIG. 5, the arithmetic device 50 according to the comparative example of the second embodiment differs in that no DMA transfer control unit is implemented in each arithmetic circuit.

The first arithmetic circuit 51 of the arithmetic device 50 transfers input data to the first arithmetic processing unit 512 via the first DMA read control unit 511, which is a DMA controller for reading from a single external memory. After that, the first arithmetic processing unit 512 of the first arithmetic circuit 51 transfers the arithmetic processing result to the external memory again via the first DMA write control unit 513, which is a DMA controller for writing.

The first DMA read controller 511 is connected to the first read descriptor memory 515 and operates according to the pointer information stored in the first read descriptor memory 515 . Similarly, the first DMA write controller 513 is connected to the first write descriptor memory 516 and operates according to pointer information stored in the first write descriptor memory 516 .

Arithmetic device 50 is not equipped with a DMA transfer control unit. Therefore, the arithmetic unit 50 needs to adjust the read start timing by inserting an arbitrary wait in anticipation of the timing when the write processing of the arithmetic result of the first arithmetic circuit to the external memory is completed. Therefore, in the arithmetic device 50, it is difficult for the second arithmetic circuit 52 to read the arithmetic result of the first arithmetic circuit from the external memory immediately after the writing of the arithmetic result of the first arithmetic circuit 51 to the external memory is completed.

As a result, it is difficult to provide an arithmetic circuit, an arithmetic device, a method, and a program capable of shortening the processing time when using the result of the first arithmetic processing in the second arithmetic processing.

<Action>
FIG. 6 is a flowchart illustrating the operation of the arithmetic device according to the comparative example of the second embodiment;

The operation of the software will be explained.
As shown in FIG. 6, first, pointer information to the external memory is stored in the first read descriptor memory 515 of the first arithmetic circuit 51 (step S301).

Pointer information to the external memory is stored in the first write descriptor memory 516 of the first arithmetic circuit 51 (step S302).

A wait process (Wait process) is executed (step S303).

The pointer information to the external memory is stored in the second read descriptor memory 525 of the second arithmetic circuit 52 (step S304).

The pointer information to the external memory is stored in the second write descriptor memory 526 of the second arithmetic circuit 12 (step S305).

The operation of the hardware will be explained.
As shown in FIG. 6, first, based on step S301, read processing to the external memory of the first arithmetic circuit 51 is executed (step S401).

Arithmetic processing of the first arithmetic circuit 51 is executed (step S402).

Based on step S302, write processing to the external memory of the first arithmetic circuit 51 is executed (step S403).

Based on step S304, read processing to the external memory of the second arithmetic circuit 52 is executed (step S404).

Arithmetic processing of the second arithmetic circuit 52 is executed (step S405).

Based on step S305, the writing process to the external memory of the second arithmetic circuit 52 is executed (step S406).

In the arithmetic device 50 according to the comparative example, it is necessary to execute wait processing (Wait processing) as in step S303. As a result, the arithmetic unit 50 allows the second arithmetic circuit 52 to read the arithmetic result of the first arithmetic circuit 51 from the external memory immediately after the writing of the arithmetic result of the first arithmetic circuit 51 to the external memory is completed. difficult.

As a result, it is difficult to provide an arithmetic circuit, an arithmetic device, a method, and a program capable of shortening the processing time when using the result of the first arithmetic processing in the second arithmetic processing.

Although the present invention has been described as a hardware configuration in the above embodiment, the present invention is not limited to this. The present invention can also be implemented by causing a CPU (Central Processing Unit) to execute a computer program to process each component.

In the above embodiments, the programs can be stored and delivered to computers using various types of non-transitory computer readable media. Non-transitory computer-readable media include various types of tangible storage media. Examples of non-transitory computer-readable media include magnetic recording media (specifically flexible disks, magnetic tapes, hard disk drives), magneto-optical recording media (specifically magneto-optical discs), CD-ROMs (Read Only Memory ), CD-R, CD-R/W, semiconductor memory (specifically, mask ROM, PROM (Programmable ROM), EPROM (Erasable PROM)), flash ROM, and RAM (Random Access Memory). The program may also be delivered to the computer on various types of transitory computer readable medium. Examples of transitory computer-readable media include electrical signals, optical signals, and electromagnetic waves. Transitory computer-readable media can deliver the program to the computer via wired channels, such as wires and optical fibers, or wireless channels.

Further, although acts have been depicted in a particular order, this does not mean that such acts are performed in the specific order or sequential order shown, or It should not be understood as requiring that all actions be performed. Multitasking and parallelism can be advantageous in certain situations. Similarly, while details of several specific embodiments have been included in the above discussion, these should not be construed as limitations on the scope of this disclosure, but as illustrations of features unique to those particular embodiments. should. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable combination.

Although the present invention has been described with reference to the embodiments, the present invention is not limited to the above. Various changes that can be understood by those skilled in the art can be made to the configuration and details of the present invention within the scope of the invention.

It should be noted that the present invention is not limited to the above embodiments, and can be modified as appropriate without departing from the scope of the invention.

10, 20, 50... Arithmetic device 11, 51... First arithmetic circuit, another arithmetic circuit 111, 511... First DMA read controller 112, 512... First arithmetic processor 113, 513... First DMA write controller 114... First DMA transfer controller 115, 515 First read descriptor memory 116, 516 First write descriptor memory 12, 52 Second arithmetic circuit, arithmetic circuit 121, 521 Second DMA read controller 122, 522 Second arithmetic Processing Units 123, 523...Second DMA write controller 124...Second DMA transfer controller 125, 525...Second read descriptor memory 126, 526...Second write descriptor memory

Claims (10)

The second data obtained as a result of arithmetic processing of the first data by another arithmetic circuit and stored in the external memory is read from the external memory, and the second data is transferred to the arithmetic processing unit. a DMA read controller;
the arithmetic processing unit that performs arithmetic processing on the second data and outputs third data;
a DMA write controller that writes the third data to the external memory;
DMA transfer for controlling the DMA read control unit to read the second data from the external memory after obtaining a write completion notification indicating completion of writing of the second data from the other arithmetic circuit. a control unit;
Arithmetic circuit with After obtaining the write completion notification, the DMA transfer control unit controls to read the second data from the external memory within a predetermined period.
2. The arithmetic circuit according to claim 1. a read descriptor memory for storing pointer information for read operations;
a write descriptor memory that stores pointer information for write operations;
further comprising
The DMA read control unit operates based on the read operation pointer information,
The DMA write control unit operates based on the write operation pointer information.
3. The arithmetic circuit according to claim 1 or 2. storing the read operation pointer information in the read descriptor memory and storing the write operation pointer information in the write descriptor memory are performed by software;
4. The arithmetic circuit according to claim 3. The DMA transfer control unit
stopping the reading process of reading the second data from the external memory;
controlling the DMA read control unit to restart the read processing when the write completion notification is obtained;
The arithmetic circuit according to any one of claims 1 to 4. The DMA transfer control unit
In order to stop the read processing, Ack or Ready is not returned for access to the DMA read control unit,
Returning the Ack or the Ready in response to access to the DMA read control unit in order to resume the read processing when the write completion notification is acquired;
to control the DMA read control unit to
6. The arithmetic circuit according to claim 5. a first arithmetic circuit that performs arithmetic processing on first data and outputs second data after the arithmetic processing;
a second arithmetic circuit that performs arithmetic processing on the second data and outputs third data after the arithmetic processing;
with
The first arithmetic circuit is
a first DMA read control unit that reads the first data from an external memory and transfers the first data to a first arithmetic processing unit;
a first arithmetic processing unit that arithmetically processes the first data and outputs the second data;
a first DMA write controller that writes the second data to the external memory;
a first DMA transfer control unit that controls read timing of the first data;
The second arithmetic circuit is
a second DMA read control unit that reads the second data from the external memory and transfers the second data to a second arithmetic processing unit;
a second arithmetic processing unit that arithmetically processes the second data and outputs the third data;
a second DMA write controller that writes the third data to the external memory;
controlling the second DMA read control unit to read the second data from the external memory after obtaining from the first DMA write control unit a write completion notification indicating that the writing of the second data is completed; a second DMA transfer control unit;
Arithmetic unit. After obtaining the write completion notification, the second DMA transfer control unit controls to read the second data from the external memory within a predetermined period.
A computing device according to claim 7 . The second data obtained as a result of arithmetic processing of the first data by another arithmetic circuit and stored in the external memory is read from the external memory, and the second data is transferred to the arithmetic processing unit. and
Arithmetic processing of the second data to output third data;
writing the third data to the external memory;
reading the second data from the external memory after obtaining a write completion notification indicating that the writing of the second data has been completed from the other arithmetic circuit;
How to prepare. The second data obtained as a result of arithmetic processing of the first data by another arithmetic circuit and stored in the external memory is read from the external memory, and the second data is transferred to the arithmetic processing unit. and
Arithmetic processing of the second data to output third data;
writing the third data to the external memory;
reading the second data from the external memory after obtaining a write completion notification indicating that the writing of the second data has been completed from the other arithmetic circuit;
A program that makes a computer run

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