JP2023005616A - wiring board - Google Patents

Abstract

To provide a wiring board that achieves excellent connection reliability.SOLUTION: A wiring board 10 according to the present invention includes a first insulating layer 1111, a second insulating layer 115 provided on the first insulating layer 1111, and two or more electrodes 112P interposed between the first insulating layer 1111 and the second insulating layer 115, and the second insulating layer 115 includes a laminate 11 having a through hole at each of the positions of the two or more electrodes 112P, and two or more first metal posts 14 each filling the through hole and protruding from the second insulating layer 115, and the height at any position between the two or more electrodes 112P is lower than the height of the second insulating layer 115 at a position adjacent to the through hole.SELECTED DRAWING: Figure 1

Description

The present invention relates to wiring boards.

2. Description of the Related Art Recently, with the development of the electronic industry, there is a demand for high performance, high functionality, and miniaturization of semiconductor chips. Along with this, there is a rapid increase in demand for high integration, thinning, and fine circuit patterning in mounting technologies such as SIP (System in Package) and 3D packaging.

For example, in surface mounting technology of a semiconductor chip on a substrate, a flip chip bonding method is often used to connect the semiconductor chip to a motherboard. In the flip-chip bonding method, first, external connection terminals (ie, bumps) made of gold, solder, or other metal and having a height of several tens to several hundred μm are formed on a semiconductor chip. After that, the semiconductor chip on which the bumps are formed is flipped and mounted on the substrate so that the surface of the semiconductor chip on which the bumps are formed faces the substrate.

Further, in recent years, the miniaturization and high integration of conductor patterns in semiconductor chips have been progressing. Under such circumstances, a method is adopted in which a semiconductor chip is connected to a mother board via a wiring board, for example, a wiring board for FC-BGA (Flip Chip-Ball Grid Array).

Conventionally, in a wiring board for FC-BGA, a solder resist having openings is provided at the position of a land pattern, and connection terminals with a semiconductor chip are formed in the openings. The connection terminal is made of a metal material such as solder and has a height of several tens of μm.

The flip-chip bonding method used here has evolved to use metal posts in order to narrow the pitch of the connection terminals of the semiconductor chip.

In an FC-BGA wiring board using metal posts, metal posts having a diameter of several tens of μm and a height of several tens of μm are formed in openings of a solder resist, and solder bumps are formed on the metal posts. By connecting the solder bumps to the metal posts on the semiconductor chip side, a semiconductor device is obtained in which the distance between the semiconductor chip and the wiring substrate is several tens of μm.
Examples using metal posts are disclosed in Patent Documents 1 and 2, for example.

JP 2010-129996 A JP 2020-188139 A

An object of the present invention is to provide a wiring board that achieves excellent connection reliability.

According to one aspect of the present invention, a first insulating layer, a second insulating layer provided on the first insulating layer, and two or more insulating layers interposed between the first insulating layer and the second insulating layer an electrode, wherein the second insulating layer comprises a laminate having a through hole at each of the positions of the two or more electrodes; and two electrodes each filling the through hole and projecting from the second insulating layer. A wiring board comprising the above first metal posts, wherein the height at any position between the two or more electrodes is compared with the height of the second insulating layer at a position adjacent to the through hole. A lower wiring board is provided.

According to still another aspect of the present invention, there is provided the wiring board according to the above aspect, wherein the second insulating layer is opened so that the first insulating layer is exposed at any position between the two or more electrodes. be.

According to still another aspect of the present invention, there is provided the wiring board according to the above aspect, wherein the second insulating layer is opened to form one or more grooves.

According to still another aspect of the present invention, each of the one or more grooves has one end connected directly or via another one or more grooves to the area outside the arrangement of the two or more electrodes and the first position. and the other end communicates with the region outside the array of the two or more electrodes directly or via one or more other grooves at a second position. be done.

According to still another aspect of the present invention, the second insulating layer includes a plurality of insulating portions spaced apart from each other with the one or more grooves therebetween, and the first insulating layer and the second insulating layer The wiring board according to any one of the above aspects, wherein the outer contour of each of the plurality of insulating parts orthographically projected onto a plane perpendicular to the stacking direction is circular.

According to still another aspect of the present invention, the second insulating layer includes a plurality of insulating portions spaced apart from each other with the one or more grooves therebetween, and the first insulating layer and the second insulating layer orthographic projection of the plurality of insulating portions onto a plane perpendicular to the stacking direction of the plurality of insulating portions, each of which has a shape extending in one direction, and the plane includes a first strip-shaped region, a width of the first strip-shaped region, and and a third strip-shaped region adjacent to the second strip-shaped region in the width direction with the first strip-shaped region interposed therebetween. Among them, those located in the first strip-shaped region have an extension direction substantially parallel to the length direction of the first strip-shaped region, and those located in the second strip-shaped region have an extension direction as described above. Wiring according to any of the above modes, which is inclined clockwise with respect to the length direction, and the wiring located in the third band-shaped region has an extension direction inclined counterclockwise with respect to the length direction A substrate is provided.

According to still another aspect of the present invention, the wiring board according to the above aspect, wherein the ratio L/W of the length L of the orthogonal projection to the width W of the orthogonal projection is in the range of greater than 1 and 1.5 or less. is provided.

According to still another aspect of the present invention, the ratio D2/D1 of the diameter D2 of the first metal post to the shortest distance D1 between the two adjacent insulating portions is in the range of 1.2 to 1.7. A wiring substrate according to any of the aspects is provided.

According to still another aspect of the present invention, there is provided the wiring board according to any one of the above aspects, wherein the thickness of the second insulating layer is in the range of 15 μm to 45 μm.

According to still another aspect of the present invention, a wiring board according to any one of the above aspects, a functional device mounted on the second insulating layer side surface of the wiring board, and a combination of the wiring board and the functional device. A semiconductor device is provided with an encapsulating resin layer interposed therebetween.

Here, the "functional device" is a device that operates by being supplied with at least one of electric power and electric signals, a device that outputs at least one of electric power and electric signals in response to an external stimulus, or a device that outputs at least one of electric power and electric signals. It is a device that operates when supplied with at least one of them and outputs at least one of electric power and electrical signals in response to stimulation from the outside. A functional device is in the form of a chip, for example, a semiconductor chip or a chip in which circuits and elements are formed on a substrate made of a material other than a semiconductor, such as a glass substrate. A functional device can include, for example, one or more of a large scale integrated circuit (LSI), a memory, an imaging device, a light emitting device, and MEMS (Micro Electro Mechanical Systems). MEMS are, for example, one or more of pressure sensors, acceleration sensors, gyro sensors, tilt sensors, microphones, and acoustic sensors. According to one example, the functional device is a semiconductor chip including an LSI.

According to still another aspect of the present invention, the first insulating layer and the two or more electrodes provided thereon have a first through hole at each of the positions of the two or more electrodes; forming a second insulating layer having openings between the electrodes; and forming a resist layer that fills the gap between the two or more electrodes and has a second through hole that communicates with the first through hole. a method of manufacturing a wiring board, comprising: forming a first metal post in which the first through hole and the second through hole are embedded; and removing the resist layer.

According to still another aspect of the present invention, a functional device is bonded to the second insulating layer side surface of the wiring substrate according to any of the above aspects, and thereafter, the wiring substrate and the functional device are bonded together. and filling an underfill material.

According to still another aspect of the present invention, an insulating resin layer is interposed between the surface of the wiring substrate on the side of the second insulating layer and the functional device according to any of the above aspects, and the wiring substrate and the functional device are connected to each other. A method of manufacturing a semiconductor device is provided, which includes bonding a .

According to the present invention, a wiring board that achieves excellent connection reliability is provided.

1 is a cross-sectional view schematically showing a semiconductor device according to one embodiment of the present invention; FIG. FIG. 4 is a cross-sectional view schematically showing one step in the method of manufacturing a wiring board according to one embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 4 is a cross-sectional view schematically showing still another step in the wiring board manufacturing method according to the embodiment of the present invention; FIG. 11 is a plan view schematically showing the upper surface of the wiring substrate shown in FIG. 10; FIG. 2 is a cross-sectional view schematically showing a semiconductor device according to a comparative example; FIG. 13 is a cross-sectional view schematically showing a wiring substrate used for manufacturing the semiconductor device shown in FIG. 12; FIG. 4 is a plan view schematically showing the upper surface of a wiring board according to another embodiment of the present invention; FIG. 4 is a plan view schematically showing the upper surface of a wiring board according to still another embodiment of the present invention;

Embodiments of the present invention will be described below with reference to the drawings. The embodiments described below embody any of the above aspects more specifically. The embodiments shown below are examples embodying the technical idea of the present invention. It is not limited. Various modifications can be made to the technical idea of the present invention within the technical scope defined by the claims.

In the drawings referred to in the following description, the same reference numerals are given to components having the same or similar functions. Here, the drawings are schematic, and the relationship between the dimension in the thickness direction and the direction perpendicular to the thickness direction, that is, the dimension in the in-plane direction, the relationship between the dimensions in the thickness direction of a plurality of layers, etc. , may differ from reality. Therefore, specific dimensions should be determined with reference to the following description. It should also be noted that the dimensional relationships of two or more components may differ between the drawings.

In the present disclosure, the “upper surface” and the “lower surface” refer to the two main surfaces of the plate-shaped member or the layer included therein, that is, the surface perpendicular to the thickness direction and having the largest area and the back surface thereof. , respectively denote the surface shown above and the surface shown below in the drawing. In addition, "side surface" means a surface that is perpendicular to or inclined with respect to the main surface.

Also, in this disclosure, the description "AA on top of BB" is used regardless of the direction of gravity. The condition identified by the statement "AA on BB" encompasses the condition where AA is in contact with BB. Reference to "AA over BB" does not exclude the interposition of one or more other components between AA and BB.

<Structure>
FIG. 1 is a cross-sectional view schematically showing a semiconductor device 1 according to one embodiment of the invention.

A semiconductor device 1 shown in FIG. 1 includes a wiring board 10A, a functional device 20, a sealing resin layer 30, a bonding electrode 40, and a second metal post 50. As shown in FIG.

The functional device 20 is, for example, a semiconductor chip or a chip in which circuits and elements are formed on a substrate made of a material other than a semiconductor, such as a glass substrate. Here, as an example, functional device 20 is assumed to be a semiconductor chip.

The second metal post 50 is provided on the surface of the functional device 20 facing the wiring board 10A. The second metal post 50 is made of copper, for example. The second metal post 50 is connected with the bonding electrode 40 .

A semiconductor device 1 includes a plurality of functional devices 20 . Semiconductor device 1 may include only one functional device 20 .

The functional device 20 is bonded to the wiring substrate 10A via the bonding electrode 40. As shown in FIG. The functional device 20 is bonded to the wiring substrate 10A by flip chip bonding.

The junction electrodes 40 are arranged between the functional device 20 and the wiring board 10A. The joint electrode 40 is made of solder, for example.

The sealing resin layer 30 includes a portion interposed between the functional device 20 and the wiring board 10A. The sealing resin layer 30 fixes the functional device 20 to the wiring board 10A. The sealing resin layer 30 is made of, for example, an insulating resin layer. The insulating resin layer is obtained from an underfill material, according to one example.

The wiring board 10A includes a laminate 11, a seed layer 12, and first metal posts 14. As shown in FIG.

The wiring board 10A is, for example, a FC-BGA wiring board. The wiring board 10A is bonded to, for example, a mother board (not shown).

The laminate 11 includes a core layer 110 , an insulating layer 111 , a conductor layer 112 , an insulating layer 113 , a second bonding conductor 114 and a second insulating layer 115 .

Core layer 110 is an insulating layer. The core layer 110 is, for example, a fiber-reinforced substrate made of woven fabric or non-woven fabric impregnated with a thermosetting insulating resin. As woven or non-woven fabrics, for example glass fibres, carbon fibres, or aramid fibres, can be used. For example, an epoxy resin can be used as the insulating resin.

The core layer 110 is provided with through holes. A portion of the conductor layer 112 covers the side wall of the through hole. Here, part of the conductor layer 112 covers the sidewalls of the through holes provided in the core layer 110 so as to create through holes with conductor sidewalls. These through-holes whose side walls are made of a conductor may be filled with an insulator.

The rest of the conductor layer 112 and the insulating layer 111 form a multilayer wiring structure on both main surfaces of the core layer 110 . Each multilayer wiring structure includes conductor layers 112 and insulating layers 111 that are alternately laminated.

Each insulating layer 111 included in the multilayer wiring structure is, for example, an insulating resin layer. Through holes are provided in the insulating layer 111 .

The conductor layer 112 is made of a metal such as copper or an alloy. The conductor layer 112 may have a single layer structure or a multilayer structure.

Each conductor layer 112 included in the multilayer wiring structure includes a wiring portion and a land portion. The conductor layer 112 facing the core layer 110 with the insulating layer 111 therebetween further includes a via portion covering the side wall of the through hole provided in the insulating layer 111 .

The insulating layer 113 is provided on the multilayer wiring structure adjacent to the lower surface of the core layer 110 . The insulating layer 113 is, for example, an insulating resin layer such as a solder resist. The insulating layer 113 is provided with through-holes communicating with the conductor layer 112 located on the outermost surface of the multilayer wiring structure.

The second bonding conductor 114 is a metal bump provided on the exposed portion of the conductor layer 112 at the position of the through hole of the insulating layer 113 . Note that the joining conductor is also called a joining terminal. The second joining conductor 114 is made of solder, for example.

In the multilayer wiring structure provided on the upper surface of the core layer 110, the conductor layer 112 located on the outermost surface facing the functional device 20 is hereinafter referred to as an electrode 112P. In addition, of the multilayer wiring structure provided on the top surface of the core layer 110 , the insulating layer 111 located on the outermost surface on the side facing the functional device 20 is called a first insulating layer 1111 .

The first insulating layer 1111 is made of insulating resin, for example. The main component of the insulating resin is, for example, epoxy resin or polyimide resin. The insulating resin may be a thermosetting resin or a photosensitive resin. The first insulating layer 1111 may further contain a filler such as silica (SiO ₂ ).
The thickness of the first insulating layer 1111 is, for example, in the range of 3 μm to 35 μm.

Two or more electrodes 112 P are interposed between the first insulating layer 1111 and the second insulating layer 115 . Each electrode 112</b>P fills the through hole provided in the first insulating layer 1111 and protrudes from the first insulating layer 1111 .

The second insulating layer 115 has a first through hole at each position of the two or more electrodes 112P. The second insulating layer 115 is opened so that the first insulating layer 1111 is exposed between two or more electrodes 112P.

The first through hole preferably has a forward tapered cross section parallel to the thickness direction of the second insulating layer 115 . In this case, the seed layer 12 and the second insulating layer 115 are likely to adhere to each other.

The second insulating layer 115 includes a plurality of insulating portions 1151 spaced apart from each other with one or more grooves therebetween. The second insulating layer 115 is an insulating resin layer such as solder resist.

The second bonding conductor 114 is a metal bump provided on the exposed portion of the conductor layer 112 at the position of the through hole of the insulating layer 113 . Note that the joining conductor is also called a joining terminal. The second joining conductor 114 is made of solder, for example.

Seed layer 12 is interposed between first metal post 14 and second insulating layer 115 . The seed layer 12 plays a role as a power feeding layer in film formation by electrolytic plating. Seed layer 12 includes, for example, copper.

Each of the two or more first metal posts 14 fills the first through hole of the second insulating layer 115 and protrudes from the second insulating layer 115 . The first metal post 14 has conductivity. Also, the melting point of the material of the first metal post 14 is higher than the melting point of the material of the first joining conductor 16, which will be described later. The first metal post 14 is made of, for example, a metal such as copper or an alloy.

The semiconductor device 1 shown in FIG. 1 has been described above.

A metal layer may be provided between the electrode 112P and the first metal post 14. FIG. According to one example, the metal layer includes a metal such as Au, Ag, Cu or Al, an alloy thereof, or a metal composite obtained by plating Cu with Au or the like. The metal layer comprises, according to another example, a solder such as Sn, Sn--Pb, Sn--Ag, Sn--Cu, Sn--Ag--Cu, Sn--Bi or Au based.

<Method for manufacturing wiring board>
The wiring board 10A included in the semiconductor device 1 described above can be manufactured, for example, by the following method.

2 to 10 are diagrams schematically showing a method of manufacturing a wiring board according to one embodiment of the present invention.

In this method, first, as shown in FIG. Prepare a structure with The conductor layer 112 can be formed by, for example, a semi-additive method or a subtractive method.

Next, as shown in FIG. 3, a second insulating layer 115 is formed on the first insulating layer 1111 . The second insulating layer 115 has a first through hole at each position of the two or more electrodes 112P. Also, the second insulating layer 115 has openings between the two or more electrodes 112P. Specifically, the second insulating layer 115 is opened so as to form one or more grooves G. As shown in FIG. The groove G preferably forms an obtuse angle between the bottom surface and the side wall of the groove G in a cross section perpendicular to the length direction thereof. In this case, for example, air bubbles are less likely to remain between the wiring board 10A and the functional device 20 when filling the underfill material to form the sealing resin layer 30 .

According to one example, each of the one or more grooves G has one end communicating directly or via another one or more grooves G with a region outside the array of the two or more electrodes 112P at a first position; The end communicates, either directly or via one or more other grooves G, with a region outside the array of two or more electrodes 112P at a second location. When such a groove G is formed, air bubbles are less likely to remain between the wiring board 10A and the functional device 20 when the underfill material is filled. Moreover, it is preferable that these grooves G form a mesh pattern.

The second insulating layer 115 shown in FIG. 3 includes a plurality of insulating portions 1151 spaced apart from each other with one or more grooves G therebetween.
As described above, the laminate 11 is obtained.

Next, as shown in FIG. 4, the seed layer 12 is formed by electroplating on the upper surface of the first insulating layer 1111, the surface of the second insulating layer 115, and the exposed portion of the electrode 112P. The seed layer 12 may be formed by vacuum deposition. The material of the seed layer 12 is copper, for example. The thickness of the seed layer 12 is preferably in the range of 40 nm to 400 nm, more preferably in the range of 100 nm to 350 nm.

Next, as shown in FIG. 5, a resist layer 13 is formed on the seed layer 12 . The resist layer 13 fills the gaps between the two or more electrodes 112P. The resist layer 13 has second through holes communicating with the first through holes. The resist layer 13 can be formed by photolithography, for example.

Next, as shown in FIG. 6, a first metal post 14 is formed on the seed layer 12. Next, as shown in FIG. The first metal post 14 fills the first through hole and the second through hole. The first metal post 14 is formed, for example, so that its upper surface is lower than the upper surface of the resist layer 13 . The first metal post 14 is formed by electrolytic plating, for example.

Next, as shown in FIG. 7, a surface treatment layer 15 is formed on the first metal post 14. Next, as shown in FIG. The surface treatment layer 15 is provided for the purpose of preventing oxidation of the surface of the first metal post 14 and improving wettability with solder. Here, as an example, an electroless Ni/Pd/Au plating layer is formed as the surface treatment layer 15 .

As the surface treatment layer 15, an OSP (Organic Solderability Preservative) film, that is, a surface treatment layer using a water-soluble preflux may be formed. Alternatively, as the surface treatment layer 15, an electroless tin plating layer or an electroless Ni/Au plating layer may be formed.

Next, as shown in FIG. 8, a first joining conductor 16 is formed. The first joining conductor 16 can be formed, for example, by placing a solder material such as a solder ball on the surface treatment layer 15, melting it, and then cooling it to fix it to the surface treatment layer 15. . As shown in FIG. 8, the first joining conductor 16 is, for example, dome-shaped.

Next, as shown in FIG. 9, the resist layer 13 is removed. The resist layer 13 is removed by, for example, a dry etching method, or dissolved or peeled off by immersion in an alkaline solution or solvent.

Next, as shown in FIG. 10, the exposed portion of seed layer 12 is removed. The seed layer 12 can be removed, for example, by immersing it in a chemical solution.

10 A of wiring boards are obtained as mentioned above.

FIG. 11 is a plan view schematically showing the upper surface of wiring board 10A shown in FIG. As shown in FIG. 11, the outline of each of the plurality of insulating portions 1151 is circular when orthogonally projected onto a plane perpendicular to the stacking direction of the first insulating layer 1111 and the second insulating layer 115 .

A distance D1 shown in FIG. 11 is the shortest distance between two adjacent insulating portions 1151 . A diameter D<b>2 shown in FIG. 11 is the diameter of the first metal post 14 . The diameter of the first metal post 14 is the diameter of the portion of the first metal post 14 protruding from the second insulating layer 115 . A distance D3 shown in FIG. 11 is the center-to-center distance between two adjacent first metal posts 14 .

The distance D1 is preferably in the range of 20 μm to 70 μm, more preferably in the range of 30 μm to 50 μm. When the diameter D2 is constant, the stress applied to the first metal post 14 by the insulating portion 1151 can be easily relieved by increasing the distance D1. Further, when the diameter D2 is constant and the distance D1 is reduced, the underfill material is less likely to flow when it is filled between the wiring board 10A and the functional device 20 .

The diameter D2 is preferably in the range of 20 μm to 70 μm, more preferably in the range of 30 μm to 50 μm. If the diameter D2 is reduced, the first metal post 14 is likely to be broken, so it is difficult to increase the height of the first metal post 14 . Therefore, the distance between the wiring board 10A and the functional device 20 is shortened. Further, when it is attempted to increase the height of the first metal post 14, the height of the first metal post 14 tends to vary.

The distance D3 is preferably in the range of 70 μm to 150 μm, more preferably in the range of 70 μm to 110 μm.

The ratio D2/D1 of the diameter D2 to the distance D1 is preferably in the range of 1.2 to 1.7, more preferably in the range of 1.3 to 1.7. In this case, since the first metal post 14 is less likely to break or bend, high connection reliability is achieved.

Also, the thickness T1 of the second insulating layer 115 is preferably in the range of 15 μm to 45 μm, more preferably in the range of 20 μm to 40 μm. When the second insulating layer 115 is thickened, the underfill material flows easily when the underfill material is filled between the wiring board 10A and the functional device 20 . If the second insulating layer 115 is too thin, the underfill material will not easily flow. If the second insulating layer 115 is too thick, the height of the first metal post 14 will increase. In this case, the height of the first metal post 14 tends to vary.

Here, the thickness T1 of the second insulating layer 115 is the maximum height of the second insulating layer 115 when the height of the upper surface of the first insulating layer 1111 is used as a reference.

Also, the diameter of the land portion of the electrode 112P is preferably in the range of 30 μm to 90 μm, more preferably in the range of 40 μm to 70 μm.

Further, when the diameter of the land portion of the electrode 112P is in the range of 40 μm to 70 μm, the diameter D2 of the first metal post is in the range of 35 μm to 55 μm, and the thickness T1 of the second insulating layer 115 is in the range of 15 μm to 45 μm. is preferably within the range of In this case, when the functional device 20 is mounted on the wiring board 10A, the stress applied to the first metal posts 14 can be easily alleviated. Therefore, bending and breaking of the first metal post 14 are less likely to occur.

<Method for manufacturing a semiconductor device>
The semiconductor device 1 shown in FIG. 1 can be manufactured by using the wiring substrate 10A obtained by the method described above.

First, the wiring substrate 10A shown in FIG. 10 and the functional device 20 provided with the second metal posts 50 are prepared.
Next, the functional device 20 is bonded to the surface of the wiring board 10A on the second insulating layer 115 side. Specifically, the first joining conductor 16 and the second metal post 50 are joined.
Next, an underfill material is filled between the wiring substrate 10A and the functional device 20 to form the sealing resin layer 30 .

As the underfill material, for example, a mixture of resin and filler can be used. As the resin, for example, one of epoxy resin, urethane resin, silicone resin, polyester resin, oxetane resin, and maleimide resin, or a mixture of two or more of these resins can be used. As fillers, for example, one or more of silica, titanium oxide, aluminum oxide, magnesium oxide, and zinc oxide can be used.
An example of the method for manufacturing the semiconductor device 1 has been described above.

<effect>
As described above, the flip chip bonding method has evolved to use metal posts. When metal posts are used, for example, the wiring board and the functional device can be spaced apart by several tens of μm, for example. Therefore, the distance between the functional device and the wiring board is ensured, and short-circuiting between adjacent metal posts is less likely to occur. This makes it possible to narrow the pitch of the connection terminals. In addition, by securing the distance between the functional device and the wiring board, the heat dissipation performance of the semiconductor device is improved.

In recent years, due to the increase in the number of electrodes and the reduction in the height of semiconductor packages, the gap between the functional device and the wiring board has become narrower, and the distance between adjacent connection terminals has become smaller. there is For this reason, it is difficult to fill the underfill material, and air bubbles called voids remain in the underfill layer, and when heated, the air bubbles expand to cause poor bonding.

FIG. 12 is a cross-sectional view schematically showing a semiconductor device according to a comparative example. 13 is a cross-sectional view schematically showing a wiring substrate used for manufacturing the semiconductor device shown in FIG. 12. FIG. A semiconductor device 1' shown in FIG. 12 is the same as the semiconductor device 1 shown in FIG. Similarly, a wiring board 10' shown in FIG. 13 is the same as the wiring board 10A shown in FIG. The second insulating layer 115' is not open between the two or more electrodes 112P. That is, in the wiring board 10' shown in FIG. 13, the height at the position between the two or more electrodes 112P is the same as the height of the second insulating layer 115' at the position adjacent to the through hole of the second insulating layer 115'. is.

In the manufacture of the semiconductor device 1', when the wiring board 10' and the functional device 20 are bonded together and an underfill material is filled between them, the gap between the wiring board 10' and the functional device 20 is narrow. In particular, when the pattern of the first metal post 14 is miniaturized, the gap is narrower. For this reason, the underfill material is less likely to flow, and air bubbles tend to remain in the gaps. Therefore, it is difficult to achieve high connection reliability with the wiring board 10'.

On the other hand, in the wiring board 10A described above, the height of the laminate 11 at any position between the two or more electrodes 112P is the second height at the position adjacent to the first through hole of the second insulating layer 115. Lower compared to the height of the insulating layer 115 . Therefore, the cross-section of the flow path of the underfill material, which is perpendicular to the flow direction, is wide. Therefore, in the manufacture of the semiconductor device 1' using the wiring board 10A described above, the underfill material flows easily, and air bubbles are less likely to remain in the gaps. Therefore, the wiring board 10A described above can achieve high connection reliability.

In addition, in the above-described semiconductor device 1, if the second insulating layer 115 is omitted, the cross section of the flow path of the underfill material perpendicular to the flow direction is wide. However, when the second insulating layer 115 is omitted, the stress applied to the first metal post 14 increases due to deformation such as warping of the functional device 20 and the wiring substrate 10A due to heating. In this case, breakage or deformation of the first metal post 14 is likely to occur. Therefore, it is difficult to achieve high connection reliability.

<Wiring board according to another embodiment>
Wiring boards according to other embodiments of the present invention will be described below.
FIG. 14 is a plan view schematically showing the upper surface of a wiring board according to another embodiment of the invention. A wiring board 10B shown in FIG. 14 is the same as the wiring board 10A shown in FIGS. 10 and 11 except that it has the following configuration. Wiring board 10B has a shape in which each of insulating portions 1151 is orthogonally projected onto a plane perpendicular to the stacking direction of first insulating layer 1111 and second insulating layer 115 and extends in one direction. In the wiring substrate 10B, the extending directions of the orthogonal projections of the insulating portions 1151 are the same.

According to such a configuration, when the underfill material is injected in the extension direction of the orthogonal projection of the insulating portion 1151, the underfill material tends to flow in the extension direction. Therefore, air bubbles are less likely to remain in the gap between the wiring board 10B and the functional device 20 .

The ratio L/W of the length L of the orthogonal projection, i.e. the maximum length of the orthogonal projection, to the width W of the orthogonal projection, i.e. the maximum length in the direction perpendicular to the direction having the maximum length L is preferably in the range of greater than 1 and 1.5 or less, more preferably in the range of 1 to 1.4.

The above orthographic projection is, for example, an ellipse. If the orthogonal projection is an ellipse, the maximum length L and width W correspond to the major and minor axes of the ellipse, respectively. The orthogonal projection above may be oval.

FIG. 15 is a plan view schematically showing the upper surface of a wiring board according to still another embodiment of the invention. A wiring board 10C shown in FIG. 15 is the same as the wiring board 10B shown in FIG. 14 except that it has the following configuration. A plane of the wiring board 10C perpendicular to the stacking direction of the first insulating layer 1111 and the second insulating layer 115 is divided into a first strip region R1, a second strip region R2, and a third strip region R3. In this case, among the orthogonal projections of the plurality of insulating portions 1151, those positioned within the first strip-shaped region R1 have extension directions substantially parallel to the length direction of the first strip-shaped region R1. Further, among the above orthogonal projections of the plurality of insulating portions 1151, those positioned within the second strip-shaped region R2 are inclined clockwise with respect to the longitudinal direction of the first strip-shaped region R1. Further, among the above orthogonal projections of the plurality of insulating portions 1151, those positioned within the third band-shaped region R3 are inclined counterclockwise with respect to the length direction of the first band-shaped region R1. The second strip region R2 is a region adjacent to the first strip region R1 in the width direction. The third strip-shaped region R3 is a region adjacent to the second strip-shaped region R2 in the width direction with the first strip-shaped region R1 interposed therebetween.

According to such a configuration, when the underfill material is filled from the left side in FIG. 15, the underfill material tends to flow substantially radially from the injection position of the underfill material without causing turbulence. Therefore, air bubbles are less likely to remain in the gap between the wiring board 10C and the functional device 20 .

In FIG. 15, the insulating portions 1151 are arranged in a row in each band-shaped region, but normally the insulating portions 1151 are arranged in a plurality of rows. When the insulating portions 1151 are arranged in a plurality of rows, the orthographic projections of the insulating portions 1151 positioned in each band-shaped region have the same inclination in the extension direction with respect to the length direction of the first band-shaped region R1. may Alternatively, in each of the second and third strip-shaped regions, the orthogonal projection of the insulating portion 1151 located within the strip-shaped region increases the length of the first strip-shaped region R1 as the distance from the first strip-shaped region R1 increases. You may change so that the inclination of the extension direction with respect to a direction may become large.

In the wiring boards 10A, 10B, and 10C described above, the second insulating layer 115 is open in all of the gaps between the two adjacent electrodes 112P, but part of the gaps between the two adjacent electrodes 112P are open. It is not necessary to open at other parts.

For example, in the wiring boards 10A, 10B, and 10C described above, one insulating portion 1151 covers one electrode 112P, but one insulating portion 1151 may cover two or more electrodes 112P. For example, in the wiring substrate 10C described above, the second insulating layer 115 may be connected between two laterally adjacent electrodes 112P. In this case, compared to the case where the second insulating layer 115 has openings between two electrodes 112P adjacent to each other in the lateral direction, the ease of flow of the underfill material in the lateral direction is excellent. In addition, the number of electrodes 112P covered by one insulating portion 1151 may be different for each insulating portion 1151 .

Moreover, in the wiring boards 10A, 10B, and 10C described above, the opening may be made only at the position of the first metal post 14 . In this case, by making the thickness of the second insulating layer 115 between the two or more electrodes 112P smaller than the maximum height of the second insulating layer 115, the height of any position between the two or more electrodes 112P can be reduced. A wiring board having a lower height than the height of the second insulating layer 115 at the position adjacent to the first through hole is obtained.

In the above case, the difference between the height of the second insulating layer 115 at a position adjacent to the first through hole of the second insulating layer 115 and the height of the wiring board at any position between the two or more electrodes 112P is , preferably within the range described above for the thickness of the second insulating layer 115 .

Further, in the semiconductor device 1 described above, an insulating resin layer made of an underfill material is formed as the sealing resin layer 30, but the insulating resin layer is made of an insulating resin film or a non-conductive paste. It may be a different layer. The insulating resin film is, for example, an anisotropic conductive film (ACF) or a film-like bonding material (Non Conductive Film, NCF).

Even when an insulating resin film is used, the insulating resin tends to spread in the gap between the wiring board 10A and the functional device 20, so air bubbles are less likely to remain in this gap. Therefore, a semiconductor device 1 having high connection reliability can be obtained. Even when a non-conductive paste is used, a semiconductor device 1 having high connection reliability can be obtained as in the case of using an insulating resin film.

As the insulating resin layer, in addition to insulating properties, a layer having high thermal conductivity or magnetic resistance may be used.

DESCRIPTION OF SYMBOLS 1... Semiconductor device 1'... Semiconductor device 10A... Wiring board 10B... Wiring board 10C... Wiring board 10'... Wiring board 11... Laminated body 12... Seed layer 13... Resist layer 14... Second Reference Signs List 1 metal post 15 surface treatment layer 16 first junction conductor 20 functional device 30 sealing resin layer 40 junction electrode 50 second metal post 110 core layer 111 insulation Layer 112... Conductor layer 112P... Electrode 113... Insulating layer 114... Second joining conductor 115... Second insulating layer 115'... Second insulating layer 1111... First insulating layer 1151... Insulating part .

Claims (13)

a first insulating layer, a second insulating layer provided on the first insulating layer, and two or more electrodes interposed between the first insulating layer and the second insulating layer; The insulating layer is a laminate having a through hole at each of the positions of the two or more electrodes;
A wiring board comprising two or more first metal posts each filling the through hole and protruding from the second insulating layer,
A wiring board in which the height at any position between the two or more electrodes is lower than the height of the second insulating layer at a position adjacent to the through hole. 2. The wiring board according to claim 1, wherein said second insulating layer has an opening such that said first insulating layer is exposed at any position between said two or more electrodes. 3. The wiring board according to claim 2, wherein the second insulating layer is opened to form one or more grooves. Each of the one or more grooves has one end communicating directly or via one or more other grooves with a region outside the arrangement of the two or more electrodes at a first position, and the other end communicating directly or 4. The wiring board according to claim 3, wherein the wiring board communicates with the region outside the arrangement of the two or more electrodes at a second position via one or more other grooves. The second insulating layer includes a plurality of insulating portions spaced apart from each other with the one or more grooves interposed therebetween, and a plane perpendicular to a stacking direction of the first insulating layer and the second insulating layer. 5. The wiring board according to claim 3, wherein each of said plurality of insulating portions has a circular outer contour in orthogonal projection. The second insulating layer includes a plurality of insulating portions spaced apart from each other with the one or more grooves interposed therebetween, and a plane perpendicular to a stacking direction of the first insulating layer and the second insulating layer. the orthographic projection of the plurality of insulating portions of each has a shape extending in one direction,
The plane includes a first strip-shaped region, a second strip-shaped region adjacent to the first strip-shaped region in the width direction, and a second strip-shaped region adjacent to the second strip-shaped region in the width direction with the first strip-shaped region interposed therebetween. 3 strips and
Among the orthogonal projections of the plurality of insulating portions, those located within the first strip-shaped region have extension directions substantially parallel to the length direction of the first strip-shaped region, and are located within the second strip-shaped region. , the direction of extension is inclined clockwise with respect to the length direction, and the direction of extension is inclined counterclockwise with respect to the length direction of those located in the third band-shaped region. 5. The wiring board according to claim 3 or 4. 7. The wiring board according to claim 6, wherein a ratio L/W of the length L of the orthogonal projection and the width W of the orthogonal projection is in the range of greater than 1 and 1.5 or less. 8. The method according to any one of claims 5 to 7, wherein a ratio D2/D1 of a diameter D2 of said first metal post to a shortest distance D1 between said two adjacent insulating parts is within a range of 1.2 to 1.7. A wiring board as described. 9. The wiring board according to claim 1, wherein the thickness of said second insulating layer is in the range of 15 [mu]m to 45 [mu]m. A wiring board according to any one of claims 1 to 9;
a functional device mounted on the surface of the wiring substrate on the second insulating layer side;
A semiconductor device comprising a sealing resin layer interposed between the wiring board and the functional device. A second insulation having a first through-hole on each of the first insulating layer and two or more electrodes provided thereon and opening between the two or more electrodes. forming a layer;
forming a resist layer that fills the gap between the two or more electrodes and has a second through hole communicating with the first through hole;
forming a first metal post in which the first through hole and the second through hole are embedded;
and removing the resist layer. bonding a functional device to the second insulating layer side surface of the wiring board according to any one of claims 1 to 9;
and filling an underfill material between the wiring board and the functional device. 10. The wiring board and the functional device are joined by interposing an insulating resin layer between the surface of the wiring board according to claim 1 on the second insulating layer side and the functional device. A method of manufacturing a semiconductor device comprising:

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