JP2023001140A - Display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display device in which the variation in threshold voltage of a transistor can be compensated and the variation in luminance can be suppressed, and a driving method using the same.

SOLUTION: In a first period, an initial voltage is held in a holding capacitor. In a second period, a voltage based on a video signal voltage and a transistor threshold voltage is held in the holding capacitor. In a third period, the voltage held in the holding capacitor in the second period is applied to a gate electrode of the transistor, so that current is supplied to a light-emitting element to cause the light-emitting element to emit light. By this operation process, current in which the influence from the variation in threshold voltage of the transistor is compensated can be supplied to the light-emitting element and the variation in luminance can be suppressed.

SELECTED DRAWING: Figure 3

COPYRIGHT: (C)2023,JPO&INPIT

Description

The present invention relates to a configuration of a display device having transistors and a driving method thereof. In particular, the present invention relates to a configuration of an active matrix display device having thin film transistors and a driving method thereof. The present invention also relates to an electronic device using such a display device as a display portion.

2. Description of the Related Art In recent years, so-called self-luminous display devices in which pixels are formed of light-emitting elements such as light-emitting diodes (LEDs) have attracted attention. Light-emitting elements used in such self-luminous display devices include organic light-emitting diodes (OLEDs).
Diode), organic EL element, electroluminescence (Electro Lumi
nessence (also referred to as an EL) element) is attracting attention and is being used in EL displays and the like. Since light-emitting elements such as OLED are self-luminous,
Compared to liquid crystal displays, it has advantages such as high pixel visibility, no need for a backlight, and fast response speed. Also, the brightness of the light emitting element is controlled by the value of the current flowing therethrough.

In recent years, active matrix display devices in which a light-emitting element and a transistor for controlling light emission of the light-emitting element are provided for each pixel have been developed. Active-matrix display devices not only enable high-definition, large-screen displays that are difficult to achieve with passive-matrix display devices, but also achieve lower power consumption and higher reliability than passive-matrix display devices. and is expected to be put to practical use.

Methods for driving pixels in an active matrix display device can be classified into a voltage input method and a current input method when classified according to the type of signal input to the pixel. The former voltage input method is a method in which a video signal (voltage) to be input to a pixel is input to the gate electrode of a driving element and the driving element is used to control the luminance of the light emitting element. The latter current input method is a method of controlling the luminance of a light emitting element by causing a set signal current to flow through the light emitting element.

Here, an example of pixel configuration and its driving method in a display device to which a voltage input method is applied will be briefly described with reference to FIG. Note that an EL display device will be described as an example of a typical display device.

FIG. 67 is a diagram showing an example of a pixel configuration in a display device to which a voltage input method is applied (see Patent Document 1). The pixel shown in FIG. 67 has a driving transistor 6701, a switching transistor 6702, a holding capacitor 6703, a signal line 6704, a scanning line 6705, first and second power supply lines 6706 and 6707, and a light emitting element 6708.

Note that, in this specification, that a transistor is on means that the gate of the transistor is on.
Refers to a state in which the voltage across the source exceeds its threshold voltage and current flows between the source and drain, and a transistor is off when the voltage across its gate-source falls below its threshold voltage and the source and drain A state in which no current flows between

When the potential of the scanning line 6705 changes and the switching transistor 6702 is turned on, the video signal input to the signal line 6704 is input to the gate electrode of the driving transistor 6701 . The voltage between the gate and source of the driving transistor 6701 is determined according to the potential of the input video signal, and the current flowing between the source and drain of the driving transistor 6701 is determined. This current is supplied to the light emitting element 6708 and the light emitting element 6708
emits light.

In this way, the voltage input method uses the potential of the video signal to
This is a method in which a source-to-source voltage and a current flowing between a source and a drain are set, and a light-emitting element emits light with luminance corresponding to the current.

A polysilicon (p-Si) transistor is used as a semiconductor element for driving the light emitting element. However, polysilicon transistors tend to have variations in electrical characteristics such as threshold voltage, on-current, and mobility due to defects in crystal grain boundaries. In the pixel shown in FIG. 67, if the characteristics of the driving transistor 6701 vary from pixel to pixel, even if the same video signal is input, the magnitude of the drain current of the driving transistor 6701 varies accordingly. The brightness of 6708 will vary.

In the conventional pixel circuit (FIG. 67), the storage capacitor is connected between the gate and source of the driving transistor. becomes substantially equal to the threshold voltage of the MOS transistor, no channel region is induced in the MOS transistor, and the MOS transistor no longer functions as a storage capacitor. As a result, the video signal cannot be held correctly.

JP-A-2001-147659

As described above, in the conventional voltage input method, variations in luminance occur due to variations in electrical characteristics of transistors.

SUMMARY OF THE INVENTION In view of such problems, an object of the present invention is to provide a semiconductor device, a display device, and a method of driving the same that can compensate for variations in threshold voltage of transistors and reduce variations in luminance. .

Note that the object of the present invention is not limited to semiconductor devices and display devices having light-emitting elements, and an object of the present invention is to suppress variations in drain current caused by variations in threshold voltages of transistors. Therefore, the destination to which the drain current of the driving transistor is supplied is not limited to the light emitting element. In the following, the destination to which the drain current is supplied is also collectively referred to as a load.

The present invention is a semiconductor device having a pixel, and the pixel includes at least a signal line to which a video signal is applied, a capacitor line, a first electrode electrically connected to the signal line, and a second electrode. a first transistor electrically connected to a load and a second transistor functioning as a switch for selecting whether or not to electrically connect the second electrode and the gate electrode of the first transistor and a storage capacitor having a first electrode electrically connected to the gate electrode of the first transistor and a second electrode electrically connected to a capacitor line, the first electrode of the storage capacitor and A potential obtained by adding or subtracting the absolute value of the threshold voltage of the first transistor from the video signal voltage applied to the gate electrode of the first transistor and the potential of the first electrode of the first transistor flow to the load. The semiconductor device is characterized in that the amount of current is determined.

The present invention is a semiconductor device having a pixel, and the pixel includes at least a signal line, a capacitor line, and a first electrode electrically connected to the signal line, and a second electrode electrically connected to a load. connected first
a second transistor having a function as a switch for selecting whether or not to electrically connect the second electrode and the gate electrode of the first transistor; and the first electrode being the first transistor and a storage capacitor having a second electrode electrically connected to the gate electrode of the capacitor, based on the video signal voltage applied to the signal line and the threshold voltage of the first transistor The semiconductor device is characterized in that the voltage is held in a holding capacitor, and the current set in the first transistor according to the voltage is supplied to the load.

The present invention is a semiconductor device having a pixel, and the pixel includes a signal line, a capacitor line, a power supply line,
A first transistor that has a function of supplying current to a load, a second transistor that functions as a switch that electrically connects a first electrode of the first transistor and a signal line, and the first transistor A third transistor functioning as a switch for electrically connecting the first electrode of the first transistor to the power supply line and whether or not to electrically connect the second electrode and the gate electrode of the first transistor A fourth transistor functioning as a switch for selection, a fifth transistor functioning as a switch for electrically connecting the second electrode of the first transistor and the load, and the first electrode a video signal voltage applied to the signal line and a threshold of the first transistor; A semiconductor device is characterized in that a voltage based on a voltage is held in a holding capacitor, and current set in a first transistor according to the voltage is supplied from a power supply line to a load.

The present invention is a semiconductor device having a pixel, and the pixel includes a signal line, a capacitor line, a power supply line,
A first transistor that has a function of supplying current to a load, a second transistor that functions as a switch that electrically connects a first electrode of the first transistor and a signal line, and the first transistor A third transistor functioning as a switch for electrically connecting the first electrode of the first transistor to the power supply line and whether or not to electrically connect the second electrode and the gate electrode of the first transistor a fourth transistor functioning as a selection switch; and a storage capacitor having a first electrode electrically connected to the gate electrode of the first transistor and a second electrode electrically connected to a capacitance line a voltage based on the video signal voltage applied to the signal line and the threshold voltage of the first transistor is held in the holding capacitor, and the current set in the first transistor corresponding to the voltage is supplied from the power supply line A semiconductor device that supplies power to a load.

Note that in the semiconductor device of the present invention, the pixel may further include a sixth transistor, and an initial potential may be applied to the second electrode of the first transistor through the sixth transistor.

Note that in the semiconductor device of the present invention, the second electrode of the first transistor may be electrically connected to a wiring included in the pixel through the sixth transistor.

Note that in the semiconductor device of the present invention, the pixel may further have an initialization line electrically connected to the second electrode of the first transistor through the sixth transistor.

Note that in the semiconductor device of the present invention, another wiring included in the pixel may be used as the capacitor line.

Note that in the semiconductor device of the present invention, the first transistor has the largest ratio W/L of the channel length L to the channel width W of the transistors included in the pixel. It is desirable to have

Note that in the semiconductor device of the present invention, the second transistor and the third transistor are
Different conductive types may be used.

Note that in the semiconductor device of the present invention, a pixel may further have a plurality of scanning lines, and gate electrodes of at least two transistors included in the pixel may be electrically connected to the same scanning line.

Note that the semiconductor device of the present invention may further include a plurality of scan lines, and gate electrodes of a plurality of transistors included in the pixel may be electrically connected to different scan lines.

Note that in the semiconductor device of the present invention, the fourth transistor may be of an N-channel type.

The present invention includes a signal line, a capacitor line, a power supply line, a first transistor having a first electrode electrically connected to the signal line and a second electrode electrically connected to a load, and a first transistor. 1 transistor second
a second transistor having a function as a switch for selecting whether or not to electrically connect the electrode and the gate electrode of the first transistor; the first electrode is electrically connected to the gate electrode of the first transistor; 2 electrodes are electrically connected to a capacitor line, and a current is passed through a load to hold a predetermined initial voltage in the storage capacitor, and then the second transistor is turned on. holding a voltage based on the video signal voltage supplied from the signal line and the threshold voltage of the first transistor in the storage capacitor as a state, and applying a voltage based on the voltage to the gate electrode of the first transistor; A method of driving a semiconductor device is characterized in that a current is supplied to a load from a power supply line through a first transistor.

The present invention includes a signal line, a capacitor line, a power supply line, a first transistor having a first electrode electrically connected to the signal line and a second electrode electrically connected to a load, and a first transistor. 1 transistor second
and a switch for applying an initial potential to the second electrode of the first transistor. a pixel including a third transistor having a function and a storage capacitor having a first electrode electrically connected to the gate electrode of the first transistor and a second electrode electrically connected to a capacitor line; Then, after the initial potential is applied to the second electrode of the first transistor by turning on the third transistor, the second transistor is turned on to supply the video signal to the storage capacitor through the signal line. holding a voltage and a voltage based on the threshold voltage of the first transistor, applying a voltage based on the voltage to the gate electrode of the first transistor;
A method of driving a semiconductor device is characterized in that a current is supplied to a load from a power supply line through a first transistor.

Note that the driving method of the present invention further includes an initialization line electrically connected to the second electrode of the first transistor through the third transistor, and supplies an initial potential from the initialization line. may

Note that in the driving method of the present invention, the period during which the storage capacitor retains the video signal voltage supplied from the signal line and the voltage based on the threshold voltage of the first transistor and the period other than this period are different from each other. Different voltages may be applied.

Further, in the above structure, the load may be a light-emitting element.

Note that it is difficult to distinguish between a source and a drain of a transistor due to its structure. Furthermore, depending on the operation of the circuit, the high and low potentials may be interchanged. Therefore, in this specification,
A source and a drain are not particularly specified, and are described as a first electrode and a second electrode. For example, when the first electrode is the source, the second electrode refers to the drain, and conversely, when the first electrode is the drain, the second electrode refers to the source. .

In this document (specifications, claims, drawings, etc.), one pixel indicates one color element. Therefore, in the case of a color display device composed of R (red), G (green) and B (blue) color elements, the minimum unit of an image is composed of three pixels of R pixel, G pixel and B pixel. shall be Note that the color elements are not limited to three colors, more colors may be used, and colors other than RGB may be used. For example, RGBW may be obtained by adding white (W). Moreover, one or more colors such as yellow, cyan, and magenta may be added to RGB. Also, for example, a similar color may be added for at least one of RGB. For example, it may be R, G, B1, and B2. Both B1 and B2 are blue, but have different wavelengths. By using such color elements, a more realistic display can be achieved, and power consumption can be reduced. Note that brightness may be controlled using a plurality of areas for one color element. In this case, one color element is assumed to be one pixel, and each area for controlling the brightness is assumed to be a sub-pixel. Therefore, for example, when the area coverage gradation method is used, each color element has a plurality of areas for controlling brightness, and gradation is expressed by the entire area. Pixels. Therefore, in that case, one color element is composed of a plurality of sub-pixels. In that case, the size of the region that contributes to display may differ depending on the sub-pixel. In addition, in a plurality of brightness control regions for one color element, that is, in a plurality of sub-pixels constituting one color element, the signals supplied to each are slightly different, and the viewing angle is adjusted. You may make it expand.

Note that in this document (the specification, claims, drawings, etc.), pixels are arranged (arranged) in a matrix. Here, the arrangement (arrangement) of the pixels in a matrix includes the case where the pixels are arranged in a straight line in the vertical direction or the horizontal direction, and the case where the pixels are arranged in a jagged line. Thus, for example, three color elements (
For example, in the case of performing full-color display in RGB), it includes the case of stripe arrangement and the case of so-called delta arrangement of dots of three color elements. Furthermore, it also includes the case of Bayer arrangement. Note that the size of the display area may be different for each dot of the color element. As a result, power consumption can be reduced or the life of the display element can be extended.

Note that a light-emitting element in this document (specifications, claims, drawings, etc.) refers to an element whose luminance can be controlled by a current value flowing through the element. Typically E
L-elements can be applied. The EL element may be an organic EL element or an inorganic EL element.
It may be an element. Besides the EL element, for example, a field emission display (FE
D) Element used in SED (Surface-conduction) which is a kind of FED
A light-emitting element such as an Electron-emitter Display) can be applied.

Note that various types of transistors can be used as the transistor described in this document (the specification, claims, drawings, or the like). Therefore, the type of transistor to be used is not limited. For example, a thin film transistor (TFT) including a non-single-crystal semiconductor film typified by amorphous silicon, polycrystalline silicon, microcrystalline (also called microcrystalline or semi-amorphous) silicon, or the like can be used. The use of TFTs has various advantages. For example, since it can be manufactured at a lower temperature than in the case of single crystal silicon, it is possible to reduce the manufacturing cost or increase the size of the manufacturing apparatus. Since the manufacturing equipment can be made large, it can be manufactured on a large substrate. Therefore, since a large number of display devices can be manufactured at the same time, they can be manufactured at low cost. Furthermore, since the manufacturing temperature is low, a substrate with low heat resistance can be used. Therefore, a transistor can be manufactured on a transparent substrate. Transistors on a transparent substrate can then be used to control the transmission of light through the display element. Alternatively, since the film thickness of the transistor is thin, part of the film forming the transistor can transmit light. Therefore, the aperture ratio can be improved.

By using a catalyst (such as nickel) when manufacturing polycrystalline silicon, crystallinity can be further improved, and a transistor with good electrical characteristics can be manufactured. As a result, gate driver circuits (scanning line driving circuits) and source driver circuits (signal line driving circuits)
, a signal processing circuit (a signal generation circuit, a gamma correction circuit, a DA conversion circuit, etc.) can be integrally formed on the substrate.

Note that crystallinity can be further improved by using a catalyst (such as nickel) when microcrystalline silicon is manufactured, so that a transistor with excellent electrical characteristics can be manufactured. At this time, crystallinity can be improved only by applying heat treatment without using a laser. As a result, the gate driver circuit (scanning line driver circuit) and part of the source driver circuit (analog switch, etc.) can be integrally formed on the substrate. Furthermore, when a laser is not used for crystallization, uneven crystallinity of silicon can be suppressed. Therefore, a clear image can be displayed.

However, it is possible to produce polycrystalline silicon and microcrystalline silicon without using a catalyst (such as nickel).

Alternatively, a transistor can be formed using a semiconductor substrate, an SOI substrate, or the like. As a result, it is possible to manufacture small-sized transistors with little variation in characteristics, size, shape, etc., high current supply capability, and the like. By using these transistors, the power consumption of the circuit can be reduced or the circuit can be highly integrated.

Alternatively, a transistor including a compound semiconductor or oxide semiconductor such as ZnO, a-InGaZnO, SiGe, GaAs, IZO, ITO, or SnO, or a thin film transistor obtained by thinning any of these compound semiconductors or oxide semiconductors can be used. I can. As a result, the manufacturing temperature can be lowered, and for example, the transistor can be manufactured at room temperature. As a result, a transistor can be formed directly on a substrate having low heat resistance, such as a plastic substrate or a film substrate. Note that these compound semiconductors or oxide semiconductors are
It can be used not only for the channel portion of a transistor, but also for other purposes. For example, these compound semiconductors or oxide semiconductors can be used as resistance elements, pixel electrodes, and transparent electrodes. Furthermore, since they can be deposited or formed at the same time as the transistors, costs can be reduced.

Alternatively, a transistor or the like formed by an inkjet method or a printing method can be used. These allow fabrication at room temperature, in low vacuum, or on large substrates. Moreover, since it is possible to manufacture without using a mask (reticle), the layout of the transistor can be easily changed. Furthermore, since it is not necessary to use a resist, the material cost can be reduced and the number of steps can be reduced. Furthermore, since the film is applied only to the necessary portions, the material is not wasted and the cost can be reduced as compared with the manufacturing method in which the film is formed on the entire surface and then etched.

Alternatively, a transistor including an organic semiconductor, a carbon nanotube, or the like can be used. These allow a transistor to be formed on a bendable substrate.
Therefore, it can be strongly impact-resistant.

Furthermore, transistors with various structures can be used. For example, a MOS transistor, a junction transistor, a bipolar transistor, or the like can be used as the transistor described in this document (specification, claims, drawings, etc.). By using a MOS transistor, the size of the transistor can be reduced. Therefore,
A large number of transistors can be mounted. A large current can flow by using a bipolar transistor. Therefore, the circuit can be operated at high speed.

Note that a MOS transistor, a bipolar transistor, and the like may be mixed and formed on one substrate. As a result, low power consumption, miniaturization, high-speed operation, and the like can be achieved.

In addition, various transistors can be used.

Note that various kinds of substrates over which transistors are formed can be used and are not limited to specific substrates. Substrates on which transistors are formed include, for example, single crystal substrates, SOI substrates, glass substrates, quartz substrates, plastic substrates, paper substrates, cellophane substrates, stone substrates, wood substrates, cloth substrates (natural fibers (silk, cotton, hemp), ), synthetic fibers (nylon, polyurethane, polyester) or recycled fibers (acetate, cupra, rayon, recycled polyester), etc.), leather substrates, rubber substrates, stainless steel substrates, substrates with stainless steel foil, etc. can be used. Alternatively, the skin (epidermis, dermis) or subcutaneous tissue of animals such as humans may be used as the substrate. Alternatively, a transistor may be formed on one substrate, then transferred to another substrate, and placed on the other substrate. Substrates on which transistors are transferred include single crystal substrates, SOI substrates,
Glass substrate, quartz substrate, plastic substrate, paper substrate, cellophane substrate, stone substrate, wood substrate, cloth substrate (natural fiber (silk, cotton, hemp), synthetic fiber (nylon, polyurethane, polyester) or recycled fiber (acetate, (including cupra, rayon, recycled polyester), a leather substrate, a rubber substrate, a stainless steel substrate, a substrate having a stainless steel foil, and the like can be used. Alternatively, the skin (epidermis, dermis) or subcutaneous tissue of animals such as humans may be used as the substrate. Alternatively, a transistor may be formed on a substrate and the substrate may be polished to be thin. Substrates to be polished include single crystal substrates, SOI substrates, glass substrates, quartz substrates, plastic substrates, paper substrates, cellophane substrates, stone substrates, wood substrates, cloth substrates (natural fibers (silk, cotton, linen), synthetic Fibers (nylon, polyurethane, polyester) or recycled fibers (acetate, cupra, rayon, recycled polyester), etc.), leather substrates, rubber substrates, stainless steel substrates, substrates with stainless steel foil, etc. can be used. can. Alternatively, the skin (epidermis, dermis) or subcutaneous tissue of animals such as humans may be used as the substrate. By using these substrates, it is possible to form a transistor with excellent characteristics, a transistor with low power consumption, manufacture a device that is not easily broken, impart heat resistance, and reduce the weight or thickness of the device.

In this document (specifications, claims, drawings, etc.), being connected is synonymous with being electrically connected. Therefore, in the configuration disclosed by the present invention, in addition to the predetermined connection relationship, other elements (for example, other elements, switches, etc.) that enable electrical connection may be arranged therebetween.

Note that switches shown in this document (specifications, claims, drawings, etc.) can be of various forms, and examples thereof include electrical switches and mechanical switches. In other words, any device can be used as long as it can control the flow of current, and various devices can be used without being limited to a specific one. For example, it may be a transistor or a diode (eg, P
an N diode, a PIN diode, a Schottky diode, a diode-connected transistor, etc.), a thyristor, or a logic circuit combining them. Therefore, when a transistor is used as a switch, the transistor simply operates as a switch, and the polarity (conductivity type) of the transistor is not particularly limited. however,
When a smaller off-state current is desirable, it is desirable to use a transistor having a polarity with a smaller off-state current. As a transistor with low off-state current, there are a transistor provided with an LDD region, a transistor with a multi-gate structure, and the like. In addition, when the potential of the source terminal of the transistor operated as a switch operates in a state close to the low potential side power supply (VSS, GND, 0 V, etc.), the N-channel type is used. It is desirable to use a P-channel type when operating in a state close to a side power supply (VDD, etc.). This is because the absolute value of the voltage between the gate and the source can be increased, so that it can easily function as a switch.
Note that both the N-channel type and the P-channel type may be used to form a CMOS type switch. If a CMOS switch is used, current can flow if either the P-channel switch or the N-channel switch is turned on, so that it can easily function as a switch. for example,
Whether the voltage of the input signal to the switch is high or low, the voltage can be output appropriately. Moreover, since the voltage amplitude value of the signal for turning on/off the switch can be reduced, power consumption can be reduced.

In addition, in this document (specifications, claims, drawings, etc.) The description of "on" is not limited to being in direct contact with a certain object. It includes the case where they are not in direct contact, that is, the case where another object is sandwiched between them. Therefore, for example, when a layer B is formed on a layer A (or on a layer A), the case where the layer B is formed directly on the layer A and the case where the layer B is formed on the layer A directly in contact with another layer (e.g. layer C
, layer D, etc.) are formed, and layer B is formed in direct contact thereon. The same applies to the description of above, and it is not limited to being in direct contact with a certain object, but also includes the case where another object is sandwiched between them. Therefore, for example, when the layer B is formed above the layer A, the case where the layer B is formed directly on the layer A and the case where the layer B is formed directly on the layer A and another layer (For example, layer C, layer D, etc.) are formed, and layer B is formed in direct contact thereon. It should be noted that the case of "under" or "below" is the same, and includes the case of being in direct contact and the case of not being in contact.

According to the present invention, it is possible to suppress variations in current values caused by variations in threshold voltages of transistors. Therefore, a desired current can be supplied to a load such as a light emitting element. In particular, when a light-emitting element is used as a load, the display device of the present invention can compensate for variations in the threshold voltage of the transistor, so that the current flowing through the light-emitting element is determined without depending on the threshold voltage of the transistor. Accordingly, variation in luminance of the light-emitting element can be reduced, and image quality of the display device can be improved.

FIG. 4 is a diagram showing an example of the basic configuration of a pixel in the display device of the invention; FIG. 4 is a diagram showing an example of the basic configuration of a pixel in the display device of the invention; FIG. 4 is a diagram showing an example of a pixel configuration in a display device of the present invention; FIG. 10 is a diagram explaining a timing chart of a pixel circuit in a display device of the present invention; FIG. 4 is a diagram for explaining the operation of a pixel circuit in the display device of the invention; FIG. 4 is a diagram for explaining the operation of a pixel circuit in the display device of the invention; FIG. 4 is a diagram for explaining the operation of a pixel circuit in the display device of the invention; FIG. 4 is a diagram showing an example of a pixel configuration in a display device of the present invention; FIG. 10 is a diagram explaining a timing chart of a pixel circuit in a display device of the present invention; FIG. 4 is a diagram showing an example of a pixel configuration in a display device of the present invention; FIG. 4 is a diagram showing an example of a pixel configuration in a display device of the present invention; FIG. 4 is a diagram showing an example of a pixel configuration in a display device of the present invention; FIG. 4 is a diagram showing an example of a pixel configuration in a display device of the present invention; FIG. 4 is a diagram showing an example of a pixel configuration in a display device of the present invention; FIG. 4 is a diagram showing an example of a pixel configuration in a display device of the present invention; FIG. 4 is a diagram showing an example of a pixel configuration in a display device of the present invention; FIG. 10 is a diagram explaining a timing chart of a pixel circuit in a display device of the present invention; FIG. 4 is a diagram showing an example of a pixel configuration in a display device of the present invention; FIG. 10 is a diagram explaining a timing chart of a pixel circuit in a display device of the present invention; FIG. 4 is a diagram showing an example of a pixel configuration in a display device of the present invention; FIG. 4 is a diagram showing an example of a pixel configuration in a display device of the present invention; FIG. 10 is a diagram explaining a timing chart of a pixel circuit in a display device of the present invention; FIG. 4 is a diagram showing an example of a pixel configuration in a display device of the present invention; FIG. 10 is a diagram explaining a timing chart of a pixel circuit in a display device of the present invention; FIG. 4 is a diagram showing an example of a pixel configuration in a display device of the present invention; FIG. 10 is a diagram explaining a timing chart of a pixel circuit in a display device of the present invention; FIG. 4 is a diagram for explaining the operation of a pixel circuit in the display device of the invention; FIG. 4 is a diagram showing an example of a pixel configuration in a display device of the present invention; FIG. 4 is a diagram showing an example of a pixel configuration in a display device of the present invention; FIG. 4 is a diagram showing an example of a pixel configuration in a display device of the present invention; FIG. 4 is a diagram for explaining the operation of a pixel circuit in the display device of the invention; FIG. 4 is a diagram showing an example of a pixel configuration in a display device of the present invention; FIG. 4 is a diagram showing an example of a pixel configuration in a display device of the present invention; FIG. 10 is a diagram explaining a timing chart of a pixel circuit in a display device of the present invention; FIG. 4 is a diagram showing an example of a pixel configuration in a display device of the present invention; FIG. 4 is a diagram showing an example of a pixel configuration in a display device of the present invention; FIG. 4 is a diagram showing an example of a pixel configuration layout in a display device of the present invention; FIG. 10 is a diagram showing a configuration example of a display device of the present invention; FIG. 4 is a diagram showing a configuration example of a scanning line driver circuit in the display device of the present invention; FIG. 4 is a diagram showing a configuration example of a signal line driver circuit in the display device of the present invention; FIG. 10 is a diagram showing a configuration example of a display device of the present invention; FIG. 10 is a diagram showing a configuration example of a display device of the present invention; FIG. 10 is a diagram showing a configuration example of a display device of the present invention; FIG. 11 is a diagram showing an example of the configuration of a display panel used in the display device of the present invention; FIG. 13 is a diagram showing an example of a structure of a light-emitting element used in the display device of the present invention; 1A and 1B are diagrams showing an example of a configuration of a display device of the present invention; FIG. 1A and 1B are diagrams showing an example of a configuration of a display device of the present invention; FIG. 1A and 1B are diagrams showing an example of a configuration of a display device of the present invention; FIG. 1A and 1B are diagrams showing an example of a configuration of a display device of the present invention; FIG. 1A and 1B are diagrams showing an example of a configuration of a display device of the present invention; FIG. 1A and 1B are diagrams showing an example of a configuration of a display device of the present invention; FIG. 1A and 1B are diagrams showing an example of a configuration of a display device of the present invention; FIG. 1A and 1B are diagrams showing an example of a configuration of a display device of the present invention; FIG. FIG. 13 is a diagram showing the structure of a transistor used in the display device of the present invention; 4A and 4B are diagrams for explaining a method for manufacturing a transistor used in a display device of the present invention; 4A and 4B are diagrams for explaining a method for manufacturing a transistor used in a display device of the present invention; 4A and 4B are diagrams for explaining a method for manufacturing a transistor used in a display device of the present invention; 4A and 4B are diagrams for explaining a method for manufacturing a transistor used in a display device of the present invention; 4A and 4B are diagrams for explaining a method for manufacturing a transistor used in a display device of the present invention; 4A and 4B are diagrams for explaining a method for manufacturing a transistor used in a display device of the present invention; FIG. 4 is a diagram showing an example of hardware that controls the display device of the present invention; FIG. 10 is a diagram showing an example of an EL module using the display device of the present invention; FIG. 10 is a diagram showing a configuration example of a display panel using the display device of the present invention; FIG. 10 is a diagram showing a configuration example of a display panel using the display device of the present invention; FIG. 10 is a diagram showing an example of an EL television receiver using the display device of the present invention; 1A and 1B are diagrams each showing an example of an electronic device to which a display device of the present invention is applied; FIG. FIG. 10 is a diagram showing a conventional pixel configuration;

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments of the present invention will be described with reference to the drawings. Those skilled in the art will readily appreciate, however, that the present invention may be embodied in many different forms and that various changes in form and detail may be made therein without departing from the spirit and scope of the invention. be done. Therefore, it should not be construed as being limited to the description of this embodiment.

(Embodiment 1)
First, the basic configuration of the pixel circuit in the display device of this embodiment will be described with reference to FIG. Note that an EL element will be described as an example of a light emitting element.

FIG. 1 is a diagram showing a circuit configuration for acquiring a voltage based on a video signal voltage and a threshold voltage of a transistor in the pixel configuration of this embodiment. FIG. 1 shows first and second transistors 101 and 102, a holding capacitor 103, a scanning line 104, a signal line 105, a power supply line 106,
It is composed of a capacitor line 107 and a light emitting element 108 .

Note that in FIG. 1, both the first and second transistors 101 and 102 are of P-channel type.

The gate electrode of the first transistor 101 is the second electrode of the second transistor 102,
and a first electrode of the storage capacitor 103, the first electrode is connected to the signal line 105,
The second electrode is connected to the first electrode of the second transistor 102 . A gate electrode of the second transistor 102 is connected to the scan line 104 . A second electrode of the holding capacitor 103 is connected to the capacitor line 107 . In the light emitting element, the second electrode is connected to the power line 106
It is connected to the.

A video signal voltage V _data is applied to the signal line 105 and a potential V _CL is applied to the capacitor line 107 . Note that the magnitude relationship between the potentials is V _data >V _CL . A power supply potential VSS is applied to the power supply line 106 .

Here, the first transistor 101 has a function of supplying current to the light emitting element 108 .
In addition, the second transistor functions as a switch that puts the first transistor 101 in a diode-connected state.

Note that in this specification, diode connection refers to a state in which a gate electrode of a transistor is connected to a first or second electrode.

In the pixel circuit shown in FIG. 1, turning on the second transistor 102 puts the first transistor 101 in a diode-connected state, causing a current to flow through the storage capacitor 103.
The holding capacitor 103 is charged. When the storage capacitor 103 is charged, the voltage held in the storage capacitor ₁₀₃ is the difference V _data −| between the video signal voltage V _data , the threshold voltage |V _th | This continues _until V _th | _{−V CL} is _reached .

Through the above operation, a voltage based on the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 101 can be held in the storage capacitor 103 .

FIG. 2 shows a circuit configuration for obtaining the threshold voltage of the first transistor when the first transistor is an N-channel transistor.

FIG. 2 shows first and second transistors 201 and 202, a storage capacitor 203, a scanning line 204,
It is composed of a signal line 205 , a power line 206 , a capacitor line 207 and a light emitting element 208 .

Note that the second transistor 202 is an N-channel transistor in FIG.

A video signal voltage V _data is applied to the signal line 205 and a potential V _CL is applied to the capacitor line 207 . Note that the magnitude relationship between the potentials is V _CL >V _data . A power supply potential VDD is applied to the power supply line 206 .

In the pixel circuit shown in FIG. 2, turning on the second transistor 202 puts the first transistor 201 in a diode-connected state, causing a current to flow through the storage capacitor 203.
The holding capacitor 203 is charged. When the storage capacitor 203 is charged, the voltage stored in the storage capacitor 203 is the potential V _CL of the capacitor line 207 , the video signal voltage V _data , and the first transistor 20 .
It continues until the difference V _{CL −V data} −|V _th | with the threshold voltage |V _th | of 1 is _{reached .} The transistor 201 is turned off, and no current flows through the storage capacitor 203 .

Through the above operation, a voltage based on the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 101 can be held in the storage capacitor 203 .

Note that in FIGS. 1 and 2, the second transistor functions as a switch that puts the first transistor in a diode-connected state. Therefore, another element having a function as a switch may be used instead of the second transistor. For example, it may be a diode (for example, a PN diode, a PIN diode, a Schottky diode, a diode-connected transistor, etc.), a thyristor, or a logic circuit combining them.

Next, the pixel configuration of this embodiment having the basic circuit configuration shown in FIG. 1 or 2 will be described. Note that an EL element will be described as an example of a light emitting element.

FIG. 3 is a diagram showing a circuit diagram of the pixel circuit of this embodiment. The pixel circuit of this embodiment includes the first
to fifth transistors 301 to 305, holding capacitor 306, signal line 307, first to fourth scanning lines 308 to 311, first and second power supply lines 312 and 313, capacity line 314, light emitting element 3
15, etc.

Here, the first transistor 301 is used as a transistor that supplies current to the light emitting element 316, and the second to fifth transistors 302 to 305 are used as switches for selecting whether to connect wiring.

The gate electrode of the first transistor 301 is the second electrode of the fourth transistor 304,
and a first electrode of the storage capacitor 306 , and the first electrode is connected to the second transistor 302 .
and the second electrode of the third transistor 303, and the second electrode is connected to
It is connected to the first electrode of the fourth transistor 304 and the first electrode of the fifth transistor 305 . The second transistor 302 has a gate electrode connected to the first scan line 308 and a first electrode connected to the signal line 307 . The third transistor 303 is
A gate electrode is connected to a second scanning line 309 and a first electrode is connected to a first power supply line 312 . A gate electrode of the fourth transistor 304 is connected to the third scan line 310 . The fifth transistor 305 has a gate electrode connected to the fourth scan line 311 and a second electrode connected to the first electrode of the light emitting element 315 . The holding capacity 306 is
A second electrode is connected to the capacitance line 314 . In the light emitting element 315, the second electrode is the second electrode.
is connected to the power supply line 313 of the

A power supply potential VDD is applied to the first power supply line 312, and a power supply potential VDD is applied to the second power supply line 313.
A power supply potential VSS is applied, and a potential _VCL is applied to the capacitor line 314 . Note that the magnitude relationship between the potentials is VDD>VSS and VDD> _VCL .

Note that in the pixel circuit shown in FIG. 3, the first to fifth transistors 301 to 305 are all P-channel type.

Note that the first transistor 301 in FIG. 3 corresponds to the first transistor 10 in FIG.
1. Also, the fourth transistor 304 in FIG. 3 corresponds to the second transistor 102 in FIG. Also, the second power line 313 in FIG. 3 corresponds to the power line 106 in FIG.

Next, the operation of the pixel circuit of this embodiment will be described with reference to FIGS. 4 to 7. FIG.

FIG. 4 shows a timing chart of video signal voltages and pulses input to the signal line 307 and the first to fourth scanning lines 308 to 311. In accordance with each operation of the pixel circuits shown in FIGS. It is divided into three periods of first to third periods T1 to T3.

5 to 7 are diagrams showing the connection state of the pixel circuit of this embodiment in each period.
In FIGS. 5 to 7, the portions shown by solid lines are conductive, and the portions shown by broken lines are not conductive.

First, the operation of the pixel circuit in the first period T1 is described with reference to FIG. FIG. 5 is a diagram showing the connection state of the pixel circuits in the first period T1. In the first period T1, the second to fourth scanning lines 309 to 311 are at L level, and the third to fifth transistors 303 to
305 turns on. Also, the first scanning line 308 becomes H level, and the second transistor 3
02 is turned off. As a result, the first transistor 301 is in a diode-connected state, and current flows through the light-emitting element 315 . As a result, the second electrode of the first transistor 301,
Also, the potential of the first electrode of the holding capacitor 306 drops, and a certain initial voltage is held in the holding capacitor 306 .

By the above operation, a certain initial voltage is held in the holding capacitor 306 in the first period T1.
This operation is referred to herein as initialization.

Next, operation of the pixel circuit in the second period T2 is described with reference to FIG. FIG. 6 is a diagram showing the connection state of the pixel circuits in the second period T2. In the second period T2, the first and third scanning lines 308 and 310 are at L level, and the second and fourth transistors 30
2, 304 turn on. Also, the second and fourth scanning lines 309 and 311 become H level,
The third and fifth transistors 303, 305 are turned off. A video signal voltage V _data is applied to the signal line 307 . As a result, the second electrode of the first transistor 301 is connected to the signal line 307, and the first transistor 301 is diode-connected, so that current flows through the holding capacitor 306 and the holding capacitor 306 is charged. be. Holding capacity 3
06, the voltage held in the holding capacitor 306 is the difference V _data between the video signal voltage V _data , the threshold voltage |V _th | of the first transistor 301 and the potential V _CL of the capacitor line 314 .
−|V _th |−V _CL , and the voltage held in the holding capacitor 306 becomes V _data −
When |V _th |−V _CL is reached, the first transistor 301 is turned off, and no current flows through the storage capacitor 306 .

By the above operation, the video signal voltage V _data is applied to the storage capacitor 306 in the second period T2.
and the voltage based on the threshold voltage |V _th | of the first transistor 301 is held.

Note that in order to hold a voltage based on the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 301 in the holding capacitor 306 in the second period T2, must be kept lower than the difference V _data −|V _th | between the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 301 . Therefore, by applying a current to the light emitting element 315 in the first period T1,
The potential of the second electrode of the first transistor 301 can be reliably made lower than V _data −|V _th |, and the threshold voltage can be reliably obtained.

Next, operation of the pixel circuit in the third period T3 is described with reference to FIG. FIG. 7 is a diagram showing the connection state of the pixel circuits in the third period T3. In the third period T3, the second and fourth scanning lines 309 and 311 are at L level, and the third and fifth transistors 30
3, 305 turn on. Also, the first and third scanning lines 308 and 310 become H level,
The second and fourth transistors 302, 304 are turned off. Accordingly, the second electrode of the first transistor 301 is connected to the first power supply line 312 . In addition, the gate electrode of the first transistor 301 is applied with the voltage V _data -|
Since the sum V _data −|V _th | of _th |−V _CL and the potential V _CL of the capacitor line 314 is added, the voltage between the gate and source of the first transistor 301 in the period T3 is V _gs (T3).
Then, V _gs (T3) is represented by the following equation (1).

Therefore, the current _IOLED flowing between the drain and source of the first transistor 301 is represented by the following equation (2). emits light.

However, β is a constant given by the mobility and size of the transistor, the capacity of the oxide film, and the like.

By the above operation, in the third period T3, the current _IOLED depending on the video signal voltage V _data is supplied to the light emitting element 315 to cause the light emitting element 315 to emit light.

Here, in the operation process of the pixel circuit shown in FIG.
The functions of 305 will be explained again.

The first transistor 301 has a function of supplying current to the light emitting element 315 in the third period T3.

The second transistor 302 functions as a switch that connects the first electrode of the first transistor 301 and the signal line 307 to input the video signal voltage V _data to the pixel in the second period T2.

The third transistor 303 is connected to the first transistor 30 during the first and third periods T1, T3.
In order to apply the potential of the first power supply line 312 to the first electrode of 1, the first transistor 3
01 and the first power supply line 312 as a switch.

The fourth transistor 304 connects the holding capacitor 306 to the first transistor 3 in the second period T2.
01 threshold voltage |V _th |
function as a switch that puts into a diode-connected state.

The fifth transistor 305 operates so that current flows through the light emitting element 315 in the first and third periods T1 and T3 and does not flow through the light emitting element 315 in the second period T2. In other words, it functions as a switch that connects the second electrode of the first transistor 301 and the first electrode of the light emitting element 315 in order to control current supply to the light emitting element 315 .

Through the operation process as described above, the current _IOLED is supplied to the light emitting element 315 and the light emitting element 3
15 can be caused to emit light with a brightness dependent on the current I _OLED . At this time, as shown in equation (2), the current I _OLED flowing through the light emitting element 315 is expressed in a form that does not depend on the threshold voltage |V _th | of the first transistor 301. Variation can be compensated for.

Note that a voltage based on the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 301 is held in the storage capacitor 306 in the second period T2, and In order to turn on the transistor 301 of 1, the range of the video signal voltage V _data is V _CL +|V _th |<V _data ≦VDD.

Note that the potential V _CL of the capacitor line 314 is the video signal voltage V _data and the potential of the first transistor 3
01 threshold _voltage |V _{th |} .
Note that in order to ensure that the storage capacitor 306 holds a voltage based on the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 301, the potential V _CL of the capacitor line 314 is Lower is better.

Although the first transistor 301 is of a P-channel type in the pixel circuit shown in FIG. 3, the first transistor may be of an N-channel type. Here, FIG. 8 shows a pixel configuration when the first transistor is an N-channel type.

FIG. 8 is a diagram showing a circuit diagram of the pixel circuit of this embodiment. The pixel circuit of this embodiment includes the first
to fifth transistors 801 to 805, holding capacitor 806, signal line 807, first to fourth scanning lines 808 to 811, first and second power supply lines 812 and 813, capacity line 814, light emitting element 8
It consists of 15

Note that in the pixel circuit of FIG. 8, the second to fifth transistors 802 to 805 are all N-channel type.

Here, the first transistor 801 is used as a transistor that supplies current to the light emitting element 815, and the second to fifth transistors 802 to 805 are used as switches that select whether or not to connect wiring.

The gate electrode of the first transistor 801 is the second electrode of the fourth transistor 804,
and a first electrode of the storage capacitor 806 , and the first electrode is connected to the second transistor 802 .
and the second electrode of the third transistor 803, the second electrode of
A first electrode of the fourth transistor 804 and a first electrode of the fifth transistor 805 are connected. The second transistor 802 has a gate electrode connected to the first scan line 808 and a first electrode connected to the signal line 807 . The third transistor 803 is
A gate electrode is connected to a second scanning line 809 and a first electrode is connected to a first power supply line 812 . A gate electrode of the fourth transistor 804 is connected to a third scan line 810 . The fifth transistor 805 has a gate electrode connected to the fourth scan line 811 and a second electrode connected to the second electrode of the light emitting element 815 . The holding capacity 806 is
A second electrode is connected to the capacitor line 814 . In the light-emitting element 815, the first electrode is the second electrode.
is connected to the power supply line 813 of the

A power supply potential VSS is applied to the first power supply line 812, and a second power supply line 813 is supplied with
A power supply potential VDD is applied, and a potential _VCL is applied to the capacitor line 814 . Note that the magnitude relationship between the potentials is VDD>VSS and V _CL >VSS.

Note that the first transistor 801 in FIG. 8 corresponds to the first transistor 20 in FIG.
1. Also, the fourth transistor 804 in FIG. 8 corresponds to the second transistor 202 in FIG. A second power line 813 in FIG. 8 corresponds to the power line 206 in FIG.

Next, the operation of the pixel circuit of this embodiment will be described with reference to FIG.

FIG. 9 shows a timing chart of video signal voltages and pulses input to the signal line 807 and the first to fourth scanning lines 808-811. Since the first to fifth transistors are all N-channel transistors, the timing of the pulses input to the first to fourth scanning lines 808 to 811 is different when all the transistors are P-channel transistors (see FIG. 4). ), the H level and L level are inverted. Further, in accordance with each operation of the pixel circuit, the first to third periods T1 to
It is divided into three periods of T3.

The operation of the pixel circuit in FIG. 8 during the first to third periods T1 to T3 is the same as the operation of the pixel circuit shown in FIG. That is, a certain initial voltage is held in the holding capacitor 806 in the first period T1. That is, initialization is performed. Next, in the second period T2, a voltage based on the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 801 is held in the holding capacitor 806 . Then, in the third period T3, the current _IOLED dependent on the video signal voltage _{V_data} is supplied to the light emitting element 815 to cause the light emitting element 815 to emit light. Note that the light emitting element 815
The current _IOLED flowing through is expressed by the following equation (3).

Note that in order to hold a voltage based on the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 801 in the holding capacitor 806 in the second period T2, must be kept higher than V _data + |V _th |, the sum of the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 801 . Therefore, by passing a current through the light emitting element 815 in the first period T1,
The potential of the second electrode of the first transistor 801 can be reliably set higher than V _data + |V _th |, and the threshold voltage can be reliably obtained and compensated.

Note that in the operation process of the pixel circuit shown in FIG.
05 have the same functions as the first to fifth transistors 301 to 305 in the pixel circuit shown in FIG.

Through the operation process as described above, the current _IOLED is supplied to the light emitting element 815, and the light emitting element 8
15 can be caused to emit light with a brightness dependent on the current I _OLED . At this time, as shown in equation (3), the current I _OLED flowing through the light emitting element 815 is expressed in a form that does not depend on the threshold voltage |V _th | of the first transistor 801. Variation can be compensated for.

Note that a voltage based on the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 801 is held in the storage capacitor 806 in the second period T2, and In order to turn on the transistor 801 of 1, the range of the video signal voltage V _data is VSS≦V _data <V _CL −|V _th |.

Note that the potential V _CL of the capacitor line 814 is the video signal voltage V _data and the potential of the first transistor 3
01 threshold voltage |V _th | and V _data + |V _th |
Note that in order to ensure that the storage capacitor 806 holds a voltage based on the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 801, the potential V _CL of the capacitor line 814 is Higher is better.

As described above, the pixel configuration of the present embodiment can compensate for variations in threshold voltage of transistors and reduce variations in luminance, thereby improving image quality.

In addition, in the pixel circuit of the present embodiment, as shown in formulas (2) and (3), the current _IOLED flowing through the light-emitting element is substantially constant when the magnitude of the video signal voltage _Vdata is determined. Become. Therefore, a constant current corresponding to the video signal voltage can be supplied to the light-emitting element, and the light-emitting element can emit light with a constant luminance, thereby reducing luminance unevenness during the light-emitting period (T3).

In addition, since the current _IOLED flowing through the light emitting element does not depend on the capacitance value of the storage capacitor, even if the capacitance value varies from pixel to pixel due to manufacturing errors such as misalignment of the mask pattern during manufacturing, It is possible to supply a constant current to the light emitting element.

In addition, in the pixel circuit of the present embodiment, the threshold voltage |V _th | of the first transistor and the video signal voltage V _data are obtained in the same period, so that the preparation period until the light emitting element emits light is reduced. can be made shorter, the light emission period can be made longer than one frame period. Therefore, the duty ratio (ratio of light emission period in one frame period) can be increased, and the voltage applied to the light emitting element can be reduced.
As a result, power consumption can be reduced, and deterioration of the light emitting element can be reduced.

In addition, since the preparation period until the light emitting element emits light can be shortened, the length of one frame period can be shortened, and the frame frequency can be increased.
As a result, pseudo contours and flickering can be suppressed in moving image display, etc., and image quality can be improved.

Note that in this embodiment, the first electrode of the first transistor is connected to the first power supply line through the third transistor when the initialization is performed in the period T1. The connection destination of the first electrode is not limited to this. the first electrode of the first transistor,
Initialization may be performed by connecting to the signal line through the second transistor and applying a potential to the signal line so that the first transistor is turned on.

Note that in this embodiment mode, the first electrode of the first transistor is connected to the first power supply line through the third transistor when current is supplied to the light emitting element in the period T3.
The connection destination of the first electrode of the transistor is not limited to this. A first electrode of the first transistor is connected to a signal line through the second transistor, and a potential is applied to the signal line so that the first transistor is turned on, thereby causing a current to flow through the light emitting element. may be supplied.

In addition, in this embodiment, the storage capacitor may be formed of a metal, or may be formed of a MOS transistor. In particular, when the storage capacitor is formed of a MOS transistor, the area occupied by the storage capacitor can be made smaller than when the storage capacitor is formed of metal, so the aperture ratio of the pixel can be increased.

For example, in the pixel circuit shown in FIG. 3, examples in which the storage capacitor is formed by a MOS transistor are shown in FIGS. 10 and 11. FIG.

FIG. 10 shows a case where the storage capacitor 306 is formed of a P-channel transistor. P.
When a storage capacitor is formed by a channel transistor, it is necessary to induce a channel region in the P-channel transistor in order to retain charge. It must be lower than the potential of the first and second electrodes of the transistor. By the way, in the case of the pixel circuit shown in FIG.
, the potential of the first electrode is higher than that of the second electrode. Therefore, in order for the P-channel transistor to function as a storage capacitor, the first and second electrodes of the P-channel transistor are used as the first electrode of the storage capacitor 306, and the gate electrode and the second electrode of the first transistor 301 are used. 4 is connected to the second electrode of the transistor 304 of No. 4. In addition, the gate electrode of the P-channel transistor is used as the second electrode of the storage capacitor 306 and connected to the capacitor line 314 .

FIG. 11 shows a case where the holding capacitor 306 is formed by an N-channel transistor. N.
When forming the storage capacitor with a channel transistor, it is necessary to induce a channel region in the N-channel transistor in order to hold charge. It must be higher than the potential of the first and second electrodes of the transistor. Therefore, in order for the N-channel transistor to function as a storage capacitor, the gate electrode of the N-channel transistor is connected to the first capacitor of the storage capacitor 306 .
and is connected to the gate electrode of the first transistor 301 and the second electrode of the fourth transistor 304 . Further, the first and second electrodes of the N-channel transistor are used as the second electrode of the storage capacitor 306 and connected to the capacitor line 314 .

As another example, in the pixel circuit shown in FIG. 8, the first and second storage capacitors are MOS
FIGS. 12 and 13 show examples of the case of forming with a transistor.

FIG. 12 shows a case where the storage capacitor 806 is formed by an N-channel transistor. In the case of the pixel circuit shown in FIG. 8, the potential of the second electrode in the storage capacitor 806 is higher than that of the first electrode. Therefore, in order for the N-channel transistor to function as a storage capacitor, the first and second electrodes of the N-channel transistor are used as the first electrode of the storage capacitor 806, and the gate electrode and the second electrode of the first transistor 801 are used. 4 of the transistors 804
electrode. In addition, the gate electrode of the N-channel transistor is used as the second electrode of the storage capacitor 806 and connected to the capacitor line 814 .

FIG. 13 shows the case where the storage capacitor 806 is formed of a P-channel transistor. P.
In order for the channel transistor to function as a storage capacitor, the gate electrode of the P-channel transistor is used as the first electrode of the storage capacitor 806, and the gate electrode of the first transistor 801 and the second electrode of the fourth transistor 804 are used. Connect with Further, the first and second electrodes of the P-channel transistor are used as the second electrode of the storage capacitor 806 and connected to the capacitor line 814 .

By connecting the storage capacitor between the gate electrode of the first transistor and the capacitor line as in the present embodiment, especially when the storage capacitor is formed of a MOS transistor, between the gate and source of the MOS transistor, Since a voltage higher than the threshold voltage of the MOS transistor is always applied, a channel region can always be induced in the MOS transistor, and the MOS transistor can always function as a storage capacitor. Therefore, it is possible to correctly hold a desired voltage in the holding capacitor during the operation process of the pixel circuit.

Further, in the pixel configuration of the present embodiment, among the values of the ratio W/L of the channel length L to the channel width W of each of the first to fifth transistors, the value of W/L of the first transistor is maximized, the current flowing between the drain and source of the first transistor can be increased. Therefore, when the voltage based on the video signal voltage V _data and the threshold voltage |V _th | of the first transistor is obtained in the period T2, the operation can be performed with a larger current, and thus the operation can be performed more quickly. become able to. In addition, the current _IOLED flowing through the light emitting element in the period T3 can be increased, and the luminance can be increased.

Note that in the present embodiment, the timings of the pulses input to the second scanning line and the fourth scanning line are the same. It may be controlled by any one of the four scanning lines.

For example, FIG. 14 shows an example in which the third and fifth transistors 303 and 305 are controlled by the second scanning line 309 in the pixel circuit shown in FIG. In addition, in FIG.
and a gate electrode of the fifth transistor 305 are connected to the second scan line 309 .

As another example, in the pixel circuit shown in FIG. 8, the third and fifth transistors 80
3, 805 is controlled by the fourth scanning line 811 is shown in FIG. In addition, Fig. 1
5 , the gate electrode of the third transistor 803 and the gate electrode of the fifth transistor 805 are connected to the fourth scan line 811 .

By controlling the third and fifth transistors with the same scanning line in this manner, the number of scanning lines can be reduced and the aperture ratio of the pixel can be increased.

In this embodiment, the second to fifth transistors are all of the same conductivity type, such as P-channel type or N-channel type, but the present invention is not limited to this. Both the P-channel type and the N-channel type may be used to configure the circuit.

For example, in FIG. 3, the fourth transistor 304 may be an N-channel type and the transistors other than the fourth transistor 304 may be P-channel types. This pixel circuit is shown in FIG. FIG. 17 shows a timing chart of video signal voltages and pulses input to the signal line 307 and the first to fourth scanning lines 308 to 311. FIG.

Thus, if the fourth transistor 304 is an N-channel type, the fourth transistor 3
04 is smaller than in the case of a P-channel transistor, the storage capacitor 3
06 leaks less, and the fluctuation of the voltage held in the holding capacitor 306 becomes smaller. Accordingly, a constant voltage is always applied to the gate electrode of the first transistor 301 particularly in the light emission period (T3), so that a constant current can be supplied to the light emitting element 315 . As a result, the light emitting element 315 can emit light with a constant luminance, and luminance unevenness can be reduced.

As another example, in FIG. 3, the second transistor 302 may be an N-channel type and the transistors other than the second transistor 302 may be P-channel types. This pixel circuit is shown in FIG. FIG. 19 shows a timing chart of video signal voltages and pulses input to the signal line 307 and the first to fourth scanning lines 308 to 311. FIG.

In this way, when the second transistor 302 is of the N-channel type, the timings of the pulses input to the first scanning line 308, the second scanning line 309, and the fourth scanning line 311 become the same. Second transistor 302, third transistor 303, and fifth transistor 3
05 can be controlled by any one of the first scan line 308 or the second scan line 309 or the fourth scan line 311 .

Here, the second transistor 302, the third transistor 303, and the fifth transistor 3
05 is controlled by the first scanning line 308 is shown in FIG. Note that the gate electrode of the second transistor 302, the gate electrode of the third transistor 303, and the gate electrode of the fifth transistor 305 are connected to the first scan line 308 in FIG.

In this way, by making the second transistor a conductive type different from that of the transistors other than the second transistor, the number of scanning lines can be reduced and the aperture ratio of the pixel can be increased.

Which of the second to fifth transistors has which conductivity type is not limited to the above description.

In addition, the present embodiment is an example of a case where the content (or part of it) described in another embodiment is embodied, an example of a slightly modified case, an example of a partially changed case, and an improved case. An example of the case,
An example of detailed description, an example of application, and an example of related parts are shown. Therefore, the contents described in other embodiments can be freely applied, combined, or replaced with this embodiment.

In the present embodiment, descriptions have been made using various diagrams, but the contents described in each diagram (
may be part of it) shall apply, combine, or
Alternatively, replacement can be freely performed. Furthermore, in the figures described so far, more figures can be configured by combining each part with another part.

Similarly, the content (may be part of) described in each drawing of this embodiment may be applied, combined, replaced, etc. with respect to the content (may be part of) described in the drawing of another embodiment. can be done freely. Furthermore, in the drawings of this embodiment, more drawings can be configured by combining each part with another embodiment.

(Embodiment 2)
Although the capacitive line is provided separately in the first embodiment, other existing wiring may be used instead of the capacitive line. For example, by using any one of the first to fourth scanning lines of pixels in another row as a substitute for the capacitance line, the capacitance line of the pixel can be deleted. In this embodiment, instead of the capacitance line of the pixel, first to
A case of using any one of the fourth scanning lines will be described. As the light emitting element, E
An L element will be described as an example.

For example, in the pixel circuit shown in FIG. 3, FIG. 21 shows an example of a pixel circuit in which the second scanning line of the pixel in the previous row is used instead of the capacitor line of the pixel.

FIG. 21 shows a configuration of a pixel Pixel(i) in a certain i-th row and a pixel Pixel(i-1) in the (i-1)-th row, which is the previous row. (i-1)th row pixel Pixel (i-1
) is composed of first to fifth transistors 2101 to 2105, a holding capacitor 2106, first to fourth scanning lines 2108 to 2111, a light emitting element 2115, and the like. Further, the i-th pixel Pixel(i) includes the first to fifth transistors 2121 to 2125 and the storage capacitor 21
26, first to fourth scanning lines 2128 to 2131, a light emitting element 2135, and the like. Further, the i-th pixel Pixel(i) and the (i-1)-th pixel Pixel(i-1)
The signal line 2107 and the first and second power supply lines 2112 and 2113 are shared by .

In FIG. 21, the connection of each element in each pixel is almost the same as the pixel circuit shown in FIG. 3, so detailed description is omitted. The difference between FIG. 3 and FIG. 21 is that the second scanning line 2109 of the (i−1)th row pixel Pixel(i−1) is used instead of the capacitance line of the ith row pixel Pixel(i).
is used, and the second electrode of the storage capacitor 2126 of the pixel Pixel(i) in the i-th row is connected to the second scanning line 2109 of the pixel Pixel(i-1) in the (i-1)th row. This is the point.

In addition, in the (i-1)th row pixel Pixel (i-1), the (i-1)th row pixel Pixel
Instead of the l(i-1) capacity line, the second scanning line 2149 of the (i-2)th row pixel Pixel(i-2) is used, and the (i-1)th row pixel Pixel( i-1) storage capacity 21
06 is the second scanning line 214 of the (i−2)th row pixel Pixel(i−2).
9 is connected.

Here, the signal line 2107 and the first to fourth pixels of the pixel Pixel (i−1) in the (i−1) row
2 is a timing chart of video signal voltages and pulses input to the scanning lines 2108 to 2111 of the i-th row pixel Pixel(i) and the first to fourth scanning lines 2128 to 2131 of the i-th row pixel Pixel(i).
2. Note that the periods T1 to T3 shown in FIG. 22 correspond to the operation of the i-th pixel Pixel(i).

With the pixel configuration as shown in FIG. 21, the storage capacitor 212 of the i-th pixel Pixel(i)
6, the second scanning line 210 of the (i-1)th row pixel Pixel (i-1)
The potential applied to 9 is applied. Therefore, the second electrode of the storage capacitor 2126 of the i-th pixel Pixel(i) is applied with an H level potential in the period T1, and is applied in the periods T2 and T3.
At , an L level potential is applied. As a result, in each period, the i-th pixel Pixel(i
) can be applied to the second electrode of the storage capacitor 2126, the pixel circuit can operate as described in Embodiment Mode 1. FIG.

Note that in FIG. 21, the same operation as described above can be performed by using the fourth scanning line of the pixel in the previous row instead of the capacitor line of the pixel. This is because the timings of pulses input to the second scanning line and the fourth scanning line of the (i−1)th row pixel Pixel(i−1) are the same.

Note that the scanning line used instead of the capacitor line of the pixel is the second scanning line of the pixels in the preceding row.
Alternatively, it is not limited to the fourth scanning line. Instead of the capacitance line of the pixel, the first or third scanning line of the pixels in the previous row may be used. Also, the first to
Any one of the fourth scan lines may be used.

Note that in the pixel, a constant potential is preferably applied to the capacitor line during the periods T2 and T3. Further, it is desirable that a low potential be applied to the capacitor line during the periods T2 and T3. In this way, the threshold voltage of the first transistor and the video signal voltage can be obtained more accurately, and the current flowing through the light-emitting element during the light-emitting period of the pixel can be kept constant. The device can be made to emit light with constant brightness. In view of the above, instead of the capacitance line of the pixel in question, the second or fourth capacitance line of the pixel in the preceding row can be
It is desirable to use .

As another example, in the pixel circuit shown in FIG. 8, FIG. 23 shows an example in which the second scanning line of the pixel in the previous row is used instead of the capacitor line of the pixel.

FIG. 23 shows the configuration of a certain i-th row pixel Pixel(i) and the (i-1)-th row pixel Pixel(i-1) which is the previous row. (i-1)th row pixel Pixel (i-1
) is composed of first to fifth transistors 2301 to 2305, a holding capacitor 2306, first to fourth scanning lines 2308 to 2311, a light emitting element 2315, and the like. Further, the i-th pixel Pixel(i) includes the first to fifth transistors 2321 to 2325 and the storage capacitor 23
26, first to fourth scanning lines 2328 to 2331, a light emitting element 2335, and the like. Further, the i-th pixel Pixel(i) and the (i-1)-th pixel Pixel(i-1)
The signal line 2307 and the first and second power supply lines 2312 and 2313 are shared by .

In FIG. 23, the connection of each element in each pixel is almost the same as the pixel circuit shown in FIG. 8, so detailed description is omitted. The difference between FIG. 8 and FIG. 23 is that the second scanning line 2309 of the (i−1)th row pixel Pixel(i−1) is used instead of the capacitance line of the ith row pixel Pixel(i).
is used, and the second electrode of the storage capacitor 2326 of the i-th pixel Pixel(i) is connected to the second scanning line 2309 of the (i-1)-th pixel Pixel(i-1). This is the point.

In addition, in the (i-1)th row pixel Pixel (i-1), the (i-1)th row pixel Pixel
Instead of the l(i-1) capacity line, the second scanning line 2349 of the (i-2)th row pixel Pixel(i-2) is used, and the (i-1)th row pixel Pixel( i-1) storage capacity 23
06 is the second scanning line 234 of the (i−2)th row pixel Pixel(i−2).
9 is connected.

Here, the first to fourth pixels of the signal line 2307 and the (i−1)th row pixel Pixel(i−1)
2 is a timing chart of video signal voltages and pulses input to the scanning lines 2308 to 2311 of the i-th row pixel Pixel(i) and the first to fourth scanning lines 2328 to 2331 of the i-th row pixel Pixel(i).
4. Note that the periods T1 to T3 shown in FIG. 24 correspond to the operation of the i-th pixel Pixel(i).

With the pixel configuration as shown in FIG. 23, the storage capacitor 232 of the i-th pixel Pixel(i)
6, the second scanning line 230 of the (i−1)th row pixel Pixel(i−1)
The potential applied to 9 is applied. Therefore, the second electrode of the storage capacitor 2326 of the i-th pixel Pixel(i) is applied with an L level potential in the period T1, and is applied in the periods T2 and T3.
At , an H level potential is applied. As a result, in each period, the i-th pixel Pixel(i
) can be applied to the second electrode of the storage capacitor 2326, the pixel circuit can operate as described in Embodiment Mode 1. FIG.

Note that in FIG. 23, the same operation as described above can be performed by using the fourth scanning line of the pixel in the previous row instead of the capacitor line of the pixel. This is because the timings of pulses input to the second scanning line and the fourth scanning line of the (i−1)th row pixel Pixel(i−1) are the same.

Note that the scanning line used instead of the capacitor line of the pixel is the second scanning line of the pixels in the previous row.
Alternatively, it is not limited to the fourth scanning line. Instead of the capacitance line of the pixel, the first or third scanning line of the pixels in the previous row may be used. Also, the first to
Any one of the fourth scan lines may be used.

Note that in the pixel, a constant potential is preferably applied to the capacitor line during the periods T2 and T3. Further, it is desirable that a high potential be applied to the capacitor line during the periods T2 and T3. In this way, the threshold voltage of the first transistor and the video signal voltage can be obtained more accurately, and the current flowing through the light-emitting element during the light-emitting period of the pixel can be kept constant. The device can be made to emit light with constant brightness. In view of the above, instead of the capacitance line of the pixel in question, the second or fourth capacitance line of the pixel in the preceding row can be
It is desirable to use .

In this way, by using the second scanning line of the pixel in the previous row instead of the capacitor line of the pixel, it is not necessary to provide a new capacitor line in the pixel, so that the number of wirings can be reduced. It is possible to increase the aperture ratio of the pixel. Moreover, since there is no need to generate a new voltage to be applied to the capacitor line, the circuit for that purpose can be reduced, and power consumption can also be reduced.

In addition, the present embodiment is an example of a case where the content (or part of it) described in another embodiment is embodied, an example of a slightly modified case, an example of a partially changed case, and an improved case. An example of the case,
An example of detailed description, an example of application, and an example of related parts are shown. Therefore, the contents described in other embodiments can be freely applied, combined, or replaced with this embodiment.

In the present embodiment, descriptions have been made using various diagrams, but the contents described in each diagram (
may be part of it) shall apply, combine, or
Alternatively, replacement can be freely performed. Furthermore, in the figures described so far, more figures can be configured by combining each part with another part.

Similarly, the content (may be part of) described in each drawing of this embodiment may be applied, combined, replaced, etc. with respect to the content (may be part of) described in the drawing of another embodiment. can be done freely. Furthermore, in the drawings of this embodiment, more drawings can be configured by combining each part with another embodiment.

(Embodiment 3)
In Embodiments 1 and 2, a current is passed through the light-emitting element for initialization. It is also possible to In this embodiment, a method of performing initialization using an initialization transistor will be described. Note that an EL element will be described as an example of a light emitting element.

For initialization, the second electrode of the first transistor needs to be set to some initial potential. At this time, the second electrode of the first transistor and the electrode of another element or another wiring are connected through an initialization transistor, and the initialization transistor is turned on to turn on the first transistor. The second electrode can be set to the potential of the connection destination electrode or wiring.

That is, the initialization transistor connects the second electrode of the first transistor and the electrode of another element or another wiring in order to set the potential of the second electrode of the first transistor to a certain initial potential. Acts as a switch to connect.

For example, in the case of the pixel circuit shown in FIG. 3, in order to hold a voltage based on the video signal voltage V _data and the threshold voltage |V _th | The potential of the second electrode of transistor 301 is the video signal voltage V _data and the first
must be lower than the difference V _data −|V _th | from the threshold voltage |V _th | Therefore, in the first period T1, the second transistor of the first transistor 301
and an electrode of another element or another wiring through an initialization transistor, the potential of the second electrode of the first transistor 301 is set to an initial value lower than V _data −|V _th | voltage can be set.

FIG. 25 shows an example in which an initialization transistor is provided in the pixel circuit shown in FIG. FIG. 25 shows an example in which the second electrode of the first transistor 301 and the capacitor line 314 are connected through an initialization transistor.

In FIG. 25, a sixth transistor 2516 as an initialization transistor and a fifth scanning line 2517 are newly added to the pixel circuit shown in FIG. Note that the sixth transistor 251
6 has a gate electrode connected to the fifth scan line 2517, and has first electrodes connected to the second electrode of the first transistor 301, the first electrode of the fourth transistor 304, and the fifth electrode. A first electrode of the transistor 305 is connected, and a second electrode is connected to the capacitor line 314 .

Next, the operation of the pixel circuit shown in FIG. 25 will be described with reference to FIGS. 26 and 27. FIG.

FIG. 26 shows a timing chart of video signal voltages and pulses input to the signal line 307 and the first to fifth scanning lines 308 to 311, 2517. divided into three periods.

Operation of the pixel circuit in the first period T1 is described with reference to FIG. In the period T1, the second, third and fifth scanning lines 309, 310 and 2517 are at L level, and the third and fourth scanning lines are at L level.
, the sixth transistors 303, 304, 2516 are turned on. Also, the first and fourth scanning lines 308 and 311 become H level, and the second and fifth transistors 302 and 305 are turned off. Accordingly, the second electrode of the first transistor 302 and the capacitor line 314 are connected to each other; The potential of the first electrode of 306 becomes equal to the potential V _CL of the capacitor line 314 .

Through the above operation, in the period T1, the potentials of the second electrode of the first transistor 301 and the first electrode of the storage capacitor 306 are set to the potential V _CL of the capacitor line 314 as initial potentials.

Thus, in the period T1, the potential of the second electrode of the first transistor 301 is changed to V _data
The potential of the second electrode of the first transistor 301 is ensured to be lower than V _data −|V _th | by setting the potential V _CL of the capacitor line 314 which is lower than −|V _th | Threshold voltage compensation can be reliably performed.

Note that in the periods T2 and T3, the fifth scan line 2517 is at H level and the sixth transistor 2516 is turned off. Then, the same operation as that of the pixel circuit shown in FIG. 3 is performed. That is, in the period T2, the storage capacitor 306 receives the video signal voltage V _data and the first transistor 3
01 threshold voltage |V _th |. Then, in the period T3, the light emitting element 315 is supplied with the current I _OLED that depends on the video signal voltage V _data , and the light emitting element 315
light up.

Note that in the sixth transistor ₂₅₁₆ , the second electrode of the first transistor 301 is Vd.
The connection may be made so that the potential is set to be lower than _ata −|V _th |. For example, FIG.
, the first electrode of the sixth transistor 2516 is connected to the first transistor 301
, the second electrode of the fourth transistor 304 , and the first electrode of the storage capacitor 306 .
may be connected to the electrodes of

Note that although the second electrode of the sixth transistor 2516 is connected to the capacitor line 314 in FIG. 25, the second electrode of the sixth transistor 2516 may be connected to an existing wiring other than the capacitor line. . In particular, any wiring to which a potential lower than V _data −|V _th | is applied in the period T1 may be used.

For example, the second electrode of the sixth transistor 2516 may be connected to the second scan line 309 as shown in FIG. In the period T1, since an L-level potential is applied to the second scan line 309, the potential of the second electrode of the first transistor 301 is V _data −|V _th |
can be set to a potential lower than

Note that the second electrode of the sixth transistor 2516 may be connected to the third scan line 310 because an L-level potential is also applied to the third scan line 310 in the period T1.

In addition, a new initialization line (power supply line for initialization) may be provided in order to set the second electrode of the first transistor 301 to a certain initial potential.

For example, FIG. 30 shows an example in which an initialization transistor and an initialization line are provided in the pixel circuit shown in FIG. In FIG. 30, a sixth transistor 2516, a fifth scanning line 2517, and an initialization line 3018, which are initialization transistors, are newly added to the pixel circuit shown in FIG.
Note that the sixth transistor 2516 has a gate electrode connected to the fifth scan line 2517 and a first electrode connected to the second electrode of the first transistor 301 and the fourth transistor 30 .
4 and the first electrode of the fifth transistor 305 , and the second electrode is connected to the initialization line 3018 .

An initialization potential V _ini is applied to the initialization line 3018 . Note that the magnitude relationship between the potentials is V _ini <V _data −|V _th |.

FIG. 31 shows the operation of the pixel circuit shown in FIG. 30 in the first period T1. In the period T1, the first transistor 301 is diode-connected and current flows through the initialization line 3018 . As a result, the potentials of the second electrode of the first transistor 301 and the first electrode of the storage capacitor 306 become equal to the potential of the initialization line 3018, and the storage capacitor 306 is supplied with the initialization potential _Vin .
The difference V _ini −V _CL between _i and the potential V _CL of the capacitor line 314 is held.

By the above operation, in the period T1, the initialization line 3018 is applied as the initial voltage to the storage capacitor 306.
The difference V _ini −V _CL between the potential V _ini of the capacitor line 314 and the potential V _CL of the capacitor line 314 is held.

Thus, by providing the initialization line 3018 and setting the potential of the second electrode of the first transistor 301 to the initialization potential V _ini which is lower than V _data −|V _th | The potential of the second electrode of the transistor 301 of 1 can be reliably made lower than V _data −|V _th |, and threshold voltage compensation can be reliably performed.

In particular, by newly providing an initialization line, the initialization potential V _ini is set to V _data −|V _th
|, the second potential of the first transistor 301 can be set to any potential lower than |
can be made lower than V _data −|V _th | more reliably, and threshold voltage compensation can be performed more reliably.

Note that the sixth transistor 2516 may be connected so that the second electrode of the first transistor 301 is set to the initialization potential V _ini . For example, as shown in FIG.
A first electrode of the transistor 2516 may be connected to the gate electrode of the first transistor 301 , the second electrode of the fourth transistor 304 , and the first electrode of the storage capacitor 306 .

In this way, by newly adding an initialization transistor and an initialization line and performing initialization, acquisition and compensation of the threshold voltage of the first transistor can be performed more reliably.

In addition, in the initialization method described in Embodiment 1, current flows through the light-emitting element during initialization, so that the light-emitting element emits light in the period T1. In this method, since current does not flow through the light emitting element during initialization, the light emitting element does not emit light during the period T1, and light emission from the light emitting element can be suppressed during periods other than the light emitting period.

Note that in the present embodiment, the sixth transistor, which is the initialization transistor, is of the P-channel type, but the present invention is not limited to this. It may be of N-channel type.

Note that in the present embodiment, the fifth scanning line is used to control the sixth transistor, but other existing wiring of pixels in other rows may be used instead of the fifth scanning line. In particular, it is desirable to use a wiring to which a voltage that turns on the sixth transistor is applied during the period T1 for initialization. For example, if the sixth transistor is of P-channel type, the fifth transistor of the pixel is
The first scanning line of pixels in the previous row may be used instead of the scanning line of the previous row. Further, when the sixth transistor is an N-channel transistor, the second scanning line of the pixel in the previous row may be used instead of the fifth scanning line of the pixel. In this way, by using the existing wiring instead of the fifth scanning line, there is no need to newly provide the fifth scanning line for the pixel, so the number of wirings can be reduced, and the aperture ratio of the pixel can be reduced. can be raised.

In this embodiment, only the example in which the first transistor is of the P-channel type (FIG. 3) has been described. , the first transistor is of N-channel type.

Note that when an initialization transistor is added to the pixel circuit shown in FIG. 8, the potential of the second electrode of the first transistor 801 is the video signal voltage V _data and
and the threshold voltage |V _th | of V _data + |V _th |. Further, when adding an initialization line, the potential V _ini applied to the initialization line is V _da
A potential higher than _ta + |V _th | is set.

In addition, the present embodiment is an example of a case where the content (or part of it) described in another embodiment is embodied, an example of a slightly modified case, an example of a partially changed case, and an improved case. An example of the case,
An example of detailed description, an example of application, and an example of related parts are shown. Therefore, the contents described in other embodiments can be freely applied, combined, or replaced with this embodiment.

In the present embodiment, descriptions have been made using various diagrams, but the contents described in each diagram (
may be part of it) shall apply, combine, or
Alternatively, replacement can be freely performed. Furthermore, in the figures described so far, more figures can be configured by combining each part with another part.

Similarly, the content (may be part of) described in each drawing of this embodiment may be applied, combined, replaced, etc. with respect to the content (may be part of) described in the drawing of another embodiment. can be done freely. Furthermore, in the drawings of this embodiment, more drawings can be configured by combining each part with another embodiment.

(Embodiment 4)
In Embodiments 1 to 3, the potential of the second power supply line is a fixed potential.
The potential of the second power supply line may be changed according to the fourth period. In this embodiment, the first to fourth
A case in which the potential of the second power supply line is changed according to the period of . Note that an EL element will be described as an example of a light emitting element.

For example, in the pixel circuit shown in FIG. 3, during the second period T2, the fifth transistor 30
5 is turned off, current does not flow to the light emitting element 315. For example, the fifth transistor 305 is removed and the second electrode of the first transistor 301 and the second electrode of the light emitting element 315 are connected. 1 electrode, and the potential of the second power supply line 313 is made higher than the potential of the first electrode of the light emitting element 315 in the second period T2, so that current does not flow to the light emitting element 315. can do. This is because the potential of the second power supply line 313 is
This is because a reverse bias is applied to the light emitting element 315 by making the potential higher than the potential of the first electrode of . Examples of this case are shown in FIGS.

33, the second electrode of the first transistor 301 is directly connected to the first electrode of the light emitting element 316 in contrast to the pixel circuit shown in FIG. 34 shows a timing chart of video signal voltages and pulses input to the signal line 307, the first to third scanning lines 308 to 310, and the second power supply line 313. FIG. Note that the first to third scanning lines 308 to 310
is the same as that of the pixel circuit shown in FIG.

In the second period T2, the potential of the second power supply line 313 is set to be equal to or more than the difference V _data −|V _th | between the video signal voltage V _data and the threshold voltage |V _th | , a reverse bias can be applied to the light emitting element 315 . This gives the period T
2, it is possible to stop the current from flowing through the light emitting element 315 .

In addition, in the first and third periods T1 and T3, the potential of the second power supply line 313 is the difference V _data −|V between the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 301 .
_th | Accordingly, current can flow through the light emitting element 315 in the periods T1 and T3.

Note that the initialization method using the initialization transistor described in Embodiment Mode 3 may be used as an initialization method. An example of this case is shown in FIG.

In the pixel circuit shown in FIG. 35, the fifth transistor 305 and the fourth scanning line 311 are removed from the diagram (FIG. 25) showing an example of initialization using the initialization transistor, and the first The second electrode of the transistor 301 and the first electrode of the light emitting element 315 are connected. In this case, by setting the potential of the second power supply line 313 higher than the potential of the second electrode of the first transistor 301 in the period T1, initialization can be performed without current flowing through the light emitting element 315. It becomes possible.

Further, as an initialization method, a method of performing initialization using an initialization transistor and an initialization line, which is described in Embodiment Mode 3, may be used. An example of this case is shown in FIG.

In the pixel circuit shown in FIG. 36, the fifth transistor 305 and the fourth scanning line 31 in the diagram (FIG. 30) showing an example of the case of performing initialization using the initialization transistor and the initialization line.
1 is removed, and the second electrode of the first transistor 301 and the first electrode of the light emitting element 315 are connected. In this case, the potential of the second power supply line 313 is changed to the initialization potential V _in during the period T1.
By setting it to _i or more, initialization can be performed without applying a current to the light emitting element 315 .

In this embodiment, only the example in which the first transistor is of the P-channel type (FIG. 3) has been described. , the first transistor is of N-channel type.

In the pixel circuit shown in FIG. 8, when changing the potential of the second power supply line 813 according to the period,
By making the potential of the second power supply line 813 lower than the potential of the second electrode of the light emitting element 815 in the period T2, a reverse bias can be applied to the light emitting element 815 . Accordingly, current can be stopped from flowing to the light emitting element 815 in the period T2.

Note that in the period T2, the potential of the second power supply line 813 is set to V _data + |V _th | which is the sum of the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 801 or less. The above operations can be performed.

In addition, in the first and third periods T1 and T3, the potential of the second power supply line 813 is the sum of the video signal voltage V _data and the threshold voltage |V _th | of the first transistor 801, V _data + |V.
By making it higher than _th |, the light emitting element 815 can be forward biased. Thus, current can flow through the light-emitting element 815 in the periods T1 and T3.

Note that the initialization method using the initialization transistor described in Embodiment Mode 3 may be used as an initialization method. In this case, the potential of the second power supply line 813 is set lower than the potential of the second electrode of the first transistor 801 in the period T1, so that the light emitting element 815
can be initialized without applying current to the

Further, as an initialization method, a method of performing initialization using an initialization transistor and an initialization line, which is described in Embodiment Mode 3, may be used. In this case, during the period T1, the second power supply line 813
is set to be equal to or lower than the initialization potential V _ini , initialization can be performed without applying current to the light emitting element 815 .

Thus, by changing the potential of the second power supply line depending on the period, the light emission period (T3
), the light emission of the light emitting element can be suppressed during the period other than the light emitting period. Further, since it is not necessary to provide the fifth transistor and the fourth scan line, the aperture ratio of the pixel can be increased. In addition, since the number of scanning line driver circuits can be reduced, power consumption can be reduced.

In addition, a reverse bias can be applied to the light emitting element by changing the potential of the second power supply line depending on the period. In particular, when the light-emitting element is an EL element, by applying a reverse bias, the deterioration state of the EL element can be improved, the reliability can be improved, and the life can be extended.

It should be noted that the pixel configuration of the present invention may be applied to a pixel configuration for performing the area coverage modulation method. That is, in a pixel configuration in which one pixel is divided into a plurality of sub-pixels, the pixel configuration of the present invention may be applied to each sub-pixel. As a result, it is possible to reduce the variation in brightness for each sub-pixel, and it is possible to display high-quality images with multiple gradations.

In addition, the present embodiment is an example of a case where the content (or part of it) described in another embodiment is embodied, an example of a slightly modified case, an example of a partially changed case, and an improved case. An example of the case,
An example of detailed description, an example of application, and an example of related parts are shown. Therefore, the contents described in other embodiments can be freely applied, combined, or replaced with this embodiment.

In the present embodiment, descriptions have been made using various diagrams, but the contents described in each diagram (
may be part of it) shall apply, combine, or
Alternatively, replacement can be freely performed. Furthermore, in the figures described so far, more figures can be configured by combining each part with another part.

Similarly, the content (may be part of) described in each drawing of this embodiment may be applied, combined, replaced, etc. with respect to the content (may be part of) described in the drawing of another embodiment. can be done freely. Furthermore, in the drawings of this embodiment, more drawings can be configured by combining each part with another embodiment.

(Embodiment 5)
In this embodiment, the layout of pixels in the display device of the present invention will be described. for example,
FIG. 37 shows a layout diagram of the pixel circuit shown in FIG. Note that the numbers attached to FIG. 37 match the numbers attached to FIG. Note that the layout diagram is not limited to FIG.

The pixel circuit shown in FIG. 3 includes first to fifth transistors 301 to 305, a storage capacitor 306,
signal line 307, first to fourth scanning lines 308 to 311, first and second power supply lines 312, 31
3. It is composed of a capacitor line 314 and a light emitting element 315 .

The first to fourth scanning lines 308 to 311 are formed by the first wiring, the signal line 307, the first
Also, the second power supply lines 312 and 313 and the capacitor line 314 are formed by the second wiring.

In the case of the top-gate structure, films are formed in the order of substrate, semiconductor layer, gate insulating film, first wiring, interlayer insulating film, and second wiring. In the case of the bottom gate structure, films are formed in the order of substrate, first wiring, gate insulating film, semiconductor layer, interlayer insulating film, and second wiring.

In the pixel configuration of this embodiment, among the values of the ratio W/L between the channel length L and the channel width W of each of the first to fifth transistors, the value of W/L of the first transistor is is maximized, a larger current can flow between the drain and source of the first transistor. Therefore, when the voltage based on the video signal voltage V _data and the threshold voltage |V _th | of the first transistor is obtained in the period T2, the operation can be performed with a larger current, and thus the operation can be performed more quickly. become able to. In addition, the current _IOLED flowing through the light emitting element in the period T3 can be increased, and the luminance can be increased. Therefore, in order to maximize the value of W/L of the first transistor, in FIG. I have to.

Note that although the first to fifth transistors 301 to 305 are described as having a single gate structure in this embodiment, the present invention is not limited to this. The structure of the first through fifth transistors 301-305 can take various forms. For example, a multi-gate structure having two or more gate electrodes may be used. When the multi-gate structure is used, the channel regions are connected in series, so that a plurality of transistors are connected in series. By using a multi-gate structure, the off-current is reduced, the breakdown voltage of the transistor is improved, and the reliability is improved. A flat characteristic can be obtained because the current does not change much. Alternatively, a structure in which gate electrodes are arranged above and below the channel may be used. The structure in which the gate electrodes are arranged above and below the channel increases the channel region, so that the current value can be increased, and a depletion layer can be easily formed, making it possible to reduce the S coefficient (subthreshold coefficient). . When the gate electrodes are arranged above and below the channel, the configuration is such that a plurality of transistors are connected in parallel. Further, a structure in which a gate electrode is arranged above a channel, a structure in which a gate electrode is arranged below a channel, a staggered structure, or a staggered structure may be used. , the channel region may be divided into a plurality of regions, may be connected in parallel, or may be connected in series. A source electrode or a drain electrode may overlap with the channel (or part thereof). A structure in which a source electrode or a drain electrode overlaps with a channel (or part of it) can prevent electric charges from accumulating in part of the channel, resulting in unstable operation. Also, L
There may be a DD area. By providing the LDD region, the off-state current can be reduced, the breakdown voltage of the transistor can be improved to improve reliability, and when operating in the saturation region, the drain and
Even if the voltage between the sources changes, the current between the drain and the source does not change so much, and flat characteristics can be obtained.

Wiring, electrodes, conductive layers, conductive films, terminals, vias, plugs, etc. are made of aluminum (Al).
, tantalum (Ta), titanium (Ti), molybdenum (Mo), tungsten (W), neodymium (Nd), chromium (Cr), nickel (Ni), platinum (Pt), gold (Au), silver (
Ag), copper (Cu), magnesium (Mg), scandium (Sc), cobalt (Co), zinc (Zn), niobium (Nb), silicon (Si), phosphorus (P
), boron (B), arsenic (As), gallium (Ga), indium (In), tin (
Sn), one or more elements selected from the group consisting of oxygen (O), or compounds, alloy materials (e.g., indium tin oxide (ITO), indium zinc oxide (IZO), indium tin oxide containing silicon oxide (ITSO), zinc oxide (ZnO), tin oxide (SnO), cadmium tin oxide (
CTO), aluminum neodymium (Al—Nd), magnesium silver (Mg—Ag), molybdenum niobium (Mo—Nb), etc.). Alternatively, wirings, electrodes, conductive layers, conductive films, terminals, and the like are preferably formed using a material obtained by combining these compounds. Alternatively, a compound (silicide) of one or more elements selected from the group and silicon (for example, aluminum silicon, molybdenum silicon, nickel silicide, etc.), or a compound (silicide) of one or more elements selected from the group and nitrogen It is preferably formed of a compound (eg, titanium nitride, tantalum nitride, molybdenum nitride, etc.).

Silicon (Si) contains n-type impurities (such as phosphorus) or p-type impurities (such as boron).
may contain Impurities in silicon improve its conductivity and allow it to behave like a normal conductor. Therefore, it becomes easy to use as a wiring, an electrode, and the like.

As silicon, silicon having various crystallinities such as single crystal, polycrystal (polysilicon), and microcrystal (microcrystal silicon) can be used. Alternatively, non-crystalline silicon such as amorphous silicon can be used as the silicon. By using single crystal silicon or polycrystalline silicon, the resistance of wirings, electrodes, conductive layers, conductive films, terminals, and the like can be reduced. By using amorphous silicon or microcrystalline silicon, wiring or the like can be formed through a simple process.

Note that aluminum or silver has high conductivity, so that signal delay can be reduced.
Furthermore, since it is easy to etch, patterning is easy and fine processing can be performed.

Note that since copper has high conductivity, signal delay can be reduced. When using copper,
In order to improve adhesion, it is desirable to have a laminated structure.

Note that molybdenum or titanium is desirable because it does not cause defects even when in contact with an oxide semiconductor (ITO, IZO, or the like) or silicon, is easy to etch, and has high heat resistance.

Tungsten is desirable because it has advantages such as high heat resistance.

Neodymium is desirable because it has advantages such as high heat resistance. In particular, the use of an alloy of neodymium and aluminum improves the heat resistance and prevents aluminum from forming hillocks.

Note that silicon is desirable because it can be formed at the same time as a semiconductor layer included in a transistor and has high heat resistance.

Note that ITO, IZO, ITSO, zinc oxide (ZnO), silicon (Si), tin oxide (S
nO) and cadmium tin oxide (CTO) have translucency and can be used for a portion through which light is transmitted. For example, it can be used as a pixel electrode or a common electrode.

Note that IZO is desirable because it is easily etched and processed. When IZO is etched, it is less likely that a residue will remain. Therefore, if IZO is used as the pixel electrode, it is possible to reduce the occurrence of defects (short circuit, alignment disorder, etc.) in the liquid crystal element and the light emitting element.

Wirings, electrodes, conductive layers, conductive films, terminals, vias, plugs, and the like may have a single-layer structure,
It may have a multilayer structure. By using a single-layer structure, the manufacturing steps of wirings, electrodes, conductive layers, conductive films, terminals, etc. can be simplified, the number of process days can be reduced, and the cost can be reduced. Alternatively, by forming a multi-layer structure, it is possible to reduce the demerits of each material while taking advantage of the merits of each material, thereby forming wirings, electrodes, and the like with good performance.
For example, by including a low-resistance material (aluminum, etc.) in the multilayer structure, it is possible to reduce the resistance of the wiring. Also, by forming a laminated structure in which a low heat-resistant material is sandwiched between high heat-resistant materials, the heat resistance of wiring, electrodes, and the like can be increased while taking advantage of the merits of the low heat-resistant material. For example, it is desirable to have a stacked structure in which a layer containing aluminum is sandwiched between layers containing molybdenum, titanium, neodymium, or the like.

Moreover, when wiring, electrodes, etc. are in direct contact with each other, they may adversely affect each other. For example, one wiring, electrode, etc., enters the other wiring, electrode, etc., into the material of the other, changing its properties and making it impossible to achieve its original purpose. As another example, when forming or manufacturing high resistance portions, problems may arise that prevent successful manufacturing. In such a case, it is preferable to sandwich or cover a material that reacts readily with a layered structure with a material that does not react easily. For example, when connecting ITO and aluminum, it is desirable to sandwich titanium, molybdenum, or neodymium alloy between ITO and aluminum. When connecting silicon and aluminum, titanium, molybdenum,
It is desirable to sandwich a neodymium alloy.

Note that the wiring refers to an arrangement in which a conductor is arranged. It may extend linearly, or may be arranged short without extending. Therefore, the electrodes are included in the wiring.

Note that carbon nanotubes may be used as wirings, electrodes, conductive layers, conductive films, terminals, vias, plugs, and the like. Furthermore, since carbon nanotubes are translucent, they can be used for light-transmitting portions. For example, it can be used as a pixel electrode or a common electrode.

In addition, the present embodiment is an example of a case where the content (or part of it) described in another embodiment is embodied, an example of a slightly modified case, an example of a partially changed case, and an improved case. An example of the case,
An example of detailed description, an example of application, and an example of related parts are shown. Therefore, the contents described in other embodiments can be freely applied, combined, or replaced with this embodiment.

In the present embodiment, descriptions have been made using various diagrams, but the contents described in each diagram (
may be part of it) shall apply, combine, or
Alternatively, replacement can be freely performed. Furthermore, in the figures described so far, more figures can be configured by combining each part with another part.

Similarly, the content (may be part of) described in each drawing of this embodiment may be applied, combined, replaced, etc. with respect to the content (may be part of) described in the drawing of another embodiment. can be done freely. Furthermore, in the drawings of this embodiment, more drawings can be configured by combining each part with another embodiment.

(Embodiment 6)
In this embodiment, configurations and operations of a signal line driver circuit, a scanning line driver circuit, and the like in a display device will be described.

First, as a pixel configuration, a case of using a pixel configuration in which operation is controlled using a signal line and first to fourth scanning lines as shown in FIGS. 3 and 8 will be described. Here, a case where the pixel configuration shown in FIG. 3 is used as the pixel configuration will be described as an example. FIG. 38 shows a configuration example of a display device in this case.

The display device shown in FIG. 38 includes a pixel portion 3801, first to fourth scanning line driver circuits 3802 to
805, has a signal line driver circuit 3806, the first scanning line driver circuit 3802 and the first scanning line 308 are connected, the second scanning line driver circuit 3803 and the second scanning line 309 are connected. The third scanning line driver circuit 3804 and the third scanning line 310 are connected, the fourth scanning line driver circuit 3805 and the fourth scanning line 311 are connected, and the signal line driver circuit 3806 and the signal line are connected. line 307 is connected. The reference numerals attached to the first to fourth scanning lines and signal lines are the same as those shown in FIG.
corresponds to the sign attached to .

First, the scanning line driving circuit will be described. The first scanning line driver circuit 3802 is a circuit for sequentially outputting selection signals to the first scanning lines 308 . Second to fourth scanning line driving circuits 3
The same is true for 803-3805. Accordingly, a selection signal is written to the pixel portion 3801 .

FIG. 39 shows a configuration example of the first to fourth scanning line driving circuits 3802 to 3805. In FIG. first
The to fourth scanning line driving circuits 3802 to 3805 mainly have a shift register 3901, an amplifier circuit 3902, and the like.

Next, operations of the first to fourth scanning line driving circuits 3802 to 3805 shown in FIG. 39 will be briefly described. A clock signal (G-CLK), a start pulse (
G-SP) and an inverted clock signal (G-CLKB) are input, and sampling pulses are sequentially output according to the timing of these signals. The output sampling pulse is amplified by the amplifier circuit 3902 and input from each scanning line to the pixel section (X54)01.

Note that the amplifier circuit 3902 may have a buffer circuit or a level shifter circuit. In addition, the scanning line driver circuit includes a shift register 3901 and an amplifier circuit 39.
02, a pulse width control circuit or the like may be arranged.

Next, the signal line driving circuit will be described. A signal line driver circuit 3806 is a circuit for sequentially outputting video signals to the signal lines 307 connected to the pixel portion. Signal line driver circuit 3806
A video signal output from is input to the pixel portion 3801 . The pixel portion 3801 displays an image by controlling the light emission state of the pixels according to the video signal.

Here, FIG. 40 shows a configuration example of the signal line driver circuit 3806 . FIG. 40A shows an example of a signal line driver circuit 3806 in the case of supplying signals to pixels by line-sequential driving. The signal line driver circuit 3806 in this case mainly includes the shift register 4001 and the first latch circuit 4002.
, a second latch circuit 4003, an amplifier circuit 4004, and the like. Note that the amplifier circuit 40
04 may have a buffer circuit, a level shifter circuit, a circuit having a function of converting a digital signal into an analog signal, or a function of performing gamma correction. You may have a circuit with

Next, operation of the signal line driver circuit 3806 shown in FIG. 40A is briefly described. A clock signal (S-CLK), a start pulse (S-SP), and an inverted clock signal (S-CLKB) are input to the shift register 4001, and sampling pulses are sequentially output according to the timing of these signals.

A sampling pulse output from the shift register 4001 is transferred to the first latch circuit 400
2. A video signal is input to the first latch circuit 4002 from the video signal line at a voltage V _data , and the video signal is held in each column according to the timing at which the sampling pulse is input.

In the first latch circuit 4002, when the holding of the video signal is completed up to the last column, the latch signal is input from the latch control line during the horizontal blanking period, and the video signal held in the first latch circuit 4002 is , are transferred to the second latch circuit (X56) 03 all at once. After that, the video signal held in the second latch circuit 4003 is simultaneously applied to the amplifier circuit 400 for one row.
4 is input. Then, the amplitude of the video signal voltage V _data is amplified by the amplifier circuit 4004, and the video signal is input to the pixel portion 3801 from each signal line.

While the video signal held in the second latch circuit 4003 is input to the amplifier circuit 4004 and input to the pixel portion 3801, the shift register 4001 outputs sampling pulses again. That is, two operations are performed at the same time. This enables line-sequential driving. After that, this operation is repeated.

Note that signals may be supplied to pixels by dot-sequential driving. Signal line drive circuit 380 in that case
6 is shown in FIG. 40(B). The signal line driver circuit 3806 in this case has a shift register 4001, a sampling circuit 4005, and the like. From the shift register 4001,
A sampling pulse is output to sampling circuit 4005 . A video signal with voltage V _data is input to the sampling circuit 4005 from a video signal line, and the video signal is sequentially output to the pixel portion 3801 according to the sampling pulse. This enables dot sequential driving.

Note that the signal line driver circuit and part thereof (such as a current source circuit and an amplifier circuit) are not on the same substrate as the pixel portion 3801, and may be configured using an external IC chip, for example.

The pixel circuit of the present invention can be driven by using the scanning line driver circuit and the signal line driver circuit as described above.

Note that, for example, in the pixel circuits shown in FIGS. 3 and 8, mutually inverted selection signals are input to the first and second scanning lines. Therefore, one of the first and second scanning line driving circuits is used to control the selection signal input to one of the first and second scanning lines, and the other scanning line is supplied with the corresponding signal. An inverted signal may be input. FIG. 41 shows a configuration example of the display device in this case.
shown in

The display device shown in FIG. 41 includes a pixel portion 3801, first, third and fourth scanning line driver circuits 380
2, 3804, 3805, a signal line drive circuit 3806, and an inverter 3807,
The first scanning line driving circuit 3802 and the first scanning line 308 are connected, and the second scanning line 309
is connected to the first scanning line driver circuit 3802 via an inverter 3807 . Connections of other scanning line driving circuits and signal line driving circuits are the same as those of the display device shown in FIG. 38, and thus description thereof is omitted here. The reference numerals attached to the first to fourth scanning lines and signal lines correspond to the reference numerals attached to FIG.

In the display device shown in FIG. 41, the first scanning line driver circuit 3802 is used to drive the first scanning lines 30
8, and an inverted signal of the selection signal input to the first scanning line 308, which is generated using an inverter 3807, is input to the second scanning line 309. FIG.

Further, for example, in the pixel configurations shown in FIGS. 3 and 8, the same selection signal is input to the second and fourth scanning lines. Therefore, as in the pixel configurations shown in FIGS. 14 and 15, the third and fifth transistors may be controlled using the same scanning line. FIG. 42 shows a configuration example of the display device in this case. Note that the case where the pixel configuration shown in FIG. 14 is used as the pixel configuration will be described as an example.

FIG. 42 shows a configuration example of a display device in which the third and fifth transistors 303 and 305 are controlled using the second scanning line 309. In FIG. The display device shown in FIG. 42 includes a pixel portion 3801,
It has first to third scanning line driving circuits 3802 to 3804 and a signal line driving circuit 3806 . Since the connection of each drive circuit is the same as that of the display device shown in FIG. 38, the explanation is omitted here. The reference numerals attached to the first to third scanning lines, signal lines, and third and fifth transistors correspond to the reference numerals attached to FIG.

Further, for example, as in the pixel configuration shown in FIG.
and the third transistor and the fifth transistor can be controlled by the same scan line. FIG. 43 shows a configuration example of a display device in this case.

FIG. 43 shows that the second, third and fifth transistors 302, 303, 305 are connected to the first scan line 3
08 is a configuration example of a display device. The display device shown in FIG. 43 includes a pixel portion 3801, first and third scanning line driver circuits 3802 and 3804, a signal line driver circuit
6. Since the connection of each drive circuit is the same as that of the display device shown in FIG. 38, the explanation is omitted here. Note that the reference numerals attached to the first and third scanning lines, the signal lines, and the second, third, and fifth transistors correspond to the reference numerals attached to FIG.

Thus, by configuring the display device as shown in FIGS. 41 to 43, the pixel circuit of the present invention can be driven.

By adopting the structure of the display device as shown in FIGS. 41 to 43, the number of scanning lines and scanning line driving circuits can be reduced, so that the aperture ratio of the pixel portion can be increased. Moreover, power consumption can be reduced. In addition, by reducing the number of scanning line driver circuits, the frame can be narrowed, and the area occupied by the pixel portion can be increased.

Note that the configurations of the signal line driver circuit, the scanning line driver circuit, and the like are not limited to those shown in FIGS.

Note that the transistor in the present invention may be any type of transistor and may be formed on any substrate. Therefore, the circuits as shown in FIGS. 38 to 43 may all be formed on a glass substrate, a plastic substrate, or a single crystal substrate. , may be formed on an SOI substrate, or may be formed on any substrate. Alternatively, part of the circuits in FIGS. 38-43 may be formed on one substrate and another part of the circuits in FIGS. 38-43 may be formed on another substrate. In other words, not all the circuits in FIGS. 38 to 43 may be formed on the same substrate. For example, in FIGS. 38 to 43, a pixel portion and a scanning line driver circuit are formed on a glass substrate using transistors, and a signal line driver circuit (or part thereof) is formed on a single crystal substrate, COG (Chip On Glass
) and placed on the glass substrate. Alternatively, the IC chip is TAB (Ta
PE Automated Bonding) or a printed circuit board may be used to connect to the glass substrate. Since part of the circuit is formed on the same substrate in this way, it is possible to reduce the number of parts, thereby reducing the cost, and to reduce the number of connections with circuit parts, thereby improving reliability. In addition, power consumption is increased in portions where the drive voltage is high and in portions where the drive frequency is high. If such portions are not formed on the same substrate, an increase in power consumption can be prevented.

In addition, the present embodiment is an example of a case where the content (or part of it) described in another embodiment is embodied, an example of a slightly modified case, an example of a partially changed case, and an improved case. An example of the case,
An example of detailed description, an example of application, and an example of related parts are shown. Therefore, the contents described in other embodiments can be freely applied, combined, or replaced with this embodiment.

In the present embodiment, descriptions have been made using various diagrams, but the contents described in each diagram (
may be part of it) shall apply, combine, or
Alternatively, replacement can be freely performed. Furthermore, in the figures described so far, more figures can be configured by combining each part with another part.

Similarly, the content (may be part of) described in each drawing of this embodiment may be applied, combined, replaced, etc. with respect to the content (may be part of) described in the drawing of another embodiment. can be done freely. Furthermore, in the drawings of this embodiment, more drawings can be configured by combining each part with another embodiment.

(Embodiment 7)
In this embodiment mode, a display panel used for the display device of the present invention will be described with reference to FIG. 44 and the like. 44(a) is a top view showing the display panel, and FIG. 44(b) is a cross-sectional view taken along line AA' of FIG. 44(a). A signal line driver circuit 4401 and a pixel portion 44 indicated by dotted lines
02, a first scanning line driver circuit 4403 and a second scanning line driver circuit 4406. FIG. also,
A sealing substrate 4404 and a sealant 4405 are provided, and the inside surrounded by the sealant 4405 is a space 4407 .

Note that a wiring 4408 is a wiring for transmitting signals input to the first scanning line driver circuit 4403, the second scanning line driver circuit 4406, and the signal line driver circuit 4401. signal, clock signal, start signal, etc. FP
IC chips (semiconductor chips on which memory circuits, buffer circuits, etc. are formed) 4422 and 4423 are COG (Chip On Glass) on the junction between the C4409 and the display panel.
), etc. Although only the FPC is shown here, a printed wiring board (PWB) may be attached to this FPC.

Next, the cross-sectional structure will be described with reference to FIG. 44(b). A pixel portion 44 is formed on the substrate 4410
02 and its peripheral driving circuits (first scanning line driving circuit 4403, second scanning line driving circuit 440
6 and a signal line driver circuit 4401) are formed.
1 and pixel portion 4402 are shown.

Note that the signal line driver circuit 4401 includes many transistors such as the transistors 4420 and 4421 . In this embodiment mode, a display panel in which a peripheral driver circuit is integrally formed on a substrate is shown, but this is not always necessary, and all or part of the peripheral driver circuit is formed on an IC chip or the like and mounted by COG or the like. may

In addition, the pixel portion 4402 has a plurality of circuits which form a pixel including a switching transistor 4411 and a driving transistor 4412 . Note that the driving transistor 4
A source electrode 412 is connected to the first electrode 4413 . Also, the first electrode 4413
An insulator 4414 is formed over the ends of the . Here, it is formed by using a positive photosensitive acrylic resin film.

In addition, in order to improve coverage, the insulator 4414 is formed with a curved surface having a curvature at the upper end or the lower end. For example, when positive photosensitive acrylic is used as the material of the insulator 4414, only the upper end of the insulator 4414 has a radius of curvature (0.2 μm to 3 μm).
It is preferred to have a curved surface with m). As the insulator 4414, either a negative type that becomes insoluble in an etchant by photosensitive light or a positive type that becomes soluble in an etchant by light can be used.

A layer 4416 containing an organic compound and a second electrode 4417 are formed over the first electrode 4413 . Here, as a material used for the first electrode 4413 functioning as an anode, a material with a large work function is preferably used. Examples include single-layer films such as ITO (indium tin oxide), indium zinc oxide (IZO), titanium nitride, chromium, tungsten, Zn, and Pt, as well as titanium nitride and aluminum as main components. It is possible to use a layered structure of a film containing a titanium nitride film, a three-layer structure of a titanium nitride film, a film containing aluminum as a main component, and a titanium nitride film. In the case of a laminated structure, the wiring resistance is low, good ohmic contact can be obtained, and the wiring can function as an anode.

The layer 4416 containing an organic compound is formed by an evaporation method using an evaporation mask or an inkjet method. A Group 4 metal complex of the periodic table is used as part of the layer 4416 containing an organic compound. In addition, materials that can be used in combination include high-molecular-weight materials even though they are low-molecular-weight materials. There may be. In addition, as the material used for the layer containing an organic compound, an organic compound is usually used in a single layer or a laminated layer in many cases. shall be included.
Furthermore, it is also possible to use known triplet materials.

Further, as a material used for the second electrode 4417 which is a cathode formed on the layer 4416 containing an organic compound, a material with a small work function (Al, Ag, Li, Ca, or alloys thereof MgAg, MgIn, AlLi, CaF ₂ , or calcium nitride) may be used. When the light generated in the layer 4416 containing an organic compound is transmitted through the second electrode 4417, the second electrode 4417 may be a thin metal thin film and a transparent conductive film (ITO (indium tin oxide)). material)), indium oxide zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO), etc.).

Furthermore, by bonding the sealing substrate 4404 to the substrate 4410 with the sealing material 4405, a structure in which a light-emitting element 4418 is provided in a space 4407 surrounded by the substrate 4410, the sealing substrate 4404, and the sealing material 4405 is obtained. . Note that the space 4407 contains an inert gas (
In addition to the case where nitrogen, argon, etc.) is filled, a structure where the sealing material 4405 is filled is also included.

Note that an epoxy resin is preferably used for the sealant 4405 . In addition, it is desirable that these materials be materials that are impermeable to moisture and oxygen as much as possible. Also, the sealing substrate 440
In addition to glass substrates and quartz substrates, materials used for 4 include FRP (Fiberglass-Resin
informed Plastics), PVF (polyvinyl fluoride), Mylar,
A plastic substrate made of polyester, acrylic, or the like can be used.

As described above, a display panel having the pixel configuration of the present invention can be obtained.

As shown in FIG. 44, by integrally forming the signal line driver circuit 4401, the pixel portion 4402, the first scan line driver circuit 4403, and the second scan line driver circuit 4406, the cost of the display device can be reduced. Note that the signal line driver circuit 4401, the pixel portion 4402, and the first scan line driver circuit 4
By using unipolar transistors for the transistors 403 and the second scan line driver circuit 4406, the manufacturing process can be simplified, and the cost can be further reduced. Also, the signal line drive circuit 4
401, a pixel portion 4402, a first scanning line driver circuit 4403, and a second scanning line driver circuit 44
By applying amorphous silicon to the semiconductor layer of the transistor used in 2006, further cost reduction can be achieved.

Note that the configuration of the display panel includes a signal line driver circuit 4401 as shown in FIG.
, the pixel portion 4402, the first scanning line driver circuit 4403, and the second scanning line driver circuit 4406 are not limited to the configuration in which the signal line driver circuit corresponding to the signal line driver circuit 4401 is integrated.
It may be formed on a C chip and mounted on the display panel by COG or the like.

In other words, only the signal line driver circuit that requires high-speed operation of the driver circuit is implemented using CMOS or the like.
Formed on a C chip to reduce power consumption. Further, by using a semiconductor chip such as a silicon wafer as the IC chip, higher speed operation and lower power consumption can be achieved.

Further, cost reduction can be achieved by integrally forming the scanning line driver circuit with the pixel portion. Further cost reduction can be achieved by using unipolar transistors for the scanning line driver circuit and the pixel portion. As the structure of pixels included in the pixel portion, the structures described in Embodiments 1 to 4 can be applied. In addition, the use of amorphous silicon for a semiconductor layer of a transistor simplifies the manufacturing process and further reduces the cost.

In this way, the cost of a high-definition display device can be reduced. Also, the FPC 4409 and the substrate 441
By mounting an IC chip with a functional circuit (memory and buffer) formed on the connection portion with 0, the substrate area can be effectively used.

Further, the signal line driver circuit 4401, the first scanning line driver circuit 4403 and the second scanning line driver circuit 4403 in FIG.
A signal line driver circuit corresponding to the scanning line driver circuit 4406, a first scanning line driver circuit, and a second scanning line driver circuit may be formed over an IC chip and mounted on a display panel by COG or the like. . In this case, it is possible to reduce the power consumption of a high-definition display device. Therefore, it is desirable to use polysilicon for a semiconductor layer of a transistor used in a pixel portion in order to obtain a display device that consumes less power.

In addition, cost reduction can be achieved by using amorphous silicon for the semiconductor layer of the transistor in the pixel portion 4402 . Furthermore, it becomes possible to manufacture a large-sized display panel.

Note that the scanning line driver circuit and the signal line driver circuit are not limited to being provided in the row direction and the column direction of the pixels.

Next, FIG. 45 shows an example of a light-emitting element that can be applied to the light-emitting element 4418. FIG.

An anode 4502, a hole-injection layer 4503 made of a hole-injection material, a hole-transport layer 4504 made of a hole-transport material, a light-emitting layer 4505, an electron-transport layer 4506 made of an electron-transport material, and an electron It has an element structure in which an electron injection layer 4507 made of an injection material and a cathode 4508 are laminated. Here, the light-emitting layer 4505 may be formed from only one type of light-emitting material, but may be formed from two or more types of materials. Further, the structure of the element of the present invention is
It is not limited to this structure.

In addition to the laminated structure in which each functional layer is laminated as shown in FIG. 45, there are variations such as an element using a polymer compound and a high-efficiency element using a triplet light-emitting material that emits light from a triplet excited state in the light-emitting layer. Diverse. It can also be applied to a white light emitting device obtained by controlling the recombination region of carriers with a hole blocking layer and dividing the light emitting region into two regions.

Next, a method for fabricating the element of the present invention shown in FIG. 45 will be described. First, anode 4502 (IT
A hole-injecting material, a hole-transporting material, and a light-emitting material are sequentially deposited on a substrate 4501 having O (indium tin oxide). Next, an electron transport material and an electron injection material are vapor-deposited, and finally a cathode 4508 is formed by vapor deposition.

Next, materials suitable for hole injection materials, hole transport materials, electron transport materials, electron injection materials, and luminescent materials are listed below.

Examples of hole injection materials include organic compounds such as porphyrin compounds and phthalocyanine (
hereinafter referred to as "H ₂ Pc"), copper phthalocyanine (hereinafter referred to as "CuPc") and the like are effective. Any material that has a smaller ionization potential than the hole-transporting material used and has a hole-transporting function can also be used as the hole-injecting material. There are also materials obtained by chemically doping conductive polymer compounds, such as polyethylenedioxythiophene (hereinafter referred to as "PEDOT") doped with polystyrene sulfonic acid (hereinafter referred to as "PSS"),
and polyaniline. Insulating polymer compounds are also effective in flattening the anode, and polyimide (hereinafter referred to as "PI") is often used. Furthermore, inorganic compounds are also used, and in addition to metal thin films such as gold and platinum, there are ultra-thin films of aluminum oxide (hereinafter referred to as "alumina").

The most widely used hole-transporting materials are aromatic amine compounds (that is, those having a benzene ring-nitrogen bond). As widely used materials, 4,4
'-Bis(diphenylamino)-biphenyl (hereinafter referred to as "TAD") and its derivative 4,4'-bis[N-(3-methylphenyl)-N-phenyl-amino]-biphenyl (hereinafter , abbreviated as “TPD”) and 4,4′-bis[N-(1-naphthyl)-N-phenyl-amino]-biphenyl (hereinafter abbreviated as “α-NPD”). 4,4′,4″-tris(N,N-diphenyl-amino)-triphenylamine (hereinafter referred to as “TDATA”), 4,4′,4″-tris[N-(3-methylphenyl) -N-phenyl-amino]-triphenylamine (hereinafter referred to as "MTDATA") and other starburst type aromatic amine compounds.

Metal complexes are often used as electron transport materials, and tris(8-quinolinolato)aluminum (hereinafter referred to as "Alq ₃ "), BAlq, tris(4-methyl-8-quinolinolato)aluminum (hereinafter referred to as "Almq"). ), bis (10-hydroxybenzo [h]-
and metal complexes having a quinoline skeleton or a benzoquinoline skeleton such as quinolinato)beryllium (hereinafter referred to as "Bebq"). In addition, bis[2-(2-hydroxyphenyl)-benzoxazolato]zinc (hereinafter referred to as “Zn(BOX) ₂ ”), bis[2-(2
-Hydroxyphenyl)-benzothiazolato]zinc (hereinafter referred to as "Zn(BTZ) ₂ ") and other metal complexes having oxazole and thiazole ligands. Furthermore, in addition to metal complexes, 2-(4-biphenylyl)-5-(4-tert-butylphenyl)-1,
3,4-oxadiazole (hereinafter referred to as “PBD”), oxadiazole derivatives such as OXD-7, TAZ, 3-(4-tert-butylphenyl)-4-(4-ethylphenyl)-5 -(4-biphenylyl)-1,2,4-triazole (hereinafter referred to as "p-EtTAZ
”), bathophenanthroline (hereinafter referred to as “BPhen”), and phenanthroline derivatives such as BCP have electron-transport properties.

As the electron injection material, the electron transport material described above can be used. In addition, ultra-thin films of insulators such as metal halides such as calcium fluoride, lithium fluoride and cesium fluoride, and alkali metal oxides such as lithium oxide are often used. Alkali metal complexes such as lithium acetylacetonate (hereinafter referred to as “Li(acac)”) and 8-quinolinolato-lithium (hereinafter referred to as “Liq”) are also effective.

Alq ₃ , Almq, BeBq, BAlq, Zn (BOX
) ₂ , Zn(BTZ) ₂ , and various fluorescent dyes are effective. Fluorescent dyes include blue 4,4′-bis(2,2-diphenyl-vinyl)-biphenyl and red-orange 4-(dicyanomethylene)-2-methyl-6-(p-dimethylaminostyryl)- 4
and H-pyran. Triplet light-emitting materials are also possible, and are mainly composed of complexes with platinum or iridium as the central metal. tris(2-phenylpyridine)iridium, bis(2-(4′-tolyl)pyridinato-N,C ^2′ )acetylacetonatoiridium (hereinafter referred to as “acacIr(tpy) ₂ ”), as triplet light-emitting materials; 2,3,7,8,12
, 13,17,18-octaethyl-21H,23H porphyrin-platinum and the like are known.

A highly reliable light-emitting element can be manufactured by combining the materials having each function as described above.

A light-emitting element in which layers are formed in the order opposite to that in FIG. 45 can also be used. That is, over a substrate 4501, a cathode 4508, an electron-injecting layer 4507 made of an electron-injecting material, an electron-transporting layer 4506 made of an electron-transporting material, a light-emitting layer 4505, a hole-transporting layer 4504 made of a hole-transporting material, and a positive electrode It has an element structure in which a hole injection layer 4503 made of a hole injection material and an anode 4502 are laminated.

At least one of the anode and the cathode of the light-emitting element should be transparent in order to emit light. Then, a transistor and a light-emitting element are formed on a substrate, and top emission for extracting light from the surface opposite to the substrate, bottom emission for extracting light from the surface on the substrate side, and the surface on the side of the substrate and the surface opposite to the substrate. There is a light emitting element with a double emission structure in which light is emitted from a double-sided emission structure, and the pixel configuration of the present invention can be applied to any light emitting element with an emission structure.

First, a light-emitting element having a top emission structure will be described with reference to FIG.

A driving transistor 4601 is formed over a substrate 4600 and
A first electrode 4602 is formed in contact with the source electrode of , and a layer 46 containing an organic compound is formed thereon.
03 and a second electrode 4604 are formed.

Also, the first electrode 4602 is the anode of the light-emitting element. A second electrode 4604 is a cathode of the light emitting element. That is, the portion where the layer 4603 containing an organic compound is sandwiched between the first electrode 4602 and the second electrode 4604 serves as a light-emitting element.

Here, as a material used for the first electrode 4602 functioning as an anode, it is preferable to use a material with a large work function. For example, in addition to single-layer films such as a titanium nitride film, a chromium film, a tungsten film, a Zn film, and a Pt film, a laminate of a film containing titanium nitride and aluminum as main components, and a film containing titanium nitride and aluminum as main components and a titanium nitride film, or the like can be used. In the case of a laminated structure, the wiring resistance is low, good ohmic contact can be obtained, and the wiring can function as an anode. By using a metal film that reflects light, an anode that does not transmit light can be formed.

Materials used for the second electrode 4604 functioning as a cathode include materials with a small work function (Al, Ag, Li, Ca, or their alloys MgAg, MgIn, AlLi, C
A laminate of a metal thin film made of aF ₂ or calcium nitride) and a transparent conductive film (ITO (indium tin oxide), indium zinc oxide (IZO), zinc oxide (ZnO), etc.) is preferably used. In this way, a cathode capable of transmitting light can be formed by using a thin metal thin film and a transparent conductive film having transparency.

In this way, it is possible to take out the light from the light emitting element to the upper surface as indicated by the arrow in FIG. 46(a). That is, when applied to the display panel of FIG. 44, light is emitted to the sealing substrate 4404 side. Therefore, when a light-emitting element with a top emission structure is used for a display device, a substrate having a light-transmitting property is used as the sealing substrate 4404 .

In addition, in the case of providing an optical film, the optical film may be provided on the sealing substrate 4404 .

Note that the first electrode 4602 can also be formed using a metal film that functions as a cathode and is made of a material with a small work function, such as MgAg, MgIn, or AlLi. In this case, the second
The electrode 4604 includes an ITO (indium tin oxide) film, an indium zinc oxide (IZO)
etc. can be used. Therefore, according to this configuration, the transmittance of top emission can be increased.

Next, a light-emitting element having a bottom emission structure will be described with reference to FIG. 46(b). Since the light-emitting element has the same structure as that of FIG.

Here, as a material used for the first electrode 4602 functioning as an anode, a material with a large work function is preferably used. For example, a transparent conductive film such as an ITO (indium tin oxide) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having transparency, an anode which can transmit light can be formed.

Materials used for the second electrode 4604 functioning as a cathode include materials with a small work function (Al, Ag, Li, Ca, or their alloys MgAg, MgIn, AlLi, C
A metal film made of aF ₂ or calcium nitride) can be used. Thus, by using a metal film that reflects light, a cathode that does not transmit light can be formed.

Thus, it is possible to extract light from the light emitting element to the bottom surface as indicated by the arrow in FIG. 46(b). That is, when applied to the display panel of FIG. 44, light is emitted to the substrate 4410 side. Therefore, when a light-emitting element having a bottom emission structure is used for a display device, the substrate 4
410 uses a substrate having optical transparency.

In addition, in the case of providing an optical film, the substrate 4410 may be provided with the optical film.

Next, a light emitting element having a double emission structure will be described with reference to FIG. 46(c). Since the light-emitting element has the same structure as that of FIG.

Here, as a material used for the first electrode 4602 functioning as an anode, a material with a large work function is preferably used. For example, a transparent conductive film such as an ITO (indium tin oxide) film or an indium zinc oxide (IZO) film can be used. By using a transparent conductive film having transparency, an anode which can transmit light can be formed.

Materials used for the second electrode 4604 functioning as a cathode include materials with a small work function (Al, Ag, Li, Ca, or their alloys MgAg, MgIn, AlLi, C
aF ₂ or calcium nitride) and a transparent conductive film (ITO (indium tin oxide), indium oxide zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO)
etc.). In this way, a cathode capable of transmitting light can be formed by using a thin metal thin film and a transparent conductive film having transparency.

In this way, the light from the light emitting element can be extracted from both sides as indicated by the arrows in FIG. 46(c). That is, when applied to the display panel of FIG. 44, light is emitted to the substrate 4410 side and the sealing substrate 4404 side. Therefore, in the case of using a light-emitting element with a double emission structure for a display device, a light-transmitting substrate is used for both the substrate 4410 and the sealing substrate 4404 .

In the case of providing an optical film, both the substrate 4410 and the sealing substrate 4404 may be provided with the optical film.

In addition, the present invention can also be applied to a display device that realizes full-color display using white light-emitting elements and color filters.

As shown in FIG. 47, a base film 4702 is formed over a substrate 4700 , a driving transistor 4701 is formed over the base film 4702 , and a first electrode 4703 is formed in contact with the source electrode of the driving transistor 4701 . , and a layer 4704 containing an organic compound and a second electrode 4705 are formed thereon.

Also, the first electrode 4703 is the anode of the light-emitting element. A second electrode 4705 is a cathode of the light emitting element. In other words, the portion where the layer 4704 containing an organic compound is sandwiched between the first electrode 4703 and the second electrode 4705 serves as a light emitting element. The configuration of FIG. 47 emits white light. A red color filter 4706R, a green color filter 4706G, and a blue color filter 4706B are provided above the light-emitting element, so that full-color display can be performed. A black matrix (also called BM) 4707 is provided to separate these color filters.

The structures of the light-emitting elements described above can be used in combination, and can be used as appropriate for the display device of the present invention. Further, the structure of the display panel and the light-emitting element described above are merely examples, and can be applied to a display device having a structure different from the structure described above.

Next, a partial cross-sectional view of a pixel portion of the display panel is shown.

First, the case of using a polysilicon (p-Si:H) film for the semiconductor layer of a transistor will be described with reference to FIGS. 48, 49 and 50. FIG.

Here, the semiconductor layer is formed, for example, by forming an amorphous silicon (a-Si) film on the substrate by a known film forming method. Note that the film is not necessarily limited to an amorphous silicon film, and any semiconductor film (including a microcrystalline semiconductor film) having an amorphous structure may be used. Further, a compound semiconductor film including an amorphous structure such as an amorphous silicon germanium film may be used.

Then, the amorphous silicon film is crystallized by a laser crystallization method, a thermal crystallization method using RTA or an annealing furnace, a thermal crystallization method using a metal element that promotes crystallization, or the like. Of course, you may carry out combining these.

The crystallization described above forms a partially crystallized region in the amorphous semiconductor film.

Further, the crystalline semiconductor film whose crystallinity is partially enhanced is patterned into a desired shape to form an island-like semiconductor film from the crystallized region. This semiconductor film is used as a semiconductor layer of a transistor.

As shown in FIG. 48A, a base film 4802 is formed on a substrate 4801, and a semiconductor layer is formed thereon. The semiconductor layer is the channel formation region 4 of the driving transistor 4818.
803, LDD regions 4804, and impurity regions 4805 to be source or drain regions.
, and a channel formation region 4806 and an LDD region 48 that serve as lower electrodes of the capacitive element 4819 .
07 and an impurity region 4808 . Note that the channel formation regions 4803 and 4806 may be channel-doped.

A glass substrate, a quartz substrate, a ceramic substrate, or the like can be used as the substrate. Further, as the base film ₄₈₀₂ , a single layer of aluminum nitride ( _AlN ), silicon oxide ( _SiO.sub.2 ), silicon oxynitride (SiO.sub.xN.sub.y), or a lamination thereof can be used.

A gate electrode 4810 and a capacitor 481 are formed over the semiconductor layer with a gate insulating film 4809 interposed therebetween.
9 upper electrodes 4811 are formed.

An interlayer insulating film 4812 is formed to cover the capacitive element 4819 and the driving transistor 4818, and a wiring 4813 is formed on the interlayer insulating film 4812 through a contact hole.
05. A pixel electrode 4814 is formed in contact with the wiring 4813 and a pixel electrode 481 is formed.
4 and the wiring 4813 are covered with an insulator 4815 . Here, it is formed by using a positive photosensitive acrylic resin film. A layer 4816 containing an organic compound and a counter electrode 4817 are formed over the pixel electrode 4814, and a light-emitting element 4820 is formed in a region where the layer 4816 containing an organic compound is sandwiched between the pixel electrode 4814 and the counter electrode 4817. there is

Also, as shown in FIG.
A region 4821 overlapping with the upper electrode 4811 of the capacitor 4819 may be provided. 48(a) are denoted by the same reference numerals, and description thereof will be omitted.

Further, as shown in FIG. 49A, the capacitive element 4823 has a second upper electrode 4822 formed in the same layer as the wiring 4813 in contact with the impurity region 4805 of the driving transistor 4818 .
may have 48(a) are denoted by the same reference numerals, and description thereof will be omitted. Since the second upper electrode 4822 is in contact with the impurity region 4808, the upper electrode 48
11 and a channel formation region 4806 with a gate insulating film 4809 interposed therebetween.
and a second capacitor formed by interposing an interlayer insulating film 4812 between an upper electrode 4811 and a second upper electrode 4822 are connected in parallel. A capacitive element 4823 is formed from a capacitive element. Since the capacitance of the capacitor 4823 is a combined capacitance obtained by adding the capacitances of the first capacitor and the second capacitor, a capacitor with a large capacitance can be formed in a small area. In other words, when it is used as a capacitive element of the pixel structure of the present invention, the aperture ratio can be further improved.

Alternatively, the capacitive element may be configured as shown in FIG. 49(b). A base film 4902 is formed over a substrate 4901, and a semiconductor layer is formed thereover. The semiconductor layer has a channel formation region 4903 of the driving transistor 4918, an LDD region 4904, and an impurity region 4905 serving as a source region or a drain region. Note that the channel formation region 4903 may be channel-doped.

A glass substrate, a quartz substrate, a ceramic substrate, or the like can be used as the substrate. Further, as the base film 4902, a single layer of aluminum nitride (AlN), silicon oxide (SiO ₂ ), silicon oxynitride (SiO _x N _y ), or the like or a lamination thereof can be used.

A gate electrode 4907 and a first electrode 49 are formed over the semiconductor layer with a gate insulating film 4906 interposed therebetween.
08 is formed.

A first interlayer insulating film 4909 covers the driving transistor 4918 and the first electrode 4908 .
is formed, and the wiring 4910 is in contact with the impurity region 4905 through the contact hole on the first interlayer insulating film 4909 . A second electrode 4911 made of the same material as the wiring 4910 is formed in the same layer as the wiring 4910 .

Further, a second interlayer insulating film 4912 is formed to cover the wiring 4910 and the second electrode 4911, and a pixel electrode 4913 is formed over the second interlayer insulating film 4912 in contact with the wiring 4910 through a contact hole. It is In addition, the pixel electrode 4913 is formed in the same layer as the pixel electrode 4913 .
A third electrode 4914 made of the same material as 913 is formed. Here, the first electrode 4
908, the second electrode 4911, and the third electrode 4914. A capacitor element 4919 is formed.

A layer 4916 containing an organic compound and a counter electrode 4917 are formed over the pixel electrode 4913, and in a region where the layer 4916 containing an organic compound is sandwiched between the pixel electrode 4913 and the counter electrode 4917,
A light emitting element 4920 is formed.

As described above, structures of transistors using a crystalline semiconductor film as a semiconductor layer include structures shown in FIGS. Note that the structures of the transistors illustrated in FIGS. 48 and 49 are examples of top-gate transistors. That is, the LDD region may or may not overlap the gate electrode. Moreover, some regions of the LDD regions may overlap. Furthermore, the gate electrode may have a tapered shape, and the LDD region may be provided in a self-aligned manner under the tapered portion of the gate electrode. Also, the number of gate electrodes is not limited to two, and a multi-gate structure of three or more may be employed, or one gate electrode may be employed.

A scanning line driver circuit and a signal line driver circuit are integrally formed with a pixel portion by using a crystalline semiconductor film for a semiconductor layer (a channel formation region, a source region, a drain region, etc.) of a transistor constituting a pixel of the present invention. becomes easier. Also, part of the signal line driving circuit may be formed integrally with the pixel portion, and part thereof may be formed on an IC chip and mounted by COG or the like as shown in the display panel of FIG. With such a configuration, the manufacturing cost can be reduced.

Further, as a structure of a transistor using polysilicon (p-Si:H) for a semiconductor layer, a structure in which a gate electrode is sandwiched between a substrate and a semiconductor layer, that is, a bottom structure in which the gate electrode is positioned below the semiconductor layer A transistor with a gate structure may be applied. Here, FIG. 50 shows a partial cross-sectional view of a pixel portion of a display panel to which a transistor with a bottom-gate structure is applied.

As shown in FIG. 50( a ), a base film 5002 is formed on a substrate 5001 . Furthermore, a gate electrode 5003 is formed on the underlying film 5002 . A first electrode 5004 made of the same material as the gate electrode 5003 is formed in the same layer as the gate electrode 5003 .
Phosphorus-added polycrystalline silicon can be used as the material of the gate electrode 5003 . In addition to polycrystalline silicon, silicide, which is a compound of metal and silicon, may be used.

A gate insulating film 5005 is formed to cover the gate electrode 5003 and the first electrode 5004 . A silicon oxide film, a silicon nitride film, or the like is used as the gate insulating film 5005 .

A semiconductor layer is formed on the gate insulating film 5005 . The semiconductor layer includes a channel formation region 5006, an LDD region 5007, an impurity region 5008 that serves as a source region or a drain region, and a channel formation region 5009, an LDD region 5010, and an impurity region that serve as a second electrode of the capacitor 5023 of the driving transistor 5022. 5011. Note that the channel formation regions 5006 and 5009 may be channel-doped.

A glass substrate, a quartz substrate, a ceramic substrate, or the like can be used as the substrate. As the base film 5002, a single layer of aluminum nitride (AlN), silicon oxide (SiO ₂ ), silicon oxynitride (SiO _x N _y ), or a lamination thereof can be used.

A first interlayer insulating film 5012 is formed covering the semiconductor layer, and a wiring 5013 is in contact with the impurity region 5008 through a contact hole on the first interlayer insulating film 5012 . A third electrode 5014 is formed in the same layer as the wiring 5013 and using the same material as the wiring 5013 .
A capacitor 5023 is formed by the first electrode 5004 , the second electrode, and the third electrode 5014 .

An opening 5015 is formed in the first interlayer insulating film 5012 . A second interlayer insulating film 50 is formed so as to cover the driving transistor 5022 , the capacitor 5023 and the opening 5015 .
16 is formed, and the pixel electrode 5 is formed on the second interlayer insulating film 5016 through the contact hole.
017 is formed. An insulator 5018 is formed to cover the edge of the pixel electrode 5017 . For example, a positive photosensitive acrylic resin film can be used. A layer 5019 containing an organic compound and a counter electrode 5020 are formed over the pixel electrode 5017, and a light emitting element 5021 is formed in a region where the layer 5019 containing an organic compound is sandwiched between the pixel electrode 5017 and the counter electrode 5020. there is An opening 5015 is positioned below the light emitting element 5021 . That is, when the light emitted from the light emitting element 5021 is taken out from the substrate side, the transmittance can be increased because the opening 5015 is provided.

Further, in FIG. 50(a), a fourth electrode 5024 may be formed in the same layer as the pixel electrode 5017 using the same material to form a structure as shown in FIG. 50(b). Then, the first electrode 50
04, the second electrode, the third electrode 5014, and the fourth electrode 5024 can form a capacitor 5025. FIG.

Next, a case where an amorphous silicon (a-Si:H) film is used for a semiconductor layer of a transistor will be described with reference to FIGS. 51, 52 and 53. FIG.

FIG. 51 shows a partial cross-sectional view of a pixel portion of a display panel to which a top-gate transistor using amorphous silicon for a semiconductor layer is applied. As shown in FIG. 51(a), a substrate 510
1, a base film 5102 is formed. Furthermore, a pixel electrode 5103 is formed on the base film 5102 .
is formed. A first electrode 5104 made of the same material as the pixel electrode 5103 is formed in the same layer as the pixel electrode 5103 .

A glass substrate, a quartz substrate, a ceramic substrate, or the like can be used as the substrate. Further, as the base film 5102, a single layer of aluminum nitride (AlN), silicon oxide (SiO ₂ ), silicon oxynitride (SiO _x N _y ), or the like, or a lamination thereof can be used.

A wiring 5105 and a wiring 5106 are formed over a base film 5102 , and the edge of the pixel electrode 5103 is covered with the wiring 5105 . N-type semiconductor layers 5107 and 5108 having N-type conductivity are formed over the wirings 5105 and 5106 . A semiconductor layer 5109 is formed over the base film 5102 between the wiring 5105 and the wiring 5106 . Part of the semiconductor layer 5109 is the N-type semiconductor layer 5107 and the N-type semiconductor layer 5
It extends up to 108. Note that this semiconductor layer 5109 is made of amorphous silicon (
a-Si:H), a microcrystalline semiconductor (μ-Si:H), or other non-crystalline semiconductor film.

A gate insulating film 5110 is formed over the semiconductor layer 5109 . Also, the gate insulating film 5
An insulating film 5111 made of the same material as the gate insulating film 5110 is also formed on the first electrode 5104 in the same layer as the gate insulating film 5110 . Note that a silicon oxide film, a silicon nitride film, or the like is used as the gate insulating film 5110 .

A gate electrode 5112 is formed on the gate insulating film 5110 . Also, the gate electrode 5
A second electrode 5113 made of the same material as the gate electrode 5112 is formed in the same layer as the gate electrode 5112 on the first electrode 5104 with an insulating film 5111 interposed therebetween. Thereby, the first electrode 51
A capacitor 5119 having a structure in which an insulating film 5111 is sandwiched between the 04 and the second electrode 5113 is formed. An interlayer insulating film 5114 is formed to cover the end portion of the pixel electrode 5103, the driving transistor 5118, and the capacitor 5119. FIG.

A layer 5115 containing an organic compound and a counter electrode 5116 are formed over the interlayer insulating film 5114 and the pixel electrode 5103 located in the opening thereof, and the layer 5115 containing the organic compound is sandwiched between the pixel electrode 5103 and the counter electrode 5116. A light emitting element 5117 is formed in the region.

Also, the first electrode 5104 shown in FIG. 51(a) may be formed of the first electrode 5120 as shown in FIG. 51(b). Note that the first electrode 5120 shown in FIG.
It is formed in the same layer as 105 and 5106 and with the same material as the wirings 5105 and 5106 .

Next, FIGS. 52 and 53 are partial cross-sectional views of a pixel portion of a display panel to which a bottom-gate transistor using amorphous silicon as a semiconductor layer is applied.

As shown in FIG. 52( a ), a base film 5202 is formed on a substrate 5201 . Furthermore, a gate electrode 5203 is formed on the base film 5202 . Also, the gate electrode 5203
A first electrode 5204 made of the same material as the gate electrode 5203 is formed in the same layer as the gate electrode 5203 . Phosphorus-added polycrystalline silicon can be used as the material of the gate electrode 5203 . In addition to polycrystalline silicon, silicide, which is a compound of metal and silicon, may be used.

A gate insulating film 5205 is formed to cover the gate electrode 5203 and the first electrode 5204 . As the gate insulating film 5205, a silicon oxide film, a silicon nitride film, or the like is used.

A semiconductor layer 5206 is formed over the gate insulating film 5205 . Also, the semiconductor layer 520
6, a semiconductor layer 5207 made of the same material as the semiconductor layer 5206 is formed.

A glass substrate, a quartz substrate, a ceramic substrate, or the like can be used as the substrate. As the base film ₅₂₀₂ , a single layer of aluminum nitride ( _AlN ), silicon oxide ( _SiO.sub.2 ), silicon oxynitride (SiO.sub.xN.sub.y), or a lamination thereof can be used.

N-type semiconductor layers 5208 and 5209 having N-type conductivity are formed on the semiconductor layer 5206 , and an N-type semiconductor layer 5210 is formed on the semiconductor layer 5207 .

Wirings 5211 and 5212 are formed on the N-type semiconductor layers 5208 and 5209, respectively.
A conductive layer 5213 made of the same material as the wirings 5211 and 5212 is formed on the N-type semiconductor layer 5210 in the same layer as the wirings 5211 and 5212 .

As a result, the second layer composed of the semiconductor layer 5207, the N-type semiconductor layer 5210 and the conductive layer 5213 is formed.
electrodes are configured. Note that the gate insulating film 520 is formed by the second electrode and the first electrode 5204 .
A capacitive element 5220 having a structure in which 5 is sandwiched is formed.

One end of the wiring 5211 extends, and a pixel electrode 5214 is formed in contact with the upper portion of the extended wiring 5211 .

An insulator 5215 is formed so as to cover an end portion of the pixel electrode 5214 , the driving transistor 5219 and the capacitor 5220 .

A layer 5216 containing an organic compound and a counter electrode 5217 are formed over the pixel electrode 5214 and the insulator 5215 .
A light-emitting element 5218 is formed in a region where 16 is sandwiched.

Note that the semiconductor layer 5207 and the N-type semiconductor layer 5 which are part of the second electrode of the capacitor 5220
210 may not be provided. That is, the conductive layer 5213 may be used as the second electrode of the capacitor 5220 , and the structure of the capacitor 5220 may be such that the gate insulating film is sandwiched between the first electrode 5204 and the conductive layer 5213 .

In FIG. 52(a), by forming the pixel electrode 5214 before forming the wiring 5211, as shown in FIG. A second electrode 5221 can be formed. Thereby, the second electrode 5
221 and a first electrode 5204 with a gate insulating film 5205 interposed therebetween.
2 can be formed.

Note that FIG. 52 shows an example in which a transistor with an inversely staggered channel-etch structure is applied, but a transistor with a channel protection structure may of course be applied. A case where a transistor having a channel protection structure is applied will be described with reference to FIGS.

The channel protective transistor shown in FIG. 53(a) serves as an etching mask on the region where the channel of the semiconductor layer 5206 of the driving transistor 5219 of the channel-etched structure shown in FIG. 52(a) is formed. The difference is that an insulator 5301 is provided, and common reference numerals are used for other common parts.

Similarly, the channel protection type transistor shown in FIG.
2 is different in that an insulator 5301 serving as an etching mask is provided on the region where the channel of the semiconductor layer 5206 of the driving transistor 5219 having the channel-etch structure is formed. A common code is used.

Manufacturing cost can be reduced by using an amorphous semiconductor film for a semiconductor layer (a channel formation region, a source region, a drain region, etc.) of a transistor constituting a pixel of the present invention.

Note that the structure of a transistor and the structure of a capacitor that can be applied to a pixel portion of a display device of the present invention are not limited to the above structures, and various structures of transistors and structures of capacitors can be used. can.

In addition, the present embodiment is an example of a case where the content (or part of it) described in another embodiment is embodied, an example of a slightly modified case, an example of a partially changed case, and an improved case. An example of the case,
An example of detailed description, an example of application, and an example of related parts are shown. Therefore, the contents described in other embodiments can be freely applied, combined, or replaced with this embodiment.

In the present embodiment, descriptions have been made using various diagrams, but the contents described in each diagram (
may be part of it) shall apply, combine, or
Alternatively, replacement can be freely performed. Furthermore, in the figures described so far, more figures can be configured by combining each part with another part.

Similarly, the content (may be part of) described in each drawing of this embodiment may be applied, combined, replaced, etc. with respect to the content (may be part of) described in the drawing of another embodiment. can be done freely. Furthermore, in the drawings of this embodiment, more drawings can be configured by combining each part with another embodiment.

(Embodiment 8)
In this embodiment mode, a method for manufacturing a semiconductor device using plasma treatment will be described as a method for manufacturing a semiconductor device such as a transistor.

FIG. 54 is a diagram showing a structural example of a semiconductor device including transistors. In FIG. 54, FIG. 54(B) corresponds to a cross-sectional view between a and b in FIG. 54(A), and FIG.
It corresponds to the cross-sectional view between cd in (A).

The semiconductor device shown in FIG. 54 includes semiconductor films 5403a and 5403b provided over a substrate 5401 with an insulating film 5402 interposed therebetween, and gate insulating films 5403a and 5403b over the semiconductor films 5403a and 5403b.
404, insulating films 5406 and 5407 provided to cover the gate electrodes, and the insulating film 5407 connected to the source region or the drain region of the semiconductor films 5403a and 5403b and provided on the insulating film 5407. and a conductive film 5408 . Note that FIG. 54 shows the case where an N-channel transistor 5410a using part of the semiconductor film 5403a as a channel region and a P-channel transistor 5410b using part of the semiconductor film 5403b as a channel region are provided. but not limited to this configuration. For example, in FIG. 54, the N-channel transistor 5410a is provided with the LDD region and the P-channel transistor 5410b is not provided with the LDD region. It is possible.

Note that in this embodiment, the substrate 5401, the insulating film 5402, the semiconductor films 5403a and 5403a and 5403a
403b, at least one of the gate insulating film 5404, the insulating film 5406, and the insulating film 5407 is oxidized or nitrided by plasma treatment, thereby oxidizing or nitriding the semiconductor film or the insulating film. A semiconductor device shown in FIG. By oxidizing or nitriding a semiconductor film or an insulating film by plasma treatment in this way, the surface of the semiconductor film or insulating film is modified, and the surface properties of the semiconductor film or insulating film are improved as compared with an insulating film formed by a CVD method or a sputtering method. Since a dense insulating film can be formed, defects such as pinholes can be suppressed and the characteristics of the semiconductor device can be improved.

Note that in this embodiment mode, the semiconductor films 5403a and 5403b or the gate insulating film 5404 in FIGS. The method will be described with reference to the drawings.

First, the case where an island-shaped semiconductor film is provided over a substrate and an end portion of the island-shaped semiconductor film is provided in a nearly right-angled shape will be described.

First, island-shaped semiconductor films 5403a and 5403b are formed on a substrate 5401 (see FIG. 55A).
)). The island-shaped semiconductor films 5403a and 5403b are formed on an insulating film 5402 formed in advance on a substrate 5401 using a known method (sputtering method, LPCVD method, plasma CVD method, etc.) using silicon (Si) as a main component. It can be provided by forming an amorphous semiconductor film using a material (eg, Si _x Ge _1-x or the like), crystallizing the amorphous semiconductor film, and selectively etching the semiconductor film. Crystallization of the amorphous semiconductor film may be performed by a laser crystallization method, a thermal crystallization method using RTA or a furnace annealing furnace, a thermal crystallization method using a metal element that promotes crystallization, or a combination of these methods. can be carried out by the known crystallization method of Note that in FIG. 55, the end portions of the island-shaped semiconductor films 5403a and 5403b are provided in a shape close to a right angle (θ=85 to 100°).

Next, plasma treatment is performed to oxidize or nitride the semiconductor films 5403a and 5403b, so that oxide films or nitride films 54 are formed on the surfaces of the semiconductor films 5403a and 5403b, respectively.
21a and 5421b (hereinafter also referred to as insulating films 5421a and 5421b) are formed (FIG. 55B). For example, when Si is used as the semiconductor films 5403a and 5403b,
As the insulating films 5421a and 5421b, silicon oxide (SiOx) or silicon nitride (
SiNx) is formed. Alternatively, after the semiconductor films 5403a and 5403b are oxidized by plasma treatment, the semiconductor films 5403a and 5403b may be nitrided by plasma treatment again. In this case, silicon oxide (SiOx) is formed in contact with the semiconductor films 5403a and 5403b, and silicon nitride oxide (SiNxOy) (x>y) is formed on the surface of the silicon oxide. Note that when the semiconductor film is oxidized by plasma treatment, an oxygen atmosphere (for example, oxygen (O ₂ ) and a rare gas (He
, Ne, Ar, Kr, and Xe) atmosphere or oxygen and hydrogen (H ₂ )
and rare gas atmosphere or dinitrogen monoxide and rare gas atmosphere). on the other hand,
When the semiconductor film is nitrided by plasma treatment, it is performed under a nitrogen atmosphere (for example, nitrogen (N ₂ )
and a rare gas (including at least one of He, Ne, Ar, Kr, and Xe), nitrogen, hydrogen and a rare gas, or _NH3 and a rare gas. For example, Ar can be used as the rare gas. Alternatively, a mixed gas of Ar and Kr may be used. Therefore, the insulating films 5421a and 5421b are made of the rare gas (H
containing at least one of e, Ne, Ar, Kr, and Xe), and when Ar is used, the insulating films 5421a and 5421b contain Ar.

Further, the plasma treatment has an electron density of 1×10 ¹¹ cm ⁻³ in the above gas atmosphere.
1×10 ¹³ cm ⁻³ or more, and the plasma electron temperature is 0.5 eV or more and 1.5 eV
Do below. Since the electron density of plasma is high and the electron temperature is low near the object to be processed (here, the semiconductor films 5403a and 5403b) formed over the substrate 5401, the object to be processed can be prevented from being damaged by the plasma. can be done. Moreover, the electron density of the plasma is 1×
Since it has a high density of 10 ¹¹ cm ⁻³ or more, an oxide or nitride film formed by oxidizing or nitriding an object to be irradiated using plasma processing is a film formed by a CVD method, a sputtering method, or the like. A dense film can be formed with excellent uniformity in film thickness and the like compared to the conventional method.
In addition, since the electron temperature of plasma is as low as 1 eV or less, oxidation or nitridation can be performed at a lower temperature than conventional plasma processing or thermal oxidation. For example, even if the plasma treatment is performed at a temperature 100 degrees or more lower than the strain point temperature of the glass substrate, the oxidation or nitridation treatment can be sufficiently performed. The frequency for forming plasma is microwave (2.4
A high frequency such as 5 GHz) can be used. Unless otherwise specified, the plasma treatment is performed under the above conditions.

Next, a gate insulating film 5404 is formed to cover the insulating films 5421a and 5421b (FIG. 55(C)). The gate insulating film 5404 is formed of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x>y), nitriding using known means (sputtering method, LPCVD method, plasma CVD method, etc.). It can be provided with a single-layer structure of an insulating film containing oxygen or nitrogen such as silicon oxide (SiNxOy) (x>y), or a stacked-layer structure thereof. For example, Si is used for the semiconductor films 5403a and 5403b, and insulating films 5421a and 5421a are formed on the surfaces of the semiconductor films 5403a and 5403b by oxidizing the Si by plasma treatment.
When silicon oxide is formed as 5421b, silicon oxide (SiOx) is formed as a gate insulating film over the insulating films 5421a and 5421b. Further, in FIG. 55B, when the insulating films 5421a and 5421b formed by oxidizing or nitriding the semiconductor films 5403a and 5403b by plasma treatment have a sufficient thickness, the insulating film 542 is formed.
1a and 5421b can also be used as gate insulating films.

Next, by forming a gate electrode 5405 and the like over the gate insulating film 5404, a semiconductor device having an N-channel transistor 5410a and a P-channel transistor 5410b using island-shaped semiconductor films 5403a and 5403b as channel regions is manufactured. (Fig. 55(D)).

Thus, before providing the gate insulating film 5404 over the semiconductor films 5403a and 5403b,
By oxidizing or nitriding the surfaces of the semiconductor films 5403a and 5403b by plasma treatment, a short circuit or the like between the gate electrode and the semiconductor film due to poor coverage of the gate insulating film 5404 at the ends 5451a and 5451b of the channel region can be prevented. can be done. In other words, when the end of the island-shaped semiconductor film has a shape close to a right angle (θ = 85 to 100°), C
When a gate insulating film is formed so as to cover a semiconductor film by a VD method, a sputtering method, or the like, there is a possibility that a coating failure problem may occur due to discontinuity of the gate insulating film at the edge of the semiconductor film.
By oxidizing or nitriding the surface of the semiconductor film in advance by plasma treatment, it is possible to prevent poor coverage of the gate insulating film at the edge of the semiconductor film.

Further, in FIG. 55, the gate insulating film 5404 may be oxidized or nitrided by plasma treatment after the gate insulating film 5404 is formed. In this case, a gate insulating film 5404 (FIG. 56A) is formed so as to cover the semiconductor films 5403a and 5403b.
Then, plasma treatment is performed to oxidize or nitride the gate insulating film 5404, thereby forming an oxide film or a nitride film (hereinafter also referred to as an insulating film 5423) on the surface of the gate insulating film 5404 (FIG. 56B). The conditions for the plasma treatment can be the same as in FIG. 55(B). In addition, the insulating film 5523 contains a rare gas used for plasma processing, such as Ar
is used, the insulating film 5523 contains Ar.

In FIG. 56B, the gate insulating film 5404 may be nitrided by performing plasma treatment again in a nitrogen atmosphere after oxidizing the gate insulating film 5404 by once performing plasma treatment in an oxygen atmosphere. In this case, silicon oxide (SiOx) is applied to the semiconductor films 5403a and 5403b.
Alternatively, silicon oxynitride (SiOxNy) (x>y) is formed, and silicon nitride oxide (SiNxOy) (x>y) is formed in contact with the gate electrode 5405 . After that, by forming a gate electrode 5405 and the like over the insulating film 123, a semiconductor device having an N-channel transistor 5410a and a P-channel transistor 5410b using the island-shaped semiconductor films 5403a and 5403b as channel regions is manufactured. (Fig. 56(C)). By subjecting the gate insulating film to plasma treatment in this way, the surface of the gate insulating film is oxidized or nitrided, thereby modifying the surface of the gate insulating film and forming a dense film. An insulating film obtained by plasma treatment is denser and has fewer defects such as pinholes than an insulating film formed by a CVD method or a sputtering method; therefore, transistor characteristics can be improved.

Note that FIG. 56 shows the case where the surfaces of the semiconductor films 5403a and 5403b are oxidized or nitrided by performing plasma treatment on the semiconductor films 5403a and 5403b in advance, but the semiconductor films 5403a and 5403b are subjected to plasma treatment. Alternatively, plasma treatment may be performed after the gate insulating film 5404 is formed. By performing the plasma treatment before forming the gate electrode in this way, even if a poor coating occurs due to a break in the gate insulating film at the edge of the semiconductor film, the exposed semiconductor film due to the poor coating can be removed. can be oxidized or nitrided, it is possible to prevent a short circuit between the gate electrode and the semiconductor film due to poor coverage of the gate insulating film at the edge of the semiconductor film.

As described above, even when the end portion of the island-shaped semiconductor film is provided in a nearly right-angled shape, the semiconductor film or the gate insulating film is subjected to plasma treatment to oxidize or nitride the semiconductor film or the gate insulating film. Thus, it is possible to prevent a short circuit between the gate electrode and the semiconductor film due to poor coverage of the gate insulating film at the edge of the semiconductor film.

Next, the case where an end portion of an island-shaped semiconductor film provided over a substrate is provided in a tapered shape (θ=30 to 85°) will be described.

First, island-shaped semiconductor films 5403a and 5403b are formed on a substrate 5401 (see FIG. 57A).
)). The island-shaped semiconductor films 5403a and 5403b are formed on an insulating film 5402 formed in advance on a substrate 5401 using a known method (sputtering method, LPCVD method, plasma CVD method, etc.) using silicon (Si) as a main component. An amorphous semiconductor film is formed using a material (eg, Si _x Ge _1-x , etc.), and the amorphous semiconductor film is subjected to a laser crystallization method, a thermal crystallization method using RTA or a furnace annealing furnace, or a crystallization method. It can be provided by crystallizing by a known crystallization method such as a thermal crystallization method using a metal element that promotes , and selectively etching and removing the semiconductor film. Note that in FIG. 57, the end portion of the island-shaped semiconductor film is tapered (θ=3
0 to 85°).

Next, a gate insulating film 5404 is formed to cover the semiconductor films 5403a and 5403b (
FIG. 57(B)). The gate insulating film 5404 is formed of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x>y), nitriding using known means (sputtering method, LPCVD method, plasma CVD method, etc.). It can be provided with a single-layer structure of an insulating film containing oxygen or nitrogen such as silicon oxide (SiNxOy) (x>y), or a stacked-layer structure thereof.

Next, plasma treatment is performed to oxidize or nitride the gate insulating film 5404, thereby forming an oxide film or a nitride film (hereinafter also referred to as an insulating film 5424) on the surface of the gate insulating film 5404 (FIG. 57C). )). Note that plasma treatment conditions can be the same as those described above. For example, when silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x>y) is used as the gate insulating film 5404, the gate insulating film 5404 is oxidized by plasma treatment in an oxygen atmosphere. A dense film having fewer defects such as pinholes can be formed on the surface of the film, compared with a gate insulating film formed by a CVD method, a sputtering method, or the like. On the other hand, silicon oxynitride (SiNxOy) (x>y) can be provided as an insulating film 5424 on the surface of the gate insulating film 5404 by nitriding the gate insulating film 5404 by plasma treatment in a nitrogen atmosphere. Alternatively, after the gate insulating film 5404 is once oxidized by performing plasma treatment in an oxygen atmosphere, it may be nitrided by performing plasma treatment again in a nitrogen atmosphere. In addition, the insulating film 5424 contains a rare gas used for plasma treatment. For example, when Ar is used, the insulating film 5424 contains Ar.

Next, by forming a gate electrode 5405 and the like over the gate insulating film 5404, a semiconductor device having an N-channel transistor 5410a and a P-channel transistor 5410b using island-shaped semiconductor films 5403a and 5403b as channel regions is manufactured. (Fig. 57(D)).

By subjecting the gate insulating film to plasma treatment in this way, an insulating film made of an oxide film or a nitride film can be provided on the surface of the gate insulating film, and the surface of the gate insulating film can be modified.
An insulating film that is oxidized or nitrided by plasma treatment is denser and has fewer defects such as pinholes than a gate insulating film formed by a CVD method or a sputtering method; therefore, transistor characteristics can be improved. can. Further, by tapering the end portion of the semiconductor film, a short circuit or the like between the gate electrode and the semiconductor film due to poor coverage of the gate insulating film at the end portion of the semiconductor film can be suppressed. Short-circuiting between the gate electrode and the semiconductor film can be further prevented by performing plasma treatment after the formation.

Next, a method for manufacturing a semiconductor device different from that shown in FIG. 57 will be described with reference to the drawings. Specifically, the case of performing plasma treatment selectively on the end portion of a semiconductor film having a tapered shape is shown.

First, island-shaped semiconductor films 5403a and 5403b are formed on a substrate 5401 (see FIG. 58A).
)). The island-shaped semiconductor films 5403a and 5403b are formed on an insulating film 5402 formed in advance on a substrate 5401 using a known method (sputtering method, LPCVD method, plasma CVD method, etc.) using silicon (Si) as a main component. An amorphous semiconductor film is formed using a material (for example, Si _x Ge _1-x or the like) or the like, the amorphous semiconductor film is crystallized, and resists 5425 a and 542 are formed.
5b can be used as a mask to selectively etch the semiconductor film.
Crystallization of the amorphous semiconductor film may be performed by a laser crystallization method, a thermal crystallization method using RTA or a furnace annealing furnace, a thermal crystallization method using a metal element that promotes crystallization, or a combination of these methods. can be carried out by the known crystallization method of

Next, before removing the resists 5425a and 5425b used for etching the semiconductor films, plasma treatment is performed to selectively oxidize or nitridize the ends of the island-shaped semiconductor films 5403a and 5403b, thereby removing the semiconductor films. An oxide film or a nitride film (hereinafter also referred to as an insulating film 5426) is formed at each end of the films 5403a and 5403b (FIG. 58B). Plasma treatment is performed under the conditions described above. In addition, the insulating film 5426 contains a rare gas used for plasma treatment.

Next, a gate insulating film 5404 is formed to cover the semiconductor films 5403a and 5403b (
FIG. 58(C)). A gate insulating film 5404 can be provided in the same manner as described above.

Next, by forming a gate electrode 5405 and the like over the gate insulating film 5404, a semiconductor device having an N-channel transistor 5410a and a P-channel transistor 5410b using island-shaped semiconductor films 5403a and 5403b as channel regions is manufactured. (Fig. 58(D)).

When the end portions of the semiconductor films 5403a and 5403b are tapered, the semiconductor film 5403
The end portions 5452a and 5452b of the channel regions formed in the portions of 5403b a and 5403b are also tapered, and the film thickness of the semiconductor film and the film thickness of the gate insulating film change compared to the central portion.
It may affect the characteristics of the transistor. Therefore, here, the edge of the channel region is selectively oxidized or nitrided by plasma treatment, and an insulating film is formed on the semiconductor film that serves as the edge of the channel region, whereby the transistor caused by the edge of the channel region is reduced. can reduce the impact on

Note that FIG. 58 shows an example in which only the edges of the semiconductor films 5403a and 5403b are oxidized or nitrided by plasma treatment, but of course the gate insulating film 5404 is also subjected to plasma treatment as shown in FIG. 60 (A
)).

Next, a method for manufacturing a semiconductor device, which is different from the above method, will be described with reference to the drawings. Specifically, the case where a semiconductor film having a tapered shape is subjected to plasma treatment will be described.

First, island-shaped semiconductor films 5403a and 5403b are formed on a substrate 5401 in the same manner as described above (FIG. 59A).

Next, plasma treatment is performed to oxidize or nitride the semiconductor films 5403a and 5403b, so that oxide films or nitride films 54 are formed on the surfaces of the semiconductor films 5403a and 5403b, respectively.
27a and 5427b (hereinafter also referred to as insulating films 5427a and 5427b) are formed (FIG. 59B). Plasma treatment can similarly be performed under the conditions described above. for example,
When Si is used for the semiconductor films 5403a and 5403b, silicon oxide (SiOx) or silicon nitride (SiNx) is formed as the insulating films 5427a and 5427b. Alternatively, after the semiconductor films 5403a and 5403b are oxidized by plasma treatment, the semiconductor films 5403a and 5403b may be nitrided by plasma treatment again. In this case, semiconductor films 5403a and 5403
Silicon oxide (SiOx) or silicon oxynitride (SiOxNy) (x>y) is formed in contact with b, and silicon nitride oxide (SiNxOy) (x>y) is formed on the surface of the silicon oxide. Therefore, the insulating films 5427a and 5427b contain the rare gas used for the plasma treatment.
Note that edge portions of the semiconductor films 5403a and 5403b are also oxidized or nitrided at the same time by the plasma treatment.

Next, a gate insulating film 5404 is formed to cover the insulating films 5427a and 5427b (FIG. 59(C)). The gate insulating film 5404 is formed of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy) (x>y), nitriding using known means (sputtering method, LPCVD method, plasma CVD method, etc.). It can be provided with a single-layer structure of an insulating film containing oxygen or nitrogen such as silicon oxide (SiNxOy) (x>y), or a stacked-layer structure thereof. For example, by using Si as the semiconductor films 5403a and 5403b and oxidizing them by plasma treatment, insulating films 5427a and 5427 are formed on the surfaces of the semiconductor films 5403a and 5403b.
When silicon oxide is formed for b, silicon oxide (SiOx) is formed as a gate insulating film over the insulating films 5427a and 5427b.

Next, by forming a gate electrode 5405 and the like over the gate insulating film 5404, a semiconductor device having an N-channel transistor 5410a and a P-channel transistor 5410b using island-shaped semiconductor films 5403a and 5403b as channel regions is manufactured. (Fig. 59(D)).

When the end portions of the semiconductor film are tapered, the end portions 5453a and 5453b of the channel regions formed in part of the semiconductor film are also tapered, which may affect the characteristics of the semiconductor element. Therefore, when the semiconductor film is oxidized or nitrided by plasma treatment, the edge of the channel region is also oxidized or nitrided, so that the influence on the semiconductor element can be reduced.

FIG. 59 shows an example in which only the semiconductor films 5403a and 5403b are oxidized or nitrided by plasma treatment.
4 can be oxidized or nitrided by plasma treatment (FIG. 60(B)). In this case, the gate insulating film 5404 may be nitrided by performing plasma treatment again in a nitrogen atmosphere after oxidizing the gate insulating film 5404 by once performing plasma treatment in an oxygen atmosphere. In this case, the semiconductor films 5403a and 5403b are made of silicon oxide (SiOx) or silicon oxynitride (
SiOxNy) (x>y) is formed, and silicon oxynitride (Si) is formed in contact with the gate electrode 5405 .
NxOy) (x>y) are formed.

In this manner, by performing plasma treatment to oxidize or nitridize the semiconductor film or the gate insulating film to modify the surface thereof, a dense insulating film with good film quality can be formed. As a result, even if the insulating film is formed thin, defects such as pinholes can be prevented, and miniaturization and high performance of semiconductor elements such as transistors can be achieved.

Note that in this embodiment mode, the semiconductor films 5403a and 5403b or the gate insulating film 5404 in FIGS. The layer to be oxidized or nitrided using is not limited to this. For example, the substrate 5401 or the insulating film 5402 may be subjected to plasma treatment, or the insulating film 5406 or the insulating film 5407 may be subjected to plasma treatment.

In addition, the present embodiment is an example of a case where the content (or part of it) described in another embodiment is embodied, an example of a slightly modified case, an example of a partially changed case, and an improved case. An example of the case,
An example of detailed description, an example of application, and an example of related parts are shown. Therefore, the contents described in other embodiments can be freely applied, combined, or replaced with this embodiment.

In the present embodiment, descriptions have been made using various diagrams, but the contents described in each diagram (
may be part of it) shall apply, combine, or
Alternatively, replacement can be freely performed. Furthermore, in the figures described so far, more figures can be configured by combining each part with another part.

Similarly, the content (may be part of) described in each drawing of this embodiment may be applied, combined, replaced, etc. with respect to the content (may be part of) described in the drawing of another embodiment. can be done freely. Furthermore, in the drawings of this embodiment, more drawings can be configured by combining each part with another embodiment.

(Embodiment 9)
In this embodiment, hardware for controlling the driving methods described in the first to sixth embodiments will be described.

A rough configuration diagram is shown in FIG. A pixel portion 6104 , a signal line driver circuit 6106 , and a scanning line driver circuit 6105 are arranged over a substrate 6101 . In addition, a power supply circuit, a precharge circuit, a timing generation circuit, and the like may be arranged. Note that the signal line driver circuit 6106 and the scanning line driver circuit 6105 may not be provided. In that case, substrate 610
Anything not placed in 1 may be formed in the IC. The IC is on the substrate 6101,
It may be arranged by COG (Chip On Glass). Alternatively, an IC may be arranged on the connection board 6107 that connects the peripheral circuit board 6102 and the board 6101 .

A signal 6103 is input to the peripheral circuit board 6102 . and controller 6108
stores the signals in memories 6109, 6110, etc. under the control of . If the signal 6103 is an analog signal, after performing analog-to-digital conversion, then memory 6109, 611
It is often stored as 0. Then, the controller 6108 stores the memories 6109 and 61
10 or the like is used to output a signal to the substrate 6101 .

In order to realize the driving methods described in Embodiments 1 to 6, controller 6108
controls the order of appearance of subframes and outputs a signal to the substrate 6101 .

In addition, the present embodiment is an example of a case where the content (or part of it) described in another embodiment is embodied, an example of a slightly modified case, an example of a partially changed case, and an improved case. An example of the case,
An example of detailed description, an example of application, and an example of related parts are shown. Therefore, the contents described in other embodiments can be freely applied, combined, or replaced with this embodiment.

In the present embodiment, descriptions have been made using various diagrams, but the contents described in each diagram (
may be part of it) shall apply, combine, or
Alternatively, replacement can be freely performed. Furthermore, in the figures described so far, more figures can be configured by combining each part with another part.

Similarly, the content (may be part of) described in each drawing of this embodiment may be applied, combined, replaced, etc. with respect to the content (may be part of) described in the drawing of another embodiment. can be done freely. Furthermore, in the drawings of this embodiment, more drawings can be configured by combining each part with another embodiment.

(Embodiment 10)
In this embodiment, configuration examples of an EL module and an EL television receiver using the display device of the present invention will be described.

FIG. 62 shows an EL module in which a display panel 6201 and a circuit board 6202 are combined. A display panel 6201 includes a pixel portion 6203 , a scanning line driver circuit 6204 and a signal line driver circuit 6205 . The circuit board 6202 includes, for example, a control circuit 6206
and a signal dividing circuit 6207 are formed. Display panel 6201 and circuit board 6202
are connected by a connection wiring 6208 . FPC or the like can be used for the connection wiring.

The control circuit 6206 is the controller 6108 and the memory 6 in the ninth embodiment.
109, 6110, etc. Mainly, the control circuit 6206 controls the order of appearance of subframes.

In the display panel 6201, a pixel portion and some peripheral driver circuits (driver circuits with low operating frequencies among the plurality of driver circuits) are integrally formed on a substrate using transistors. A driver circuit with a high operating frequency among circuits) is formed over an IC chip, and the IC chip is preferably mounted on the display panel 6201 by COG (Chip On Glass) or the like. Alternatively, the IC chip is TAB (Tape Automated Bonding
) or a printed circuit board.

Further, by impedance-converting a signal set to a scanning line or a signal line by a buffer circuit, it is possible to shorten the writing time of pixels for each row. Therefore, a high-definition display device can be provided.

In order to further reduce power consumption, a pixel portion is formed on a glass substrate using transistors, all signal line driving circuits are formed on an IC chip, and the IC chip is a COG (Ch.
ip On Glass) display panel.

For example, the entire screen of the display panel is divided into several areas, and an IC chip formed with a part or all of the peripheral driving circuits (signal line driving circuit, scanning line driving circuit, etc.) is arranged in each area, and the COG (Chip On Glass) or the like may be mounted on the display panel. FIG. 63 shows the configuration of the display panel in this case.

FIG. 63 shows an example in which the entire screen is divided into four areas and eight IC chips are used for driving. The configuration of the display panel includes a substrate 6310, a pixel portion 6311, and FPCs 6312a to 631.
2h, has IC chips 6313a to 6313h. 6313 out of 8 IC chips
A signal line driving circuit is formed in a to 6313d, and a scanning line driving circuit is formed in 6313e to 6313h. By driving an arbitrary IC chip, it is possible to drive only an arbitrary screen area among the four screen areas. For example, IC chip 6
By driving only 313a and 6313e, only the upper left area of the four screen areas can be driven. By doing so, power consumption can be reduced.

Also, FIG. 64 shows an example of a display panel having another structure. In the display panel of FIG. 64, a pixel portion 6421 in which a plurality of pixels 6430 are arranged on a substrate 6420, a scanning line driver circuit 6422 that controls the signal of the scanning line 6433, and a signal line driver circuit 64 that controls the signal of the signal line 6431.
23. A monitor circuit 6424 for correcting a change in luminance of the light emitting element included in the pixel 6430 may be provided. A light-emitting element included in the pixel 6430 and a light-emitting element included in the monitor circuit 6424 have the same structure. A light-emitting element has a structure in which a layer containing a material that exhibits electroluminescence is sandwiched between a pair of electrodes.

An input terminal 6425 for inputting a signal from an external circuit to the scanning line driver circuit 6422 and an input terminal 6426 for inputting a signal from an external circuit to the signal line driver circuit 6423 are provided in the peripheral portion of the substrate 6420 .
, and an input terminal 6429 for inputting a signal to the monitor circuit 6424 .

In order for the light-emitting element provided in the pixel 6430 to emit light, power must be supplied from an external circuit. A power supply line 6432 provided in the pixel portion 6421 is connected to an external circuit through an input terminal 6427 . Since the power supply line 6432 causes resistance loss depending on the length of the wiring, it is preferable to provide the input terminals 6427 at a plurality of locations on the peripheral portion of the substrate 6420 . Input terminal 6427
are provided at both ends of the substrate 6420 so as to make luminance unevenness in the plane of the pixel portion 6421 inconspicuous. In other words, it prevents one side of the screen from becoming bright and the other side from becoming dark. In addition, the electrode of the light-emitting element having a pair of electrodes, which is opposite to the electrode connected to the power supply line 6432, is formed as a common electrode shared by the plurality of pixels 6430, and the resistance loss of this electrode is also reduced. Therefore, a plurality of terminals 6428 are provided.

Such a display panel is effective especially when the screen size is increased because the power line is made of a low resistance material such as Cu. For example, if the screen size is 13 inches, the diagonal length is 340 mm, but if it is 60 inches, it is 1500 mm or longer. In such a case, since the wiring resistance cannot be ignored, it is preferable to use a low resistance material such as Cu as the wiring. In consideration of wiring delay, signal lines and scanning lines may be formed in the same manner.

An EL television receiver can be completed with the EL module having the panel configuration as described above. FIG. 65 is a block diagram showing the main configuration of an EL television receiver. A tuner 6501 receives a video signal and an audio signal. The video signal is amplified by the video signal amplifier circuit 6502.
A video signal processing circuit 6503 that converts signals output therefrom into color signals corresponding to red, green, and blue, and a control circuit 6206 that converts the video signals into the input specifications of the driving circuit. be done. The control circuit 6206 outputs signals to the scanning line side and the signal line side, respectively. In the case of digital driving, a signal dividing circuit 6207 may be provided on the signal line side to divide the input digital signal into M signals and supply them.

Of the signals received by tuner 6501 , audio signals are sent to audio signal amplifier circuit 6504 , and the output is supplied to speaker 6506 via audio signal processing circuit 6505 . The control circuit 6507 receives control information on the reception station (reception frequency) and volume from the input section 6508 and sends signals to the tuner 6501 and the audio signal processing circuit 6505 .

An EL module can be incorporated into a housing to complete a television receiver. A display portion is formed by the EL module. In addition, a speaker, a video input terminal, etc. are appropriately provided.

Of course, the present invention is not limited to television receivers, but can be applied to personal computer monitors,
It can be applied to various uses as a large-area display medium, such as an information display board at a railway station or an airport, or an advertisement display board on a street.

As described above, by using the display device and the method for driving the display device of the present invention, a clear image with reduced luminance variation can be displayed.

In addition, the present embodiment is an example of a case where the content (or part of it) described in another embodiment is embodied, an example of a slightly modified case, an example of a partially changed case, and an improved case. An example of the case,
An example of detailed description, an example of application, and an example of related parts are shown. Therefore, the contents described in other embodiments can be freely applied, combined, or replaced with this embodiment.

In the present embodiment, descriptions have been made using various diagrams, but the contents described in each diagram (
may be part of it) shall apply, combine, or
Alternatively, replacement can be freely performed. Furthermore, in the figures described so far, more figures can be configured by combining each part with another part.

Similarly, the content (may be part of) described in each drawing of this embodiment may be applied, combined, replaced, etc. with respect to the content (may be part of) described in the drawing of another embodiment. can be done freely. Furthermore, in the drawings of this embodiment, more drawings can be configured by combining each part with another embodiment.

(Embodiment 11)
Electronic devices using the display device of the present invention include video cameras, digital cameras, goggle-type displays (head-mounted displays), navigation systems, sound reproduction devices (car audio systems, audio components, etc.), laptop personal computers, game machines, Portable information terminals (mobile computers, mobile phones, portable game machines, e-books, etc.),
An image reproducing device equipped with a storage medium (specifically, a Digital Versatile Di
and a device equipped with a display capable of reproducing a storage medium such as sc (DVD) and displaying the image thereof. Specific examples of those electronic devices are shown in FIG.

FIG. 66A shows a self-luminous display including a housing 6601, a support base 6602, a display portion 6603, a speaker portion 6604, a video input terminal 6605, and the like. The present invention can be used for a display device that forms the display portion 6603, and a clear image with reduced luminance variation can be displayed. Since it is self-luminous, it does not require a backlight, and the display section can be made thinner than a liquid crystal display. The display includes all display devices for displaying information, such as for personal computers, for receiving TV broadcasts, and for displaying advertisements.

FIG. 66B shows a digital still camera including a main body 6606, a display portion 6607, and an image receiving portion 6.
608, operation keys 6609, an external connection port 6610, a shutter 6611, and the like. The present invention can be used for a display device forming the display portion 6607, and a clear image with reduced luminance variation can be displayed.

FIG. 66C shows a notebook personal computer including a main body 6612, a housing 6613,
It includes a display portion 6614, a keyboard 6615, an external connection port 6616, a pointing mouse 6617, and the like. The present invention can be used for a display device constituting the display portion 6614,
According to the present invention, it is possible to view a clear image with reduced variations in brightness.

FIG. 66D shows a mobile computer including a main body 6618, a display portion 6619, a switch 6620, operation keys 6621, an infrared port 6622, and the like. The present invention provides a display unit 661
9, and the present invention makes it possible to view clear images with reduced variations in brightness.

FIG. 66(E) shows an image reproducing device (specifically, for example, a DVD reproducing device) provided with a storage medium reading unit, and includes a main body 6623, a housing 6624, a display portion A 6625, a display portion B 6626, and a storage medium (DVD, etc.). ) includes a reading unit 6627, operation keys 6628, a speaker unit 6629, and the like.
The display portion A6625 mainly displays image information, and the display portion B6626 mainly displays character information. The present invention can be used for a display device that forms the display portion A 6625 and the display portion B 6626. According to the present invention, a clear image with reduced luminance variation can be viewed. Note that the image reproducing device equipped with a recording medium includes a home-use game machine.

FIG. 66(F) shows a goggle-type display (head-mounted display).
630, a display portion 6631, an arm portion 6632, and the like. The present invention can be used for a display device that forms the display portion 6631, and a clear image with reduced luminance variation can be displayed.

FIG. 66G shows a video camera including a main body 6633, a display portion 6634, a housing 6635, an external connection port 6636, a remote control receiving portion 6637, an image receiving portion 6638, and a battery 6639.
, voice input unit 6640, operation keys 6641, and the like. The present invention can be used for a display device forming the display portion 6634, and a clear image with reduced luminance variation can be displayed.

FIG. 66H shows a mobile phone including a main body 6642, a housing 6643, a display portion 6644, an audio input portion 6645, an audio output portion 6646, operation keys 6647, an external connection port 6648, an antenna 6649, and the like. The present invention can be used for a display device forming the display portion 6644 . Note that the display portion 6644 can reduce current consumption of the mobile phone by displaying white characters on a black background. Further, according to the present invention, it is possible to view a clear image with reduced variations in brightness.

If a light-emitting material with high emission luminance is used, it is possible to enlarge and project light containing output image information with a lens or the like and use it for a front-type or rear-type projector.

Moreover, in recent years, the above electronic devices often display information distributed through electronic communication lines such as the Internet and CATV (cable television), and in particular, opportunities to display moving image information are increasing. Since the response speed of the light-emitting material is very high, the light-emitting device is preferable for displaying moving images.

In addition, since the light-emitting portion of a light-emitting display device consumes power, it is desirable to display information so as to reduce the light-emitting portion as much as possible. Therefore, when a light-emitting type display device is used for a display portion mainly containing character information such as a mobile information terminal, particularly a mobile phone or an audio player, the character information is formed in the light-emitting portion with the non-light-emitting portion as the background. It is desirable to drive

As described above, the scope of application of the present invention is extremely wide, and it can be used in electronic devices in all fields. Further, the electronic device of this embodiment may use any of the display devices shown in Embodiments 1 to 10. FIG.

101 transistor 102 transistor 103 holding capacitor 104 scanning line 105 signal line 106 power line 107 capacitor line 108 light emitting element 123 insulating film 201 transistor 202 transistor 203 holding capacitor 204 scanning line 205 signal line 206 power line 207 capacitor line 208 light emitting element 301 transistor 302 Transistor 303 Transistor 304 Transistor 305 Transistor 306 Holding capacitor 307 Signal line 308 First scanning line 309 Second scanning line 310 Third scanning line 311 Fourth scanning line 312 Power supply line 313 Power supply line 314 Capacitance line 315 Light-emitting element 316 Light-emitting element 801 Transistor 802 Transistor 803 Transistor 804 Transistor 805 Transistor 806 Holding capacitor 807 Signal line 808 First scanning line 809 Second scanning line 810 Third scanning line 811 Fourth scanning line 812 Power supply line 813 Power supply line 814 Capacitance Line 815 Light-emitting element 2101 Transistor 2102 Transistor 2103 Transistor 2104 Transistor 2105 Transistor 2106 Holding capacitor 2107 Signal line 2108 First scanning line 2109 Second scanning line 2110 Third scanning line 2111 Fourth scanning line 2112 Power supply line 2113 Power supply line 2115 light-emitting element 2121 transistor 2122 transistor 2123 transistor 2124 transistor 2125 transistor 2126 storage capacitor 2128 first scanning line 2129 second scanning line 2130 third scanning line 2131 fourth scanning line 2135 light-emitting element 2149 second scanning line 2301 Transistor 2302 Transistor 2303 Transistor 2304 Transistor 2305 Transistor 2306 Holding capacitor 2307 Signal line 2308 First scanning line 2309 Second scanning line 2310 Third scanning line 2311 Fourth scanning line 2312 Power line 2315 Light-emitting element 2321 Transistor 2322 Transistor 2323 Transistor 2324 Transistor 2325 Transistor 2326 Holding capacitor 2328 First scanning line 2329 Second scanning line 2330 Third scanning line 2331 Fourth scanning line 2335 Light emitting element 2349 Second scanning line 2516 Transistor 2517 Fifth scanning line

Claims (2)

a P-channel first transistor, a P-channel second transistor, an N-channel third transistor, a P-channel fourth transistor, and a P-channel fifth transistor; having a capacitive element, a light emitting element, a signal line, and a power supply line,
one of the source and the drain of the first transistor is electrically connected to the signal line;
the other of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor;
the other of the source and the drain of the second transistor is electrically connected to the power supply line;
the other of the source or drain of the first transistor is electrically connected to one of the source or drain of the fifth transistor;
the other of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the third transistor;
the other of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the fourth transistor;
the gate of the fifth transistor is electrically connected to the other of the source or the drain of the third transistor;
a gate of the fifth transistor is electrically connected to the capacitive element;
the other of the source or drain of the fourth transistor is electrically connected to the light emitting element;
When an L level signal is input to the gate of the first transistor and the first transistor is turned on,
an H level signal is input to the gate of the second transistor to turn off the second transistor;
an H level signal is input to the gate of the third transistor to turn on the third transistor;
an H level signal is input to the gate of the fourth transistor to turn off the fourth transistor;
When the light emitting element emits light,
an H level signal is input to the gate of the first transistor to turn off the first transistor;
an L level signal is input to the gate of the second transistor to turn on the second transistor;
an L level signal is input to the gate of the third transistor to turn off the third transistor;
A display device in which an L level signal is input to the gate of the fourth transistor to turn on the fourth transistor. a P-channel first transistor, a P-channel second transistor, an N-channel third transistor, a P-channel fourth transistor, and a P-channel fifth transistor; having a capacitive element, a light emitting element, a signal line, and a power supply line,
one of the source and the drain of the first transistor is electrically connected to the signal line;
the other of the source or drain of the first transistor is electrically connected to one of the source or drain of the second transistor;
the other of the source and the drain of the second transistor is electrically connected to the power supply line;
the other of the source or drain of the first transistor is electrically connected to one of the source or drain of the fifth transistor;
the other of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the third transistor;
the other of the source or drain of the fifth transistor is electrically connected to one of the source or drain of the fourth transistor;
the gate of the fifth transistor is electrically connected to the other of the source or the drain of the third transistor;
a gate of the fifth transistor is electrically connected to the capacitive element;
the other of the source or drain of the fourth transistor is electrically connected to the light emitting element;
When an L level signal is input to the gate of the first transistor and the first transistor is turned on,
an H level signal is input to the gate of the second transistor to turn off the second transistor;
an H level signal is input to the gate of the third transistor to turn on the third transistor;
an H level signal is input to the gate of the fourth transistor to turn off the fourth transistor;
When the light emitting element emits light,
an H level signal is input to the gate of the first transistor to turn off the first transistor;
an L level signal is input to the gate of the second transistor to turn on the second transistor;
an L level signal is input to the gate of the third transistor to turn off the third transistor;
an L level signal is input to the gate of the fourth transistor to turn on the fourth transistor;
A display device in which the third transistor includes an oxide semiconductor in a channel formation region.

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