JP2022502907A - Methods and circuits for reducing wave heights for cable TV amplifiers - Google Patents

Abstract

The wave height reduction (CFR) system includes a digital gradient filter coupled to the input of the CFR system. In some embodiments, the digital gradient filter is configured to receive a system input signal and generate a digital gradient filter output signal at the digital gradient filter output. In some examples, the CFR system further comprises a CFR module coupled to the digital gradient filter output, which receives the digital gradient filter output signal and performs a CFR process on the digital gradient filter output signal. Therefore, the CFR module output is configured to generate a CFR module output signal. Further, the CFR system may include a digital tilt equalizer coupled to the CFR module output, which is configured to receive the CFR module output signal and generate a system output signal. [Selection diagram] FIG. 4A

Description

The examples of the present disclosure generally relate to integrated circuits (“ICs: integrated circuits”), and more specifically to embodiments relating to performing cable television (cable TV) amplifier wave height reduction.

The cable industry has adopted the new Data Over Cable Service Interface Specification (DCSIS) 3.1 standard to meet the demand for increased data rates for the Internet, telecommunications, and video services. We are deploying new high data rate and wideband remote PHY nodes based on this. DOCSIS 3.1 supports 4096 Quadrature Amplitude Modulation (QAM) and uses Orthogonal Frequency Division Multiplexing (OFDM). Therefore, the transmission signal quality requirements of DOCSIS 3.1 are much higher than the current standard DOCSIS 3.0. Cable television (CATV) amplifiers may operate in the non-linear region due to the higher functionality associated with DOCSIS 3.1. Due to the non-linear effect of the CATV amplifier, the quality of the transmitted signal is significantly reduced. In addition, the new components that provide higher functionality at the higher data rates of DOCSIS 3.1 consume power in their own right. However, since the power supply to each node (eg, each remote PHY node) is fixed, it is necessary to reduce the power consumption of other components (eg, CATV amplifier). Therefore, while it is desirable to provide the advanced performance of DOCSIS 3.1, it is possible to provide the advanced performance while improving the transmission signal quality and reducing the power consumption of other components (eg, CATV amplifier). It was difficult to do.

Therefore, there is a need for improved methods and circuits for reducing the peak factor of CATV amplifiers.

In some embodiments according to the present disclosure, the crest factor reduction (CFR) system comprises a digital tilt filter coupled to the input of the CFR system. In some embodiments, the digital gradient filter is configured to receive a system input signal and generate a digital gradient filter output signal at the digital gradient filter output. In some examples, the CFR system further comprises a CFR module coupled to the digital gradient filter output, which receives the digital gradient filter output signal and performs a CFR process on the digital gradient filter output signal. Therefore, the CFR module output is configured to generate a CFR module output signal. Further, the CFR system may include a digital tilt equalizer coupled to the CFR module output, which is configured to receive the CFR module output signal and generate a system output signal.

In some embodiments, the CFR system further comprises a digital predistortion (DPD) module coupled to the CFR module output, the DPD module receiving the CFR module output signal and relative to the CFR module output signal. It is configured to execute the DPD process and generate a DPD module output signal at the DPD module output. In some examples, the digital tilt equalizer is coupled to the DPD module output and the digital tilt equalizer is configured to receive the DPD module output signal and generate a system output signal.

In some embodiments, the system input signal has a first peak-to-average power ratio (PAPR) and the CFR module output signal is smaller than the first PAPR. Has PAPR.

In some embodiments, the CFR system further comprises a first linear data path that is coupled to the inputs of the CFR system in parallel with the CFR module and the DPD module to generate a first time delay signal. In some examples, the CFR system also includes a first combiner configured to combine a digital tilt equalizer output signal with a first time delay signal to produce a system output signal.

In some embodiments, the CFR system further comprises a second linear data path that is coupled to the input of the CFR system in parallel with the CFR module to generate a second time delay signal. As an example, the second combiner is configured to combine the CFR module output signal and the second time delay signal to generate the first output signal, and the third combiner is the first output signal and the DPD. It is configured to generate a system output signal in combination with a module output signal.

In some embodiments, the CFR system further comprises a non-linear data path coupled to the CFR module output, the non-linear data path comprising a plurality of parallel data path elements each coupled to the CFR module output and a plurality of parallels. Each of the data path elements is configured to add a different inverse nonlinear component to the CFR module output signal corresponding to the non-linear component of the amplifier, and the combiner combines the outputs of each of the multiple parallel data path elements into a DPD module output. It is configured to generate a signal.

In some embodiments, a digital-to-analog converter (DAC) is configured to receive a system output signal and generate a DAC output signal, and an analog gradient filter is a DAC output signal. Is configured to receive and generate an analog gradient filter output signal, and the digital gradient filter is configured to model the analog gradient filter.

In some embodiments, the digital tilt equalizer is configured to model the reciprocal of the analog tilt filter.

In some embodiments, the CFR system further comprises a single sideband hillbelt filter, the single sideband hillbelt filter input is configured to receive a DPD module output signal, and the single sideband hillbelt filter output is , Combined with the digital tilt equalizer input.

In some embodiments, the CFR system further comprises an adaptive engine configured to receive feedback data from the amplifier output, which is configured to update the configuration of the CFR module based on the feedback data. To.

In some embodiments according to the present disclosure, a digital front-end (DFE) system is configured to perform a peak factor reduction (CFR) process and the DFE system receives a baseband data input signal. And includes a digital upconverter (DUC) configured to convert and generate a composite signal. In various embodiments, the DFE system further comprises a CFR system, including a digital tilt filter, a CFR module, and a digital tilt equalizer, the digital tilt filter receiving a composite signal and generating a digital tilt filter output signal. The CFR module is configured to receive a digital tilt filter output signal, perform a CFR process on the digital tilt filter output signal, and generate a CFR module output signal, digital tilt equalization. The instrument is configured to receive the CFR module output signal and generate a CFR system output signal, which is coupled to the amplifier. In some examples, the DFE system further includes an adaptive engine configured to receive feedback data from the output of the amplifier, which is configured to update the configuration of the CFR system based on the feedback data. To.

In some embodiments, the CFR process is configured to reduce the peak-to-average power ratio (PAPR) of the digital gradient filter output signal.

In some embodiments, the CFR system further comprises a digital predistortion (DPD) module that includes a non-linear data path coupled to the CFR module output, and the non-linear data path is a plurality of parallels, each coupled to the CFR module output. Each of the multiple parallel data path elements, including the data path element, is configured to model a different inverse nonlinear component that corresponds to the non-linear component of the amplifier, and the combiner outputs each of the multiple parallel data path elements. Combined to generate a DPD module output signal, the digital tilt equalizer is configured to receive the DPD module output signal and generate a CFR system output signal.

In some embodiments, a digital-to-analog converter (DAC) is configured to receive a CFR system output signal and generate a DAC output signal, and an analog gradient filter receives the DAC output signal and analog tilt. The filter is configured to generate an output signal, and the digital gradient filter is configured to model an analog gradient filter.

In some embodiments, the digital tilt equalizer is configured to model the reciprocal of the analog tilt filter.

In some embodiments according to the present disclosure, the method comprises receiving an input signal at the digital gradient filter of a crest factor reduction (CFR) system and generating a digital gradient filter output signal at the digital gradient filter output. In various examples, the method further comprises performing a CFR process on the digital tilt filter output signal in the CFR module of the CFR system to generate the CFR module output signal, the CFR process performing the digital tilt filter output. It is configured to reduce the peak-to-average power ratio (PAPR) of the signal. In some examples, the method further comprises receiving a CFR module output signal and generating a system output signal with a digital tilt equalizer of the CFR system. In some embodiments, the method further comprises providing a system output signal to the amplifier.

In some embodiments, the method further comprises updating the configuration of the CFR system in response to feedback data received from the output of the amplifier.

In some embodiments, the method further comprises performing a DPD process on the CFR module output signal in the digital predistortion (DPD) module of the CFR system to generate the DPD module output signal. In some examples, the method further comprises receiving a DPD module output signal and generating a system output signal with a digital tilt equalizer of the CFR system.

In some embodiments, the DPD module further comprises a non-linear data path coupled to the output of the CFR module, and the non-linear data path comprises a plurality of parallel data path elements each coupled to the output of the CFR module. Each of the parallel data path elements is configured to model a different inverse nonlinear component that corresponds to the non-linear component of the amplifier, and the combiner combines the outputs of each of the multiple parallel data path elements to generate a DPD module output signal. It is configured to do.

In some embodiments, the method further comprises operating the amplifier in the non-linear region and reducing the power consumption of the amplifier in response to providing the system output signal to the amplifier.

In some embodiments according to the present disclosure, a digital predistortion (DPD) system comprises an input configured to receive a DPD input signal. In some embodiments, the DPD system further comprises a non-linear data path coupled to the input, the non-linear data path comprises a plurality of parallel data path elements each coupled to the input, and a plurality of parallel data path elements. Each is configured to add a different inverse nonlinear component to the DPD input signal corresponding to the non-linear component of the amplifier, and the first combiner combines the outputs of each of the plurality of parallel data path elements into a first predistortion. It is configured to generate a signal. In some embodiments, the DPD system comprises a linear data path coupled to the input in parallel with the nonlinear data path to produce a second predistortion signal, a first predistortion signal, and a second predistortion signal. Also includes a second combiner configured to combine to generate a DPD output signal.

In some embodiments, the plurality of parallel data path elements includes a baseband DPD data path, a video bandwidth DPD data path, a second harmonic DPD data path, and a third harmonic DPD data path.

In some embodiments, the baseband DPD data path is configured to add a inverse non-linear baseband component to the DPD input signal.

In some embodiments, the video bandwidth DPD data path is configured to add a inverse non-linear video bandwidth component to the DPD input signal.

In some embodiments, the second harmonic DPD data path is configured to add an inverse second harmonic component to the DPD input signal.

In some embodiments, the third harmonic DPD data path is configured to add an inverse third harmonic component to the DPD input signal.

In some embodiments, the DPD system further comprises a digital gradient filter configured to model an analog gradient filter, the digital gradient filter input is coupled to the input and the digital gradient filter output is coupled to the nonlinear data path. Will be done.

In some embodiments, the DPD system further comprises a digital tilt equalizer configured to model the inverse of the analog tilt filter, the digital tilt equalizer input receives a first predistortion signal. The second combiner is configured to combine the digital tilt equalizer output with the second predistortion signal to generate a DPD output signal.

In some embodiments, the DPD system further comprises a single sideband hillbelt filter, the single sideband hillbelt filter input is configured to receive a first predistortion signal, and the single sideband hillbelt filter. The output is coupled to the digital tilt equalizer input.

In some embodiments, the DPD output signal is coupled to the amplifier input to produce an amplified output signal, which is configured to compensate for the plurality of non-linear components of the amplifier.

In some embodiments according to the present disclosure, a digital front-end (DFE) system configured to perform a digital predistortion (DPD) process receives and converts a baseband data input signal to produce a composite signal. Includes a digital upconverter (DUC) configured as described above. In some embodiments, the DFE system further comprises a DPD system configured to receive a composite signal at the DPD input and perform a DPD process on the composite signal, where the DPD input is a plurality of parallel data paths. Combined to the element, at least one of the plurality of parallel data path elements is configured to add an inverse harmonic component to the composite signal corresponding to the non-linear harmonic component of the amplifier, and the combiner is configured to have multiple data paths. The outputs of each of the elements are combined to produce a DPD output signal, which is coupled to the amplifier. In some embodiments, the DPD output signal is configured to compensate for the non-linear harmonic component of the amplifier.

In some embodiments, the plurality of parallel data path elements includes a baseband DPD data path, a video bandwidth DPD data path, a second harmonic DPD data path, and a third harmonic DPD data path.

In some embodiments, the DUC is configured to perform an interpolation process on the baseband data input signal to generate an interpolated signal, and the DUC performs a mixing process on the interpolated signal to generate a composite signal. Is configured to generate.

In some embodiments, the DPD system further comprises a digital gradient filter configured to model an analog gradient filter, the digital gradient filter input is configured to receive a composite signal, and the digital gradient filter output. Is combined into multiple parallel data path elements.

In some embodiments, the DPD system further comprises a digital tilt equalizer configured to model the inverse of the analog tilt filter, the digital tilt equalizer input is each of the plurality of data path elements. It is configured to receive the combined output, and another combiner is configured to combine the digital tilt equalizer output with the linear DPD signal to produce a DPD output signal.

In some embodiments according to the present disclosure, the method comprises receiving a DPD input signal at the input of a digital predistortion (DPD) system. In some embodiments, the method further comprises receiving a DPD input signal in a nonlinear data path coupled to the input of the DPD system, where the nonlinear data path is a plurality of parallel data path elements each coupled to the input. including. In some embodiments, the method further comprises adding a inverse non-linear component to the DPD input signal corresponding to the non-linear component of the amplifier by each of the plurality of parallel data path elements. In some embodiments, the method further comprises combining the outputs of each of the plurality of parallel data path elements by a first combiner to generate a first predistortion signal. In some embodiments, the method further comprises receiving a DPD input signal in a linear data path coupled to the input in parallel with the nonlinear data path to generate a second predistortion signal. In some embodiments, the method further comprises combining a first predistortion signal with a second predistortion signal to generate a DPD output signal by a second combiner.

In some embodiments, the plurality of parallel data path elements includes a baseband DPD data path, a video bandwidth DPD data path, a second harmonic DPD data path, and a third harmonic DPD data path.

In some embodiments, the method is to add a inverse nonlinear baseband component to the DPD input signal by means of a baseband DPD data path and a inverse nonlinear video bandwidth component to the DPD input signal by video bandwidth DPD data path. And adding an inverse second harmonic component to the DPD input signal by the second harmonic DPD data path, and adding an inverse third harmonic component to the DPD input signal by the third harmonic DPD data path. Including adding and further.

In some embodiments, the method further comprises providing a DPD output signal to the amplifier input to generate an amplified output signal, the DPD output signal being configured to compensate for multiple non-linear components of the amplifier. ..

In some embodiments, the method further comprises operating the amplifier in the non-linear region and reducing the power consumption of the amplifier in response to providing the DPD output signal to the amplifier.

Other aspects and features will be clarified by reading the following detailed description and accompanying drawings.

FIG. 3 is a block diagram illustrating an exemplary architecture of an IC, according to some embodiments of the present disclosure. It is a schematic diagram of an exemplary cable network according to some embodiments. FIG. 3 is a schematic representation of an exemplary Digital Front End (DFE) system, according to some embodiments. FIG. 5 is a diagram of a Digital Predistortion (DPD) -Pulture Cavity Reduction (CFR) system according to some embodiments. It is a figure which shows an example of the DPD module by some embodiments. It is a figure which shows the exemplary DPD-CFR input spectrum and DPD-CFR output spectrum, respectively, by some embodiments. It is an exemplary plot diagram showing the normalized magnitude of the analog gradient filter output sampled over time and showing the effect of performing the CFR process, according to some embodiments. FIG. 5 shows a power spectrum at the output of an analog gradient filter after performing a CFR process, according to some embodiments. It is an exemplary plot diagram showing the normalized magnitude of the CATV amplifier output sampled over time and showing the effect of performing the CFR process, according to some embodiments. FIG. 6 is a diagram of a single carrier cumulative distribution function (CCDF) plot showing the effect of performing a CFR process according to some embodiments. FIG. 6 is a diagram of the power spectrum in which the CFR process was performed, corresponding to the data in FIG. 8A, according to some embodiments. Of the plot of the CATV amplifier transfer function, according to some embodiments, showing amplitude vs. amplitude distortion (AM / AM) and showing the effect of performing one or both of the DPD and CFR processes. It is a figure. FIG. 6 is a plot of DPD output stability performance showing the effect of performing the CFR process according to some embodiments. It is a table showing the effect on the MER data when the modulation error ratio (MER) data of the CATV amplifier is included and the correction provided by the DPD-CFR system is applied according to some embodiments. It is a flow diagram which shows the method for performing a wave height reduction process and a digital predistortion process in a DPD-CFR system according to some embodiments. It is a figure which shows the equation which provides the derivation of the nonlinear data path element of FIG. 4 by some embodiments, including a diagrammatic representation. It is a figure which shows the equation which provides the derivation of the nonlinear data path element of FIG. 4 by some embodiments, including a diagrammatic representation. It is a figure which shows the equation which provides the derivation of the nonlinear data path element of FIG. 4 by some embodiments, including a diagrammatic representation. It is a figure which shows the equation which provides the derivation of the nonlinear data path element of FIG. 4 by some embodiments, including a diagrammatic representation. It is a figure which shows the power spectrum of a single carrier which shows the non-linear effect of a CATV amplifier by some embodiments. FIG. 5 is a power spectrum diagram showing the results of applying baseband DPD correction to the power spectrum of FIG. 17 according to some embodiments. It is a figure of the power spectrum which shows the result of applying the 2nd harmonic DPD correction to the power spectrum of FIG. 17 by some embodiments. It is a figure of the power spectrum which shows the result of applying the 3rd harmonic DPD correction to the power spectrum of FIG. 17 by some embodiments. FIG. 3 is a power spectrum diagram showing the results of applying both baseband DPD correction and video bandwidth DPD correction according to some embodiments. FIG. 6 is a power spectrum diagram showing adjacent channel power ratio (ACPR) corrections resulting from the application of the corrections provided by the DPD system, according to some embodiments. It is a table showing the effect on the MER data when the modulation error ratio (MER) data of the CATV amplifier is included and the correction provided by the DPD system is applied according to some embodiments. FIG. 6 is a flow diagram illustrating a method for performing a digital predistortion process in a DPD system, according to some embodiments.

Hereinafter, various embodiments will be described with reference to the drawings showing exemplary embodiments. However, the claimed invention can be embodied in various forms and should not be construed as being limited to the embodiments described herein. Throughout, similar reference numbers refer to similar elements. Therefore, similar elements will not be described in detail with reference to the description of each figure. It should also be noted that the figures are only intended to facilitate the description of embodiments. The figure is neither intended as an exhaustive description of the claimed invention nor as a limitation to the scope of the claimed invention. Moreover, the illustrated embodiments do not necessarily have all of the aspects or advantages shown. The embodiments or advantages described with respect to a particular embodiment are not necessarily limited to that embodiment, even if not indicated to be possible in any other embodiment, or so explicit. Such implementation is possible even if it is not described in. Features, functions, and advantages may be achieved independently in various embodiments, or may be combined in yet other embodiments.

Before explaining the exemplary embodiments exemplified by some of the figures, a schematic introduction is provided for further understanding.

As explained above, the cable industry is launching new high data rate and wideband remote PHY nodes based on the DOCSIS 3.1 standard to meet the demand for improved data rates for the Internet, telephone communications, and video services. It is expanding. DOCSIS 3.1 supports 4096 (4K) Quadrature Amplitude Modulation (QAM) and uses Orthogonal Frequency Division Multiplexing (OFDM). Therefore, the transmission signal quality requirements of DOCSIS 3.1 are much higher than the current standard DOCSIS 3.0. Cable television (CATV) amplifiers may operate in the non-linear region due to the higher functionality associated with DOCSIS 3.1. Due to the non-linear effect of the CATV amplifier, the quality of the transmitted signal is significantly reduced. In addition, the new components that provide the higher data rates and more advanced features of DOCSIS 3.1 consume power in their own right. However, since the power supply to each node (eg, each remote PHY node) is fixed, it is necessary to reduce the power consumption of other components (eg, CATV amplifier). Therefore, while it is desirable to provide the advanced performance of DOCSIS 3.1, it is possible to provide the advanced performance while improving the transmission signal quality and reducing the power consumption of other components (eg, CATV amplifier). It was difficult to do.

At least some existing techniques use tilt equalizers (tilt filters) with significant attenuation of up to 22 dB over the 1.2 GHz cable spectrum to compensate for coaxial cable loss (eg, from CATV amplifiers to cable modems). ) Is implemented in the analog transmission line. However, the DOCSIS 3.1 waveform using 4K QAM OFDM modulation shows a high peak-to-average power ratio (PAPR) compared to the current DOCSIS 3.0 standard. Therefore, in the case of the same RMS power output of the CATV amplifier of DOCSIS3.0, the peak of the DOCSIS3.1 waveform is within the non-linear region of the CATV amplifier. Therefore, the transmission signal quality is deteriorated. Digital predistortion (DPD) can be used to improve the signal quality of a CATV amplifier, for example by operating the CATV in a more efficient region. DPDs have been used in wireless communication technologies where the signal bandwidth is much narrower than the bandwidth used in cable communication technologies. Moreover, in wireless communication, the harmonics of the non-linear effects of wireless components are not classified as signal bandwidth. Therefore, the DPD for wireless communication only needs to model the non-linear component projected around the baseband frequency. However, in cable applications, the harmonics of the non-linear effect of the CATV amplifier signal are classified as signal bandwidth. Therefore, in DPD implementations for cable applications, the harmonic content of the nonlinear effect of the CATV amplifier should be modeled. Apart from this, it is not possible to implement a tilt equalizer with significant attenuation in the digital domain, and mounting a digital tilt equalizer is due to the finite digital resolution of the digital-to-analog converter (DAC). As a result, the quality of the transmission waveform of the low frequency carrier deteriorates.

Moreover, as mentioned above, the DOCSIS 3.1 waveform using 4K QAM OFDM modulation shows higher PAPR compared to the current DOCSIS 3.0 standard. The effects of high PAPR include in-band and out-of-band distortion (including, for example, an increase in adjacent channel leakage power ratio (ACLR)). CFR reduction (CFR) can be used to reduce the PAPR of a signal by clipping the signal and allowing additional gain at the CFR output. Clipping works by deliberately limiting the signal so that the amplitude is limited to a maximum within the desired range. By adopting CFR, an amplifier (such as a CATV amplifier) can be operated close to its 1 dB compression point, thereby improving the efficiency of the CATV amplifier. In addition, in combination with DPD, CFR can be used to significantly improve the stability of DPD (eg, avoid divergence of DPD) and further improve the efficiency of CATV amplifiers. For integrated circuit (IC) solutions, the CFR and DPD data paths mounted within the digital front-end (DFE) chip provide a solution for the high PAPR, DPD stability, and CATV amplifier efficiency of the DCSIS 3.1 waveform. Together, it has been discovered that it can provide modeling of the harmonic components of the non-linear effects of CATV amplifiers and the significant attenuation over the transmission spectrum in CATV amplifiers. Accordingly, embodiments of the present disclosure provide improved transmission signal quality, improved efficiency of CATV amplifiers, and reduced power consumption of CATV amplifiers.

With the above schematic understanding in mind, various embodiments for providing methods and circuits for CFR of CATV amplifiers are outlined below. Since one or more of the above embodiments are exemplified using certain types of ICs, a detailed description of such ICs is given below. However, it should be understood that other types of ICs may benefit from one or more of the embodiments described herein.

A programmable logic device (“PLD”) is a well-known type of integrated circuit that can be programmed to perform a specified logic function. A field programmable gate array (“FPGA: field programmable gate array”), which is a type of PLD, typically includes an array of programmable tiles. These programmable tiles are, for example, input / output blocks (“IOB: input / output block”), configurable logic blocks (“CLB: composite logic block”), and dedicated random access memory blocks (“BRAM: random access memory block”). ”), Multipliers, digital signal processing blocks (“DSP: digital signal processing block”), processors, clock managers, delay lock loops (“DLL: memory lock loop”), and the like. As used herein, "includes" and "includes" means include without limitation.

Each programmable tile typically contains both programmable interconnects and programmable logic. The programmable interconnects typically include a number of interconnect lines of different lengths interconnected by programmable interconnect points (“PIPs”). Programmable logic implements user-designed logic using programmable elements that may include, for example, function generators, registers, arithmetic logic, and so on.

Programmable interconnects and programmable logic are typically programmed by loading a stream of configuration data that defines how the programmable elements are constructed into internal configuration memory cells. The configuration data can be read from memory (eg, from an external PROM) or written to the FPGA by an external device. The aggregated state of the individual memory cells then determines the function of the FPGA.

Another type of PLD is a complex programmable logic device (CPLD). CPLDs include two or more "functional blocks" that are connected to each other by an interconnect switch matrix and connected to input / output ("I / O") resources. Each functional block of the CPLD contains a two-level AND / OR structure similar to that used in programmable logic arrays (“PLA: Programmable Logical Array”) and programmable array logic (“PAL: Programmable Array Logic”) devices. .. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, the configuration data is stored on-chip in non-volatile memory and then downloaded to volatile memory as part of the initial configuration (programming) sequence.

Generally, in each of these programmable logic devices (“PLD”), the functionality of the device is controlled by the configuration data provided to the device for that purpose. Configuration data can be stored in volatile memory (eg, static memory cells common in FPGAs and some CPLDs), non-volatile memory (eg, flash memory in some CPLDs), or any other type of memory cell. Can be stored.

Other PLDs are programmed by applying a processing layer such as a metal layer that programmables various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example using fuse or anti-fuse technology. The terms "PLD" and "programmable logic device" include, but are not limited to, these exemplary devices, as well as partially programmable devices. For example, one type of PLD comprises a combination of hard-coded transistor logic and a programmable switch fabric that programmatically interconnects the hard-coded transistor logic.

As mentioned above, advanced FPGAs can include several different types of programmable logic blocks within an array. For example, FIG. 1 shows an exemplary FPGA architecture 100. The FPGA architecture 100 includes a multi-gigabit transceiver (“MGT: multi-gigabit transistor”) 101, a configurable logic block (“CLB”) 102, a random access memory block (“BRAM”) 103, an input / output block (“IOB”). 104, configuration and clocking logic (“CONFIG / CLOCKS”) 105, digital signal processing block (“DSP”) 106, specialized I / O block (“I / O”) 107 (eg, “I / O”) 107. Includes a number of different programmable tiles, including configuration ports and clock ports), as well as other programmable logic 108 such as digital clock managers, analog / digital converters, system monitoring logic, and the like. Some FPGAs also include a dedicated processor block (“PROC: processor block”) 110. In some embodiments, the FPGA Architecture 100 comprises a plurality of radio frequency analog / digital converters (RF-ADC: radio freedom analog-to-digital converter) and a plurality of radio frequency digital / analog converters (RF-DAC:). Includes an RF data converter subsystem, including a radio freedom digital-to-analog converter). In various examples, the RF-ADC and RF-DAC may be configured individually for real data or in pairs for real and imaginary I / Q data. In at least some examples, FPGA architecture 100 may implement RFSoC devices.

In some FPGAs, each programmable tile has at least one programmable interconnect that has connections to the input and output terminals 120 of programmable logic elements in the same tile, as shown by the example contained at the top of FIG. The element (“INT: integral”) 111 can be included. Each programmable interconnect element 111 may also include a connection of adjacent programmable interconnect elements within the same tile or other tile to the interconnect segment 122. Each programmable interconnect element 111 can also include a connection of common routing resources between logical blocks (not shown) to the interconnect segment 124. A common routing resource is routing between a logical block (not shown) containing tracks in an interconnect segment (eg, interconnect segment 124) and a switch block (not shown) for connecting the interconnect segments. Can include channels. An interconnect segment of a typical routing resource (eg, interconnect segment 124) can span one or more logical blocks. The programmable interconnect element 111 implements the illustrated programmable interconnect structure for FPGA (“programmable interconnect”), along with common routing resources.

In an exemplary implementation, the CLB 102 may be programmed to implement a single programmable interconnect element (“INT”) 111 in addition to the user logic (“CLE: configurable logical element”) 112. Can be included. The BRAM 103 can include a BRAM logical element (“BRL: BRAM logical element”) 113 in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements contained in a tile depends on the height of the tile. In the illustrated example, the height of the BRAM tile is the same as the 5 CLBs, but other numbers (eg, 4) can be used. The DSP tile 106 can include a DSP logical element (“DSPL: DSP logical element”) 114 in addition to an appropriate number of programmable interconnect elements. The IOB 104 can include, for example, one instance of the programmable interconnect element 111, as well as two instances of the input / output logical element (“IOL: input / output logical element”) 115. As will be apparent to those of skill in the art, for example, the actual I / O pad connected to the I / O logic element 115 is typically not limited to the area of the input / output logic element 115.

In the example of FIG. 1, the area (shown horizontally) near the center of the die (eg, formed by regions 105, 107, and 108 shown in FIG. 1) is configured, clocked, and other controls. Can be used for logic. Rows 109 (shown vertically) extending from this horizontal area or other rows may be used to distribute the clock and component signals over the width of the FPGA.

Some FPGAs that utilize the architecture shown in FIG. 1 include additional logical blocks that disrupt the regular columnar structure that makes up the majority of the FPGA. The additional logic blocks can be programmable blocks and / or dedicated logic. For example, PROC110 spans multiple columns of CLB and BRAM. The PROC 110 can include a variety of components ranging from a single microprocessor to a comprehensive programmable processing system such as a microprocessor, memory controller, peripherals and the like.

In one aspect, the PROC 110 is mounted as a dedicated circuit manufactured as part of a die that mounts the programmable circuit of the IC, eg, a hardwired processor. The PROC 110 has a variety of different processor types and / Or it may represent one of the systems.

In another aspect, PROC 110 is omitted from Architecture 100 and may be replaced with one or more of the other types of programmable blocks described. Further, such blocks are to form a "soft processor" in that, as in the case of PROC110, various blocks of programmable circuits can be used to form a processor capable of executing program code. May be used.

The term "programmable circuit" refers to programmable circuit elements within an IC, such as various programmable or configurable circuit blocks or tiles described herein, as well as various circuit blocks according to the configuration data loaded into the IC. It may refer to an interconnect circuit that selectively connects tiles and / or elements. For example, the part outside the PROC 110 such as CLB 102 and BRAM 103 shown in FIG. 1 can be regarded as a programmable circuit of an IC.

In some embodiments, the functionality and connectivity of the programmable circuit is not established until the configuration data is loaded into the IC. A set of configuration data can be used to program programmable circuits in ICs such as FPGAs. Configuration data is sometimes referred to as a "configuration bitstream." In general, programmable circuits do not operate or function unless the constituent bitstream is first loaded into the IC. Configuration bitstreams effectively implement or instantiate a particular circuit design within a programmable circuit. The circuit design specifies, for example, the functional aspects of the programmable circuit block and the physical connections between the various programmable circuit blocks.

In some embodiments, "hard-wired" or "hardened" or non-programmable circuits are manufactured as part of the IC. Unlike programmable circuits, hardwired circuits or circuit blocks are not implemented after the IC is manufactured by loading the constituent bitstream. Hardwired circuits are generally considered to have dedicated circuit blocks and interconnects that function, for example, without first loading the constituent bitstream into an IC, eg PROC 110.

In some cases, the hardwired circuit can have one or more modes of operation that can be set or selected according to register settings or values stored in one or more memory elements in the IC. The operation mode can be set, for example, by loading the constituent bitstream into the IC. Despite this functionality, hardwired circuits are not considered programmable circuits because they are operational and have specific functionality when manufactured as part of an IC.

FIG. 1 is intended to illustrate an exemplary architecture that can be used to implement a programmable circuit, eg, an IC that includes a programmable fabric. For example, the number of logical blocks in a row, the relative width of the row, the number and order of rows, the type of logical block contained in the row, the relative size of the logical block, and the interconnection / logical implementation included at the top of Figure 1. , Is just an example. For example, in a real IC, where CLB is displayed, usually contains two or more adjacent CLB rows to facilitate efficient implementation of user logic, but in adjacent CLB rows. The number varies with the overall size of the IC. Further, the FPGA in FIG. 1 shows an example of a programmable IC that can use the example of the interconnect circuit described herein. The interconnect circuits described herein can be used in other types of programmable ICs such as CPLDs, or in any type of programmable IC having a programmable interconnect structure for selectively coupling logic elements. can.

The ICs on which the methods and circuits for CFR of the CATV amplifier can be implemented are not limited to the exemplary ICs shown in FIG. Note that methods and circuits for CFR can be implemented.

Next, with reference to FIG. 2, a cable network 200 showing a signal path starting from a data fiber (which may include, for example, an optical fiber) and through a remote node to an end-user location (eg, at home) is shown. .. The cable network 200 can be part of a hybrid fiber coaxial network, where the data fiber runs from the central headend to the remote node and the coaxial cable runs from the remote node to the end user. In some examples, the remote node includes a remote PHY node based on the DOCSIS 3.1 standard. The remote PHY node, in some embodiments, includes a baseband and digital front-end (DFE) chip 202, a digital-to-analog converter (DAC) 204, and a driver 206 (eg, an amplifier). It may include an analog gradient filter 208, a power divider 210, and a CATV amplifier 212. In various examples, the baseband and DFE chip 202 may be mounted as a single chip or as separate chips including a baseband processor chip and a separate DFE chip. In some embodiments, the DAC 204 may be implemented as an RF DAC or an IF DAC, for example, depending on the input to the DAC 204. Further, in some embodiments, the baseband and DFE chip 202, as well as the DAC204, may be mounted as a single chip (eg, as in an RFSoC device). Further, one or more components of the remote PHY node may be implemented in a programmable logic device such as the programmable logic device of FIG. As shown in FIG. 2, the data fiber is connected as an input to the baseband and the DFE chip 202, and the output of the baseband and the DFE chip 202 is connected as an input to the DAC 204. The (no gradient) power spectrum 214 provides an example of the shape of the signal at the output of the baseband and DFE chip 202. The output of the DAC 204 is connected as an input to the driver 206, and the output of the driver 206 is connected as an input to the analog gradient filter 208. For cable applications, the analog gradient filter 208 can be used to change the gain of the entire power spectrum of the signal. In other words, the analog gradient filter 208 is used to add a gradient to the power level of the signal over the entire power spectrum. The power spectrum 216 shows the gradient of the signal at the output of the analog gradient filter 208 compared to the power spectrum 214 (eg, a positive gradient in this example).

In some embodiments, the output of the analog gradient filter 208 is connected as an input to the power divider 210. In the example of FIG. 2, the power divider 210 includes a 1x4 power divider having a single input and four outputs. However, in some embodiments, the power divider 210 is a 1x2 power divider having a single input and two outputs, a 1x2 power divider (eg, for producing four outputs). Cascade of, or another type of power divider may be included. In this example, each of the four outputs of the power divider 210 is connected as an input to the CATV amplifier 212. The output of each CATV amplifier 212 is then coupled to a coaxial cable, which is further coupled to the cable modem at the end user position (eg, at home). In at least some embodiments, the cable network 200 implements a node + 0 architecture, which is along the coaxial cable path between the remote PHY node and the end user location (beyond the CATV amplifier 212 on the remote PHY node). Means that there is no additional CATV amplifier. FIG. 2 further shows a power spectrum 218 showing a coaxial cable loss spectrum (eg with a negative gradient), a power spectrum 219 showing the output signal of the CATV amplifier 212, and a signal reaching the end user position (without a gradient). ) The power spectrum 220 showing the power spectrum is shown. As previously described, the analog gradient filter 208 is used to compensate for coaxial cable loss (eg, from the CATV amplifier 212 to the cable modem at the end user location).

In at least some existing cable networks, CATV amplifiers operate in the linear region. This is because the amount of non-linearity at the output of the CATV amplifier is small enough that no additional signal processing is required and the signal at the output of the CATV amplifier is at the end user position on the coaxial cable for demodulation and information transfer. Means that it can be sent directly to your cable modem. However, with the transition to more advanced features and additional power consumption components related to DOCSIS 3.1, the power supply to each node (eg, each remote PHY node) is limited and therefore, such as CATV amplifiers. It is desirable to reduce the power consumption of other components. Currently, the efficiency of CATV amplifiers is about 2-3%, so for example, a single CATV amplifier with an input power of 20 watts will output about 1/2 watts of output power. For four CATV amplifiers (eg, as shown in FIG. 2), an input power of 100 watts outputs an output power of about 2 watts. Therefore, it is highly desirable to make the CATV amplifier more efficient.

At least one option being considered to make the CATV amplifier more efficient is to operate the CATV amplifier in a more non-linear region. However, doing so means that without some additional digital signal processing, the signal at the output of the CATV amplifier cannot be transmitted directly to the end user location on the coaxial cable as provided by embodiments of the present disclosure. do. For example, the embodiments disclosed herein add functionality within the baseband and DFE chip 202, as described in more detail below, thereby the base even when the CATV amplifier operates in the non-linear region. The band and DFE chip 202 will be able to invert or alter the signal so that the signal at the output of the CATV amplifier is still linear and can be easily demodulated by the cable modem at the end user position. In other words, if the non-linearity of the CATV amplifier is "x", the functions in the baseband and DFE chip 202 have the inverse non-linearity "1 / x" offset by the non-linearity "x" of the CATV amplifier. Configured to add. Therefore, the signal at the output of the CATV amplifier is clean and linear. Generally, the process of pre-adding non-linearity (eg, adding inverse non-linearity in baseband and DFE chip 202) is called pre-distortion, or pre-distortion. Pre-distortion is sometimes referred to as digital pre-distortion (DPD) because distortion is added digitally in the context of baseband and DFE chip 202. According to various embodiments, the DPD process is performed using the knowledge of the type of non-linearity "x" possessed by the CATV amplifier (eg, CATV amplifier 212, etc.) so that the DPD process is properly inversely non-linear. The sex "1 / x" can be added. Therefore, according to embodiments of the present disclosure, the DPD process is a first function added within the baseband and DFE chip 202.

In addition, a second function added within the baseband and DFE chip 202 may include a CFR process. As described above, the CFR process may be used to reduce the PAPR of the signal by clipping the signal and allowing additional gain at the CFR output. By adopting CFR, the CATV amplifier can be operated close to its 1 dB compression point, which improves the efficiency of the CATV amplifier. In addition, in combination with the DPD process, the CFR process can be used to significantly improve the stability of the DPD (eg, avoid the divergence of the DPD) and further improve the efficiency of the CATV amplifier. In various embodiments, the DPD and CFR processes are between the baseband and DFE chip 202 and the CATV amplifier 212, including the efficiency and / or distortion provided by the DAC 204, the driver 206, and the analog gradient filter 208, respectively. It is carried out using the knowledge of the signal chain. In various embodiments, the DPD and CFR processes disclosed herein improve the efficiency of the CATV amplifier and reduce power consumption.

In some embodiments, the functions within the baseband and DFE chip 202 (including, for example, the DPD process and the CFR process) are implemented primarily as DFE functions in which the baseband output signal is provided as an input to the DFE chip. May be done. Accordingly, with reference to FIG. 3 herein, a DFE system 300 is shown that provides a DFE design configured to perform one or more aspects of the present disclosure. In some embodiments, the DFE system 300 comprises a digital upconverter (DUC) 302. In various examples, the DUC 302 connects one or more channels of data from a baseband signal to a set of one or more specified radio frequencies or intermediate frequencies (RF: radio frequency or IF: intermediate frequencies). Used to convert to a passband signal containing carriers modulated in. As an example, the DUC 302 performs interpolation (eg, to increase the sample rate), filters (eg, to provide spectral shaping and removal of interpolated images), and (eg, desired signal spectrum). This is achieved by mixing (to shift to the carrier frequency of). In general, the sample rate at the input to the DUC 302, eg the symbol rate of a digital communication system, is relatively low, but the output, eg the input sample to the DAC, which converts the digital sample to an analog waveform for further analog processing and frequency conversion. The rate is a much higher rate.

As shown in the example of FIG. 3, the DUC 302 is provided with a baseband data input. Baseband data inputs are represented by multiple different carriers as _{s 1} (n), s ₂ (n), s ₃ (n), s ₄ (n), s ₅ (n), and s _{6 (n).} including. In some embodiments, the sampling rate of the baseband data input is approximately 204.8 MHz, which corresponds to the OFDM symbol clock. As an example, the DUC 302 first generates multiple different carriers (eg, from the baseband data input) by performing an interpolation of the baseband data input, and in this example, this interpolation is used to set the sampling rate to 8. It is multiplied by (8), thereby migrating from the first clock domain (eg, 204.8 MHz clock domain) to the second clock domain (eg, 1638.4 MHz clock domain). After the interpolation process, in order to shift the frequency of each of the different carriers to the desired carrier frequency, each of the different carriers is from a numerically controlled oscillator (NCO), each of which has a different frequency. Mixed with the signal. For example, carrier s ₁ (n) is mixed with a first NCO (NCO 1) having a first frequency and carrier s ₂ (n) is mixed with a second NCO (NCO 2) having a second frequency. The carrier s ₃ (n) is mixed with a third NCO (NCO 3) having a third frequency, and the carrier s ₄ (n) is mixed with a fourth NCO (NCO 4) having a fourth frequency. The carrier s ₅ (n) is mixed with a fifth NCO (NCO 5) having a fifth frequency, and the carrier s ₆ (n) is mixed with a sixth NCO (NCO 6) having a sixth frequency. Will be done. After the mixing process, each of a plurality of different carriers is combined to form the synthetic signal c (n). Therefore, the combined signal c (n) includes each of a plurality of different carriers mixed at different frequencies. In some embodiments, as a result of the mixing process, the combined signal c (n) may appear substantially the same as the signal shown in FIG. 5A, where the frequencies are arranged side by side on each of a plurality of different carriers. be. In some cases, after the composite signal c (n) is generated, another interpolation process may be arbitrarily executed. In the example of FIG. 3, the interpolation process is used to determine the sampling rate of the composite signal c (n). It is doubled, thereby moving from a second clock domain (eg, a 1638.4 MHz clock domain) to a third clock domain (eg, a 3276.8 MHz clock domain). After signal processing by the DUC 302, the combined signal c (n) is provided as an input to the DPD-CFR system 304, which will be described in more detail below. In some embodiments, the output of the DPD-CFR system 304 undergoes a complex signal to real signal conversion 306, and the output of the complex signal to real signal conversion 306 is (eg, DAC204 in FIG. 2). (Get) Provided as an input to the DAC. Further, one or more components of the DFE system 300 may be implemented in a programmable logic device such as the programmable logic device of FIG.

As previously described, the DPD and CFR processes, and thus the DPD-CFR system 304, have knowledge of the type of non-linearity "x" that the CATV amplifier has, as well as the baseband and between the DFE chip 202 and the CATV amplifier 212. It works with the knowledge of the signal chain, so that the DPD-CFR system 304 is suitable (including, for example, adding the appropriate inverse nonlinearity "1 / x" and reducing the PAPR of the signal). DPD process and CFR process can be effectively carried out. For example, the DPD-CFR system 304 may be used to model a CATV amplifier (including, for example, non-linear effects and signal chains). Therefore, the model provided by the DPD-CFR system 304 may be generated and / or updated based on the feedback data 308, where the feedback data 308 is the output signal of the CATV amplifier (eg, for example, the CATV amplifier 212). It may be included. In some embodiments, the feedback data 308 is processed via an analog-to-digital converter (ADC) 310 and provided as digital feedback data 311 to the DPD / CFR adaptation engine 312. In various examples, the DPD / CFR adaptation engine 312 updates the DPD-CFR system 304 based on the digital feedback data 311 so that the DPD-CFR system 304 can adapt to the run-time behavior of the CATV amplifier. More specifically, in some embodiments, the DPD / CFR adaptive engine 312 may determine the coefficients of the filters or configurations of other elements within the DPD-CFR system 304, and in general, the DPD-CFR system. In 304, the CFR module and the DPD module described below may be configured. Therefore, the optimal DPD and CFR processes are implemented by continuously monitoring and updating the model provided by the DPD-CFR system 304 (eg, via feedback data 308 and DPD / CFR adaptation engine 312). can do. As an example, aspects of monitoring and updating a model (eg, features of the DPD / CFR adaptive engine 312) are implemented as software stored in memory (eg, in BRAM 103 or in another on-chip memory location). It may be run by one or more on-chip processors (eg, PROC110, etc.). Note that in some embodiments, the baseband and DFE chips 202, DAC204, and ADC310 can be mounted as a single chip (eg, as in an RFSoC device). The examples of monitoring and updating the model provided above are by no means meant to be limiting, other methods are possible, and embodiments of the present disclosure are not limited by any of the examples provided. Will be understood.

Here, with reference to FIG. 4A, a more detailed view of the above-mentioned DPD-CFR system 304 used to carry out various aspects of the present disclosure is shown. As shown, the DPD-CFR system 304 may include a digital tilt filter 402, a CFR module 404, a DPD module 406, a single sideband hillbelt filter 412, and a digital tilt equalizer 414. It should be noted that one or more components of the DPD-CFR system 304 may be implemented in a programmable logic device such as the programmable logic device of FIG.

として示すデジタル傾斜フィルタ４０２の出力は、ＣＦＲモジュール４０４への入力として提供される。様々な実施形態では、ＣＦＲモジュール４０４は、入ってくる信号（たとえば、デジタル傾斜フィルタ４０２の出力

）のＰＡＰＲを低減するためにＣＦＲプロセスを実行してもよい。本実施形態は、ＣＦＲモジュール４０４によって使用される特定のＣＦＲ技法に限定されないが、例示的なＣＦＲ技法には、適応ベースバンド、中間周波数（ＩＦ）クリッピングおよびフィルタリング、ピークウィンドウイング、または別の適切な技法が含まれ得る。ＣＦＲプロセスの後、ＣＦＲモジュール４０４は、

として示す出力を、ＤＰＤモジュール４０６に提供する。図示のように、デジタル傾斜フィルタ４０２の出力（

）はまた、データ経路４２１に沿って提供され、（たとえば、ブロック４２３において）信号

に時間遅延が導入される。例として、ＣＦＲモジュール４０４の出力（

）はさらに、データ経路４２７に沿って提供され、次いで、コンバイナ４２５を使用して、ＣＦＲモジュール４０４の出力（

）を時間遅延信号

と組み合わせて、信号

をもたらす。 The function of the DPD-CFR system 304 will be described in more detail with reference to FIG. 4A. For example, in some embodiments, an input signal x (n) that may include the combined signal c (n) described above is provided in the digital gradient filter 402. In various cases, the digital tilt filter 402 may be used to model the analog tilt filter 208 (FIG. 2). Therefore, as an example, the output of the digital tilt filter 402 can be similar to the output of the analog tilt filter 208. In some embodiments,

The output of the digital tilt filter 402, shown as, is provided as an input to the CFR module 404. In various embodiments, the CFR module 404 is an incoming signal (eg, the output of a digital tilt filter 402).

) CFR process may be performed to reduce PAPR. The present embodiment is not limited to the particular CFR technique used by the CFR module 404, but exemplary CFR techniques include adaptive baseband, intermediate frequency (IF) clipping and filtering, peak windowing, or another suitable. Techniques can be included. After the CFR process, the CFR module 404

The output shown as is provided to the DPD module 406. As shown, the output of the digital tilt filter 402 (

) Is also provided along the data path 421 and is a signal (eg, in block 423).

Introduces a time delay. As an example, the output of CFR module 404 (

) Are further provided along the data path 427, and then using the combiner 425, the output of the CFR module 404 ().

) Time delay signal

In combination with the signal

Bring.

に追加するために使用される。図４Ｂを参照すると、ＤＰＤモジュール４０６のより詳細な図が示されている。図示のように、ＣＦＲモジュール４０４の出力（

）は、非線形データ経路４０５を含むＤＰＤモジュール４０６への入力として提供される。様々な実施形態では、非線形データ経路４０５は、ビデオ帯域幅ＤＰＤデータ経路４０８、ベースバンドＤＰＤデータ経路４０９、第２高調波ＤＰＤデータ経路４１０、および第３高調波ＤＰＤデータ経路４１１を含む複数の異なる並列データ経路要素を含む。一般に、非線形データ経路４０５は、ＣＡＴＶ増幅器の逆非線形挙動をモデル化して入ってくる信号に追加するために使用される。より具体的には、非線形データ経路４０５の異なる並列データ経路要素のそれぞれを使用して、ＣＡＴＶ増幅器の逆非線形挙動の異なる態様をモデル化し、入ってくる信号（たとえば、ＣＦＲモジュール４０４の出力（

）に追加する。たとえば、ビデオ帯域幅ＤＰＤデータ経路４０８は、逆非線形ビデオ帯域幅成分をモデル化および追加してもよく、ベースバンドＤＰＤデータ経路４０９は、逆非線形ベースバンド成分をモデル化および追加してもよく、第２高調波ＤＰＤデータ経路４１０は、逆第２高調波成分をモデル化および追加してもよく、第３高調波ＤＰＤデータ経路４１１は、逆第３高調波成分をモデル化および追加してもよい。図示のように、次いで、ビデオ帯域幅ＤＰＤデータ経路４０８、ベースバンドＤＰＤデータ経路４０９、第２高調波ＤＰＤデータ経路４１０、および第３高調波ＤＰＤデータ経路４１１のそれぞれの出力が組み合わされて、ＣＡＴＶ増幅器のベースバンド成分、ビデオ成分、および高調波成分をモデル化する合成信号ｘ’（ｎ）を提供する。 In some embodiments, the DPD module 406 models the inverse baseband component, video component, and harmonic component of the CATV amplifier and the incoming signal.

Used to add to. Referring to FIG. 4B, a more detailed view of the DPD module 406 is shown. As shown, the output of the CFR module 404 (

) Is provided as an input to the DPD module 406, which includes a nonlinear data path 405. In various embodiments, the nonlinear data path 405 is a plurality of different, including a video bandwidth DPD data path 408, a baseband DPD data path 409, a second harmonic DPD data path 410, and a third harmonic DPD data path 411. Includes parallel data path elements. Generally, the nonlinear data path 405 is used to model the inverse nonlinear behavior of the CATV amplifier and add it to the incoming signal. More specifically, each of the different parallel data path elements of the nonlinear data path 405 is used to model different aspects of the inverse nonlinear behavior of the CATV amplifier and the incoming signal (eg, the output of the CFR module 404 (eg, the output of the CFR module 404).

). For example, the video bandwidth DPD data path 408 may model and add inverse harmonic video bandwidth components, and the baseband DPD data path 409 may model and add inverse nonlinear baseband components. The second harmonic DPD data path 410 may model and add the inverse second harmonic component, and the third harmonic DPD data path 411 may model and add the inverse third harmonic component. good. As shown, the outputs of the video bandwidth DPD data path 408, the baseband DPD data path 409, the second harmonic DPD data path 410, and the third harmonic DPD data path 411 are then combined to form a CATV. Provided is a synthetic signal x'(n) that models the baseband component, video component, and harmonic component of the amplifier.

が組み合わされて、信号ｘ’’（ｎ）をもたらす。その後、信号ｘ’’（ｎ）は、信号ｘ’（ｎ）をさらに変調するために使用され得る単側波帯ヒルベルトフィルタ４１２への入力として提供され、単側波帯ヒルベルトフィルタ４１２の出力は、デジタル傾斜等化器４１４への入力として提供される。例として、デジタル傾斜等化器４１４は、アナログ傾斜フィルタ２０８（図２）の逆数をモデル化し、入ってくる信号に追加するために使用されてもよい。したがって、例として、デジタル傾斜等化器４１４の出力は、アナログ傾斜フィルタ２０８の効果によって影響を受けない可能性がある（たとえば、または効果を打ち消す可能性がある）。図４Ａに示すように、いくつかの実施形態では、入力信号ｘ（ｎ）は、線形データ経路である経路４１６に沿っても送信される。いくつかの例では、データ経路４１６は、（たとえば、ブロック４１７において）単に入力信号ｘ（ｎ）に時間遅延を導入してもよい。さらに、データ経路４１６に沿って送信される入力信号ｘ（ｎ）は、デジタル傾斜フィルタ４０２、ＣＦＲモジュール４０４、ＤＰＤモジュール４０６、単側波帯ヒルベルトフィルタ４１２、およびデジタル傾斜等化器４１４をバイパスする。したがって、データ経路４１６に沿って送信される入力信号ｘ（ｎ）の信号変調の品質は、ＤＰＤ−ＣＦＲシステム３０４の他の要素による影響を受けないままとなる。また、図４Ａに示すように、コンバイナ４３１によってデジタル傾斜等化器４１４の出力と時間遅延入力信号ｘ（ｎ）４１９が組み合わされて、出力信号ｚ（ｎ）を提供する。図２、図３、および図４Ａを参照すると、ＤＰＤ−ＣＦＲシステム３０４の出力ｚ（ｎ）は、ＲＦ ＤＡＣ２０４およびアナログ傾斜フィルタ２０８によってさらに処理されて、信号ｙ（ｎ）をもたらすことができる。例として、信号ｙ（ｎ）は、

として算出されてもよく、ここで、ＡＴＦ＝アナログ傾斜フィルタであり、ＤＴＥ＝デジタル傾斜等化器であり、記号「＊」は数学的な畳み込み演算を表すために使用され、ＤＴＥ＊ＡＴＦ＝１（単位伝達関数）である。 Returning to FIG. 4A, the combiner 429 causes the output of the nonlinear data path 405 (eg, the combined signal x'(n)) and the signal.

Are combined to give the signal x'' (n). The signal x'' (n) is then provided as an input to the single sideband hillbelt filter 412 which can be used to further modulate the signal x'(n), and the output of the single sideband hillbelt filter 412 is , Provided as an input to the digital tilt equalizer 414. As an example, the digital tilt equalizer 414 may be used to model the reciprocal of the analog tilt filter 208 (FIG. 2) and add it to the incoming signal. Thus, as an example, the output of the digital tilt equalizer 414 may be unaffected by the effects of the analog tilt filter 208 (eg, or may negate the effects). As shown in FIG. 4A, in some embodiments, the input signal x (n) is also transmitted along the path 416, which is a linear data path. In some examples, the data path 416 may simply introduce a time delay into the input signal x (n) (eg, in block 417). Further, the input signal x (n) transmitted along the data path 416 bypasses the digital tilt filter 402, the CFR module 404, the DPD module 406, the single sideband hillbelt filter 412, and the digital tilt equalizer 414. .. Therefore, the quality of the signal modulation of the input signal x (n) transmitted along the data path 416 remains unaffected by other elements of the DPD-CFR system 304. Further, as shown in FIG. 4A, the combiner 431 combines the output of the digital tilt equalizer 414 with the time delay input signal x (n) 419 to provide the output signal z (n). With reference to FIGS. 2, 3 and 4A, the output z (n) of the DPD-CFR system 304 can be further processed by the RF DAC 204 and the analog tilt filter 208 to result in the signal y (n). As an example, the signal y (n) is

Here, ATF = analog tilt filter, DTE = digital tilt equalizer, the symbol "*" is used to represent a mathematical convolution operation, and DTE * ATF = 1. (Unit transfer function).

Referring to FIG. 5A, an exemplary input spectrum 502 is provided. In some embodiments, the input signal x (n) (FIG. 4A) may include an input spectrum 502. As mentioned above, the input spectrum 502 may include each of a plurality of different carriers mixed at different frequencies as previously described (eg, by DUC 302), each of the plurality of different carriers starting from about 66 MHz. Frequencies are arranged side by side over the entire bandwidth up to about 1218 MHz. Referring to FIG. 5B, an exemplary output spectrum 504 is provided. In some embodiments, the output signal z (n) (FIG. 4A) may include an output spectrum 504. As shown in FIG. 5B, the output spectrum 504 contains one or more nonlinear components 506 added to the signal by the DPD-CFR system 304. As a result of the processing performed by the DPD-CFR system 304, the efficiency and signal quality of the CATV amplifier is improved and power consumption is reduced.

Here, with reference to FIGS. 6A, 6B, 7A, 7B, 7C, 8A, 8B, 9A, 9B, 10A, 10B, and 11, various embodiments of the present disclosure. Multiple data are shown showing at least some of the benefits and benefits of. First referring to FIG. 6A, a plot 602 showing the normalized magnitude of the tilt filter output sampled over time (eg, analog tilt filter 208, etc.) is shown. Plot 602 includes a first data set 604 for which the CFR process was not performed. Therefore, the first dataset 604 shows a large (eg, greater than about 0.78) peak, which can result in higher non-linearity in the CATV amplifier. Plot 602 also includes a second dataset 606 in which the CFR process was performed and the peak magnitude was reduced (eg, to less than about 0.78). Therefore, the reduction in peaks provided by the CFR process improves the efficiency of the CATV amplifier. In addition, the CFR process can be performed without compromising the performance of the modulation error ratio (MER). FIG. 6B shows plot 608 showing the power spectrum 610 where the CFR process was performed (eg, at the output of the analog gradient filter 208), showing the advantage that the CFR process reduces the magnitude of the peaks. Note that the data shown in FIGS. 6A and 6B include simulated data and the analog gradient filter 208 has been replaced by a digital model for simulation purposes.

Referring to FIGS. 7A, 7B, and 7C, plots 702, 708, 714 showing normalized magnitudes of amplifier outputs sampled over time (eg, CATV amplifier 212, etc.) are shown. In general, the data in plots 702, 708, 714 may provide a validation of the effectiveness of the CFR process and may include snapshots of feedback data (eg, feedback data 308, etc.). As mentioned above, such feedback data may include the output signal of the CATV amplifier, and the DPD / CFR adaptation engine 312 uses that output signal to allow the DPD / CFR system 304 to adapt to the run-time behavior of the CATV amplifier. The model in the DPD-CFR system 304 can be updated to be compatible. In some cases, the data in plots 702, 708, 714 to observe and adapt the system in real time (eg, via the DPD-CFR system 304) to provide consistency between different CATV amplifiers. Snapshots of feedback data from different CATV amplifiers may be provided. Alternatively, in some examples, to observe the performance of a particular CATV amplifier over time, the data in plots 702, 708, 714 is a snapshot of the feedback data in a particular CATV amplifier at different time frames. May be provided. Referring now to FIG. 7A, plot 702 includes a first dataset in which the CFR process was not performed, the first dataset having peak 704 (eg, greater than about 0.78 in magnitude). Including, it may indicate higher non-linearity in the CATV amplifier. Plot 702 also includes a second dataset 706 in which the CFR process was performed and the peak magnitude was reduced (eg, to less than about 0.78). Similarly, plots 708 (FIG. 7B) and plots 714 (FIG. 7C) show peaks 710, 716 of the dataset in which the CFR process was not performed, and datasets 712, 718 in which the CFR process was run. As before, the reduction in peaks provided by the CFR process improves the efficiency of the CATV amplifier.

Referring here to FIG. 8A, a single carrier cumulative distribution function (CCDF) plot 802 at 1122 MHz is shown, resulting from the first CCDF curve 804 without running the CFR process, and the result of running the CFR process. The second CCDF curve 806 is shown. The CCDF curve is used to indicate the time a signal spends above a given power level, where the power level is expressed in dB with respect to the average signal power (eg, peak factor). In other words, the CCDF curve is used to indicate the probability that a signal is above a given power level. Referring to FIG. 8A, the x-axis indicates a dB value above the average signal power (eg, peak factor), and the y-axis indicates the percentage of time the signal spends above the power level specified by the x-axis. The second CCDF curve 806 (with CFR) has a crest rate reduced by about 2 dB as compared with the first CCDF curve 804 (without CFR). As a result, CATV amplifiers are expected to provide more consistent and more efficient performance. FIG. 8B provides a plot 808 showing the power spectrum 810 in which the CFR process was performed, corresponding to the second CCDF curve 806 (with CFR) and whose peak rate was reduced by the CFR process.

Referring to FIGS. 9A and 9B, plots 902,908 of the CATV amplifier transfer function showing amplitude vs. amplitude (AM / AM) distortion are shown, where AM / AM distortion measures the compression or expansion of signal gain. Used to do. In other words, if the gain of the CATV amplifier is no longer constant with respect to the input power (eg, the output power is no longer linearly related to the input power), the non-linearity of the AM / AM distortion increases. In this example, plot 902 (FIG. 9A) provides data on which the CFR process is not performed, and plot 908 (FIG. 9B) provides data on which the CFR process is performed. Further, the plot 902 includes a first curve 904 in which the DPD process is not executed and a second curve 906 in which the DPD process is executed. Referring to the first curve 904, it can be seen that the larger the input power, the more the compression of the output power (for example, it is clear that the non-linearity of the CATV amplifier increases). Using the DPD process (without CFR), the second curve 906 shows that it is possible to substantially correct the non-linearity of the CATV amplifier and reduce signal compression. Plot 908 also includes a first curve 910 in which the DPD process is not performed and a second curve 912 in which the DPD process is performed. By running the CFR process (for the data shown in plot 908) and reducing PAPR, the normalized input power is limited to about 0.8. Therefore, referring to the first curve 910 (without DPD), signal compression is relatively low, resulting in more controlled and efficient performance of the CATV amplifier. In this example, the second curve 912 is the first curve because using the DPD process (with CFR) reduces the non-linearity that the DPD process modifies by limiting the input power (by the CFR process). It shows that the improvement is slight compared to 910.

10A and 10B provide exemplary DPD performance (eg, DPD output stability performance) with and without the CFR process. FIG. 10A includes plot 1002 that provides data on which the CFR process is not performed, and FIG. 10B includes plot 1008 that provides data on which the CFR process is performed. Further, plot 1002 (without CFR) includes a first curve 1004 representing a DPD input signal and a second curve 1006 representing a DPD output signal. In this example, the DPD output signal (1006) is not stable without the CFR process and begins to diverge beyond the DPD output signal range of about 2. As described above, since the CATV amplifier has high non-linearity, the larger the input power, the more the compression of the output power increases. In order to avoid the operation of the CATV amplifier in such a high power region, the CFR process can be executed. For example, plot 1008 (with CFR) includes a first curve 1010 representing a DPD input signal and a second curve 1012 representing a DPD output signal. In this example, since the CFR process is performed, the DPD output signal (1012) is stable and does not diverge. For the data in plot 1008, a 1.3 dB CFR was applied. However, in various embodiments, the amount of CFR applied may be adjusted as needed for a particular CATV amplifier or for a particular installation / deployment. Further, although this disclosure describes the benefits of both DPD and CFR, it should be understood that various embodiments may use one or both of the DPD and CFR processes. However, in at least some examples, by using both the DPD process and the CFR process for a given deployment, maximum CATV amplifier efficiency can be achieved while avoiding DPD divergence.

Referring to FIG. 11, a table showing the effect on the MER data when applying the correction provided by the DPD-CFR system 304, including the modulation error ratio (MER) data of the CATV amplifier, is shown. As an example, MER is a measurement used to quantify the performance of a digital radio (or digital TV) transmitter or receiver in a communication system that uses digital modulation (such as QAM). In the case of the example of FIG. 11, the CATV amplifier module under test can operate at V = 34V. Comparing the MER data with the specifications of the cable industry, MER = 41 dB, 4KQAM, 76.8 dBmV / 75Ω. The CATV amplifier has been tested with 6 carriers, the first carrier is a 4K QAM signal with a carrier frequency of 204 MHz, the second carrier is a 4K QAM signal with a carrier frequency of 396 MHz, and the third carrier is. The carrier frequency is a 4K QAM signal with a carrier frequency of 588 MHz, the fourth carrier is a 4K QAM signal with a carrier frequency of 786 MHz, the fifth carrier is a 4K QAM signal with a carrier frequency of 930 MHz, and the sixth carrier is a carrier frequency. It is a 4K QAM signal of 1122 MHz. In the first test 1102, when the CATV amplifier operates at a bias current of 440 mA and there is no DPD correction or CFR correction, none of the tested carriers meet the specification of MER = 41 dB. In the second test 1104, if the CATV amplifier operates at a bias current of 440 mA, has DPD correction, and does not have CFR correction, the first carrier does not meet the specification of MER = 41 dB. In addition, in the second test 1104, the stability of the DPD is reduced and the divergence of the DPD occurs. In the third test 1106, the CATV amplifier operates at a bias current of 440 mA, both DPD and CFR corrections are applied, all the carriers tested meet the MER = 41 dB specification, and DPD divergence is avoided. .. Also, by operating the CATV amplifier at a bias current of 440 mA, a reduction of approximately 3 watts per amplifier can be achieved while maintaining MER performance (compared to some applications where the CATV amplifier operates at a bias current of 530 mA). Please also note.

（図４Ａ）として示される信号を含み、第１の出力信号は、

（図４Ａ）として示される信号を含む。方法１２００はブロック１２０６に進み、ＤＰＤ−ＣＦＲシステムのＤＰＤモジュールで、第１の出力信号に対してＤＰＤプロセスが実行されて、ＤＰＤ−ＣＦＲ出力信号を生成する。いくつかの実施形態では、ＤＰＤモジュールは、ＣＦＲモジュールの出力に結合された非線形データ経路を含む。さらに、ＤＰＤモジュールの非線形データ経路は、図４Ｂの非線形データ経路４０６を含んでもよい。したがって、非線形データ経路は、複数の並列データ経路要素を含んでもよい。いくつかの例では、複数の並列データ経路要素は、ビデオ帯域幅ＤＰＤデータ経路４０４、ベースバンドＤＰＤデータ経路４０６、第２高調波ＤＰＤデータ経路４０８、および第３高調波ＤＰＤデータ経路４１０を含む。いくつかの例では、異なる並列データ経路要素のそれぞれを使用して、入ってくる信号に、ＣＡＴＶ増幅器の逆非線形挙動の異なる態様を追加してもよい。いくつかの実施形態では、コンバイナは、複数の並列データ経路要素のそれぞれの出力を組み合わせて、合成信号ｘ’（ｎ）（図４Ｂ）を生成し、合成信号ｘ’（ｎ）は、ＣＡＴＶ増幅器のベースバンド成分、ビデオ成分、および高調波成分をモデル化する。様々な実施形態では、方法１２００はブロック１２０８に進み、ＤＰＤ−ＣＦＲ出力信号は、ＣＡＴＶ増幅器（たとえば、図２のＣＡＴＶ増幅器２１２など）に提供される。本開示の実施形態によれば、ＤＰＤ−ＣＦＲ出力信号は、信号のＰＡＰＲを低減し、ＣＡＴＶ増幅器の複数の非線形成分を補償するように構成される。次いで、方法１２００はブロック１２１０に進み、ＣＡＴＶ増幅器の出力から受信されたフィードバックデータ（たとえば、図３のフィードバックデータ３０８など）を使用して、ＤＰＤ−ＣＦＲシステムの構成を更新してもよい。方法１２００の前、最中、および後に追加の方法ステップが実施されてもよく、本開示の範囲から逸脱することなく、方法１２００の様々な実施形態に従って、上記のいくつかの方法ステップが置き換えられるか、または削除され得ることが理解されよう。 Here, with reference to FIG. 12, a method 1200 for performing a wave height reduction process and a digital predistortion process in a DPD-CFR system according to various embodiments is shown. Method 1200 starts at block 1202 and receives an input signal at the input of a DPD-CFR system such as the DPD-CFR system 304 of FIG. 4A. As mentioned above, in some embodiments, the input signal may include the input signal x (n) (FIG. 4A), further the input signal x (n) is a composite generated by the DUC 302 (FIG. 3). The signal c (n) may be included. In some examples, method 1200 proceeds to block 1204, where the CFR module of the DPD-CFR system performs a CFR process on the input signal to produce a first output signal. For example, the CFR process may be performed by the CFR module 404 (FIG. 4A). In various cases, the CFR process is performed to reduce the peak-to-average power ratio (PAPR) of the input signal. In some embodiments, the input signal is

The first output signal includes the signal shown as (FIG. 4A).

Includes the signal shown as (FIG. 4A). Method 1200 proceeds to block 1206, where the DPD module of the DPD-CFR system executes a DPD process on the first output signal to generate a DPD-CFR output signal. In some embodiments, the DPD module comprises a non-linear data path coupled to the output of the CFR module. Further, the nonlinear data path of the DPD module may include the nonlinear data path 406 of FIG. 4B. Therefore, the nonlinear data path may include a plurality of parallel data path elements. In some examples, the plurality of parallel data path elements includes a video bandwidth DPD data path 404, a baseband DPD data path 406, a second harmonic DPD data path 408, and a third harmonic DPD data path 410. In some examples, each of the different parallel data path elements may be used to add different aspects of the inverse nonlinear behavior of the CATV amplifier to the incoming signal. In some embodiments, the combiner combines the outputs of each of the plurality of parallel data path elements to generate a composite signal x'(n) (FIG. 4B), where the composite signal x'(n) is a CATV amplifier. Model the baseband, video, and harmonic components of. In various embodiments, method 1200 proceeds to block 1208 and the DPD-CFR output signal is provided to a CATV amplifier (eg, CATV amplifier 212 in FIG. 2). According to embodiments of the present disclosure, the DPD-CFR output signal is configured to reduce the PAPR of the signal and compensate for multiple non-linear components of the CATV amplifier. Method 1200 may then proceed to block 1210 and use the feedback data received from the output of the CATV amplifier (eg, feedback data 308 in FIG. 3) to update the configuration of the DPD-CFR system. Additional method steps may be performed before, during, and after method 1200, replacing some of the above method steps according to various embodiments of method 1200 without departing from the scope of the present disclosure. It will be understood that it can be deleted or deleted.

The various configurations (eg, components of the cable network 200, DFE system 300, and DPD-CFR system 304, the number of parallel data path elements in FIG. 4B, and other features and components shown in the figure) are merely. It should be noted that this is an example and is not limited beyond what is specifically stated in the appended claims. Those skilled in the art will appreciate that other configurations may be used. Also, although an exemplary cable network 200 is shown, the DPD-CFR system disclosed herein may include other communications, eg, if another communication system has an amplifier that exhibits detrimental non-linear behavior. Can be used in the system.

As explained above, the cable industry is launching new high data rate and wideband remote PHY nodes based on the DOCSIS 3.1 standard to meet the demand for improved data rates for the Internet, telephone communications, and video services. It is expanding. DOCSIS 3.1 supports 4096 (4K) Quadrature Amplitude Modulation (QAM) and uses Orthogonal Frequency Division Multiplexing (OFDM). Therefore, the transmission signal quality requirements of DOCSIS 3.1 are much higher than the current standard DOCSIS 3.0. Cable television (CATV) amplifiers may operate in the non-linear region due to the higher functionality associated with DOCSIS 3.1. Due to the non-linear effect of the CATV amplifier, the quality of the transmitted signal is significantly reduced. In addition, the new components that provide the higher data rates and more advanced features of DOCSIS 3.1 consume power in their own right. However, since the power supply to each node (eg, each remote PHY node) is fixed, it is necessary to reduce the power consumption of other components (eg, CATV amplifier). Therefore, while it is desirable to provide the advanced performance of DOCSIS 3.1, it is possible to provide the advanced performance while improving the transmission signal quality and reducing the power consumption of other components (eg, CATV amplifier). It was difficult to do.

At least some existing techniques use tilt equalizers (tilt filters) with significant attenuation of up to 22 dB over the 1.2 GHz cable spectrum to compensate for coaxial cable loss (eg, from CATV amplifiers to cable modems). ) Is implemented in the analog transmission line. However, the DOCSIS 3.1 waveform using 4K QAM OFDM modulation shows a high peak-to-average power ratio (PAPR) compared to the current DOCSIS 3.0 standard. Therefore, in the case of the same RMS power output of the CATV amplifier of DOCSIS3.0, the peak of the DOCSIS3.1 waveform is within the non-linear region of the CATV amplifier. Therefore, the transmission signal quality is deteriorated. Digital predistortion (DPD) can be used to improve the signal quality of a CATV amplifier, for example by operating the CATV in a more efficient region. DPDs have been used in wireless communication technologies where the signal bandwidth is much narrower than the bandwidth used in cable communication technologies. Moreover, in wireless communication, the harmonics of the non-linear effects of wireless components are not classified as signal bandwidth. Therefore, the DPD for wireless communication only needs to model the non-linear component projected around the baseband frequency. However, in cable applications, the harmonics of the non-linear effect of the CATV amplifier signal are classified as signal bandwidth. Therefore, in DPD implementations for cable applications, the harmonic content of the nonlinear effect of the CATV amplifier should be modeled. Apart from this, it is not possible to implement a tilt equalizer with significant attenuation in the digital domain, and mounting a digital tilt equalizer is due to the finite digital resolution of the digital-to-analog converter (DAC). As a result, the quality of the transmission waveform of the low frequency carrier deteriorates. For integrated circuit (IC) solutions, the DPD data path mounted within the digital front-end (DFE) chip is a solution for modeling the harmonic components of the non-linear effects of the CATV amplifier and the significant attenuation over the transmission spectrum of the CATV amplifier. Was discovered to be able to provide. Accordingly, embodiments of the present disclosure provide improved transmission signal quality and reduced power consumption of CATV amplifiers.

With the above schematic understanding in mind, various embodiments for providing methods and circuits for predistortion of CATV amplifiers are schematically described below. Since one or more of the above embodiments are exemplified using certain types of ICs, a detailed description of such ICs is given below. However, it should be understood that other types of ICs may benefit from one or more of the embodiments described herein.

A programmable logic device (“PLD”) is a well-known type of integrated circuit that can be programmed to perform a specified logic function. A field programmable gate array (“FPGA”), which is a type of PLD, typically includes an array of programmable tiles. These programmable tiles are, for example, input / output blocks (“IOB”), configurable logic blocks (“CLB”), dedicated random access memory blocks (“BRAM”), multipliers, digital signal processing blocks (“DSP”). ), Processor, clock manager, delay lock loop (“DLL”), etc. By "include" and "include", as used herein, is meant to include without limitation.

Each programmable tile typically contains both programmable interconnects and programmable logic. Programmable interconnects typically include a number of interconnect lines of different lengths interconnected by programmable interconnect points (“PIPs”). Programmable logic implements user-designed logic using programmable elements that may include, for example, function generators, registers, arithmetic logic, and so on.

Programmable interconnects and programmable logic are typically programmed by loading a stream of configuration data that defines how the programmable elements are constructed into internal configuration memory cells. The configuration data can be read from memory (eg, from an external PROM) or written to the FPGA by an external device. The aggregated state of the individual memory cells then determines the function of the FPGA.

Another type of PLD is a complex programmable logic device (CPLD). CPLDs include two or more "functional blocks" that are connected to each other by an interconnect switch matrix and connected to input / output ("I / O") resources. Each functional block of the CPLD contains a two-level AND / OR structure similar to that used in programmable logic arrays (“PLA: Programmable Logical Array”) and programmable array logic (“PAL: Programmable Array Logic”) devices. .. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, the configuration data is stored on-chip in non-volatile memory and then downloaded to volatile memory as part of the initial configuration (programming) sequence.

Generally, in each of these programmable logic devices (“PLD”), the functionality of the device is controlled by the configuration data provided to the device for that purpose. Configuration data can be stored in volatile memory (eg, static memory cells common in FPGAs and some CPLDs), non-volatile memory (eg, flash memory in some CPLDs), or any other type of memory cell. Can be stored.

Other PLDs are programmed by applying a processing layer such as a metal layer that programmables various elements on the device. These PLDs are known as mask programmable devices. PLDs can also be implemented in other ways, for example using fuse or anti-fuse technology. The terms "PLD" and "programmable logic device" include, but are not limited to, these exemplary devices, as well as partially programmable devices. For example, one type of PLD comprises a combination of hard-coded transistor logic and a programmable switch fabric that programmatically interconnects the hard-coded transistor logic.

As mentioned above, advanced FPGAs can include several different types of programmable logic blocks within an array. With reference to the example again, FIG. 1 shows an exemplary FPGA architecture 100. The FPGA architecture 100 includes a multi-gigabit transceiver (“MGT”) 101, a configurable logic block (“CLB”) 102, a random access memory block (“BRAM”) 103, an input / output block (“IOB”) 104, a configuration and a clock. Locking logic (“CONFIG / CLOCKS”) 105, digital signal processing block (“DSP”) 106, specialized I / O block (“I / O”) 107 (eg, configuration port and clock port), and digital clock. Includes a number of different programmable tiles, including managers, analog / digital converters, other programmable logic 108 such as system monitoring logic, and the like. Some FPGAs also include a dedicated processor block (“PROC”) 110. In some embodiments, the FPGA architecture 100 is an RF data converter subsystem that includes a plurality of radio frequency analog / digital converters (RF-ADCs) and a plurality of radio frequency digital / analog converters (RF-DACs). including. In various examples, the RF-ADC and RF-DAC may be configured individually for real data or in pairs for real and imaginary I / Q data. In at least some examples, FPGA architecture 100 may implement RFSoC devices.

In some FPGAs, each programmable tile has at least one programmable interconnect that has connections to the input and output terminals 120 of programmable logic elements in the same tile, as shown by the example contained at the top of FIG. The element (“INT”) 111 can be included. Each programmable interconnect element 111 may also include a connection of adjacent programmable interconnect elements within the same tile or other tile to the interconnect segment 122. Each programmable interconnect element 111 can also include a connection of common routing resources between logical blocks (not shown) to the interconnect segment 124. A common routing resource is routing between a logical block (not shown) containing tracks in an interconnect segment (eg, interconnect segment 124) and a switch block (not shown) for connecting the interconnect segments. Can include channels. An interconnect segment of a typical routing resource (eg, interconnect segment 124) can span one or more logical blocks. The programmable interconnect element 111 implements the illustrated programmable interconnect structure for FPGA (“programmable interconnect”), along with common routing resources.

In an exemplary implementation, the CLB 102 may include a configurable logic element (“CLE”) 112 that may be programmed to implement a single programmable interconnect element (“INT”) 111 in addition to the user logic. can. The BRAM 103 may include a BRAM logic element (“BRL”) 113 in addition to one or more programmable interconnect elements. Typically, the number of interconnect elements contained in a tile depends on the height of the tile. In the illustrated example, the height of the BRAM tile is the same as the 5 CLBs, but other numbers (eg, 4) can be used. The DSP tile 106 may include a DSP logical element (“DSPL”) 114 in addition to an appropriate number of programmable interconnect elements. The IOB 104 may include, for example, one instance of the programmable interconnect element 111 and two instances of the input / output logical element (“IOL”) 115. As will be apparent to those of skill in the art, for example, the actual I / O pad connected to the I / O logic element 115 is typically not limited to the area of the input / output logic element 115.

In the example of FIG. 1, the area (shown horizontally) near the center of the die (eg, formed by regions 105, 107, and 108 shown in FIG. 1) is configured, clocked, and other controls. Can be used for logic. Rows 109 (shown vertically) extending from this horizontal area or other rows may be used to distribute the clock and component signals over the width of the FPGA.

Some FPGAs that utilize the architecture shown in FIG. 1 include additional logical blocks that disrupt the regular columnar structure that makes up the majority of the FPGA. The additional logic blocks can be programmable blocks and / or dedicated logic. For example, PROC110 spans multiple columns of CLB and BRAM. The PROC 110 can include a variety of components ranging from a single microprocessor to a comprehensive programmable processing system such as a microprocessor, memory controller, peripherals and the like.

In one aspect, the PROC 110 is mounted as a dedicated circuit manufactured as part of a die that mounts the programmable circuit of the IC, eg, a hardwired processor. The PROC 110 has a variety of different processor types and / Or it can represent any of the systems.

In another aspect, PROC 110 is omitted from Architecture 100 and may be replaced with one or more of the other types of programmable blocks described. Further, such blocks are to form a "soft processor" in that, as in the case of PROC110, various blocks of programmable circuits can be used to form a processor capable of executing program code. May be used.

The term "programmable circuit" refers to programmable circuit elements within an IC, such as various programmable or configurable circuit blocks or tiles described herein, as well as various circuit blocks according to the configuration data loaded into the IC. It may refer to an interconnect circuit that selectively connects tiles and / or elements. For example, the part outside the PROC 110 such as CLB 102 and BRAM 103 shown in FIG. 1 can be regarded as a programmable circuit of an IC.

In some embodiments, the functionality and connectivity of the programmable circuit is not established until the configuration data is loaded into the IC. A set of configuration data can be used to program programmable circuits in ICs such as FPGAs. Configuration data is sometimes referred to as a "configuration bitstream." In general, programmable circuits do not operate or function unless the constituent bitstream is first loaded into the IC. Configuration bitstreams effectively implement or instantiate a particular circuit design within a programmable circuit. The circuit design specifies, for example, the functional aspects of the programmable circuit block and the physical connections between the various programmable circuit blocks.

In some embodiments, "hard-wired" or "hardened" or non-programmable circuits are manufactured as part of the IC. Unlike programmable circuits, hardwired circuits or circuit blocks are not implemented after the IC is manufactured by loading the constituent bitstream. Hardwired circuits are generally considered to have dedicated circuit blocks and interconnects that function, for example, without first loading the constituent bitstream into an IC, eg PROC 110.

In some cases, the hardwired circuit can have one or more modes of operation that can be set or selected according to register settings or values stored in one or more memory elements in the IC. The operation mode can be set, for example, by loading the constituent bitstream into the IC. Despite this functionality, hardwired circuits are not considered programmable circuits because they are operational and have specific functionality when manufactured as part of an IC.

As described above, FIG. 1 is intended to illustrate an exemplary architecture that can be used to implement a programmable circuit, eg, an IC that includes a programmable fabric. For example, the number of logical blocks in a row, the relative width of the row, the number and order of rows, the type of logical block contained in the row, the relative size of the logical block, and the interconnection / logical implementation included at the top of Figure 1. , Is just an example. For example, in a real IC, where CLB is displayed, usually contains two or more adjacent CLB rows to facilitate efficient implementation of user logic, but in adjacent CLB rows. The number varies with the overall size of the IC. Further, the FPGA in FIG. 1 shows an example of a programmable IC that can use the example of the interconnect circuit described herein. The interconnect circuits described herein can be used in other types of programmable ICs such as CPLDs, or in any type of programmable IC having a programmable interconnect structure for selectively coupling logic elements. can.

The ICs on which the methods and circuits for predistortion of the CATV amplifier can be implemented are not limited to the exemplary ICs shown in FIG. 1, but ICs having other configurations, or other types of ICs, may also be CATV amplifiers. Note that the methods and circuits for predistortion can be implemented.

Next, with reference to FIG. 2, a cable network 200 showing a signal path starting from a data fiber (which may include, for example, an optical fiber) and through a remote node to an end-user location (eg, at home) is shown. .. The cable network 200 can be part of a hybrid fiber coaxial network, where the data fiber runs from the central headend to the remote node and the coaxial cable runs from the remote node to the end user. In some examples, the remote node includes a remote PHY node based on the DOCSIS 3.1 standard. The remote PHY node, in some embodiments, includes a baseband and digital front-end (DFE) chip 202, a digital-to-analog converter (DAC) 204, and a driver 206 (eg, an amplifier). It may include an analog gradient filter 208, a power divider 210, and a CATV amplifier 212. In various examples, the baseband and DFE chip 202 may be mounted as a single chip or as separate chips including a baseband processor chip and a separate DFE chip. In some embodiments, the DAC 204 may be implemented as an RF DAC or an IF DAC, for example, depending on the input to the DAC 204. Further, in some embodiments, the baseband and DFE chip 202, as well as the DAC204, may be mounted as a single chip (eg, as in an RFSoC device). Further, one or more components of the remote PHY node may be implemented in a programmable logic device such as the programmable logic device of FIG. As shown in FIG. 2, the data fiber is connected as an input to the baseband and the DFE chip 202, and the output of the baseband and the DFE chip 202 is connected as an input to the DAC 204. The (no gradient) power spectrum 214 provides an example of the shape of the signal at the output of the baseband and DFE chip 202. The output of the DAC 204 is connected as an input to the driver 206, and the output of the driver 206 is connected as an input to the analog gradient filter 208. For cable applications, the analog gradient filter 208 can be used to change the gain of the entire power spectrum of the signal. In other words, the analog gradient filter 208 is used to add a gradient to the power level of the signal over the entire power spectrum. The power spectrum 216 shows the gradient of the signal at the output of the analog gradient filter 208 compared to the power spectrum 214 (eg, a positive gradient in this example).

In some embodiments, the output of the analog gradient filter 208 is connected as an input to the power divider 210. In the example of FIG. 2, the power divider 210 includes a 1x4 power divider having a single input and four outputs. However, in some embodiments, the power divider 210 is a 1x2 power divider having a single input and two outputs, a 1x2 power divider (eg, for producing four outputs). Cascades, or other types of power dividers may be included. In this example, each of the four outputs of the power divider 210 is connected as an input to the CATV amplifier 212. The output of each CATV amplifier 212 is then coupled to a coaxial cable, which is further coupled to the cable modem at the end user position (eg, at home). In at least some embodiments, the cable network 200 implements a node + 0 architecture, which is along the coaxial cable path between the remote PHY node and the end user location (beyond the CATV amplifier 212 on the remote PHY node). Means that there is no additional CATV amplifier. FIG. 2 further shows a power spectrum 218 showing a coaxial cable loss spectrum (eg with a negative gradient), a power spectrum 219 showing the output signal of the CATV amplifier 212, and a signal reaching the end user position (without a gradient). ) The power spectrum 220 showing the power spectrum is shown. As previously described, the analog gradient filter 208 is used to compensate for coaxial cable loss (eg, from the CATV amplifier 212 to the cable modem at the end user location).

In at least some existing cable networks, CATV amplifiers operate in the linear region. This is because the amount of non-linearity at the output of the CATV amplifier is small enough that no additional signal processing is required and the signal at the output of the CATV amplifier is at the end user position on the coaxial cable for demodulation and information transfer. Means that it can be sent directly to your cable modem. However, with the transition to more advanced features and additional power consumption components related to DOCSIS 3.1, the power supply to each node (eg, each remote PHY node) is limited and therefore, such as CATV amplifiers. It is desirable to reduce the power consumption of other components. Currently, the efficiency of CATV amplifiers is about 2-3%, so for example, a single CATV amplifier with an input power of 20 watts will output about 1/2 watts of output power. For four CATV amplifiers (eg, as shown in FIG. 2), an input power of 100 watts outputs an output power of about 2 watts. Therefore, it is highly desirable to make the CATV amplifier more efficient.

At least one option being considered to make the CATV amplifier more efficient is to operate the CATV amplifier in a more non-linear region. However, doing so means that without some additional digital signal processing, the signal at the output of the CATV amplifier cannot be transmitted directly to the end user location on the coaxial cable as provided by embodiments of the present disclosure. do. For example, the embodiments disclosed herein add functionality within the baseband and DFE chip 202, as described in more detail below, thereby the base even when the CATV amplifier operates in the non-linear region. The band and DFE chip 202 will be able to invert or alter the signal so that the signal at the output of the CATV amplifier is still linear and can be easily demodulated by the cable modem at the end user position. In other words, if the non-linearity of the CATV amplifier is "x", the functions in the baseband and DFE chip 202 have the inverse non-linearity "1 / x" offset by the non-linearity "x" of the CATV amplifier. Configured to add. Therefore, the signal at the output of the CATV amplifier is clean and linear. In general, the process of pre-adding non-linearity (eg, adding inverse non-linearity in baseband and DFE chip 202) is called pre-distortion, or pre-distortion. Pre-distortion is sometimes referred to as digital pre-distortion (DPD) because distortion is added digitally in the context of baseband and DFE chip 202. According to various embodiments, the DPD process is performed using the knowledge of the type of non-linearity "x" possessed by the CATV amplifier (eg, CATV amplifier 212, etc.) so that the DPD process is properly inversely non-linear. The sex "1 / x" can be added. In addition, the DPD process uses knowledge of the signal chain between the baseband and DFE chip 202 and the CATV amplifier 212, including the efficiency and / or distortion provided by each of the DAC 204, driver 206, and analog gradient filter 208. Will be executed. In various embodiments, the DPD process disclosed herein improves the efficiency of the CATV amplifier and reduces power consumption.

In some embodiments, the functions within the baseband and DFE chip 202 (configured to add inverse non-linearity) are primarily DFE functions in which the baseband output signal is provided as an input to the DFE chip. It may be implemented as. Accordingly, with reference to FIG. 3 herein, a DFE system 300 is shown that provides a DFE design configured to perform one or more aspects of the present disclosure. In some embodiments, the DFE system 300 comprises a digital upconverter (DUC) 302. In various examples, the DUC 302 is a carrier in which one or more channels of data are modulated from a baseband signal by a set of one or more specified radio frequencies or intermediate frequencies (RF or IF). Used to convert to include passband signals. As an example, the DUC 302 performs interpolation (eg, to increase the sample rate), filters (eg, to provide spectral shaping and removal of interpolated images), and (eg, desired signal spectrum). This is achieved by mixing (to shift to the carrier frequency of). In general, the sample rate at the input to the DUC 302, eg the symbol rate of a digital communication system, is relatively low, but the output, eg the input sample to the DAC, which converts the digital sample to an analog waveform for further analog processing and frequency conversion. The rate is a much higher rate.

As shown in the example of FIG. 3, the DUC 302 is provided with a baseband data input. Baseband data inputs are represented by multiple different carriers as _{s 1} (n), s ₂ (n), s ₃ (n), s ₄ (n), s ₅ (n), and s _{6 (n).} including. In some embodiments, the sampling rate of the baseband data input is approximately 204.8 MHz, which corresponds to the OFDM symbol clock. As an example, the DUC 302 first generates multiple different carriers (eg, from the baseband data input) by performing an interpolation of the baseband data input, and in this example, this interpolation is used to set the sampling rate to 8. It is multiplied by (8), thereby migrating from the first clock domain (eg, 204.8 MHz clock domain) to the second clock domain (eg, 1638.4 MHz clock domain). After the interpolation process, in order to shift the frequency of each of the different carriers to the desired carrier frequency, each of the different carriers is from a numerically controlled oscillator (NCO), each of which has a different frequency. Mixed with the signal. For example, carrier s ₁ (n) is mixed with a first NCO (NCO 1) having a first frequency and carrier s ₂ (n) is mixed with a second NCO (NCO 2) having a second frequency. The carrier s ₃ (n) is mixed with a third NCO (NCO 3) having a third frequency, and the carrier s ₄ (n) is mixed with a fourth NCO (NCO 4) having a fourth frequency. The carrier s ₅ (n) is mixed with a fifth NCO (NCO 5) having a fifth frequency, and the carrier s ₆ (n) is mixed with a sixth NCO (NCO 6) having a sixth frequency. Will be done. After the mixing process, each of a plurality of different carriers is combined to form the synthetic signal c (n). Therefore, the combined signal c (n) includes each of a plurality of different carriers mixed at different frequencies. In some embodiments, as a result of the mixing process, the combined signal c (n) may appear substantially the same as the signal shown in FIG. 5A, where the frequencies are arranged side by side on each of a plurality of different carriers. be. In some cases, after the composite signal c (n) is generated, another interpolation process may be arbitrarily executed. In the example of FIG. 3, the interpolation process is used to determine the sampling rate of the composite signal c (n). It is doubled, thereby moving from a second clock domain (eg, a 1638.4 MHz clock domain) to a third clock domain (eg, a 3276.8 MHz clock domain). After signal processing by the DUC 302, the combined signal c (n) is provided as an input to the DPD system 304, which will be described in more detail below. In some embodiments, the output of the DPD system 304 undergoes a complex signal to real signal conversion 306, and the output of the complex signal to real signal conversion 306 (eg, can be DAC 204 in FIG. 2). It is provided as an input to the DAC. Further, one or more components of the DFE system 300 may be implemented in a programmable logic device such as the programmable logic device of FIG.

As previously described, the DPD process, and thus the DPD system 304, has knowledge of the type of non-linear "x" that the CATV amplifier has, as well as knowledge of the baseband and the signal chain between the DFE chip 202 and the CATV amplifier 212. As a result, the DPD system 304 can effectively carry out the appropriate DPD process (including, for example, adding the appropriate inverse non-linearity "1 / x"). For example, the DPD system 304 may be used to model a CATV amplifier (including, for example, non-linear effects and signal chains). Therefore, the model provided by the DPD system 304 may be generated and / or updated based on the feedback data 308, which may include the output signal of the CATV amplifier (eg, such as the CATV amplifier 212). good. In some embodiments, the feedback data 308 is processed via an analog-to-digital converter (ADC) 310 and provided to the DPD adaptation engine 312 as digital feedback data 311. In various examples, the DPD adaptation engine 312 updates the DPD system 304 based on the digital feedback data 311 so that the DPD system 304 can adapt to the run-time behavior of the CATV amplifier. More specifically, in some embodiments, the DPD adaptation engine 312 may determine the coefficients of filters or configurations of other elements within the DPD system 304, generally within the DPD system 304, below. The DPD module described may be configured. Therefore, the optimal DPD process can be implemented by continuously monitoring and updating the model provided by the DPD system 304 (eg, via feedback data 308 and DPD adaptation engine 312). As an example, aspects of monitoring and updating a model (eg, features of the DPD adaptation engine 312) are implemented as software stored in memory (eg, in BRAM 103 or in another on-chip memory location), one. Alternatively, it may be executed by a plurality of on-chip processors (for example, PROC110). Note that in some embodiments, the baseband and DFE chips 202, DAC204, and ADC310 can be mounted as a single chip (eg, as in an RFSoC device). The examples of monitoring and updating the model provided above are by no means meant to be limiting, other methods are possible, and embodiments of the present disclosure are not limited by any of the examples provided. Will be understood.

Here, with reference to FIG. 4A, a more detailed view of the DPD system 304 described above used to carry out the various aspects of the present disclosure is shown. As mentioned above, the DPD system 304 may be used to model the non-linear effects of the CATV amplifier. Therefore, the model provided by the DPD system 304 may be generated and / or updated based on the feedback data (eg, feedback data 308, etc.), and the feedback data is via the ADC (eg, ADC 310, etc.). The output signal of the CATV amplifier processed by the above may be included, and the feedback data is provided to the DPD adaptation engine 312 so that the DPD system 304 can adapt to the non-linear behavior of the CATV amplifier. Therefore, using the model of the nonlinear effect of the CATV amplifier by the DPD system 304, various of the DPD system 304 such as digital gradient filter 402, nonlinear data path 405, single sideband hill belt filter 412, and digital gradient equalizer 414. Functions can be implemented. It should be noted that one or more components of the DPD system 304 may be implemented in a programmable logic device such as the programmable logic device of FIG.

The function of the DPD system 304 will be described in more detail with reference to FIG. 4A. For example, in some embodiments, a DPD input signal x (n) that may include the combined signal c (n) described above is provided in the digital gradient filter 402. In various cases, the digital tilt filter 402 may be used to model the analog tilt filter 208 (FIG. 2). Therefore, as an example, the output of the digital tilt filter 402 can be similar to the output of the analog tilt filter 208. In some embodiments, the output of the digital gradient filter 402 is provided as an input to the nonlinear data path 405, which is the video bandwidth DPD data path 404, baseband DPD data path 406, second harmonic. It contains a plurality of different parallel data path elements including a wave DPD data path 408 and a third harmonic DPD data path 410. Generally, the non-linear data path 405 is used to model the inverse non-linear behavior of the CATV amplifier and add it to the incoming signal. More specifically, each of the different parallel data path elements of the nonlinear data path 405 is used to model different aspects of the inverse nonlinear behavior of the CATV amplifier and the incoming signal (eg, the output of the digital gradient filter 402). Add to. For example, the video bandwidth DPD data path 404 may model and add inverse harmonic video bandwidth components, and the baseband DPD data path 406 may model and add inverse nonlinear baseband components. The second harmonic DPD data path 408 may model and add an inverse second harmonic component, and the third harmonic DPD data path 410 may model and add an inverse third harmonic component. good. As shown, the outputs of the video bandwidth DPD data path 404, baseband DPD data path 406, second harmonic DPD data path, and third harmonic DPD data path 410 are then combined to form a CATV amplifier. Provides a synthetic signal x'(n) that models the baseband, video, and harmonic components of.

In some embodiments, the output of the nonlinear data path 405 (eg, the combined signal x'(n)) to a single sideband Hilbert filter 412 that can be used to further modulate the combined signal x'(n). The output of the single-sideband hillbelt filter 412 is provided as an input to the digital tilt equalizer 414. As an example, the digital tilt equalizer 414 may be used to model the reciprocal of the analog tilt filter 208 (FIG. 2) and add it to the incoming signal. Thus, as an example, the output of the digital tilt equalizer 414 may be unaffected by the effects of the analog tilt filter 208 (eg, or may negate the effects). As shown in FIG. 4, in some embodiments, the DPD input signal x (n) is also transmitted along the path 416, which is a linear data path. In some examples, the data path 416 may simply introduce a time delay into the DPD input signal x (n) (eg, in block 417). Further, the DPD input signal x (n) transmitted along the data path 416 bypasses the digital tilt filter 402, the nonlinear data path 405, the single sideband hillbelt filter 412, and the digital tilt equalizer 414. Therefore, the quality of the signal modulation of the DPD input signal x (n) transmitted along the data path 416 remains unaffected by other elements of the DPD system 304. Further, as shown in FIG. 4, the output of the digital tilt equalizer 414 and the time delay DPD input signal x (n) 419 are combined to provide the DPD output signal y (n).

Referring to FIG. 5A, an exemplary DPD input spectrum 502 is provided. In some embodiments, the DPD input signal x (n) (FIG. 4) may include a DPD input spectrum 502. As mentioned above, the DPD input spectrum 502 may include each of a plurality of different carriers mixed at different frequencies as previously described (eg, by DUC 302), each of the plurality of different carriers being about 66 MHz. The frequencies are arranged side by side over the entire bandwidth from to about 1218 MHz. Referring to FIG. 5B, an exemplary DPD output spectrum 504 is provided. In some embodiments, the DPD output signal y (n) (FIG. 4A) may include the DPD output spectrum 504. As shown in FIG. 5B, the DPD output spectrum 504 contains one or more nonlinear components 506 added to the signal by the DPD system 304. As described in more detail below, as a result of the processing performed by the DPD system 304, the efficiency and signal quality of the CATV amplifier is improved and power consumption is reduced.

Here, referring to FIGS. 13 to 16, how each of the different parallel data path elements of the nonlinear data path 405 (FIG. 4A) is derived is, for example, the DPD input signal x (n) (FIG. 4A). The equation shown as a function is shown, including a schematic representation. For example, FIG. 13 shows an equation for deriving the inverse non-linear baseband component corresponding to the baseband DPD data path 406, which is expressed as:

FIG. 14 shows an equation for deriving the inverse non-linear video bandwidth component corresponding to the video bandwidth DPD data path 404, which is expressed as:

FIG. 15 shows an equation for deriving the inverse second harmonic component corresponding to the second harmonic DPD data path 408, and the equation is expressed as follows.

FIG. 16 shows an equation for deriving the inverse third harmonic component corresponding to the third harmonic DPD data path 410, and the equation is expressed as follows.

Here, with reference to FIGS. 17-23, a plurality of data showing at least some of the benefits and advantages of the various embodiments of the present disclosure are shown. First, with reference to FIG. 17, a single carrier power spectrum 1700 showing the non-linear effect of the CATV amplifier is shown. The power spectrum 1700 and the power spectra of FIGS. 18-22 are generated using a spectrum analyzer with a resolution bandwidth of 100 kHz and a video bandwidth of 1 MHz. In this example, the carrier frequency of the single carrier is equal to 254 MHz, the CATV amplifier operates at V = 34 V, the bias current = 320 mA, and the output of the CATV amplifier = 76 dbmV. In some embodiments, the waveform shown for the power spectrum 1700 is a 4K QAM DOCSIS 3.1 waveform. As shown in FIG. 17, the power spectrum 1700 further includes a non-linear baseband component 1704, a non-linear video bandwidth component 1706, a second harmonic component 1708, and a third harmonic component 1710. As mentioned above, the power spectrum 1700 relates to a single carrier. However, as previously described, consider arranging a plurality of different carriers side by side at frequency. In such cases, the non-linear components of the power spectrum 1700 (eg, non-linear baseband component 1704, non-linear video bandwidth component 1706, second harmonic component 1708, and third harmonic component 1710) are reliably adjacent carriers. Affects and degrades the power spectrum of.

Referring here to FIG. 18, a power spectrum 1700 (including the non-linear effect of the CATV amplifier) and a power spectrum 1800 showing the result of applying baseband DPD correction superimposed on the power spectrum 1700 are shown. In other words, the power spectrum 1800 shows a beneficial effect (eg, at the output of a CATV amplifier) with the addition of a non-linear baseband component via the baseband DPD data path 406. Specifically, as shown in FIG. 18, as a result of applying the baseband DPD correction, the nonlinear baseband component 1704 of the power spectrum 1700 was corrected (removed) as shown by the component 1802 of the power spectrum 1800. In the example of FIG. 18, as shown by arrow 1804, baseband DPD correction results in an improvement of about 10 dB in the power spectrum 1800.

FIG. 19 shows a power spectrum 1700 (including the non-linear effect of the CATV amplifier) and a power spectrum 1900 showing the result of applying the second harmonic DPD correction superimposed on the power spectrum 1700. In other words, the power spectrum 1900 shows a beneficial effect (eg, at the output of the CATV amplifier) with the addition of the inverse second harmonic component via the second harmonic DPD data path 408. Specifically, as shown in FIG. 19, as a result of applying the second harmonic correction, the second harmonic component 1708 of the power spectrum 1700 is corrected (removed) as shown by the component 1902 of the power spectrum 1900. .. As shown in the example of FIG. 19, the second harmonic DPD correction results in an improvement of about 5 dB in the power spectrum 1900.

Referring to FIG. 20, a power spectrum 1700 (including the non-linear effect of the CATV amplifier) and a power spectrum 2000 showing the result of applying the third harmonic DPD correction superimposed on the power spectrum 1700 are shown. In other words, the power spectrum 2000 exhibits a beneficial effect (eg, at the output of the CATV amplifier) when the inverse third harmonic component is added via the third harmonic DPD data path 410. Specifically, as shown in FIG. 20, as a result of applying the third harmonic correction, the third harmonic component 1710 of the power spectrum 1700 is corrected (removed) as shown by the component 2002 of the power spectrum 2000. .. As shown in the example of FIG. 20, the third harmonic DPD correction results in an improvement of about 5 dB in the power spectrum 2000.

Referring to FIG. 21, a power spectrum 2100 of two carriers 2103 and 2105 showing the non-linear effect of the CATV amplifier is shown. FIG. 21 also shows the results of applying the baseband DPD correction superimposed on the power spectrum 2100, as well as both the baseband DPD correction and the video bandwidth DPD correction superimposed on the power spectra 2100 and 2102. Also includes a power spectrum 2104 showing the results of applying. In other words, the power spectrum 2102 shows a beneficial effect (eg, at the output of a CATV amplifier) with the addition of a non-linear baseband component via the baseband DPD data path 406. Similarly, the power spectrum 2104 has added both a inverse nonlinear baseband component via the baseband DPD data path 406 and a inverse nonlinear video bandwidth component via the video bandwidth DPD data path 404. Shows a beneficial effect in the case (eg, at the output of a CATV amplifier). As a result of applying only the baseband DPD correction (to the power spectrum 2102), the power spectrum 2102 shows a correction (eg, as indicated by arrow 2112) as compared to the power spectrum 2100. Also, as a result of applying baseband DPD correction and video bandwidth DPD correction (to the power spectrum 2104), the power spectrum 2104 is corrected (eg, as indicated by arrows 2106 and 2110) as compared to the power spectrum 2100. Is shown. Specifically, the improvements that occur in the power spectrum 2104 in the region indicated by arrow 2110 are compared to, for example, the region indicated by arrow 2108 (eg, before applying baseband DPD correction and video bandwidth DPD correction). This is especially noticeable. The reason for this is that the carrier 2105 has higher power, resulting in a higher level of non-linearity. Therefore, the carrier 2105 will benefit more from the corrections provided by the DPD system 304.

FIG. 22 shows a power spectrum 2200 containing 6 different carriers with frequencies arranged side by side over the entire bandwidth from about 66 MHz to about 1218 MHz. In some embodiments, the waveform shown for the power spectrum 2200 is a 4K QAM DOCSIS 3.1 waveform. In some examples, the power spectrum 2200 can be the output of the analog gradient filter 208 (FIG. 2). FIG. 22 also shows the adjacent channel power ratio (ACPR) correction 2202 resulting from the application of the correction provided by the DPD system 304, as described above. For the purposes of the present disclosure, ACPR can be described as the ratio of adjacent channel power to main channel power, and it is desirable that the ACPR value be as low as possible. Therefore, the ACPR correction 2202 shown in FIG. 22 is advantageous.

Referring to FIG. 23, a table showing the effect on the MER data when the correction provided by the DPD system 304 is applied, including the modulation error ratio (MER) data of the CATV amplifier, is shown. As an example, MER is a measurement used to quantify the performance of a digital radio (or digital TV) transmitter or receiver in a communication system that uses digital modulation (such as QAM). In the case of the example of FIG. 23, the CATV amplifier module under test can operate at V = 34V. Comparing the MER data with the specifications of the cable industry, MER = 41 dB, 4KQAM, 76.8 dBmV / 75Ω. The CATV amplifier has been tested with 6 carriers, the first carrier is a 4K QAM signal with a carrier frequency of 204 MHz, the second carrier is a 4K QAM signal with a carrier frequency of 396 MHz, and the third carrier is. The carrier frequency is a 4K QAM signal with a carrier frequency of 588 MHz, the fourth carrier is a 4K QAM signal with a carrier frequency of 786 MHz, the fifth carrier is a 4K QAM signal with a carrier frequency of 930 MHz, and the sixth carrier is a carrier frequency. It is a 4K QAM signal of 1122 MHz. In the first test 2302, if the CATV amplifier operates at a bias current of 530 mA and there is no DPD correction, the sixth carrier does not meet the specification of MER = 41 dB. However, when DPD correction is applied (eg, by DPD system 304), all carriers meet the MER specification. In the second test 2304, the CATV amplifier operates at a bias current of 440 mA (a reduction of about 3 watts per amplifier compared to operating at a bias current of 530 mA), and in the absence of DPD correction, all carriers tested It does not meet the specifications of MER = 41 dB. However, when DPD correction is applied (eg, by DPD system 304), all carriers meet the MER specification.

Here, with reference to FIG. 24, a method 2400 for performing a digital predistortion process in a DPD system according to various embodiments is shown. Method 2400 starts at block 2402 and receives a DPD input signal at the input of a DPD system such as the DPD system 304 of FIG. As described above, in some embodiments, the DPD input signal may include the DPD input signal x (n) (FIG. 4), further the DPD input signal x (n) is generated by the DUC 302 (FIG. 3). The combined signal c (n) may be included. In some examples, method 2400 proceeds to block 2404 to provide a nonlinear data path coupled to the input of the DPD system. For example, the non-linear data path may include the non-linear data path 405 of FIG. 4A. Therefore, the nonlinear data path may include a plurality of parallel data path elements. In some examples, the plurality of parallel data path elements includes a video bandwidth DPD data path 404, a baseband DPD data path 406, a second harmonic DPD data path 408, and a third harmonic DPD data path 410. In some embodiments, method 2400 may proceed to block 2406 and use each of the different parallel data path elements to add different aspects of the inverse nonlinear behavior of the CATV amplifier to the incoming signal. In some examples, method 2400 then proceeds to block 2408, where the first combiner combines the outputs of each of the plurality of parallel data path elements to produce a first predistortion signal. In some cases, the first pre-distortion signal may include a synthetic signal x'(n) (FIG. 4A) that models the baseband component, video component, and harmonic component of the CATV amplifier. In some embodiments, method 2400 proceeds to block 2410 to provide a linear data path coupled to the input in parallel with the non-linear data path, which produces a second predistortion signal. In some embodiments, the second predistortion signal may include a time delay DPD input signal x (n) 419 (FIG. 4A). The method then proceeds to block 2412, where the second combiner combines the first predistortion signal with the second predistortion signal to generate a DPD output signal. In some embodiments, the DPD output signal may include the DPD output signal y (n) (FIG. 4A). In various embodiments, the method proceeds to block 2414 and the DPD output signal is provided to a CATV amplifier (eg, CATV amplifier 212 in FIG. 2). According to embodiments of the present disclosure, the DPD output signal is configured to compensate for a plurality of non-linear components of the CATV amplifier. Additional method steps may be performed before, during, and after Method 2400, replacing some of the above method steps according to various embodiments of Method 2400 without departing from the scope of the present disclosure. It will be understood that it can be deleted or deleted.

The various configurations (eg, components of cable network 200, DFE system 300, and DPD system 304, number of parallel data path elements in FIG. 4A, and other features and components shown in the figure) are merely exemplary. It should be noted that there is no limitation beyond what is specifically stated in the attached claims. Those skilled in the art will appreciate that other configurations may be used. Also, although an exemplary cable network 200 is shown, the DPD system disclosed herein is in another communication system, for example, if the other communication system has an amplifier that exhibits detrimental non-linear behavior. Can be used.

The present invention can represent one or more of the following examples, but is not limited thereto.

A wave height reduction (CFR) system, a digital gradient filter coupled to the input of a CFR system, configured to receive a system input signal and generate a digital gradient filter output signal at the digital gradient filter output. In addition, it is a CFR module coupled to a digital gradient filter and a digital gradient filter output, receives a digital gradient filter output signal, executes a CFR process on the digital gradient filter output signal, and CFR at the CFR module output. A CFR module configured to generate a module output signal and a digital tilt equalizer coupled to the CFR module output, configured to receive the CFR module output signal and generate a system output signal. Also, a CFR system including a digital tilt equalizer.

A digital predistortion (DPD) module coupled to the CFR module output that receives the CFR module output signal, executes the DPD process on the CFR module output signal, and generates the DPD module output signal at the DPD module output. The digital tilt equalizer is coupled to the DPD module output and the digital tilt equalizer receives the DPD module output signal and produces the system output signal. The CFR system according to the first embodiment, which is configured.

The CFR system according to Example 1, wherein the system input signal has a first peak to average power ratio (PAPR) and the CFR module output signal has a second PAPR that is smaller than the first PAPR.

A first linear data path coupled to the inputs of the CFR system in parallel with the CFR and DPD modules to generate a first time delay signal, combined with a digital tilt equalizer output signal and a first time delay signal. The CFR system according to Example 2, further comprising a first combiner configured to generate a system output signal.

A first output signal that combines a second linear data path that is coupled to the input of the CFR system in parallel with the CFR module to generate a second time delay signal, and a CFR module output signal and a second time delay signal. The embodiment further comprises a second combiner configured to generate a system output signal and a third combiner configured to combine a first output signal with a DPD module output signal to generate a system output signal. 4. The CFR system according to 4.

The DPD module further comprises a non-linear data path coupled to the CFR module output, the non-linear data path comprises a plurality of parallel data path elements each coupled to the CFR module output, and each of the plurality of parallel data path elements. It is configured to add different inverse nonlinear components to the CFR module output signal corresponding to the non-linear component of the amplifier, and the combiner is configured to combine the outputs of each of the multiple parallel data path elements to generate the DPD module output signal. The CFR system according to Example 2.

A digital-to-analog converter (DAC) is configured to receive a system output signal and generate a DAC output signal, and an analog gradient filter receives a DAC output signal and produces an analog gradient filter output signal. The CFR system according to Example 1, which is configured and the digital gradient filter is configured to model an analog gradient filter.

The CFR system according to Example 7, wherein the digital tilt equalizer is configured to model the reciprocal of the analog tilt filter.

A single sideband hillbelt filter is further included, the single sideband hillbelt filter input is configured to receive the DPD module output signal, and the single sideband hillbelt filter output is coupled to the digital tilt equalizer input. , CFR system according to Example 2.

The CFR system according to Example 1, further comprising an adaptive engine configured to receive feedback data from the amplifier output, wherein the adaptive engine is configured to update the configuration of the CFR module based on the feedback data.

A digital front-end (DFE) system configured to perform a peak factor reduction (CFR) process, a digital upconverter configured to receive and convert a baseband data input signal to produce a composite signal. A CFR system comprising (DUC) and a digital tilt filter, CFR module, and digital tilt equalizer, the digital tilt filter configured to receive a composite signal and generate a digital tilt filter output signal. The CFR module is configured to receive the digital tilt filter output signal and perform a CFR process on the digital tilt filter output signal to generate the CFR module output signal, and the digital tilt equalizer is the CFR module. An adaptive engine configured to receive the output signal and generate a CFR system output signal, the CFR system output signal is coupled to the amplifier, the CFR system, and the feedback data from the output of the amplifier. A digital front-end (DFE) system, including an adaptive engine, configured to update the configuration of the CFR system based on feedback data.

The DFE system according to Example 11, wherein the CFR process is configured to reduce the peak-to-average power ratio (PAPR) of the digital gradient filter output signal.

The CFR system further comprises a digital predistortion (DPD) module containing a non-linear data path coupled to the CFR module output, and the non-linear data path comprises multiple parallel data path elements each coupled to the CFR module output. Each of the parallel data path elements of the amplifier is configured to model a different inverse nonlinear component that corresponds to the non-linear component of the amplifier, and the combiner combines the outputs of each of the multiple parallel data path elements into a DPD module output signal. The DFE system according to Example 11, configured to generate and the digital tilt equalizer receiving the DPD module output signal and generating the CFR system output signal.

A digital-to-analog converter (DAC) is configured to receive a CFR system output signal and generate a DAC output signal, and an analog gradient filter receives a DAC output signal and produces an analog gradient filter output signal. The DFE system according to Example 11, wherein the digital tilt filter is configured to model an analog tilt filter.

The DFE system according to Example 14, wherein the digital tilt equalizer is configured to model the reciprocal of the analog tilt filter.

The digital gradient filter of the CFR system's CFR system receives the input signal and the digital gradient filter output generates the digital gradient filter output signal, and the CFR module of the CFR system receives the CFR for the digital gradient filter output signal. Running the process to generate the CFR module output signal, the CFR process runs a CFR process configured to reduce the peak-to-average power ratio (PAPR) of the digital gradient filter output signal. A method comprising receiving a CFR module output signal and generating a system output signal and providing the system output signal to an amplifier in a digital tilt equalizer of the CFR system.

16. The method of Example 16, further comprising updating the configuration of the CFR system in response to feedback data received from the output of the amplifier.

The DPD module output signal is generated by executing the DPD process on the CFR module output signal in the digital predistortion (DPD) module of the CFR system, and the DPD module output signal is generated in the digital tilt equalizer of the CFR system. 16. The method of Example 16, further comprising receiving and generating a system output signal.

The DPD module further comprises a non-linear data path coupled to the output of the CFR module, the non-linear data path comprises a plurality of parallel data path elements each coupled to the output of the CFR module, and each of the plurality of parallel data path elements The combiner is configured to combine the outputs of each of multiple parallel data path elements to generate a DPD module output signal, configured to model different inverse nonlinear components corresponding to the non-linear components of the amplifier. The method according to Example 18.

16. The method of Example 16, further comprising operating the amplifier in a non-linear region and reducing power consumption of the amplifier in response to providing the system output signal to the amplifier.

An input configured to receive a DPD input signal and a non-linear data path coupled to the input, wherein the non-linear data path comprises a plurality of parallel data path elements each coupled to the input and is a plurality of parallel data. Each of the path elements is configured to add a different inverse non-linear component to the DPD input signal corresponding to the non-linear component of the amplifier, and the first combiner combines the outputs of each of the plurality of parallel data path elements. A non-linear data path configured to generate a pre-distortion signal, a linear data path coupled to an input in parallel with the non-linear data path to generate a second pre-distortion signal, and a first pre-distortion signal. A digital predistortion (DPD) system comprising a second combiner configured to generate a DPD output signal in combination with a second predistortion signal.

21. The DPD system of Example 21, wherein the plurality of parallel data path elements comprises a baseband DPD data path, a video bandwidth DPD data path, a second harmonic DPD data path, and a third harmonic DPD data path.

22. The DPD system of Example 22, wherein the baseband DPD data path is configured to add a inverse non-linear baseband component to the DPD input signal.

22. The DPD system of Example 22, wherein the video bandwidth DPD data path is configured to add a inverse non-linear video bandwidth component to the DPD input signal.

22. The DPD system of Example 22, wherein the second harmonic DPD data path is configured to add an inverse second harmonic component to the DPD input signal.

22. The DPD system of Example 22, wherein the third harmonic DPD data path is configured to add an inverse third harmonic component to the DPD input signal.

21. The DPD system of Example 21, further comprising a digital gradient filter configured to model an analog gradient filter, the digital gradient filter input coupled to the input and the digital gradient filter output coupled to the nonlinear data path. ..

It further includes a digital tilt equalizer configured to model the inverse of the analog tilt filter, the digital tilt equalizer input configured to receive a first predistortion signal, and a second combiner. The DPD system according to Example 21, wherein the digital tilt equalizer output is combined with a second predistortion signal to generate a DPD output signal.

A single sideband hillbelt filter is further included, the single sideband hillbelt filter input is configured to receive a first predistortion signal, and the single sideband hillbelt filter output is coupled to the digital tilt equalizer input. 28. The DPD system according to Example 28.

21. The DPD system of Example 21, wherein the DPD output signal is coupled to an amplifier input to generate an amplified output signal, and the DPD output signal is configured to compensate for a plurality of non-linear components of the amplifier.

A digital front-end (DFE) system configured to perform a digital predistortion (DPD) process, a digital upconverter configured to receive and convert a baseband data input signal to produce a composite signal. (DUC) and a DPD system configured to receive a composite signal at the DPD input and execute the DPD process on the composite signal, where the DPD input is coupled to multiple parallel data path elements and multiple. At least one of the parallel data path elements of the amplifier is configured to add an inverse harmonic component to the composite signal corresponding to the non-linear harmonic component of the amplifier, and the combiner combines the outputs of each of the multiple data path elements. The DPD output signal is configured to generate a DPD output signal, including a DPD system coupled to the amplifier, and the DPD output signal is configured to compensate for the non-linear harmonic component of the amplifier, digital. Front end (DFE) system.

30. The DFE system of Example 30, wherein the plurality of parallel data path elements comprises a baseband DPD data path, a video bandwidth DPD data path, a second harmonic DPD data path, and a third harmonic DPD data path.

The DUC is configured to perform an interpolation process on the baseband data input signal to generate an interpolated signal, and the DUC is configured to perform a mixing process on the interpolated signal to generate a composite signal. The DFE system according to the thirty-first embodiment.

The DPD system further includes a digital gradient filter configured to model an analog gradient filter, the digital gradient filter input is configured to receive a composite signal, and the digital gradient filter output is a multiple parallel data path. The DFE system according to Example 31, which is coupled to an element.

The DPD system further includes a digital tilt equalizer configured to model the inverse of the analog tilt filter, with the digital tilt equalizer input receiving the combined output of each of the multiple data path elements. 31. The DFE system of Example 31, wherein another combiner is configured to combine the digital tilt equalizer output with a linear DPD signal to generate a DPD output signal.

Receiving the DPD input signal at the input of the digital predistortion (DPD) system and receiving the DPD input signal at the non-linear data path coupled to the input of the DPD system, with the non-linear data path at the input respectively. Receiving a DPD input signal containing multiple coupled parallel data path elements and adding an inverse non-linear component to the DPD input signal corresponding to the non-linear component of the amplifier by each of the multiple parallel data path elements. , The first combiner combines the outputs of each of the multiple parallel data path elements to generate the first predistortion signal, and the DPD input signal in a linear data path coupled to the input in parallel with the nonlinear data path. To generate a second pre-distortion signal by receiving the above, and to generate a DPD output signal by combining the first pre-distortion signal and the second pre-distortion signal by the second combiner. Method.

36. The method of Example 36, wherein the plurality of parallel data path elements comprises a baseband DPD data path, a video bandwidth DPD data path, a second harmonic DPD data path, and a third harmonic DPD data path.

The baseband DPD data path adds a inverse nonlinear baseband component to the DPD input signal, and the video bandwidth DPD data path adds an inverse nonlinear video bandwidth component to the DPD input signal, and the second harmonic. Further comprising adding an inverse second harmonic component to the DPD input signal by the DPD data path and adding an inverse third harmonic component to the DPD input signal by the third harmonic DPD data path. The method according to Example 37.

36. The method of Example 36, further comprising providing a DPD output signal to the amplifier input to generate an amplified output signal, wherein the DPD output signal is configured to compensate for a plurality of non-linear components of the amplifier.

36. The method of Example 36, further comprising operating the amplifier in a non-linear region and reducing power consumption of the amplifier in response to providing the DPD output signal to the amplifier.

Although the specific embodiments have been illustrated and described, it is understood that the claimed invention is not limited to the preferred embodiment, and various aspects are not deviated from the purpose and scope of the claimed invention. It will be apparent to those skilled in the art that various changes and modifications can be made. Therefore, the specification and drawings should be regarded as exemplary rather than limiting. The claimed invention shall include alternatives, modifications, and equivalents.

Claims (15)

CFR reduction (CFR) system,
A digital gradient filter coupled to the input of the CFR system, the digital gradient filter configured to receive the system input signal and generate a digital gradient filter output signal at the digital gradient filter output.
A CFR module coupled to the digital gradient filter output, which receives the digital gradient filter output signal, executes a CFR process on the digital gradient filter output signal, and outputs a CFR module output signal at the CFR module output. With a CFR module configured to generate,
A CFR system comprising a digital tilt equalizer coupled to the CFR module output, the digital tilt equalizer configured to receive the CFR module output signal and generate a system output signal. A digital predistortion (DPD) module coupled to the CFR module output, which receives the CFR module output signal, executes a DPD process on the CFR module output signal, and outputs the DPD module at the DPD module output. Further included, a DPD module configured to generate a signal,
The first aspect of claim 1, wherein the digital tilt equalizer is coupled to the DPD module output, and the digital tilt equalizer receives the DPD module output signal and generates the system output signal. The described CFR system. The CFR according to claim 1, wherein the system input signal has a first peak-to-average power ratio (PAPR), and the CFR module output signal has a second PAPR that is smaller than the first PAPR. system. A first linear data path coupled to the input of the CFR system in parallel with the CFR module and the DPD module to generate a first time delay signal.
The CFR system according to claim 2, further comprising a first combiner configured to combine the digital tilt equalizer output signal with the first time delay signal to generate the system output signal. A second linear data path coupled to the input of the CFR system in parallel with the CFR module to generate a second time delay signal.
A second combiner configured to generate a first output signal by combining the CFR module output signal and the second time delay signal.
The CFR system according to claim 4, further comprising a third combiner configured to combine the first output signal with the DPD module output signal to generate the system output signal. The DPD module further comprises a non-linear data path coupled to the CFR module output, the non-linear data path comprises a plurality of parallel data path elements coupled to the CFR module output, respectively, and the plurality of parallel data paths. Each of the elements is configured to add a different inverse non-linear component to the CFR module output signal corresponding to the non-linear component of the amplifier, and the combiner combines the outputs of each of the plurality of parallel data path elements into the DPD module. The CFR system according to claim 2, which is configured to generate an output signal. A digital-to-analog converter (DAC) is configured to receive the system output signal and generate a DAC output signal, and an analog gradient filter receives the DAC output signal and produces an analog gradient filter output signal. The CFR system according to claim 1, wherein the digital gradient filter is configured to model the analog gradient filter. The CFR system of claim 7, wherein the digital tilt equalizer is configured to model the reciprocal of the analog tilt filter. A single sideband hillbelt filter is further included, the single sideband hillbelt filter input is configured to receive the DPD module output signal, and the single sideband hillbelt filter output is coupled to the digital tilt equalizer input. The CFR system according to claim 2. The first aspect of claim 1, further comprising an adaptive engine configured to receive feedback data from the amplifier output, wherein the adaptive engine is configured to update the configuration of the CFR module based on the feedback data. CFR system. A digital front-end (DFE) system configured to perform a crest reduction (CFR) process.
A digital upconverter (DUC) configured to receive and convert a baseband data input signal to generate a composite signal.
A CFR system comprising a digital tilt filter, a CFR module, and a digital tilt equalizer, wherein the digital tilt filter is configured to receive the composite signal and generate a digital tilt filter output signal. The module is configured to receive the digital tilt filter output signal and perform the CFR process on the digital tilt filter output signal to generate a CFR module output signal, the digital tilt equalizer. With a CFR system configured to receive the CFR module output signal and generate a CFR system output signal, the CFR system output signal is coupled to an amplifier.
A digital front end including an adaptive engine configured to receive feedback data from the output of the amplifier, the adaptive engine configured to update the configuration of the CFR system based on the feedback data. (DFE) system. 11. The DFE system of claim 11, wherein the CFR process is configured to reduce the peak-to-average power ratio (PAPR) of the digital gradient filter output signal. The CFR system further comprises a digital predistortion (DPD) module containing a non-linear data path coupled to the CFR module output, wherein the non-linear data path comprises a plurality of parallel data path elements each coupled to the CFR module output. Each of the plurality of parallel data path elements is configured to model a different inverse nonlinear component corresponding to the non-linear component of the amplifier, and the combiner combines the outputs of each of the plurality of parallel data path elements. 11. The digital tilt equalizer is configured to receive the DPD module output signal and generate the CFR system output signal. DFE system. A digital-to-analog converter (DAC) is configured to receive the CFR system output signal and generate a DAC output signal, and an analog gradient filter receives the DAC output signal and generates an analog gradient filter output signal. 11. The DFE system of claim 11, wherein the digital tilt filter is configured to model the analog tilt filter. 14. The DFE system of claim 14, wherein the digital tilt equalizer is configured to model the reciprocal of the analog tilt filter.

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