CN114374399B

CN114374399B - High-precision IQ imbalance correction system

Info

Publication number: CN114374399B
Application number: CN202111656143.4A
Authority: CN
Inventors: 侯卫兵; 雷伟龙
Original assignee: Beijing Litong Communication Co ltd
Current assignee: Beijing Litong Communication Co ltd
Priority date: 2021-12-30
Filing date: 2021-12-30
Publication date: 2022-10-28
Anticipated expiration: 2041-12-30
Also published as: CN114374399A

Abstract

The invention discloses a high-precision IQ imbalance correction system, and relates to the technical field of imbalance correction. The invention comprises a sending end module, wherein the sending end module is connected with a receiving end module, the receiving end module is connected with a digital predistortion module, and the digital predistortion module is connected with a filter; the digital predistortion module is used for correcting by using a filter which is pre-compensated and arranged on a digital baseband, converting frequency domain response into finite long impulse response FIR filter tap coefficients of a time domain, and the compensated response comprises IQ two paths. The invention adopts a pre-correction mode at the sending end and a post-correction mode at the receiving end, combines the pre-correction with the post-correction to carry out IQ correction, sets a pre-compensated filter at the digital baseband to carry out correction, and converts the frequency domain response into the tap coefficient of the time domain finite long impulse response FIR filter, thereby effectively reducing the influence of the mirror image component, improving the performance of the system, reducing the calculation complexity and optimizing the performance of the chip.

Description

High-precision IQ imbalance correction system

Technical Field

The invention belongs to the technical field of unbalance correction, and particularly relates to a high-precision IQ unbalance correction system.

Background

Currently, the mainstream radio frequency transceiver mainly has two structures, namely a superheterodyne transceiver and a zero intermediate frequency transceiver. The superheterodyne architecture is the most widely used architecture in wireless communication transceivers, and the traditional superheterodyne architecture is the most mature architecture at present, and can achieve better transceiving performance by adopting proper design. The superheterodyne receiver has a large dynamic range, high adjacent channel selectivity and high receiving sensitivity, and the superheterodyne structure is less affected by the imbalance of IQ signals, and does not need a complex direct current compensation circuit. However, the superheterodyne structure has the problems of complex structure, low integration level and over-high cost and power consumption, which greatly limits the further development and application of the superheterodyne structure. With the development of software radio technology, the zero intermediate frequency structure has the advantages of simple structure, high integration level, small volume, low cost and power consumption, no need of an external mirror frequency suppression filter and the like, so that the practical value is increasingly prominent, and very wide attention and research are paid in recent years. However, the zero intermediate frequency structure has some inherent disadvantages due to its own characteristics, such as being susceptible to local oscillator leakage and interference, and requiring an additional dc compensation circuit; the IQ imbalance problem directly affects the performance of the transceiver due to the influence of process corners, device matching and other factors, which is one of the main reasons why the zero-if structure has not been widely applied in the past decades.

The existing IQ imbalance shows that the main signal causes serious distortion when the mirror image signal reaches a certain power, so that the dynamic range of the system is reduced, and the overall performance of the system is deteriorated.

Disclosure of Invention

The invention aims to provide a high-precision IQ imbalance correction system, which solves the problem of the overall performance of an IQ imbalance deterioration system in the prior art.

In order to achieve the purpose, the invention is realized by the following technical scheme:

a high-precision IQ imbalance correction system comprises a sending end module, wherein the sending end module is connected with a receiving end module, the receiving end module is connected with a digital predistortion module, and the digital predistortion module is connected with a filter;

the digital predistortion module is used for correcting by using a filter which is pre-compensated and arranged on a digital baseband, converting frequency domain response into finite long impulse response FIR filter tap coefficients of a time domain, and the compensated response comprises IQ two paths.

Optionally, the sending end module includes a DPD module, and the DPD module is configured to perform predistortion processing on an original baseband I/Q input signal. The receiving end module comprises a data receiving module, an analog-to-digital converter, a digital-to-analog converter and a radio frequency processing module, wherein the data receiving module receives a pre-correction signal, sends the pre-correction signal to a low noise amplifier for amplification, and converts the pre-correction signal into an intermediate frequency analog signal through an IQ (in-phase quadrature) demodulator in a down-conversion mode, and the analog-to-digital converter is used for converting the intermediate frequency analog signal into an intermediate frequency digital signal.

Optionally, the digital predistortion module corrects nonlinearity of the power amplifier and corrects local oscillator leakage and mirror image of the modulator. The image rejection ratio is larger than 60dBc, and the EVM is not higher than-42 dB. The digital predistortion module comprises an ADC module, a PA output module and a model module, wherein the ADC module is used for realizing acquisition of a PA output I path signal, the PA output module is used for inputting z and y _ I to carry out antecedent modeling on the PA, z is sent into the extracted PA antecedent behavior model module to recover a power amplifier complex baseband output signal y, y and z are respectively used as the input and the output of the model to realize updating of a DPD module coefficient, and the same principle is adopted when a Q path is observed. The two DPD structures are iterated for 4 times, and the PA is respectively improved before and after the DPD of the two open-loop structures is corrected.

Optionally, the filter is connected to an in-phase mixer, the in-phase mixer is connected to a quadrature-phase mixer, and the filter includes a plurality of low-pass filters. The time domain finite long impulse response FIR filter carries out smooth compensation on the 3dB bandwidth of the low-pass filter, and 3 half-band interpolation filters carry out interpolation or bypass by adopting 2 times of coefficients. I and Q support a passband bandwidth of up to 225MHz with TIA, signals are converted by the Σ Δ ADC and filtered in a half-band decimation stage and programmable RFIR.

The embodiment of the invention has the following beneficial effects:

according to the embodiment of the invention, the pre-correction mode is adopted at the sending end, the post-correction mode is adopted at the receiving end, the pre-correction is combined with the post-correction to carry out IQ correction, the pre-compensated filter is arranged at the digital baseband to carry out correction, and the frequency domain response is converted into the tap coefficient of the time domain finite long impulse response FIR filter, so that the influence of the mirror image component can be effectively reduced, the performance of the system is improved, the calculation complexity is reduced, and the performance of a chip is optimized.

Of course, it is not necessary for any product to practice the invention to achieve all of the above-described advantages at the same time.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the invention and, together with the description, serve to explain the invention and not to limit the invention. In the drawings:

FIG. 1 is a schematic diagram of a flow structure of a compensation response system according to an embodiment of the present invention;

fig. 2 is a schematic view of a flow structure of a local oscillator synthesis system according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of an equivalent circuit principle flow structure according to an embodiment of the present invention;

fig. 4 is a schematic flow chart of a DPD system according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.

To maintain the following description of the embodiments of the present invention clear and concise, a detailed description of known functions and known components of the invention have been omitted.

Referring to fig. 1-4, in the present embodiment, a high-precision IQ imbalance correction system is provided, including: the device comprises a sending end module, a receiving end module and a digital pre-distortion module, wherein the sending end module is connected with the receiving end module which is connected with the digital pre-distortion module;

Noise transfer of sigma-delta modulators with different orders is that in-band noise of a high-order modulator is very low, but out-of-band noise is also raised to a very high level at the same time, output quantization noise of an nth-order modulator is increased at a speed of (20 n) dB/dec, and phase noise performance of a phase-locked loop directly affects EVM of the modulator and signal-to-noise ratio of a receiving signal of a demodulator, so that performances of the whole modulator and the demodulator are affected. Optimizing the phase noise of the phase-locked loop will improve the performance of the whole modulator and demodulator.

For a transceiver, the quality of local oscillation signals directly determines the image rejection performance, the phase shift of two paths of IQ local oscillation signals deviates 90 degrees or the local oscillation amplitude is not matched, the image rejection is directly reflected by approximate IMR =6-20 log10 (delta theta), typically, the phase error of the local oscillation signals is 1 degree, the corresponding image rejection is restricted to 41dBc, when the phase error needs to reach 60dBcIMR and is controlled to be 0.1 degree, a differential frequency multiplication clock is usually input, four-phase local oscillation signals are generated by means of frequency dividers, when the local oscillation signals flo =2700Mz, fin =5400MHz needs to be input, therefore, the first to two stages of frequency dividers need to be carefully considered and optimized, the local oscillation synthesis is in a wide frequency range, when the input frequency range is appropriate, the purpose can be achieved by cascading multistage frequency dividers, the first stage adopts a current mode CML frequency divider to cover carrier frequencies as low as 100M, the subsequent five-stage DFF frequency dividers are connected in series, and the total six-stage frequency dividers can realize frequency division of 2-64; according to actual needs, the system selects a proper VCO frequency and selects a proper frequency division from 2/4/8/16/32/64 frequency divisions, and sends the frequency division to a subsequent 25-percent Duty Cycle generation circuit; in order to enable the four-phase local oscillator to achieve an accurate 90-degree phase difference, layout and routing design are mainly optimized, and finally an adjustable phase shifter is arranged, so that the optimal local oscillator quality is achieved, and the optimal IQ balance of both receiving and transmitting can be achieved.

The baseband synchronization mainly utilizes the phase locking characteristic of the phase-locked loop circuit. The baseband clock is generated by a baseband phase-locked loop whose reference clock is the system clock. Because the multichip system can share the same system clock, the output phases of the baseband phase-locked loops in each chip are consistent, and only a tiny error caused by device mismatching exists. Through using high-speed frequency divider structure and circuit optimization, can use system synchronization signal to reset the frequency divider, eliminate the phase uncertainty, the input signal that the emulation used is about 10GHz, and the output clock is about 5GHz, and the special phase discriminator of radio frequency synchronization directly compares the phase place of system clock and phase-locked loop output signal. Because the radio frequency synchronous phase discriminator directly compares radio frequency local oscillation signals, the working frequency is very high, and a frequency mixing circuit structure is selected through circuit simulation. The phase error signal generated by the phase discriminator is filtered by a digital filter and then sent to a sigma-delta modulator of a radio frequency phase-locked loop, the frequency division ratio of the feedback frequency divider is controlled to achieve the purpose of adjusting the phase of the output signal of the phase-locked loop, the broadband DC correction and IQ imbalance correction technology can be realized, and the performance that the image rejection ratio is larger than 60dBc and the EVM is not higher than-42 dB is achieved.

In order to meet the requirements of high performance, low cost and low power consumption, firstly, an ADC is needed to realize acquisition of a path I signal output by a PA, then, a PA is subjected to antecedent modeling by using PA input z and y _ I, then, z is sent into an extracted PA antecedent behavior model to recover a power amplifier complex baseband output signal y, and finally, y and z are respectively used as input and output of the model to realize updating of a DPD module coefficient, the same is true when a path Q is observed, an excitation signal of the PA is an LTE signal with the bandwidth of 40MHz and the peak-to-average ratio of 7.6dB, and the input power of the power amplifier is-21 dBm. The two DPD structures are iterated for 4 times, the algorithms under the two DPD architectures are guaranteed to be sufficiently converged, and the NMSE is improved by about 12dB and the ACPR is improved by about 13dB by the PA before and after the DPD with the two open-loop structures is corrected.

The method has the advantages that IQ correction is carried out by combining pre-correction with post-correction through adopting a pre-correction mode at a sending end and adopting a post-correction mode at a receiving end, IQ correction is carried out by setting a pre-compensated filter at a digital baseband, frequency domain response is converted into time domain finite long impulse response FIR filter tap coefficients, the influence of mirror image components can be effectively reduced, the performance of a system is improved, the calculation complexity is reduced, and the performance of a chip is optimized.

The sending end module of this embodiment includes a DPD module, the DPD module is used to perform predistortion processing on an original baseband I/Q input signal, the receiving end module includes a data receiving module, an analog-to-digital converter, a digital-to-analog converter and a radio frequency processing module, the data receiving module receives a predistortion signal, sends the predistortion signal to a low noise amplifier for amplification, and converts the predistortion signal to an intermediate frequency analog signal by an IQ quadrature demodulator, and the analog-to-digital converter is used to convert the intermediate frequency analog signal to an intermediate frequency digital signal.

The digital predistortion module of this embodiment corrects the nonlinearity of the power amplifier and corrects local oscillator leakage and mirror image of the modulator. The image rejection ratio is larger than 60dBc, and the EVM is not higher than-42 dB. The digital predistortion module comprises an ADC module, a PA output module and a model module, wherein the ADC module is used for realizing acquisition of a PA output I path signal, the PA output module is used for inputting z and y _ I to carry out antecedent modeling on the PA, z is sent into the extracted PA antecedent behavior model module to recover a power amplifier complex baseband output signal y, y and z are respectively used as the input and the output of the model to realize updating of a DPD module coefficient, and the same principle is adopted when a Q path is observed. The two DPD structures are iterated for 4 times, and the PA is respectively improved before and after the DPD of the two open-loop structures is corrected.

In the present embodiment, an in-phase mixer is connected to the filter, a quadrature-phase mixer is connected to the in-phase mixer, and the filter includes a plurality of low-pass filters. The time domain finite long impulse response FIR filter carries out smooth compensation on the 3dB bandwidth of the low-pass filter, and 3 half-band interpolation filters carry out interpolation or bypass by adopting 2 times of coefficients. I and Q support a passband bandwidth of up to 225MHz with TIA, signals are converted by the Σ Δ ADC and filtered in a half-band decimation stage and programmable RFIR.

In the receiving calibration, the IQ unbalanced signal is converted into a digital signal after passing through the ADC, and then is processed in the DSP, the processing method comprises parameter estimation and parameter compensation, the transmitting calibration needs to be carried out by an ideal receiver, and the filter module can be configured to be based on an IQ radio frequency signal which is ideal with the frequency r (t). Its mathematical model can be expressed as:

r(t)＝zI(t)cos(ωct)-zQ(t)sin(ωct)

wherein, zI (t), zQ (t)

Is IQ path ideal signal given by base band, after mixing of transmitter, r (t) is formed

When the IQ path of the receiver is ideal, i.e. there is no IQ imbalance, r (t) passes through the mixer, the following procedure is obtained:

r(t)＝zI(t)cos(ωct)-zQ(t)sin(ωct)

way I:

r(t)*cos(ωct)＝zI(t)*cos2(ωct)-zQ(t)*sin(ωct)*cos(ωct)

and a path Q:

r(t)*(-sin(ωct))＝-zI(t)*cos(ωct)*sin(ωct)+zQ(t)*sin2(ωct)。

the values of the associated filter coefficients attenuate/amplify the frequency of the input signal to provide an output filtered signal. The filter module may be configured to adjust a phase relationship between the I & Q paths for the frequency of the input signal according to a value of a filter coefficient associated with the frequency to provide an output filtered signal. With smaller IQ errors, the correction filter transfer function approaches the all-pass transfer function.

The frequency receiver is also called a direct frequency conversion receiver, compared with a super heterodyne structure, the frequency receiver structure only needs one frequency mixing, directly down-converts the central frequency of a radio frequency signal to the local frequency of a zero frequency receiver, the local frequency of the receiver is the same as the signal carrier frequency, and down-converts the signal which is amplified by low noise to two paths of frequency baseband signals (paths and Q paths) through orthogonal frequency mixing, so that no image frequency signal exists, the use of an image rejection filter with a high Q value is avoided, and meanwhile, a low-pass filter which can be integrated by a single chip is used for replacing an intermediate frequency channel selection filter, so that the complexity of a circuit is greatly reduced, and the integration level of the circuit is improved.

In order to investigate the broadband characteristic of the imbalance degree of the receiver, different local oscillation signal frequencies are set to analyze the influence of a mixer on IQ imbalance of the receiver; meanwhile, in order to analyze the influence of a mixer, an LPF, an ADC and the like on IQ imbalance of a receiver, test signals with different baseband frequencies need to be used under the same local oscillation frequency; to analyze the effect of the input signal-to-noise ratio on the IQ imbalance of the receiver, different input signal powers are used for testing. The test signal can be down-converted to a plurality of frequency points within 0-2MHz of the baseband signal bandwidth of the receiver after quadrature frequency mixing, and the imbalance degree of the receiver is quantitatively analyzed by using an image rejection ratio RR.

Three groups of local oscillation frequencies are selected: 30MHz, 60MHz and 86MHz, and 20 frequency points with 100kHz interval in the bandwidth of 0-2MHz are respectively selected as corresponding baseband signal frequency points, and the signal power is respectively set to-40 dBm,

-60Bm and-80 dBm, i.e. 180 total test frequency points. The specific test method is as follows

(1) And finishing initialization configuration such as clock module configuration, FPGA configuration, ADC configuration and the like:

(2) The output signal power of a signal source is set to be-40 dBm, and output signal frequencies are respectively set according to the frequency requirements of 60 test frequency points under the signal power

(3) The PC is connected with the digital front end FPGA through a JTAG simulator, and performs channel control configuration, DDS frequency configuration and channel gain control configuration on the receiving channel according to the frequency of the test frequency point;

(4) ADC quantization data of different test frequency points are collected and stored by a Chipscope, the data are led into Matlab for spectrum analysis, and an image rejection ratio IRR is calculated

(5) And (4) respectively setting the output signal power of the signal source to-60 dBm and-80 dBm, and repeating the steps (2), (3) and (4).

Firstly, the influence of the signal-to-noise ratio of an input signal on the imbalance of a receiver Q is analyzed, and when the power of the input signal is large, the influence of the signal-to-noise ratio of the input signal on the imbalance of the receiver IQ is small. When the input signal power is-40 dBm and-6 odBm, the change trend of the image rejection ratio under the same local oscillation frequency and the numerical value at the corresponding frequency point are basically the same, and certain deviation exists only at thousands of test frequency points. When the input signal power is-80 dBm, the change trend of the image rejection ratio is completely different from that under the conditions of-40 dBm and-60 dBm, and the accurate image rejection ratio of the receiver cannot be measured through spectrum analysis.

And then analyzing the image rejection ratios of different test frequency points in the bandwidth of 0-2MH, wherein the image rejection ratios of the receiver with the unbalanced degree and the broadband characteristic change along with the change of the baseband frequency points corresponding to the test signals in the bandwidth of 0-2MHz baseband signals, the image rejection ratios at different frequency points are different, the best image rejection ratio reaches 52dB at most, the worst image rejection ratio is only 25dB, and finally analyzing the image rejection ratios at different local oscillation frequencies. The image rejection ratio of the receiver under 30MHz local oscillation frequencies with different overall ranges and variation trends of the image rejection ratio measured under different local oscillation frequencies is 29-52 dB, and the optimal image rejection ratio is obtained at the base band frequency point 09 MHz; the image rejection ratio of the receiver under the local oscillation frequency of 60MHz is between 26 dB and 49dB, and the best image rejection ratio is provided at the baseband frequency point of 0.4 MHz; the image rejection ratio of the receiver under the local oscillation frequency of 86MHz is between 25dB and 49dB, and the best image rejection ratio is provided at the baseband frequency point of 0.2 MHz.

In summary, the IQ imbalance of the handheld software radio platform receiver can be obtained as follows:

receiver IQ imbalance has a broadband characteristic: the imbalance of signals at different frequency points in a 30-88MHz receiving frequency band is not completely the same, the IQ imbalance of a handheld platform receiver can be reasonably analyzed only under the condition that the variation range of the total image rejection ratio of the receiver is 25-52dB input signal to noise ratio, the IQ imbalance can not be analyzed by a spectrum analysis method under the condition of low signal to noise ratio, and therefore the imbalance calibration of the handheld software radio platform broadband zero intermediate frequency receiver can be obtained, the imbalance calibration must be carried out in the whole receiving frequency band of 30-8 MHz, namely the imbalance calibration related to the frequency in the 30-88MHz frequency band needs to be completed.

In the step of determining the compensated in-phase data and the compensated quadrature data having less in-phase-quadrature mismatch, the method for compensating for in-phase-quadrature mismatch may further comprise modifying the specific number of the plurality of data samples for calculating the average of the difference between the autocorrelation value of the in-phase data and the autocorrelation value of the quadrature data and the average of the cross-correlation values of the in-phase data and the quadrature data. The method for compensating for IQ mismatch may set the specific number of the data samples to a smaller number at the beginning of the determining step for compensating for IQ mismatch, and set the specific number to a larger number later. The step of determining the compensated in-phase data and the compensated quadrature data may be based on a least mean square algorithm to determine the compensated in-phase data and the quadrature data. The method of compensating for IQ mismatch may further comprise controlling a convergence rate of the LMS algorithm. The method of compensating for in-phase-quadrature mismatch can set the convergence rate to a large value at the beginning of the least mean square algorithm and to a small value at a later time. The method for compensating the in-phase and quadrature mismatch may further comprise: transmitting a second signal comprising an in-phase data and a quadrature data; and receiving a coupled signal representing the second signal, determining a plurality of coefficient values of a least mean square algorithm operable to reduce in-phase-quadrature mismatch of the coupled signal, and using the plurality of coefficient values in a least mean square algorithm to reduce in-phase-quadrature mismatch of the second signal. The step of determining the compensated in-phase data and the compensated quadrature data may further comprise: determining an image signal of the first signal by multiplying a conjugate signal of the first signal by a weight value: and subtracting the image signal of the first signal from the first signal. The method of compensating for in-phase-quadrature mismatch may further comprise calculating the weight value using a least mean square algorithm to minimize in-phase-quadrature mismatch between the compensated in-phase data and the compensated quadrature data.

In the case of a causal filter, the optimal filter can be approximated with a finite impulse response FIR filter by truncating the optimal filter by selecting only a limited number of filter taps N. The FIR filter has a finite number of taps. The FIR may be a non-causal filter if there is at least one negative tap. In the example shown in fig. 4, the FIR filter without delay includes filter taps 0 to 4 having high energy/amplitude, and does not include a negative tap. However, it is observed that filter tap-1 of the optimal filter has a larger magnitude than the magnitude of filter tap 4. In this case, the FIR filter may include filter tap-1. To select filter tap-1, an additional delay may be introduced on the feedthrough path (e.g., at delay block 111 such that filter taps-1 through 3 are all effectively shifted right by 1 unit to occupy filter taps 0 through 4. The units here refer to the number of samples, whose value is the same as the value of the delay D samples introduced into delay block 111 of fig. 1. Thus, the additional delay may improve the filtering performance of the original filter.

Under ideal conditions, a static calibration scheme may look for all filter coefficients for a given tuple of parameters including signal bandwidth, frequency band, and frequency channel. However, in practice, the number of possible combinations of these three parameters is too large, and the number of static calibrations for each combination is greatly limited. To reduce complexity, a static calibration scheme can be performed for possible signal bandwidths, using an arbitrarily selected pair of frequency bands and frequency channels. Note that the wooden static calibration scheme may compensate both FI-IQM and FD-IQM for a given frequency band, channel and signal bandwidth configuration. The FI-IQM varies with frequency band/channel, so it may not be practical to apply the present static calibration scheme for all possibilities of three parameters.

A filter is a frequency-selective device that passes certain frequency components of a signal while significantly attenuating other frequency components. By using the frequency selection function of the filter, interference noise can be filtered out or spectrum analysis can be carried out. In other words, any device or system that can pass a specific frequency component of a signal and greatly attenuate or suppress other frequency components is called a filter. The filter is a device for filtering waves. "wave" is a very broad physical concept, and in the field of electronics, is narrowly limited to refer specifically to processes that describe the variation of values of various physical quantities over time. This process is converted into a time function of voltage or current, called time waveform of various physical quantities, or called signal, by the action of various sensors. Since the argument time is continuously valued, it is called a continuous time signal, which is also conventionally called an analog signal.

The above embodiments may be combined with each other.

It should be noted that the terms "first," "second," and the like in the description and claims of this application and in the drawings described above are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the application described herein are capable of operation in sequences other than those illustrated or described herein.

Although the present invention has been described in detail with reference to the foregoing description, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.

Claims

1. A high accuracy IQ imbalance correction system, comprising: the system comprises a sending end module, a receiving end module and a digital pre-distortion module, wherein the sending end module is connected with the receiving end module which is connected with the digital pre-distortion module, and the digital pre-distortion module is connected with a filter;

the digital predistortion module is used for correcting by using a filter which is pre-compensated and arranged on a digital baseband, converting frequency domain response into finite long impulse response FIR filter tap coefficients of a time domain, wherein the compensated response comprises IQ two paths;

the digital predistortion module comprises an ADC module, a PA output module and a model module, wherein the ADC module is used for realizing acquisition of a PA output I path signal, the PA output module is used for inputting z and outputting y to carry out antecedent modeling on the PA, z is sent into the extracted PA forward model module to recover a power amplifier complex baseband output signal y ', y' and z are respectively used as the input and the output of the model to realize updating of a DPD module coefficient, and the same principle is realized during Q path observation;

wherein z represents a signal obtained after digital pre-distortion processing of the acquired I-path baseband signal, y represents a signal output after z passes through the PA output module, and y' represents a signal output by the PA forward model.

2. The IQ imbalance correction system according to claim 1, wherein the transmitting end module comprises a DPD module for pre-correcting the original baseband I/Q input signal.

3. The IQ imbalance correction system according to claim 1, wherein the receiver module comprises a data receiver module, an analog-to-digital converter, a digital-to-analog converter and a RF processing module, the data receiver module receives the pre-corrected signal and sends it to the low noise amplifier for amplification, and the pre-corrected signal is down-converted to an intermediate frequency analog signal by the IQ quadrature demodulator, and the analog-to-digital converter is used to convert the intermediate frequency analog signal to an intermediate frequency digital signal.

4. The IQ imbalance correction system according to claim 1, wherein the digital predistortion module corrects for power amplifier non-linearities and corrects for local oscillator leakage and mirror image of the modulator.

5. A high accuracy IQ imbalance correction system according to claim 1 wherein the image rejection ratio is greater than 60dbc and evm is no greater than-42 dB.

6. A high accuracy IQ imbalance correction system according to claim 1 wherein both DPD configurations are iterated 4 times and PA is refined before and after DPD correction for both open loop configurations.

7. A high accuracy IQ imbalance correction system according to claim 1 wherein the filter is coupled to an in-phase mixer and the in-phase mixer is coupled to a quadrature-phase mixer, the filter comprising a plurality of low pass filters.

8. A high precision IQ imbalance correction system according to claim 1 wherein the time domain finite long impulse response FIR filter compensates smoothly for the 3dB bandwidth of the low pass filter, the 3 half band interpolation filters interpolating or bypassing with 2 times the coefficients.

9. A high accuracy IQ imbalance correction system according to claim 1 with TIA support passband bandwidth up to 225MHz with I and Q converted by Σ Δ ADC and filtered in half band decimation stage and programmable RFIR.