KR20210063368A - Crest factor reduction method for cable TV amplifier and circuit therefor - Google Patents

Abstract

A crest factor reduction (CFR) system includes a digital tilt filter coupled to the input of the CFR system. In some embodiments, the digital tilt filter is configured to receive a system input signal and generate a digital tilt filter output signal at the digital tilt filter output. In some examples, the CFR system further comprises a CFR module coupled to a digital tilt filter output, wherein the CFR module receives the digital tilt filter output signal and generates a digital tilt to generate a CFR module output signal at the CFR module output and perform a CFR process on the filter output signal. Additionally, the CFR system can include a digital tilt equalizer coupled to the CFR module output, wherein the digital tilt equalizer is configured to receive the CFR module output signal and generate a system output signal.

Description

Crest factor reduction method for cable TV amplifier and circuit therefor

BACKGROUND OF THE INVENTION Examples of the present disclosure relate generally to integrated circuits (“ICs”), and more particularly to embodiments related to performing crest factor reduction for cable TV (CATV) amplifiers.

In order to meet the demands for higher data rates of Internet telephony, and video services, the cable industry has developed a new high data rate and broadband remote PHY based on the new Data Over Cable Service Interface Specification (DOCSIS) 3.1 standards. Deploying the node. DOCSIS 3.1 supports 4096 quadrature amplitude modulation (QAM) and uses orthogonal frequency division multiplexing (OFDM). Therefore, the transmit signal quality requirements for DOCSIS 3.1 are much higher than for the current standard DOCSIS 3.0. Due to the more sophisticated functions associated with DOCSIS 3.1, cable television (CATV) amplifiers can operate in non-linear regions. The non-linear effects of the CATV amplifier will significantly degrade the transmit signal quality. Additionally, new components that provide the higher data rates and more sophisticated features of DOCSIS 3.1 will themselves consume power. However, since the power supply to each node (eg, each remote PHY node) is fixed, the power consumption of other components (eg, CATV amplifiers) must be reduced. Thus, while providing the advanced performance of DOCSIS 3.1 is desirable, it has been difficult to do so while providing improved transmit signal quality and reduced power consumption of other components (eg, CATV amplifiers).

Accordingly, a need exists for improved methods and circuits for crest factor reduction for CATV amplifiers.

In some embodiments according to the present disclosure, a crest factor reduction (CFR) system includes a digital tilt filter coupled to an input of the CFR system. In some embodiments, the digital tilt filter is configured to receive a system input signal and generate a digital tilt filter output signal at the digital tilt filter output. In some examples, the CFR system further comprises a CFR module coupled to a digital tilt filter output, wherein the CFR module receives the digital tilt filter output signal and generates a digital tilt to generate a CFR module output signal at the CFR module output and perform a CFR process on the filter output signal. Additionally, the CFR system can include a digital tilt equalizer coupled to the CFR module output, wherein the digital tilt equalizer is configured to receive the CFR module output signal and generate a system output signal.

In some embodiments, the CFR system further comprises a digital predistortion (DPD) module coupled to the CFR module output, wherein the DPD module receives the CFR module output signal and generates a DPD module output signal at the DPD module output. is configured to perform a DPD process on the CFR module output signal. In some cases, the digital tilt equalizer is coupled to the DPD module output, the digital tilt equalizer configured to receive the DPD module output signal and generate a system output signal.

In some embodiments, the system input signal has a first peak-to-average power ratio (PAPR) and the CFR module output signal has a second PAPR less than the first PAPR.

In some embodiments, the CFR system further comprises a first linear datapath coupled to the input of the CFR system and in parallel with the CFR module and the DPD module to generate a first time-delay signal. In some examples, the CFR system also includes a first combiner configured to combine the digital tilt equalizer output signal and the first time-delay signal to generate a system output signal.

In some embodiments, the CFR system further comprises a second linear datapath coupled in parallel with the CFR module and at the input of the CFR system to generate a second time-delay signal. By way of example, the second combiner is configured to combine the CFR module output signal and the second time-delay signal to generate a first output signal, and the third combiner is configured to combine the first output signal and the DPD to generate a system output signal. configured to couple the module output signal.

In some embodiments, the CFR system further comprises a non-linear datapath coupled to the CFR module output, wherein the non-linear datapath comprises a plurality of parallel datapath elements each coupled to the CFR module output and , each of the plurality of parallel datapath elements is configured to add a different inverse non-linear component corresponding to the non-linear component of the amplifier to the CFR module output signal, and the combiner is configured to add a different inverse non-linear component to the CFR module output signal to generate the DPD module output signal. and combine the output of each of the datapath elements.

In some embodiments, a digital-to-analog converter (DAC) is configured to receive a system output signal and generate a DAC output signal, wherein the analog tilt filter is configured to receive the DAC output signal and generate an analog tilt filter output signal and the digital tilt filter is configured to model the analog tilt filter.

In some embodiments, the digital tilt equalizer is configured to model the inverse of the analog tilt filter.

In some embodiments, the CFR system further comprises a single side band Hilbert filter, wherein the single side band Hilbert filter input is configured to receive a DPD module output signal, and wherein the single side band Hilbert filter output is It is coupled to the digital tilt equalizer input.

In some embodiments, the CFR system further comprises a calibration engine configured to receive feedback data from the amplifier output, wherein, based on the feedback data, the calibration engine is configured to update a configuration of the CFR module.

In some embodiments according to the present disclosure, a digital front-end (DFE) system is configured to perform a crest factor reduction (CFR) process, and the DFE system receives and receives a baseband data input signal to generate a composite signal. and a digital upconverter (DUC) configured to convert. In various embodiments, the DFE system further comprises a CFR system comprising a digital tilt filter, a CFR module, and a digital tilt equalizer, wherein the digital tilt filter is configured to receive the composite signal and generate a digital tilt filter output signal. and the CFR module is configured to receive the digital tilt filter output signal, and perform a CFR process on the digital tilt filter output signal to generate a CFR module output signal, the digital tilt equalizer receives the CFR module output signal and receives the CFR system and generate an output signal, the CFR system output signal coupled to the amplifier. In some examples, the DFE system further comprises a steering engine configured to receive feedback data from an output of the amplifier, wherein, based on the feedback data, the adjustment engine is configured to update a configuration of the CFR system.

In some embodiments, the CFR process is configured to reduce a peak-to-average power ratio (PAPR) of the digital tilt filter output signal.

In some embodiments, the CFR system further comprises a digital predistortion (DPD) module comprising a non-linear datapath coupled to the CFR module output, wherein the non-linear datapath is each coupled to the CFR module output a plurality of parallel datapath elements, each of the plurality of parallel datapath elements configured to model a different inverse non-linear component corresponding to a non-linear component of the amplifier, the combiner to generate a DPD module output signal and wherein the digital tilt equalizer is configured to receive the DPD module output signal and generate a CFR system output signal.

In some embodiments, a digital-to-analog converter (DAC) is configured to receive a CFR system output signal and generate a DAC output signal, wherein the analog tilt filter receives the DAC output signal and generates an analog tilt filter output signal and the digital tilt filter is configured to model the analog tilt filter.

In some embodiments, the digital tilt equalizer is configured to model the inverse of the analog tilt filter.

In some embodiments according to the present disclosure, a method includes receiving an input signal at a digital tilt filter of a crest factor reduction (CFR) system, and generating a digital tilt filter output signal at a digital tilt filter output. In various examples, the method further comprises, at a CFR module of the CFR system, performing a CFR process on the digital tilt filter output signal to generate a CFR module output signal, wherein the CFR process comprises: It is configured to reduce the peak-to-average power ratio (PAPR). In some examples, the method further comprises receiving a CFR module output signal at a digital tilt equalizer of the CFR system, and generating a system output signal. In some embodiments, the method further comprises providing a system output signal to an amplifier.

In some embodiments, the method further comprises updating the configuration of the CFR system in response to the feedback data received from the output of the amplifier.

In some embodiments, the method further comprises, in a digital predistortion (DPD) module of the CFR system, performing a DPD process on the CFR module output signal to generate a DPD module output signal. In some examples, the method further comprises receiving a DPD module output signal at a digital tilt equalizer of the CFR system, and generating a system output signal.

In some embodiments, the DPD module further comprises a non-linear datapath coupled to an output of the CFR module, wherein the non-linear datapath comprises a plurality of parallel datapath elements each coupled to the CFR module output and, each of the plurality of parallel datapath elements is configured to model a different inverse non-linear component corresponding to a non-linear component of the amplifier, and the combiner includes the plurality of parallel datapath elements to generate the DPD module output signal. configured to couple the respective outputs.

In some embodiments, the method further comprises reducing power consumption of the amplifier in response to providing a system output signal to the amplifier and while operating the amplifier in the non-linear region.

In some embodiments according to the present disclosure, a digital predistortion (DPD) system includes an input configured to receive a DPD input signal. In some embodiments, the DPD system further comprises a non-linear datapath coupled to the input, wherein the non-linear datapath comprises a plurality of parallel datapath elements each coupled to the input, and wherein the plurality of parallel datapath elements are each coupled to the input. each of the datapath elements is configured to add a different inverse non-linear component corresponding to the non-linear component of the amplifier to the DPD input signal, wherein the first combiner is configured to generate a first predistortion signal in the plurality of parallel datapaths configured to couple the output of each of the elements. In some embodiments, the DPD system comprises a linear datapath coupled to the input in parallel with the non-linear datapath to generate a second predistortion signal, and a first predistortion signal to generate a DPD output signal. and a second combiner configured to couple the second predistortion signal.

In some embodiments, the plurality of parallel datapath elements comprises a baseband DPD datapath, a video bandwidth DPD datapath, a second harmonics DPD datapath, and a third harmonic DPD datapath.

In some embodiments, the baseband DPD datapath is configured to add an inverse non-linear baseband component to the DPD input signal.

In some embodiments, the video bandwidth DPD datapath is configured to add an inverse non-linear video bandwidth component to the DPD input signal.

In some embodiments, the second harmonic DPD datapath is configured to add an inverse second harmonic component to the DPD input signal.

In some embodiments, the third harmonic DPD datapath is configured to add an inverse third harmonic component to the DPD input signal.

In some embodiments, the DPD system further comprises a digital tilt filter configured to model an analog tilt filter, wherein the digital tilt filter input is coupled to the input, and the digital tilt filter output is coupled to the non-linear datapath. .

In some embodiments, the DPD system further comprises a digital tilt equalizer configured to model the inverse of the analog tilt filter, wherein the digital tilt equalizer input is configured to receive the first predistortion signal and the second combiner is the DPD output and couple the digital tilt equalizer output to the second predistortion signal to generate a signal.

In some embodiments, the DPD system further comprises a single side band Hilbert filter, wherein the single side band Hilbert filter input is configured to receive the first predistortion signal and the single side band Hilbert filter output is a digital tilt equalizer input is coupled to

In some embodiments, the DPD output signal is coupled to an amplifier input to generate an amplified output signal, the DPD output signal configured to compensate for a plurality of non-linear components of the amplifier.

In some embodiments according to the present disclosure, a digital front-end (DFE) system configured to perform a digital predistortion (DPD) process is a digital front-end (DFE) system configured to receive and convert a baseband data input signal to generate a composite signal. upconverter). In some embodiments, the DFE system further comprises a DPD system configured to receive the composite signal at the DPD input and perform a DPD process on the composite signal, wherein the DPD input is coupled to the plurality of parallel datapath elements; At least one of the plurality of parallel datapath elements is configured to add an inverse harmonic component corresponding to a non-linear harmonic component of the amplifier to the composite signal, and the combiner is configured to add an inverse harmonic component corresponding to a non-linear harmonic component of the amplifier to each of the plurality of parallel datapath elements to generate a DPD output signal and the DPD output signal is coupled to the amplifier. In some embodiments, the DPD output signal is configured to compensate for a non-linear harmonic component of the amplifier.

In some embodiments, the plurality of parallel datapath elements comprises a baseband DPD datapath, a video bandwidth DPD datapath, a second harmonic DPD datapath, and a third harmonic DPD datapath.

In some embodiments, the DUC is configured to perform an interpolation process on the baseband data input signal to generate an interpolated signal, and the DUC performs a mixing process on the interpolated signal to generate a composite signal. configured to perform

In some embodiments, the DPD system further comprises a digital tilt filter configured to model the analog tilt filter, wherein the digital tilt filter input is configured to receive the composite signal and the digital tilt filter output comprises a plurality of parallel datapath elements. is coupled to

In some embodiments, the DPD system further comprises a digital tilt equalizer configured to model the inverse of the analog tilt filter, wherein the digital tilt equalizer input is configured to receive a combined output of each of the plurality of datapath elements, Another combiner is configured to couple the digital tilt equalizer output to the linear DPD signal to generate a DPD output signal.

In some embodiments according to the present disclosure, the method includes receiving a DPD input signal at an input of a digital predistortion (DPD) system. In some embodiments, the method further comprises receiving a DPD input signal in a non-linear data path coupled to an input of the DPD system, wherein the non-linear data path includes a plurality of each coupled to the input. Contains parallel datapath elements. In some embodiments, the method further comprises adding, by each of the plurality of parallel datapath elements, to the DPD input signal an inverse non-linear component corresponding to the non-linear component of the amplifier. In some embodiments, the method further comprises combining the output of each of the plurality of parallel datapath elements to generate a first predistortion signal by the first combiner. In some embodiments, the method further comprises receiving the DPD input signal in a linear datapath coupled to the input in parallel with the non-linear datapath to generate a second predistortion signal. In some embodiments, the method further comprises combining, by a second combiner, the first predistortion signal and the second predistortion signal to generate a DPD output signal.

In some embodiments, the plurality of parallel datapath elements comprises a baseband DPD datapath, a video bandwidth DPD datapath, a second harmonic DPD datapath, and a third harmonic DPD datapath.

In some embodiments, the method further comprises adding, by a baseband DPD datapath, an inverse non-linear baseband component to the DPD input signal; adding, by the video bandwidth DPD datapath, an inverse non-linear video bandwidth component to the DPD input signal; adding an inverse second harmonic component to the DPD input signal by the second harmonic DPD datapath; and adding, by the third harmonic DPD datapath, an inverse third harmonic component to the DPD input signal.

In some embodiments, the method further comprises providing a DPD output signal to an amplifier input to generate an amplified output signal, wherein the DPD output signal is configured to compensate for a plurality of non-linear components of the amplifier .

In some embodiments, the method further comprises reducing power consumption of the amplifier in response to providing the DPD output signal to the amplifier and while operating the amplifier in the non-linear region.

Other aspects and features will become apparent from a reading of the following detailed description and accompanying drawings.

1 is a block diagram illustrating an example architecture for an IC, in accordance with some embodiments of the present disclosure.
2 is a schematic diagram of an exemplary cable network, in accordance with some embodiments.
3 is a schematic diagram of an exemplary digital front-end (DFE) system, in accordance with some embodiments.
4A provides a diagram of a digital predistortion (DPD)-crest factor reduction (CFR) system, in accordance with some embodiments.
4B provides an example of a DPD module, in accordance with some embodiments.
5A and 5B provide exemplary DPD-CFR input spectra and DPD-CFR output spectra, respectively, in accordance with some embodiments.
6A shows a normalized magnitude of an analog tilt filter output sampled over time and provides an exemplary plot showing the effect of performing a CFR process, in accordance with some embodiments.
6B illustrates a power spectrum at the output of an analog tilt filter after performing a CFR process, in accordance with some embodiments.
7A, 7B, and 7C show normalized magnitude of a CATV amplifier output sampled over time, and provide example plots showing the effect of performing a CFR process, in accordance with some embodiments.
8A illustrates a cumulative distribution function (CCDF) plot for a single carrier, showing the effect of performing a CFR process, in accordance with some embodiments.
8B illustrates a power spectrum corresponding to the data of FIG. 8A on which a CFR process has been performed, in accordance with some embodiments.
9A and 9B are of a CATV amplifier transfer function showing amplitude-to-amplitude distortion (AM/AM) and illustrating the effect of performing one or both of a DPD process and a CFR process, in accordance with some embodiments; Plots are provided.
10A and 10B provide plots of DPD output stability performance, showing the effect of performing a CFR process, in accordance with some embodiments.
11 provides a table containing MER data for a CATV amplifier showing the effect of applying corrections provided by a DPD-CFR system to modulation error ratio (MER) data, in accordance with some embodiments.
12 is a flowchart illustrating a method for performing a crest factor reduction process and a digital predistortion process in a DPD-CFR system, in accordance with some embodiments.
13 , 14 , 15 and 16 illustrate equations (including schematic representations) that provide derivations for each of the non-linear datapath elements of FIG. 4 , in accordance with some embodiments.
17 illustrates a power spectrum for a single carrier showing non-linear effects of a CATV amplifier, in accordance with some embodiments.
18 illustrates a power spectrum showing a result of applying baseband DPD correction to the power spectrum of FIG. 17 , in accordance with some embodiments.
19 illustrates a power spectrum showing a result of applying a second harmonic DPD correction to the power spectrum of FIG. 17 , in accordance with some embodiments.
20 illustrates a power spectrum showing a result of applying a third harmonic DPD correction to the power spectrum of FIG. 17 , in accordance with some embodiments.
21 illustrates a power spectrum showing results of applying both baseband DPD correction and video bandwidth DPD correction, in accordance with some embodiments.
22 illustrates a power spectrum showing an adjacent channel power ratio (ACPR) correction resulting from application of corrections provided by a DPD system, in accordance with some embodiments.
23 provides a table containing MER data for a CATV amplifier showing the effect of applying corrections provided by a DPD system to modulation error ratio (MER) data, in accordance with some embodiments.
24 is a flowchart illustrating a method for performing a digital predistortion process in a DPD system, in accordance with some embodiments.

Various embodiments are described below with reference to the drawings, in which exemplary embodiments are shown. However, the claimed invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Like reference numbers refer to like elements throughout. Accordingly, similar elements will not be described in detail in the description of each figure. It should also be noted that the drawings are only intended to facilitate description of the embodiments. They are not intended as a complete description of the claimed invention or as a limitation on the scope of the claimed invention. Additionally, an illustrated embodiment need not have all aspects or advantages shown. An aspect or advantage described in connection with a particular embodiment is not necessarily limited to that embodiment, and may be practiced in any other embodiment, even if not so illustrated or explicitly described. Features, functions, and advantages may be achieved independently in various embodiments, or may be combined in still other embodiments.

Before describing the exemplary embodiments illustrated by way of example in several figures, a general introduction is provided for further understanding.

As discussed above, the cable industry is deploying a new high data rate and broadband remote PHY node based on the DOCSIS 3.1 standards to meet the demands for higher data rates of Internet, telephony, and video services. DOCSIS 3.1 supports 4096 (4K) quadrature amplitude modulation (QAM) and uses orthogonal frequency division multiplexing (OFDM). Therefore, the transmit signal quality requirements for DOCSIS 3.1 are much higher than for the current standard DOCSIS 3.0. Due to the more sophisticated functions associated with DOCSIS 3.1, cable television (CATV) amplifiers can operate in non-linear regions. The non-linear effects of the CATV amplifier will significantly degrade the transmit signal quality. Additionally, new components that provide the higher data rates and more sophisticated features of DOCSIS 3.1 will themselves consume power. However, since the power supply to each node (eg, each remote PHY node) is fixed, the power consumption of other components (eg, CATV amplifiers) must be reduced. Thus, while providing the advanced performance of DOCSIS 3.1 is desirable, it has been difficult to do so while providing improved transmit signal quality and reduced power consumption of other components (eg, CATV amplifiers).

In at least some existing techniques, a tilt equalizer (tilt filter) with deep attenuation of up to 22 dB over the 1.2 GHz cable spectrum to compensate for coaxial cable losses (eg, from a CATV amplifier to a cable modem) is used for analog transmission. implemented in the path. However, the DOCSIS 3.1 waveform using 4K QAM OFDM modulation shows a high peak-to-average power ratio (PAPR) compared to the current DOCSIS 3.0 standard. Therefore, for the same RMS power output of a CATV amplifier in DOCSIS 3.0, the peak of the DOCSIS 3.1 waveform will be in the non-linear region of the CATV amplifier. Accordingly, the transmission signal quality is deteriorated. Digital predistortion (DPD) can be used to improve the signal quality for a CATV amplifier, for example by allowing the CATV to operate in a higher efficiency region. DPD has been used for wireless communication technologies, where the signal bandwidth is much narrower than that used for cable communication technologies. Additionally, in wireless communications, harmonics of non-linear effects of wireless components do not fall within the signal bandwidth. Therefore, DPD for wireless communications only needs to model the projected non-linear components around the baseband frequency. However, for cable applications, harmonics of non-linear effects of the CATV amplifier signal fall into the signal bandwidth. Accordingly, DPD implementations for cable applications must model the harmonic components of non-linear effects on a CATV amplifier. Separately, a tilt equalizer with deep attenuation may not be implemented in the digital domain, and a digital tilt equalizer implementation may not be implemented in the transmit waveform quality of lower frequency carriers due to the finite digital resolution of the digital-to-analog converter (DAC). will degrade

Additionally, as mentioned above, the DOCSIS 3.1 waveform using 4K QAM OFDM modulation shows a high PAPR compared to the current DOCSIS 3.0 standard. Some of the effects of high PAPR include in-band distortion and out-of-band distortion (including, for example, increased adjacent channel leakage ratio (ACLR)). Crest factor reduction (CFR) can be used to reduce the PAPR of a signal by clipping the signal and allowing additional gain in the CFR output. Clipping works by intentionally limiting the signal so that the amplitude is limited to a maximum value within a desired range. By using CFR, it is possible to operate an amplifier (eg a CATV amplifier) closer to its 1-dB compression point, which increases the efficiency of the CATV amplifier. Moreover, when combined with DPD, CFR can be used to significantly improve DPD stability (eg, and avoid DPD divergence) and further increase CATV amplifier efficiency. For integrated circuit (IC) solutions, CFR and DPD data paths implemented within a digital front-end (DFE) chip provide a solution to the high PAPR, DPD stability, and CATV amplifier efficiency of DOCSIS 3.1 waveforms as well as CATV It has been found that it can provide modeling of harmonic components of non-linear effects on an amplifier and deep attenuation across the transmit spectrum in CATV amplifiers. Accordingly, embodiments of the present disclosure provide improved transmit signal quality, increased CATV amplifier efficiency, and reduced power consumption of CATV amplifiers.

With the above general understanding in mind, various embodiments are generally described below for providing methods and circuits for CFR for CATV amplifiers. Because one or more of the above-described embodiments are illustrated using a particular type of IC, a detailed description of such an IC is provided below. However, it should be understood that other types of ICs may benefit from one or more of the embodiments described herein.

“Programmable logic devices” (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, or "FPGA" (field programmable gate array), typically includes an array of programmable tiles. These programmable tiles are, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, “DSPs”. "(digital signal processing blocks)", processors, clock managers, "DLLs" (delay lock loops), and the like. As used herein, “comprises” and “comprising” mean including without limitation.

Each programmable tile typically includes both a programmable interconnect and programmable logic. A programmable interconnect typically includes a large number of interconnect lines of various lengths interconnected by programmable interconnect points (“PIPs”). Programmable logic implements the logic of a user design using programmable elements, which may include, for example, function generators, registers, arithmetic logic, and the like.

The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data may be read from memory (eg, from an external PROM) or written to the FPGA by an external device. The aggregate states of the individual memory cells then determine the function of the FPGA.

Another type of PLD is a Complex Programmable Logic Device (CPLD). A CPLD includes two or more “functional blocks” connected together and to “I/O” (input/output) resources by an interconnecting switch matrix. Each functional block of a CPLD includes a two-level AND/OR structure similar to those used in "PLA" (Programmable Logic Array) and "PAL" (Programmable Array Logic) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory and then downloaded to volatile memory as part of an initial configuration (programming) sequence.

Generally, in each of these programmable logic devices (PLDs), the functionality of the device is controlled by configuration data provided to the device for that purpose. The configuration data is stored in volatile memory (eg, static memory cells as is common in FPGAs and some CPLDs), non-volatile memory (eg, flash memory as in some CPLDs), or any other type of memory cell. can be

Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs may also be implemented in other manners, such as using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include, but are not limited to, encompassing these exemplary devices as well as only partially programmable devices. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.

As mentioned above, advanced FPGAs may include several different types of programmable logic blocks in an array. For example, FIG. 1 illustrates an example FPGA architecture 100 . The FPGA architecture 100 includes multi-gigabit transceivers (“MGTs”) 101 , configurable logic blocks (“CLBs”) 102 , random access memory blocks (“BRAMs”) 103 , and “IOBs”. "(input/output blocks) 104, configuration and clocking logic ("CONFIG/CLOCKS") 105, "DSP" (digital signal processing blocks) 106, specialized input/output blocks ( “I/O”) 107 (eg, configuration ports and clock ports), and other programmable logic 108 such as digital clock managers, analog-to-digital converters, system monitoring logic, etc. It contains a number of different programmable tiles. Some FPGAs also include dedicated processor blocks (“PROCs”) 110 . In some embodiments, the FPGA architecture 100 includes RF data including multiple radio frequency analog-to-digital converters (RF-ADCs) and multiple radio frequency digital-to-analog converters (RF-DACs). Includes a converter subsystem. In various examples, RF-ADCs and RF-DACs may be configured individually for real data or configured in pairs for real and imaginary I/Q data. In at least some examples, FPGA architecture 100 may implement an RFSoC device.

In some FPGAs, each programmable tile has at least one having connections to input and output terminals 120 of a programmable logic element within the same tile, as shown by the examples included at the top of FIG. 1 . programmable interconnection elements (“INTs”) 111 . Each programmable interconnection element 111 may also include connections for interconnecting segments 122 of adjacent programmable interconnection element(s) in the same tile or in different tile(s). Each programmable interconnection element 111 may also include connections for interconnecting segments 124 of general routing resources between logic blocks (not shown). Typical routing resources are between logic blocks (not shown) containing tracks of interconnect segments (eg, interconnect segments 124 ) and switch blocks (not shown) for connecting interconnect segments. of routing channels. The interconnect segments (eg, interconnect segments 124 ) of general routing resources may span one or more logical blocks. The programmable interconnect elements 111 taken together with common routing resources implement the programmable interconnect structure (“programmable interconnect”) for the illustrated FPGA.

In an example implementation, CLB 102 may include a “configurable logic element” (CLE) 112 that can be programmed to implement user logic plus a single programmable interconnection element (“INT”) 111 . have. BRAM 103 may include a “BRAM logic element” (BRL) 113 in addition to one or more programmable interconnect elements. Typically, the number of interconnecting elements included in a tile depends on the height of the tile. In the example shown, the BRAM tile has the same height as 5 CLBs, but other numbers (eg, 4) may also be used. The DSP tile 106 may include a DSPL (“DSP logic element”) 114 in addition to an appropriate number of programmable interconnect elements. IOB 104 may include, for example, two instances of an “input/output logic element” (IOL) 115 in addition to one instance of programmable interconnection element 111 . As will be apparent to those skilled in the art, for example, the actual I/O pads connected to the I/O logic element 115 are typically not limited to the area of the input/output logic element 115 .

In the example of FIG. 1 , the region (shown horizontally) near the center of the die (eg, formed in regions 105 , 107 , and 108 shown in FIG. 1 ) is for configuration, clock, and other control logic can be used A column 109 (shown vertically) extending from this horizontal region or other columns may be used to distribute clocks and configuration signals across the width of the FPGA.

Some FPGAs using the architecture illustrated in FIG. 1 include additional logic blocks that interfere with the general thermal structure that makes up much of the FPGA. The additional logic blocks may be programmable blocks and/or dedicated logic. For example, PROC 110 spans several columns of CLBs and BRAMs. PROC 110 may include various components ranging from a single microprocessor to a complete programmable processing system, such as microprocessor(s), memory controllers, peripherals, and the like.

In one aspect, PROC 110 is implemented as dedicated circuitry fabricated as part of a die implementing programmable circuitry of an IC, such as a hard-wired processor. PROC 110 can be configured in a variety of different ways, ranging in complexity from an individual processor, eg, a single core capable of executing program code, to an entire processor system having one or more cores, modules, co-processors, interfaces, etc. may represent any of the systems and/or processor types.

In other aspects, PROC 110 is omitted from architecture 100 and may be replaced with one or more of the various other described programmable blocks. Additionally, such blocks may be used to form a “soft processor” in that various blocks of programmable circuitry may be used to form a processor capable of executing program code, such as in the case of PROC 110 . .

The phrase “programmable circuit” refers to programmable circuit elements within an IC (eg, various programmable or configurable circuit blocks or tiles described herein), as well as various circuit blocks depending on configuration data loaded into the IC. , tiles, and/or interconnect circuitry that selectively couples elements. For example, the portions shown in FIG. 1 that are external to PROC 110 , such as CLBs 102 and BRAMs 103 , may be considered programmable circuitry of the IC.

In some embodiments, the function and connection of the programmable circuit is not established until the configuration data is loaded into the IC. The set of configuration data may be used to program programmable circuitry of an IC, such as an FPGA. In some cases, the configuration data is referred to as a “configuration bitstream”. Generally, the programmable circuitry does not operate or function without first loading the configuration bitstream into the IC. The configuration bitstream effectively implements or instantiates a particular circuit design within the programmable circuit. Circuit design specifies, for example, functional aspects of the programmable circuit blocks and the physical connections between the various programmable circuit blocks.

In some embodiments, "hardwired" or "hardened", ie, non-programmable circuitry, is fabricated as part of the IC. Unlike programmable circuitry, hardwired circuitry or circuit blocks are not implemented through the loading of the configuration bitstream after fabrication of the IC. Hardwired circuitry is generally considered to have dedicated circuit blocks and interconnects that function without, for example, first loading a configuration bitstream into an IC, such as PROC 110 .

In some instances, a hardwired circuit may have one or more modes of operation that may be set or selected according to register settings or values stored in one or more memory elements within the IC. The operating modes may be set, for example, via loading the configuration bitstream into the IC. Despite this capability, hardwired circuitry is not considered programmable circuitry because, when manufactured as part of an IC, the hardwired circuitry is operable and has specific functions.

1 is intended to illustrate an example architecture that may be used to implement an IC comprising programmable circuitry, such as a programmable fabric. For example, the number of logic blocks in a row, the relative width of the rows, the number and order of the rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and the interconnect/logic implementation included at the top of FIG. 1 . These are purely exemplary. For example, in a real IC, whenever CLBs appear, more than one contiguous row of CLBs is typically included to facilitate efficient implementation of user logic, although the number of contiguous CLB rows varies with the overall size of the IC. . The FPGA of FIG. 1 also illustrates an example of a programmable IC that may utilize examples of interconnect circuits described herein. The interconnect circuits described herein may be used in other types of programmable ICs, such as CPLDs or any type of programmable IC having a programmable interconnect structure for selectively coupling logic elements.

The IC capable of implementing methods and circuits for CFR for CATV amplifiers is not limited to the example IC shown in FIG. 1 , ICs having other configurations or other types of ICs may also be used for CFR for CATV amplifiers. Note that it is possible to implement methods and circuits for

Referring now to FIG. 2 , a cable network 200 showing a signal path starting from a data fiber (eg, may include optical fiber) through a remote node to an end user location (eg, at home). ) is exemplified here. Cable network 200 may be part of a hybrid fiber-coaxial network, where data fibers run from a central headend to remote nodes, and coaxial cables run from remote nodes to end users. In some examples, the remote node comprises a remote PHY node based on the DOCSIS 3.1 standards. In some embodiments, the remote PHY node may include a baseband and digital front-end (DFE) chip 202 , a digital-to-analog converter (DAC) 204 , a driver 206 (eg, an amplifier). ), an analog tilt filter 208 , a power splitter 210 , and CATV amplifiers 212 . In various examples, the baseband and DFE chip 202 may be implemented as a single chip, or as separate chips including a baseband processor chip and a separate DFE chip. In some embodiments, DAC 204 may be implemented as an RF DAC or IF DAC, for example, depending on the input to DAC 204 . Additionally, in some embodiments, baseband and DFE chip 202 and DAC 204 may be implemented in a single chip (eg, as in an RFSoC device). Furthermore, one or more components of the remote PHY node may be implemented in a programmable logic device, such as the programmable logic device of FIG. 1 . As shown in FIG. 2 , the data fiber is coupled as an input to the baseband and DFE chip 202 , and the output of the baseband and DFE chip 202 is coupled as an input to the DAC 204 . Power spectrum 214 (no slope) provides an example of the shape of the signal at the output of baseband and DFE chip 202 . The output of the DAC 204 is coupled as an input to a driver 206 , and the output of the driver 206 is coupled as an input to an analog tilt filter 208 . For cable applications, the analog tilt filter 208 may be used to vary the gain across the power spectrum of the signal. Stated another way, the analog tilt filter 208 is used to add a slope to the power levels of the signal across the power spectrum. Power spectrum 216 illustrates the slope (eg, positive slope in this example) of the signal compared to power spectrum 214 at the output of analog tilt filter 208 .

In some embodiments, the output of the analog tilt filter 208 is coupled to the power divider 210 as an input. In the example of FIG. 2 , power divider 210 includes a 1×4 power divider with a single input and four outputs. However, in some embodiments, power divider 210 is a 1x2 power divider having a single input and two outputs, a cascade of 1x2 power dividers (eg, to generate 4 outputs), or other types of power dividers. In this example, each of the four outputs of the power divider 210 is connected to a CATV amplifier 212 as an input. The output of each of the CATV amplifiers 212 is then coupled to a coaxial cable, which is further coupled to a cable modem at an end user location (eg, at home). In at least some embodiments, cable network 200 implements a Node+0 architecture, which follows a coaxial cable path between a remote PHY node and an end user location (beyond CATV amplifiers 212 at the remote PHY node). ) means that there are no additional CATV amplifiers. 2 shows a power spectrum 218 showing the coaxial cable loss spectrum (eg, having a negative slope), a power spectrum 219 showing the output signal of the CATV amplifiers 212 , and the signal arriving at the end user location. Further illustrated is a power spectrum 220 showing the (without slope) power spectrum of As previously discussed, the analog tilt filter 208 is used to compensate for coaxial cable losses (eg, from the CATV amplifiers 212 to the cable modem at the end user location).

In at least some existing cable networks, CATV amplifiers operate in the linear region. This means that the amount of non-linearity at the output of the CATV amplifier is low enough that no additional signal processing is required, and the signal at the output of the CATV amplifier is transmitted directly over the coaxial cable to the end user for demodulation and information transfer. The location can be transmitted to the cable modem. However, with the transition to more sophisticated functions and additional power-consuming components associated with DOCSIS 3.1 and because the power supply to each node (eg, each remote PHY node) is fixed, CATV amplifiers and It would be desirable to reduce the power consumption of the same other components. Currently, the efficiency of CATV amplifiers is approximately 2-3%, so for example a single CATV amplifier with an input power of 20 watts will output approximately 1/2 watt of output power. For 4 CATV amplifiers (eg, as shown in FIG. 2 ), an input power of 100 watts will output approximately 2 watts of output power. Therefore, it is highly desirable to make CATV amplifiers more efficient.

At least one option being explored to make CATV amplifiers more efficient is to make them operate in a more non-linear region. However, doing this means that the signal at the output of the CATV amplifier may not be transmitted to the end user location directly over the coaxial cable without some kind of additional digital signal processing, as provided in accordance with embodiments of the present disclosure means that For example, as discussed in more detail below, embodiments disclosed herein add functionality within the baseband and DFE chip 202, so that even though CATV amplifiers operate in a non-linear region, the baseband and DFE chip 202 ) will invert or change the signal, so the signal at the output of the CATV amplifier will still be linear and can be easily demodulated by the cable modem at the end user location. Stated another way, if the CATV amplifier has a non-linearity 'x', then the functions in the baseband and DFE chip 202 will have an inverse non-linearity '1/' which will be canceled by the non-linearity 'x' of the CATV amplifier. x' is configured. Therefore, the signal at the output of the CATV amplifier is clean and linear. In general, the process of adding non-linearity beforehand (eg, adding inverse non-linearity in the baseband and DFE chip 202 ) is referred to as predistorting or predistorting. In the context of the baseband and DFE chip 202, and since distortion is added digitally, predistortion may be referred to as digital predistortion (DPD). According to various embodiments, the DPD process is performed using knowledge of the type of non-linearity 'x' that the CATV amplifier (eg, CATV amplifier 212 ) has, so that the DPD process has an appropriate inverse non-linearity ' 1/x' can be added. Thus, the DPD process is a first function added into the baseband and DFE chip 202, according to embodiments of the present disclosure.

Additionally, a second function added within the baseband and DFE chip 202 may include a CFR process. As discussed above, the CFR process can be used to reduce the PAPR of a signal by clipping the signal and allowing additional gain in the CFR output. By using CFR, it is possible to operate the CATV amplifier closer to its 1-dB compression point, which increases the efficiency of the CATV amplifier. Additionally, when combined with a DPD process, the CFR process can be used to significantly improve DPD stability (eg, and avoid DPD divergence) and further increase CATV amplifier efficiency. In various embodiments, the DPD process and the CFR process are baseband and DFE, including any effects and/or distortions introduced by DAC 204 , driver 206 , and analog tilt filter 208 respectively. This is done using knowledge of the signal chain between the chip 202 and the CATV amplifiers 212 . In various embodiments, CATV amplifier efficiency is improved and power consumption is reduced by the DPD process and CFR process disclosed herein.

In some embodiments, the functions within the baseband and DFE chip 202 (eg, including the DPD process and the CFR process) may be implemented primarily as DFE functions, where the baseband output signal is provided to the DFE chip as an input. do. Therefore, with reference now to FIG. 3 , illustrated herein is a DFE system 300 that provides a DFE design configured to perform one or more aspects of the present disclosure. In some embodiments, the DFE system 300 includes a digital upconverter (DUC) 302 . In various examples, DUC 302 is used to convert one or more channels of data from baseband to a passband signal comprising carriers modulated at one or more specified radio or set of intermediate frequencies (RF or IF). do. As an example, the DUC 302 interpolates (eg, to increase the sample rate), filters (eg, to provide rejection and spectral shaping of interpolated images), and shifts the signal spectrum (eg, to the desired carrier frequencies). to achieve this) by performing mixing. In general, the sample rate at the input to DUC 302 is relatively low: for example, the symbol rate of a digital communication system (however, the output is a much higher rate), for example converting digital samples to analog for further analog processing and frequency conversion. The input sample rate to the DAC converting it to a waveform.

As shown in the example of FIG. 3 , a baseband data input is provided to the DUC 302 . The baseband data input includes a plurality of different carriers represented by _{s 1} (n), s ₂ (n), s ₃ (n), s ₄ (n), s ₅ (n), and s _{6 (n).} do. In some embodiments, the sampling rate of the baseband data input is approximately 204.8 MHz corresponding to the OFDM symbol clock. As an example, the DUC 302 generates a plurality of different carriers (eg, from the baseband data input) by initially performing interpolation of the baseband data input, which in this example increases the sampling rate by a factor of 8; Thereby, it is used to switch from a first clock domain (eg, 204.8 MHz clock domain) to a second clock domain (eg, 1638.4 MHz clock domain). After the interpolation process, each of a plurality of different carriers is mixed with a signal from a numerically controlled oscillator (NCO) to shift the frequency of each of the plurality of different carriers to a desired carrier frequency, each NCO having a different frequency. For example, carrier s ₁ (n) is mixed with a first NCO(NCO1) having a first frequency, carrier s ₂ (n) is mixed with a second NCO(NCO2) having a second frequency, and carrier s ₃ ( n) is mixed with a third NCO (NCO3) having a third frequency, carrier s ₄ (n) is mixed with a fourth NCO (NCO4) having a fourth frequency, carrier s ₅ (n) is mixed with a fifth frequency is mixed with a fifth NCO (NCO5) having , and the carrier s ₆ (n) is mixed with a sixth NCO (NCO6) having a sixth frequency. After the mixing process, each of a plurality of different carriers is combined to form a composite signal c(n). Thus, the composite signal c(n) comprises each of a plurality of different carriers being mixed at different frequencies. In some embodiments, and as a result of the mixing process, the composite signal c(n) may appear substantially identical to the signal shown in FIG. 5A , wherein each of a plurality of different carriers are arranged side-by-side in frequency. In some cases, after generation of the composite signal c(n), another interpolation process may optionally be performed, which, in the example of FIG. 3 , increases the sampling rate of the composite signal c(n) by a factor of two, thereby is used to switch from the second clock domain (eg, the 1638.4 MHz clock domain) to the third clock domain (eg, the 3276.8 MHz clock domain). After signal processing by the DUC 302, the composite signal c(n) is provided as an input to the DPD-CFR system 304, which is described in more detail below. In some embodiments, the output of the DPD-CFR system 304 may undergo complex-to-real signal conversion 306 , wherein the output of the complex-to-real signal conversion 306 is an input is provided to the DAC (eg, this may be the DAC 204 of FIG. 2 ). Additionally, one or more components of DFE system 300 may be implemented in a programmable logic device, such as the programmable logic device of FIG. 1 .

As previously discussed, the DPD and CFR processes, and thus the DPD-CFR system 304, use knowledge of the type of non-linearity 'x' that the CATV amplifier has and the baseband and DFE chip 202 . ) and CATV amplifiers 212, the DPD-CFR system 304 adds the appropriate DPD and CFR processes (eg, the appropriate inverse non-linearity '1/x') and reducing the PAPR of the signal) can be effectively implemented. For example, the DPD-CFR system 304 can be used to model a CATV amplifier (eg, including non-linear effects and signal chains). Thus, the models provided by the DPD-CFR system 304 may be generated and/or updated based on the feedback data 308 , where the feedback data 308 is a CATV amplifier (such as a CATV amplifier 212 ). may include an output signal of In some embodiments, feedback data 308 is processed via analog-to-digital converter (ADC) 310 and provided to DPD/CFR adjustment engine 312 as digital feedback data 311 . In various examples, and based on the digital feedback data 311 , the DPD/CFR adjustment engine 312 configures the DPD-CFR system 304 so that the DPD-CFR system 304 can be tuned to the runtime behavior of the CATV amplifier. update More specifically, in some embodiments, the DPD/CFR adjustment engine 312 may determine the configuration of coefficients or other elements of the filters within the DPD-CFR system 304 , typically the DPD-CFR system ( 304), it is possible to configure the CFR and DPD modules discussed below. Thus, by continuously monitoring and updating the models provided by the DPD-CFR system 304 (eg, via the feedback data 308 and the DPD/CFR coordination engine 312 ), optimal DPD and CFR processes may be implemented. have. As an example, aspects of monitoring and updating models (eg, as a function of the DPD/CFR coordination engine 312 ) are stored in memory (eg, in the BRAMs 103 , or in another on-chip memory location). and may be implemented in software executed by one or more on-chip processors (eg, PROC 110 ). Note that in some embodiments, the baseband and DFE chip 202 , DAC 204 , and ADC 310 may be implemented in a single chip (eg, as in an RFSoC device). The example of monitoring and updating the models provided above is not intended to be limiting in any way, and while other methods are possible, it will be understood that embodiments of the present disclosure are not limited by any of the examples provided.

Referring now to FIG. 4A , illustrated herein is a more detailed diagram of the DPD-CFR system 304 described above, used to implement various aspects of the present disclosure. As shown, the DPD-CFR system 304 includes a digital tilt filter 402, a CFR module 404, a DPD module 406, a single side band Hilbert filter 412, and a digital tilt equalizer 414. may include It is noted that one or more components of the DPD-CFR system 304 may be implemented in a programmable logic device, such as the programmable logic device of FIG. 1 .

로 표기된 디지털 틸트 필터(402)의 출력은 입력으로서 CFR 모듈(404)에 제공된다. 다양한 실시예들에서, CFR 모듈(404)은 인입 신호(예컨대, 디지털 틸트 필터(402)의 출력, 즉

)의 PAPR을 감소시키기 위해 CFR 프로세스를 수행할 수 있다. 본 실시예들이 CFR 모듈(404)에 의해 이용되는 임의의 특정한 CFR 기법으로 제한되지 않지만, 예시적인 CFR 기법들은, 적응형 베이스밴드, 중간 주파수(IF) 클립핑 및 필터링, 피크 윈도우잉(peak windowing), 또는 다른 적절한 기법을 포함할 수 있다. CFR 프로세스 이후, CFR 모듈(404)은

로 표기된 출력을 DPD 모듈(406)에 제공한다. 도시된 바와 같이, 디지털 틸트 필터(402)의 출력(

)은 또한, (예컨대, 블록(423)에서) 시간 지연이 신호

)에 도입되는 데이터경로(421)를 따라 제공된다. 예로서, CFR 모듈(404)의 출력(

)은 데이터경로(427)를 따라 추가로 제공되며, 이어서 결합기(425)는 CFR 모듈(404)의 출력(

)을 시간-지연 신호

와 결합시켜 신호

를 초래하는 데 사용된다.With continued reference to FIG. 4A , the functionality of the DPD-CFR system 304 is described in greater detail. For example, in some embodiments, an input signal x(n), which may include the composite signal c(n) discussed above, is provided to the digital tilt filter 402 . In various cases, the digital tilt filter 402 may be used to model the analog tilt filter 208 ( FIG. 2 ). Thus, as an example, the output of the digital tilt filter 402 may be similar to the output of the analog tilt filter 208 . In some embodiments,

The output of the digital tilt filter 402 denoted by is provided to the CFR module 404 as an input. In various embodiments, the CFR module 404 is an incoming signal (eg, the output of the digital tilt filter 402, i.e.

), the CFR process can be performed to reduce the PAPR of Although the present embodiments are not limited to any particular CFR technique used by CFR module 404, exemplary CFR techniques include adaptive baseband, intermediate frequency (IF) clipping and filtering, peak windowing. , or other suitable techniques. After the CFR process, the CFR module 404

An output denoted by is provided to the DPD module 406 . As shown, the output of the digital tilt filter 402 (

) is also a signal that has a time delay (eg, at block 423 ).

) is provided along the data path 421 introduced in . As an example, the output of the CFR module 404 (

) is further provided along datapath 427 , and then combiner 425 is output from CFR module 404 (

) to the time-delay signal

signal by combining with

used to cause

에 추가하는 데 사용된다. 도 4b를 참조하면, DPD 모듈(406)의 더 상세한 도면이 여기에 예시된다. 도시된 바와 같이, CFR 모듈(404)의 출력(

)은 입력으로서 DPD 모듈(406)에 제공되며, 이는 비-선형 데이터경로(405)를 포함한다. 다양한 실시예들에서, 비-선형 데이터경로(405)는, 비디오 대역폭 DPD 데이터경로(408), 베이스밴드 DPD 데이터경로(409), 제2 고조파 DPD 데이터경로(410), 및 제3 고조파 DPD 데이터경로(411)를 포함하는 복수의 상이한 병렬 데이터경로 엘리먼트들을 포함한다. 일반적으로, 비-선형 데이터경로(405)는 CATV 증폭기의 역 비-선형 거동을 모델링하여 인입 신호에 추가하는 데 사용된다. 더 구체적으로, 비-선형 데이터경로(405)의 상이한 병렬 데이터경로 엘리먼트들 각각은 CATV 증폭기의 역 비-선형 거동의 상이한 양상을 모델링하여 인입 신호(예컨대, CFR 모듈(404)의 출력(

)에 추가하는 데 사용된다. 예컨대, 비디오 대역폭 DPD 데이터경로(408)가 역 비-선형 비디오 대역폭 컴포넌트를 모델링하여 추가할 수 있고, 베이스밴드 DPD 데이터경로(409)가 역 비-선형 베이스밴드 컴포넌트를 모델링하여 추가할 수 있고, 제2 고조파 DPD 데이터경로(410)가 역의 제2 고조파 컴포넌트를 모델링하여 추가할 수 있으며, 제3 고조파 DPD 데이터경로(411)가 역의 제3 고조파 컴포넌트를 모델링하여 추가할 수 있다. 도시된 바와 같이, 비디오 대역폭 DPD 데이터경로(408), 베이스밴드 DPD 데이터경로(409), 제2 고조파 DPD 데이터경로(410), 및 제3 고조파 DPD 데이터경로(411) 각각의 출력은 이어서, CATV 증폭기의 베이스밴드, 비디오, 및 고조파 컴포넌트들을 모델링하는 복합 신호 x'(n)을 제공하기 위해 결합된다.In some embodiments, the DPD module 406 models the inverse baseband, video, and harmonic components of the CATV amplifier to model the incoming signal

used to add to Referring to FIG. 4B , a more detailed diagram of the DPD module 406 is illustrated herein. As shown, the output of the CFR module 404 (

) is provided as input to the DPD module 406 , which includes a non-linear datapath 405 . In various embodiments, non-linear datapath 405 includes video bandwidth DPD datapath 408, baseband DPD datapath 409, second harmonic DPD datapath 410, and third harmonic DPD data. It includes a plurality of different parallel datapath elements including path 411 . In general, the non-linear datapath 405 is used to model the inverse non-linear behavior of the CATV amplifier and add it to the incoming signal. More specifically, each of the different parallel datapath elements of the non-linear datapath 405 models a different aspect of the inverse non-linear behavior of the CATV amplifier to model the incoming signal (e.g., the output of the CFR module 404 (

) is used to add For example, the video bandwidth DPD datapath 408 may model and add an inverse non-linear video bandwidth component, and the baseband DPD datapath 409 may model and add an inverse non-linear baseband component; The second harmonic DPD data path 410 may be added by modeling the inverse second harmonic component, and the third harmonic DPD data path 411 may be added by modeling the inverse third harmonic component. As shown, the output of each of the video bandwidth DPD datapath 408, the baseband DPD datapath 409, the second harmonic DPD datapath 410, and the third harmonic DPD datapath 411 is then CATV combined to provide a composite signal x'(n) that models the baseband, video, and harmonic components of the amplifier.

는 결합기(429)에 의해 결합되어, 신호 x''(n)을 초래한다. 그 후, 신호 x''(n)은, 신호 x'(n)을 추가로 변조하는 데 사용될 수 있는 단일 사이드 밴드 힐버트 필터(412)에 입력으로서 제공되며, 단일 사이드 밴드 힐버트 필터(412)의 출력은 디지털 틸트 등화기(414)에 입력으로서 제공된다. 예로서, 디지털 틸트 등화기(414)는 아날로그 틸트 필터(208)(도 2)의 역을 모델링하여 인입 신호에 추가하는 데 사용될 수 있다. 따라서, 예로서, 디지털 틸트 등화기(414)의 출력은 아날로그 틸트 필터(208)의 효과에 의해 영향받지 않을 수 있다(예컨대, 또는 그 효과를 상쇄시킬 수 있음). 도 4a에 도시된 바와 같이, 일부 실시예들에서, 입력 신호 x(n)은 또한 경로(416)를 따라 송신되며, 여기서 경로(416)는 선형 데이터경로이다. 일부 예들에서, 데이터경로(416)는 (예컨대, 블록(417)에서) 단지 입력 신호 x(n)에 시간 지연을 도입할 수 있다. 게다가, 데이터경로(416)를 따라 송신된 입력 신호 x(n)은 디지털 틸트 필터(402), CFR 모듈(404), DPD 모듈(406), 단일 사이드 밴드 힐버트 필터(412) 및 디지털 틸트 등화기(414)를 우회한다. 그러므로, 데이터경로(416)를 따라 송신된 입력 신호 x(n)의 신호 변조의 품질은 DPD-CFR 시스템(304)의 다른 엘리먼트들에 의해 영향받지 않게 유지될 것이다. 부가적으로, 도 4a에 도시된 바와 같이, 디지털 틸트 등화기(414)의 출력과 시간-지연 입력 신호 x(n)(419)은 출력 신호 z(n)을 제공하도록 결합기(431)에 의해 결합된다. 도 2, 도 3, 및 도 4a를 참조하면, DPD-CFR 시스템(304)의 출력 z(n)은 RF DAC(204) 및 아날로그 틸트 필터(208)에 의해 추가로 프로세싱되어, 신호 y(n)을 초래할 수 있다. 예로서, 신호 y(n)은 다음과 같이 계산될 수 있으며:4A, the output (eg, composite signal x'(n)) and signal of non-linear datapath 405

are combined by a combiner 429, resulting in a signal x''(n). The signal x''(n) is then provided as an input to a single side band Hilbert filter 412 which may be used to further modulate the signal x''(n), the The output is provided as an input to a digital tilt equalizer 414 . As an example, digital tilt equalizer 414 can be used to model the inverse of analog tilt filter 208 (FIG. 2) and add it to the incoming signal. Thus, for example, the output of the digital tilt equalizer 414 may not be affected by the effect of the analog tilt filter 208 (eg, may cancel its effect). 4A , in some embodiments, the input signal x(n) is also transmitted along path 416 , where path 416 is a linear datapath. In some examples, datapath 416 may introduce a time delay in only input signal x(n) (eg, at block 417 ). In addition, the input signal x(n) transmitted along datapath 416 includes a digital tilt filter 402, a CFR module 404, a DPD module 406, a single side band Hilbert filter 412 and a digital tilt equalizer. Bypass (414). Therefore, the quality of the signal modulation of the input signal x(n) transmitted along the datapath 416 will remain unaffected by other elements of the DPD-CFR system 304 . Additionally, as shown in Figure 4a, the output of digital tilt equalizer 414 and time-delay input signal x(n) 419 are output by combiner 431 to provide an output signal z(n). are combined 2 , 3 , and 4A , the output z(n) of the DPD-CFR system 304 is further processed by the RF DAC 204 and the analog tilt filter 208 to generate a signal y(n) ) can lead to As an example, the signal y(n) can be calculated as:

where ATF = analog tilt filter, DTE = digital tilt equalizer, symbol '*' is used to express mathematical convolution operation, DTE*ATF = 1 (single transfer function).

Referring to FIG. 5A , an exemplary input spectrum 502 is provided. In some embodiments, the input signal x(n) ( FIG. 4A ) may include an input spectrum 502 . As noted above, the input spectrum 502 may include each of a plurality of different carriers mixed at different frequencies (eg, by the DUC 302 ), as previously described, where the plurality of Each of the different carriers is arranged side-by-side in frequency over a full-bandwidth of about 66 MHz to about 1218 MHz. Referring to FIG. 5B , an exemplary output spectrum 504 is provided. In some embodiments, the output signal z(n) ( FIG. 4A ) may include an output spectrum 504 . As shown in FIG. 5B , the output spectrum 504 includes one or more non-linear components 506 that have been added to the signal by the DPD-CFR system 304 . As a result of the processing performed by the DPD-CFR system 304, CATV amplifier efficiency and signal quality are improved, and power consumption is reduced.

Referring now to FIGS. 6A, 6B, 7A, 7B, 7C, 8A, 8B, 9A, 9B, 10A, 10B, and 11 , the advantages of various embodiments of the present disclosure A plurality of data illustrating at least some of the features and advantages are shown herein. Referring first to FIG. 6A , a plot 602 depicting the normalized magnitude of a tilt filter output (eg, such as an analog tilt filter 208 ) sampled over time is illustrated herein. Plot 602 includes a first dataset 604 for which the CFR process has not been performed. Therefore, the first dataset 604 exhibits large peaks (eg, greater than about 0.78) that can lead to more non-linearity in the CATV amplifier. Plot 602 also includes a second dataset 606 showing reduced peak sizes (eg, less than about 0.78) for which the CFR process has been performed. Thus, the reduced peaks provided by the CFR process result in increased efficiency of the CATV amplifier. Additionally, the CFR process can be performed without sacrificing modulation error ratio (MER) performance. 6B provides a plot 608 illustrating (eg, at the output of analog tilt filter 208 ) a power spectrum 610 on which the CFR process has been performed, thereby benefiting from the reduced peak sizes provided by the CFR process. to exemplify Note that the data shown in FIGS. 6A and 6B includes simulated data, where the analog tilt filter 208 is replaced with a digital model for simulation purposes.

7A, 7B, and 7C, plots 702, 708, 714 illustrating the normalized magnitude of an amplifier output (eg, such as the CATV amplifier 212) sampled over time are illustrated herein. do. In general, the data in plots 702 , 708 , 714 provides validation of the efficacy of the CFR process, and may include snapshots of feedback data (eg, feedback data 308 ). As noted above, such feedback data allows the DPD/CFR adjustment engine 312 to update models within the DPD-CFR system 304 so that the DPD-CFR system 304 can be tuned to the runtime behavior of the CATV amplifier. It may include the output signal of the CATV amplifier that can be used for In some cases, the data in plots 702 , 708 , 714 is adapted to observe and adjust the system in real time (eg, via the DPD-CFR system 304 ) to provide consistency across different CATV amplifiers. It is possible to provide snapshots of feedback data in different CATV amplifiers. Alternatively, in some examples, the data in plots 702 , 708 , 714 may provide snapshots of feedback data at a particular CATV amplifier at different time windows to observe the performance of the particular CATV amplifier over time. can Referring now to FIG. 7A , a plot 702 includes a peak 704 (eg, having a magnitude greater than about 0.78) for which the CFR process has not been performed, which would indicate more non-linearity in the CATV amplifier. and a first dataset that can be Plot 702 also includes a second dataset 706 showing reduced peak sizes (eg, less than about 0.78) for which the CFR process has been performed. Similarly, plot 708 ( FIG. 7B ) and plot 714 ( FIG. 7C ) show peaks for datasets 712 , 718 on which the CFR process was performed as well as datasets for which the CFR process was not performed. (710, 716) is illustrated. As before, the reduced peaks provided by the CFR process result in increased efficiency of the CATV amplifier.

Referring now to FIG. 8A , a single at 1122 MHz showing a first cumulative distribution function (CCDF) curve 804 without performing the CFR process and a second CCDF curve 806 resulting from performing the CFR process. A CCDF plot 802 for a carrier is illustrated here. CCDF curves are used to show how much time a signal spends above a given power level, where the power level is expressed in dB relative to the average signal power (eg, crest factor). Stated another way, CCDF curves are used to show the probability that a signal will be above a given power level. Referring to FIG. 8A , the x-axis shows the dB value above the average signal power (eg, crest factor), and the y-axis shows the percentage of time the signal spends above the power level specified by the x-axis. Compared to the first CCDF curve 804 (without CFR), the second CCDF curve 806 (with CFR) exhibits about 2 dB reduction in crest factor. As a result, CATV amplifiers are expected to provide more consistent and more efficient performance. FIG. 8B provides a plot 808 that corresponds to a second CCDF curve 806 (with CFR) and illustrates a power spectrum 810 on which the CFR process was performed, in which the crest factor was reduced by the CFR process.

9A and 9B, plots 902, 908 of a CATV amplifier transfer function showing amplitude-to-amplitude distortion (AM/AM) are illustrated here, where AM/AM distortion is the gain compression of the signal. Or used to measure expansion. In other words, the non-linearity of the AM/AM distortion will increase when the CATV amplifier gain is no longer constant with respect to the input power (eg, when the output power is no longer linearly related to the input power). In this example, plot 902 ( FIG. 9A ) provides data for which the CFR process has not been performed, and plot 908 ( FIG. 9B ) provides data for which the CFR process has been performed. Additionally, the plot 902 includes a first curve 904 on which the DPD process is not performed and a second curve 906 on which the DPD process is performed. Referring to the first curve 904, it can be seen that greater input power results in increased compression in output power (eg, increased CATV amplifier non-linearity is evident). Using the DPD process (without CFR), the second curve 906 shows that it is possible to substantially correct the CATV amplifier non-linearity and reduce signal compression. The plot 908 also includes a first curve 910 on which the DPD process is not performed and a second curve 912 on which the DPD process is performed. By performing the CFR process (for the data shown in plot 908) and reducing the PAPR, the normalized input power is limited to about 0.8. Therefore, referring to the first curve 910 (without DPD), there is relatively little signal compression, resulting in a more controlled and efficient performance of the CATV amplifier. In this example, using the DPD process (with CFR), the second curve 912 is the first curve because by limiting the input power (by the CFR process), the DPD process has less non-linearity to correct for. (910) shows a slight improvement.

10A and 10B provide exemplary DPD performance (eg, DPD output stability performance) with or without the CFR process. FIG. 10A includes a plot 1002 providing data for which the CFR process has not been performed, and FIG. 10B includes a plot 1008 providing data with the CFR process performed. Additionally, the plot 1002 (without CFR) includes a first curve 1004 representing the DPD input signal and a second curve 1006 representing the DPD output signal. In this example, the DPD output signal 1006 is not stable without the CFR process and begins to diverge beyond the DPD output signal range of about two. As discussed above, higher input power results in increased compression in the output power as the CATV amplifier has more non-linearity. To avoid operating the CATV amplifier in such high power regions, a CFR process may be performed. For example, the plot 1008 (with CFR) includes a first curve 1010 representing the DPD input signal and a second curve 1012 representing the DPD output signal. In this example, and because the CFR process is performed, the DPD output signal 1012 is stable and does not diverge. For the data in plot 1008, a 1.3 dB CFR was applied. However, in various embodiments, the amount of CFR applied may be tuned as needed for a particular CATV amplifier or for a particular installation/deployment. Additionally, while this disclosure has described both the advantages of DPD and CFR, it is understood that various embodiments may utilize one or both of the DPD process and the CFR process. However, in at least some examples, by using both the DPD process and the CFR process for a given arrangement, maximum CATV amplifier efficiency can be achieved while also avoiding DPD divergence.

Referring to FIG. 11 , a table containing MER data for a CATV amplifier is illustrated here showing the effect of applying corrections provided by the DPD-CFR system 304 to the modulation error ratio (MER) data. As an example, MER is a measure used to quantify the performance of a digital radio (or digital TV) transmitter or receiver in a communication system using digital modulation (such as QAM). For the example of FIG. 11 , the CATV amplifier module under test is operable at V=34V. Compare MER data with cable industry specifications: MER = 41dB, 4KQAM, 76.8 dbmV/75Ω. The CATV amplifier is tested using 6 carriers, wherein the first carrier is a 4K QAM signal with a carrier frequency of 204 MHz, the second carrier is a 4K QAM signal with a carrier frequency of 396 MHz, and the third carrier is 588 a 4K QAM signal with a carrier frequency of MHz, the fourth carrier is a 4K QAM signal with a carrier frequency of 786 MHz, the fifth carrier is a 4K QAM signal with a carrier frequency of 930 MHz, and the sixth carrier is a 4K QAM signal with a carrier frequency of 1122 MHz. It is a 4K QAM signal with a carrier frequency. In a first test 1102 , for a CATV amplifier operating with a bias current of 440 mA and without DPD or CFR corrections, none of the tested carriers meet the specification of MER = 41 dB. In the second test 1104, for a CATV amplifier operating with a bias current of 440 mA and with DPD correction but without CFR correction, the first carrier does not meet the specification of MER = 41 dB. Moreover, in the second test 1104 , the DPD stability is degraded, and DPD divergence occurs. In a third test 1106, for a CATV amplifier operating with a bias current of 440 mA and with both DPD or CFR corrections applied, all of the tested carriers meet the specification of MER = 41 dB, and the DPD divergence is avoided. By operating the CATV amplifier with a bias current of 440 mA (compared to some applications using a bias current of 530 mA to operate the CATV amplifier), a reduction of about 3 watts per amplifier is achieved while maintaining MER performance. Also note that it can be

(도 4a)로 표기된 신호를 포함하고, 제1 출력 신호는

(도 4a)로 표기된 신호를 포함한다. 방법(1200)은 블록(1206)으로 진행하며, 여기서 DPD-CFR 출력 신호를 생성하기 위해 제1 출력 신호에 대해 DPD 프로세스가 DPD-CFR 시스템의 DPD 모듈에서 수행된다. 일부 실시예들에서, DPD 모듈은 CFR 모듈의 출력에 커플링된 비-선형 데이터경로를 포함한다. 부가적으로, DPD 모듈의 비-선형 데이터경로는 도 4b의 비-선형 데이터경로(406)를 포함할 수 있다. 그러므로, 비-선형 데이터경로는 복수의 병렬 데이터경로 엘리먼트들을 포함할 수 있다. 일부 예들에서, 복수의 병렬 데이터경로 엘리먼트들은 비디오 대역폭 DPD 데이터경로(404), 베이스밴드 DPD 데이터경로(406), 제2 고조파 DPD 데이터경로(408), 및 제3 고조파 DPD 데이터경로(410)를 포함한다. 일부 예들에서, 상이한 병렬 데이터경로 엘리먼트들 각각은 CATV 증폭기의 역 비-선형 거동의 상이한 양상을 인입 신호에 추가하는 데 사용될 수 있다. 일부 실시예들에서, 결합기는 복합 신호 x'(n)(도 4b)을 생성하기 위해 복수의 병렬 데이터경로 엘리먼트들 각각의 출력을 결합시키며, 여기서 복합 신호 x'(n)은 CATV 증폭기의 베이스밴드, 비디오, 및 고조파 컴포넌트들을 모델링한다. 다양한 실시예들에서, 방법(1200)은 블록(1208)으로 진행하며, 여기서 DPD-CFR 출력 신호는 CATV 증폭기(예컨대 이를테면, 도 2의 CATV 증폭기들(212))에 제공된다. 본 개시내용의 실시예들에 따르면, DPD-CFR 출력 신호는 신호의 PAPR을 감소시키고 CATV 증폭기의 복수의 비-선형 컴포넌트들을 보상하도록 구성된다. 이어서, 방법(1200)은 블록(1210)으로 진행하며, 여기서 CATV 증폭기의 출력으로부터 수신된 피드백 데이터(예컨대 이를테면, 도 3의 피드백 데이터(308))는 DPD-CFR 시스템의 구성을 업데이트하는 데 사용될 수 있다. 본 개시내용의 범위를 벗어나지 않으면서, 부가적인 방법 단계들이 방법(1200) 이전에, 그 동안 그리고 그 이후 구현될 수 있으며, 위에서 설명된 일부 방법 단계들이 방법(1200)의 다양한 실시예들에 따라 대체 또는 제거될 수 있다는 것을 이해할 것이다.Referring now to FIG. 12 , illustrated herein is a method 1200 for performing a crest factor reduction process and a digital predistortion process in a DPD-CFR system, in accordance with various embodiments. Method 1200 begins at block 1202, where an input signal is received at an input of a DPD-CFR system, such as DPD-CFR system 304 of FIG. 4A. As discussed above and in some embodiments, the input signal is an input signal x(n) ( FIG. 4A ), which may further include a composite signal c(n) generated by the DUC 302 ( FIG. 3 ). may include. In some examples, the method 1200 proceeds to block 1204 , where a CFR process is performed on the input signal in a CFR module of the DPD-CFR system to generate a first output signal. For example, the CFR process may be performed by the CFR module 404 ( FIG. 4A ). In various cases, the CFR process is performed to reduce the peak-to-average power ratio (PAPR) of the input signal. In some embodiments, the input signal is

(Fig. 4a) including a signal, the first output signal is

(Fig. 4a) contains the signal. The method 1200 proceeds to block 1206 , where a DPD process is performed on the first output signal in a DPD module of the DPD-CFR system to generate a DPD-CFR output signal. In some embodiments, the DPD module includes a non-linear datapath coupled to the output of the CFR module. Additionally, the non-linear data path of the DPD module may include the non-linear data path 406 of FIG. 4B . Therefore, a non-linear datapath may include a plurality of parallel datapath elements. In some examples, the plurality of parallel datapath elements connect the video bandwidth DPD datapath 404 , the baseband DPD datapath 406 , the second harmonic DPD datapath 408 , and the third harmonic DPD datapath 410 . include In some examples, each of the different parallel datapath elements can be used to add a different aspect of the inverse non-linear behavior of the CATV amplifier to the incoming signal. In some embodiments, the combiner combines the output of each of the plurality of parallel datapath elements to produce a composite signal x'(n) (FIG. 4B), wherein the composite signal x'(n) is the base of the CATV amplifier. It models band, video, and harmonic components. In various embodiments, the method 1200 proceeds to block 1208 , where the DPD-CFR output signal is provided to a CATV amplifier (eg, such as the CATV amplifiers 212 of FIG. 2 ). According to embodiments of the present disclosure, the DPD-CFR output signal is configured to reduce the PAPR of the signal and compensate for the plurality of non-linear components of the CATV amplifier. The method 1200 then proceeds to block 1210 , where feedback data received from the output of the CATV amplifier (such as feedback data 308 in FIG. 3 ) will be used to update the configuration of the DPD-CFR system. can Without departing from the scope of the present disclosure, additional method steps may be implemented before, during, and after method 1200 , some method steps described above in accordance with various embodiments of method 1200 . It will be appreciated that they may be replaced or eliminated.

The various configurations (eg, the components of the cable network 200 , the DFE system 300 , and the DPD-CFR system 304 , the number of parallel datapath elements in FIG. 4B , as well as other features illustrated in the figures and components) are exemplary only and are not intended to be limiting beyond what is specifically recited in the following claims. It will be understood by those skilled in the art that other configurations may be used. Also, while an exemplary cable network 200 is illustrated, the DPD-CFR system disclosed herein may be used, for example, in other communication systems where other communication systems deploy amplifiers that exhibit detrimental non-linear behavior.

As discussed above, the cable industry is deploying a new high data rate and broadband remote PHY node based on the DOCSIS 3.1 standards to meet the demands for higher data rates of Internet, telephony, and video services. DOCSIS 3.1 supports 4096 (4K) quadrature amplitude modulation (QAM) and uses orthogonal frequency division multiplexing (OFDM). Therefore, the transmit signal quality requirements for DOCSIS 3.1 are much higher than for the current standard DOCSIS 3.0. Due to the more sophisticated functions associated with DOCSIS 3.1, cable television (CATV) amplifiers can operate in non-linear regions. The non-linear effects of the CATV amplifier will significantly degrade the transmit signal quality. Additionally, new components that provide the higher data rates and more sophisticated features of DOCSIS 3.1 will themselves consume power. However, since the power supply to each node (eg, each remote PHY node) is fixed, the power consumption of other components (eg, CATV amplifiers) must be reduced. Thus, while providing the advanced performance of DOCSIS 3.1 is desirable, it has been difficult to do so while providing improved transmit signal quality and reduced power consumption of other components (eg, CATV amplifiers).

In at least some existing techniques, a tilt equalizer (tilt filter) with deep attenuation of up to 22 dB over the 1.2 GHz cable spectrum to compensate for coaxial cable losses (eg, from a CATV amplifier to a cable modem) is used for analog transmission. implemented in the path. However, the DOCSIS 3.1 waveform using 4K QAM OFDM modulation shows a high peak-to-average power ratio (PAPR) compared to the current DOCSIS 3.0 standard. Therefore, for the same RMS power output of a CATV amplifier in DOCSIS 3.0, the peak of the DOCSIS 3.1 waveform will be in the non-linear region of the CATV amplifier. Accordingly, the transmission signal quality is deteriorated. Digital predistortion (DPD) can be used to improve the signal quality for a CATV amplifier, for example by allowing the CATV to operate in a higher efficiency region. DPD has been used for wireless communication technologies, where the signal bandwidth is much narrower than that used for cable communication technologies. Additionally, in wireless communications, harmonics of non-linear effects of wireless components do not fall within the signal bandwidth. Therefore, DPD for wireless communications only needs to model the projected non-linear components around the baseband frequency. However, for cable applications, harmonics of non-linear effects of the CATV amplifier signal fall into the signal bandwidth. Accordingly, DPD implementations for cable applications must model the harmonic components of non-linear effects on a CATV amplifier. Separately, a tilt equalizer with deep attenuation may not be implemented in the digital domain, and a digital tilt equalizer implementation may not be implemented in the transmit waveform quality of lower frequency carriers due to the finite digital resolution of the digital-to-analog converter (DAC). will degrade For integrated circuit (IC) solutions, DPD data paths implemented within a digital front-end (DFE) chip model harmonic components of non-linear effects on CATV amplifiers and deep attenuation across the transmit spectrum in CATV amplifiers. It has been found that it can provide a solution to Accordingly, embodiments of the present disclosure provide improved transmit signal quality and reduced power consumption of CATV amplifiers.

With the general understanding above in mind, various embodiments are generally described below for providing methods and circuits for predistortion for CATV amplifiers. Because one or more of the above-described embodiments are illustrated using a particular type of IC, a detailed description of such an IC is provided below. However, it should be understood that other types of ICs may benefit from one or more of the embodiments described herein.

“Programmable logic devices” (“PLDs”) are a well-known type of integrated circuit that can be programmed to perform specified logic functions. One type of PLD, or "FPGA" (field programmable gate array), typically includes an array of programmable tiles. These programmable tiles are, for example, input/output blocks (“IOBs”), configurable logic blocks (“CLBs”), dedicated random access memory blocks (“BRAMs”), multipliers, “DSPs”. "(digital signal processing blocks)", processors, clock managers, "DLLs" (delay lock loops), and the like. As used herein, “comprises” and “comprising” mean including without limitation.

Each programmable tile typically includes both a programmable interconnect and programmable logic. A programmable interconnect typically includes a large number of interconnect lines of various lengths interconnected by programmable interconnect points (“PIPs”). Programmable logic implements the logic of a user design using programmable elements, which may include, for example, function generators, registers, arithmetic logic, and the like.

The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data may be read from memory (eg, from an external PROM) or written to the FPGA by an external device. The aggregate states of the individual memory cells then determine the function of the FPGA.

Another type of PLD is a Complex Programmable Logic Device (CPLD). A CPLD includes two or more “functional blocks” connected together and to “I/O” (input/output) resources by an interconnecting switch matrix. Each functional block of a CPLD includes a two-level AND/OR structure similar to those used in "PLA" (Programmable Logic Array) and "PAL" (Programmable Array Logic) devices. In CPLDs, configuration data is typically stored on-chip in non-volatile memory. In some CPLDs, configuration data is stored on-chip in non-volatile memory and then downloaded to volatile memory as part of an initial configuration (programming) sequence.

Generally, in each of these programmable logic devices (PLDs), the functionality of the device is controlled by configuration data provided to the device for that purpose. The configuration data is stored in volatile memory (eg, static memory cells as is common in FPGAs and some CPLDs), non-volatile memory (eg, flash memory as in some CPLDs), or any other type of memory cell. can be

Other PLDs are programmed by applying a processing layer, such as a metal layer, that programmably interconnects the various elements on the device. These PLDs are known as mask programmable devices. PLDs may also be implemented in other manners, such as using fuse or antifuse technology. The terms “PLD” and “programmable logic device” include, but are not limited to, encompassing these exemplary devices as well as only partially programmable devices. For example, one type of PLD includes a combination of hard-coded transistor logic and a programmable switch fabric that programmably interconnects the hard-coded transistor logic.

As mentioned above, advanced FPGAs may include several different types of programmable logic blocks in an array. For example, with reference again, FIG. 1 illustrates an example FPGA architecture 100 . The FPGA architecture 100 includes multi-gigabit transceivers (“MGTs”) 101 , configurable logic blocks (“CLBs”) 102 , random access memory blocks (“BRAMs”) 103 , and “IOBs”. "(input/output blocks) 104, configuration and clocking logic ("CONFIG/CLOCKS") 105, "DSP" (digital signal processing blocks) 106, specialized input/output blocks ( “I/O”) 107 (eg, configuration ports and clock ports), and other programmable logic 108 such as digital clock managers, analog-to-digital converters, system monitoring logic, etc. It contains a number of different programmable tiles. Some FPGAs also include dedicated processor blocks (“PROCs”) 110 . In some embodiments, the FPGA architecture 100 includes RF data including multiple radio frequency analog-to-digital converters (RF-ADCs) and multiple radio frequency digital-to-analog converters (RF-DACs). Includes a converter subsystem. In various examples, RF-ADCs and RF-DACs may be configured individually for real data or configured in pairs for real and imaginary I/Q data. In at least some examples, FPGA architecture 100 may implement an RFSoC device.

In some FPGAs, each programmable tile has at least one having connections to input and output terminals 120 of a programmable logic element within the same tile, as shown by the examples included at the top of FIG. 1 . programmable interconnection elements (“INTs”) 111 . Each programmable interconnection element 111 may also include connections for interconnecting segments 122 of adjacent programmable interconnection element(s) in the same tile or in different tile(s). Each programmable interconnection element 111 may also include connections for interconnecting segments 124 of general routing resources between logic blocks (not shown). Typical routing resources are between logic blocks (not shown) containing tracks of interconnect segments (eg, interconnect segments 124 ) and switch blocks (not shown) for connecting interconnect segments. of routing channels. The interconnect segments (eg, interconnect segments 124 ) of general routing resources may span one or more logical blocks. The programmable interconnect elements 111 taken together with common routing resources implement the programmable interconnect structure (“programmable interconnect”) for the illustrated FPGA.

In an example implementation, CLB 102 may include a “configurable logic element” (CLE) 112 that can be programmed to implement user logic plus a single programmable interconnection element (“INT”) 111 . have. BRAM 103 may include a “BRAM logic element” (BRL) 113 in addition to one or more programmable interconnect elements. Typically, the number of interconnecting elements included in a tile depends on the height of the tile. In the example shown, the BRAM tile has the same height as 5 CLBs, but other numbers (eg, 4) may also be used. The DSP tile 106 may include a DSPL (“DSP logic element”) 114 in addition to an appropriate number of programmable interconnect elements. IOB 104 may include, for example, two instances of an “input/output logic element” (IOL) 115 in addition to one instance of programmable interconnection element 111 . As will be apparent to those skilled in the art, for example, the actual I/O pads connected to the I/O logic element 115 are typically not limited to the area of the input/output logic element 115 .

In the example of FIG. 1 , the region (shown horizontally) near the center of the die (eg, formed in regions 105 , 107 , and 108 shown in FIG. 1 ) is for configuration, clock, and other control logic can be used A column 109 (shown vertically) extending from this horizontal region or other columns may be used to distribute clocks and configuration signals across the width of the FPGA.

Some FPGAs using the architecture illustrated in FIG. 1 include additional logic blocks that interfere with the general thermal structure that makes up much of the FPGA. The additional logic blocks may be programmable blocks and/or dedicated logic. For example, PROC 110 spans several columns of CLBs and BRAMs. PROC 110 may include various components ranging from a single microprocessor to a complete programmable processing system, such as microprocessor(s), memory controllers, peripherals, and the like.

In one aspect, PROC 110 is implemented as dedicated circuitry fabricated as part of a die implementing programmable circuitry of an IC, such as a hard-wired processor. PROC 110 can be configured in a variety of different ways, ranging in complexity from an individual processor, eg, a single core capable of executing program code, to an entire processor system having one or more cores, modules, co-processors, interfaces, etc. may represent any of the systems and/or processor types.

In other aspects, PROC 110 is omitted from architecture 100 and may be replaced with one or more of the various other described programmable blocks. Additionally, such blocks may be used to form a “soft processor” in that various blocks of programmable circuitry may be used to form a processor capable of executing program code, such as in the case of PROC 110 . .

The phrase “programmable circuit” refers to programmable circuit elements within an IC (eg, various programmable or configurable circuit blocks or tiles described herein), as well as various circuit blocks depending on configuration data loaded into the IC. , tiles, and/or interconnect circuitry that selectively couples elements. For example, the portions shown in FIG. 1 that are external to PROC 110 , such as CLBs 102 and BRAMs 103 , may be considered programmable circuitry of the IC.

In some embodiments, the function and connection of the programmable circuit is not established until the configuration data is loaded into the IC. The set of configuration data may be used to program programmable circuitry of an IC, such as an FPGA. In some cases, the configuration data is referred to as a “configuration bitstream”. Generally, the programmable circuitry does not operate or function without first loading the configuration bitstream into the IC. The configuration bitstream effectively implements or instantiates a particular circuit design within the programmable circuit. Circuit design specifies, for example, functional aspects of the programmable circuit blocks and the physical connections between the various programmable circuit blocks.

In some embodiments, "hardwired" or "hardened", ie, non-programmable circuitry, is fabricated as part of the IC. Unlike programmable circuitry, hardwired circuitry or circuit blocks are not implemented through the loading of the configuration bitstream after fabrication of the IC. Hardwired circuitry is generally considered to have dedicated circuit blocks and interconnects that function without, for example, first loading a configuration bitstream into an IC, such as PROC 110 .

In some instances, a hardwired circuit may have one or more modes of operation that may be set or selected according to register settings or values stored in one or more memory elements within the IC. The operating modes may be set, for example, via loading the configuration bitstream into the IC. Despite this capability, hardwired circuitry is not considered programmable circuitry because, when manufactured as part of an IC, the hardwired circuitry is operable and has specific functions.

As discussed above, FIG. 1 is intended to illustrate an example architecture that may be used to implement an IC that includes programmable circuitry, such as a programmable fabric. For example, the number of logic blocks in a row, the relative width of the rows, the number and order of the rows, the types of logic blocks included in the rows, the relative sizes of the logic blocks, and the interconnect/logic implementation included at the top of FIG. 1 . These are purely exemplary. For example, in a real IC, whenever CLBs appear, more than one contiguous row of CLBs is typically included to facilitate efficient implementation of user logic, although the number of contiguous CLB rows varies with the overall size of the IC. . The FPGA of FIG. 1 also illustrates an example of a programmable IC that may utilize examples of interconnect circuits described herein. The interconnect circuits described herein may be used in other types of programmable ICs, such as CPLDs or any type of programmable IC having a programmable interconnect structure for selectively coupling logic elements.

The IC capable of implementing methods and circuits for predistortion for CATV amplifiers is not limited to the exemplary IC shown in FIG. 1 , ICs with other configurations or other types of ICs are also for CATV amplifiers. Note that it is possible to implement methods and circuits for predistortion.

Referring now to FIG. 2 , there is shown a cable network 200 showing a signal path starting from a data fiber (eg, which may include optical fiber) through a remote node to an end user location (eg, at home). is exemplified Cable network 200 may be part of a hybrid fiber-coaxial network, where data fibers run from the central headend to remote nodes and coaxial cables run from remote nodes to end users. In some examples, the remote node comprises a remote PHY node based on the DOCSIS 3.1 standards. In some embodiments, the remote PHY node may include a baseband and digital front-end (DFE) chip 202 , a digital-to-analog converter (DAC) 204 , a driver 206 (eg, an amplifier). ), an analog tilt filter 208 , a power splitter 210 , and CATV amplifiers 212 . In various examples, the baseband and DFE chip 202 may be implemented as a single chip, or as separate chips including a baseband processor chip and a separate DFE chip. In some embodiments, DAC 204 may be implemented as an RF DAC or IF DAC, for example, depending on the input to DAC 204 . Additionally, in some embodiments, baseband and DFE chip 202 and DAC 204 may be implemented in a single chip (eg, as in an RFSoC device). Furthermore, one or more components of the remote PHY node may be implemented in a programmable logic device, such as the programmable logic device of FIG. 1 . As shown in FIG. 2 , the data fiber is coupled as an input to the baseband and DFE chip 202 , and the output of the baseband and DFE chip 202 is coupled as an input to the DAC 204 . Power spectrum 214 (no slope) provides an example of the shape of the signal at the output of baseband and DFE chip 202 . The output of the DAC 204 is coupled as an input to a driver 206 , and the output of the driver 206 is coupled as an input to an analog tilt filter 208 . For cable applications, the analog tilt filter 208 may be used to vary the gain across the power spectrum of the signal. Stated another way, the analog tilt filter 208 is used to add a slope to the power levels of the signal across the power spectrum. Power spectrum 216 illustrates the slope (eg, positive slope in this example) of the signal compared to power spectrum 214 at the output of analog tilt filter 208 .

In some embodiments, the output of the analog tilt filter 208 is coupled to the power divider 210 as an input. In the example of FIG. 2 , power divider 210 includes a 1×4 power divider with a single input and four outputs. However, in some embodiments, the power divider 210 is a 1x2 power divider with a single input and two outputs, a cascade of 1x2 power dividers (eg, to generate 4 outputs), or other type may include a power divider of In this example, each of the four outputs of the power divider 210 is connected to a CATV amplifier 212 as an input. The output of each of the CATV amplifiers 212 is then coupled to a coaxial cable, which is further coupled to a cable modem at an end user location (eg, at home). In at least some embodiments, cable network 200 implements a Node+0 architecture, which follows a coaxial cable path between a remote PHY node and an end user location (beyond CATV amplifiers 212 at the remote PHY node). ) means that there are no additional CATV amplifiers. 2 shows a power spectrum 218 showing the coaxial cable loss spectrum (eg, having a negative slope), a power spectrum 219 showing the output signal of the CATV amplifiers 212 , and the signal arriving at the end user location. Further illustrated is a power spectrum 220 showing the (without slope) power spectrum of As previously discussed, the analog tilt filter 208 is used to compensate for coaxial cable losses (eg, from the CATV amplifiers 212 to the cable modem at the end user location).

In at least some existing cable networks, CATV amplifiers operate in the linear region. This means that the amount of non-linearity at the output of the CATV amplifier is low enough that no additional signal processing is required, and the signal at the output of the CATV amplifier is transmitted directly over the coaxial cable to the end user for demodulation and information transfer. The location can be transmitted to the cable modem. However, with the transition to more sophisticated functions and additional power-consuming components associated with DOCSIS 3.1 and because the power supply to each node (eg, each remote PHY node) is fixed, CATV amplifiers and It would be desirable to reduce the power consumption of the same other components. Currently, the efficiency of CATV amplifiers is approximately 2-3%, so for example a single CATV amplifier with an input power of 20 watts will output approximately 1/2 watt of output power. For 4 CATV amplifiers (eg, as shown in FIG. 2 ), an input power of 100 watts will output approximately 2 watts of output power. Therefore, it is highly desirable to make CATV amplifiers more efficient.

At least one option being explored to make CATV amplifiers more efficient is to make them operate in a more non-linear region. However, doing this means that the signal at the output of the CATV amplifier may not be transmitted to the end user location directly over the coaxial cable without some kind of additional digital signal processing, as provided in accordance with embodiments of the present disclosure means that For example, as discussed in more detail below, embodiments disclosed herein add functionality within the baseband and DFE chip 202, so that even though CATV amplifiers operate in a non-linear region, the baseband and DFE chip 202 ) will invert or change the signal, so the signal at the output of the CATV amplifier will still be linear and can be easily demodulated by the cable modem at the end user location. Stated another way, if the CATV amplifier has a non-linearity 'x', then the functions in the baseband and DFE chip 202 will have an inverse non-linearity '1/' which will be canceled by the non-linearity 'x' of the CATV amplifier. x' is configured. Therefore, the signal at the output of the CATV amplifier is clean and linear. In general, the process of adding non-linearity beforehand (eg, adding inverse non-linearity in the baseband and DFE chip 202 ) is referred to as predistorting or predistorting. In the context of the baseband and DFE chip 202, and since distortion is added digitally, predistortion may be referred to as digital predistortion (DPD). According to various embodiments, the DPD process is performed using knowledge of the type of non-linearity 'x' that the CATV amplifier (eg, CATV amplifier 212 ) has, so that the DPD process has an appropriate inverse non-linearity ' 1/x' can be added. In addition, the DPD process includes the baseband and DFE chip 202 and CATV amplifier, including any effects and/or distortions introduced by the DAC 204, driver 206, and analog tilt filter 208, respectively. This is done using knowledge of the signal chain between them 212 . In various embodiments, CATV amplifier efficiency is improved and power consumption is reduced by the DPD process disclosed herein.

In some embodiments, the function within the baseband and DFE chip 202 (configured to add inverse non-linearity) may be implemented primarily as a DFE function, where the baseband output signal is provided to the DFE chip as an input. Therefore, with reference now to FIG. 3 , illustrated herein is a DFE system 300 that provides a DFE design configured to perform one or more aspects of the present disclosure. In some embodiments, the DFE system 300 includes a digital upconverter (DUC) 302 . In various examples, DUC 302 is used to convert one or more channels of data from baseband to a passband signal comprising carriers modulated at one or more specified radio or set of intermediate frequencies (RF or IF). do. As an example, the DUC 302 interpolates (eg, to increase the sample rate), filters (eg, to provide rejection and spectral shaping of interpolated images), and shifts the signal spectrum (eg, to the desired carrier frequencies). to achieve this) by performing mixing. In general, the sample rate at the input to DUC 302 is relatively low: for example, the symbol rate of a digital communication system (however, the output is a much higher rate), for example converting digital samples to analog for further analog processing and frequency conversion. The input sample rate to the DAC converting it to a waveform.

As shown in the example of FIG. 3 , a baseband data input is provided to the DUC 302 . The baseband data input includes a plurality of different carriers represented by _{s 1} (n), s ₂ (n), s ₃ (n), s ₄ (n), s ₅ (n), and s _{6 (n).} do. In some embodiments, the sampling rate of the baseband data input is approximately 204.8 MHz corresponding to the OFDM symbol clock. As an example, the DUC 302 generates a plurality of different carriers (eg, from the baseband data input) by initially performing interpolation of the baseband data input, which in this example increases the sampling rate by a factor of 8; Thereby, it is used to switch from a first clock domain (eg, 204.8 MHz clock domain) to a second clock domain (eg, 1638.4 MHz clock domain). After the interpolation process, each of a plurality of different carriers is mixed with a signal from a numerically controlled oscillator (NCO) to shift the frequency of each of the plurality of different carriers to a desired carrier frequency, each NCO having a different frequency. For example, carrier s ₁ (n) is mixed with a first NCO(NCO1) having a first frequency, carrier s ₂ (n) is mixed with a second NCO(NCO2) having a second frequency, and carrier s ₃ ( n) is mixed with a third NCO (NCO3) having a third frequency, carrier s ₄ (n) is mixed with a fourth NCO (NCO4) having a fourth frequency, carrier s ₅ (n) is mixed with a fifth frequency is mixed with a fifth NCO (NCO5) having , and the carrier s ₆ (n) is mixed with a sixth NCO (NCO6) having a sixth frequency. After the mixing process, each of a plurality of different carriers is combined to form a composite signal c(n). Thus, the composite signal c(n) comprises each of a plurality of different carriers being mixed at different frequencies. In some embodiments, and as a result of the mixing process, the composite signal c(n) may appear substantially identical to the signal shown in FIG. 5A , wherein each of a plurality of different carriers are arranged side-by-side in frequency. In some cases, after generation of the composite signal c(n), another interpolation process may optionally be performed, which, in the example of FIG. 3 , increases the sampling rate of the composite signal c(n) by a factor of two, thereby is used to switch from the second clock domain (eg, the 1638.4 MHz clock domain) to the third clock domain (eg, the 3276.8 MHz clock domain). After signal processing by the DUC 302, the composite signal c(n) is provided as an input to the DPD system 304, which is described in more detail below. In some embodiments, the output of the DPD system 304 may undergo a complex-to-real signal transformation 306, and the output of the complex-to-real signal transformation 306 may be input to a DAC (e.g., it is 204)). Additionally, one or more components of DFE system 300 may be implemented in a programmable logic device, such as the programmable logic device of FIG. 1 .

As previously discussed, the DPD process, and thus the DPD system 304, utilizes knowledge of the type of non-linearity 'x' the CATV amplifier has and uses the baseband and DFE chip 202 and CATV amplifiers. Functioning using knowledge of the signal chain between 212, DPD system 304 can effectively implement appropriate DPD processes (eg, including adding appropriate inverse non-linearity '1/x'). have. For example, the DPD system 304 may be used to model a CATV amplifier (eg, including non-linear effects and signal chains). Thus, the models provided by the DPD system 304 may be generated and/or updated based on the feedback data 308 , where the feedback data 308 is the output of a CATV amplifier (eg, CATV amplifier 212 ). It may contain signals. In some embodiments, feedback data 308 is processed via analog-to-digital converter (ADC) 310 and provided to DPD adjustment engine 312 as digital feedback data 311 . In various examples, and based on the digital feedback data 311 , the DPD adjustment engine 312 updates the DPD system 304 so that the DPD system 304 can be tuned to the runtime behavior of the CATV amplifier. More specifically, in some embodiments, the DPD adjustment engine 312 may determine the configuration of coefficients or other elements of filters within the DPD system 304 , generally within the DPD system 304 , below You can configure the DPD modules discussed in . Thus, by continuously monitoring and updating the models provided by the DPD system 304 (eg, via the feedback data 308 and the DPD adjustment engine 312 ), optimal DPD processes may be implemented. As an example, aspects of monitoring and updating models (eg, as a function of the DPD coordination engine 312 ) are stored in memory (eg, in the BRAMs 103 , or in another on-chip memory location) and one It may be implemented as software executed by the above on-chip processors (eg, PROC 110 ). Note that in some embodiments, the baseband and DFE chip 202 , DAC 204 , and ADC 310 may be implemented in a single chip (eg, as in an RFSoC device). The example of monitoring and updating the models provided above is not intended to be limiting in any way, and while other methods are possible, it will be understood that embodiments of the present disclosure are not limited by any of the examples provided.

Referring now to FIG. 4A , illustrated herein is a more detailed diagram of the DPD system 304 described above, used to implement various aspects of the present disclosure. As mentioned above, the DPD system 304 can be used to model the non-linear effects of a CATV amplifier. Thus, the models provided by the DPD system 304 may be generated and/or updated based on feedback data (eg, such as feedback data 308 ), where the feedback data is an ADC (eg, such as ADC 310 ). ) and provided to the DPD adjustment engine 312 , so that the DPD system 304 can be tuned to the non-linear behavior of the CATV amplifier. Thus, the DPD system 304 models of non-linear effects of a CATV amplifier are based on various features of the DPD system 304, such as a digital tilt filter 402, a non-linear datapath 405, a single side band Hilbert filter ( 412 ), and a digital tilt equalizer 414 . Note that one or more components of DPD system 304 may be implemented in a programmable logic device, such as the programmable logic device of FIG. 1 .

With continued reference to FIG. 4A , the functionality of the DPD system 304 is described in greater detail. For example, in some embodiments, a DPD input signal x(n), which may include the composite signal c(n) discussed above, is provided to the digital tilt filter 402 . In various cases, the digital tilt filter 402 may be used to model the analog tilt filter 208 ( FIG. 2 ). Thus, as an example, the output of the digital tilt filter 402 may be similar to the output of the analog tilt filter 208 . In some embodiments, the output of the digital tilt filter 402 is provided as an input to a non-linear datapath 405, which includes a video bandwidth DPD datapath 404, baseband a plurality of different parallel datapath elements including a DPD datapath 406 , a second harmonic DPD datapath 408 , and a third harmonic DPD datapath 410 . In general, the non-linear datapath 405 is used to model the inverse non-linear behavior of the CATV amplifier and add it to the incoming signal. More specifically, each of the different parallel datapath elements of the non-linear datapath 405 models a different aspect of the inverse non-linear behavior of the CATV amplifier to the incoming signal (e.g., the output of the digital tilt filter 402). used to add For example, the video bandwidth DPD datapath 404 may model and add an inverse non-linear video bandwidth component, and the baseband DPD datapath 406 may model and add an inverse non-linear baseband component; The second harmonic DPD datapath 408 may model the inverse second harmonic component and add it, and the third harmonic DPD datapath 410 may model the inverse third harmonic component and add it. As shown, the output of each of the video bandwidth DPD datapath 404, the baseband DPD datapath 406, the second harmonic DPD datapath, and the third harmonic DPD datapath 410 is then connected to the base of the CATV amplifier. combined to provide a composite signal x'(n) that models the band, video, and harmonic components.

In some embodiments, the output of non-linear datapath 405 (e.g., composite signal x'(n)) is provided with a single side band Hilbert filter that may be used to further modulate composite signal x'(n) 412 , and the output of a single side band Hilbert filter 412 is provided as an input to a digital tilt equalizer 414 . As an example, digital tilt equalizer 414 can be used to model the inverse of analog tilt filter 208 (FIG. 2) and add it to the incoming signal. Thus, for example, the output of the digital tilt equalizer 414 may not be affected by the effect of the analog tilt filter 208 (eg, may cancel its effect). 4 , in some embodiments, the DPD input signal x(n) is also transmitted along path 416 , where path 416 is a linear datapath. In some examples, datapath 416 may introduce a time delay in only DPD input signal x(n) (eg, at block 417 ). In addition, the DPD input signal x(n) transmitted along datapath 416 includes a digital tilt filter 402 , a non-linear datapath 405 , a single side band Hilbert filter 412 and a digital tilt equalizer 414 . ) is bypassed. Therefore, the quality of the signal modulation of the DPD input signal x(n) transmitted along the datapath 416 will remain unaffected by other elements of the DPD system 304. Additionally, as shown in As shown, the output of digital tilt equalizer 414 and time-delay DPD input signal x(n) 419 are combined to provide a DPD output signal y(n).

Referring to FIG. 5A , an exemplary DPD input spectrum 502 is provided. In some embodiments, the DPD input signal x(n) ( FIG. 4 ) may include the DPD input spectrum 502 . As noted above, the DPD input spectrum 502 may include each of a plurality of different carriers mixed at different frequencies (eg, by the DUC 302 ), as previously described, where the plurality of Each of the different carriers of ? are arranged side-by-side in frequency over a full-bandwidth of about 66 MHz to about 1218 MHz. Referring to FIG. 5B , an exemplary DPD output spectrum 504 is provided. In some embodiments, the DPD output signal y(n) ( FIG. 4A ) may include the DPD output spectrum 504 . 5B , the DPD output spectrum 504 includes one or more non-linear components 506 that have been added to the signal by the DPD system 304 . As described in more detail below, and as a result of the processing performed by the DPD system 304 , CATV amplifier efficiency and signal quality are improved, and power consumption is reduced.

Referring now to FIGS. 13-16 , how each of the different parallel datapath elements of the non-linear datapath 405 ( FIG. 4A ) is derived, eg, a function of the DPD input signal x(n) ( FIG. 4A ). Equations (including schematic representations) shown as , are exemplified herein. For example, FIG. 13 provides an equation for deriving an inverse non-linear baseband component, corresponding to the baseband DPD datapath 406 , where the equation is expressed as:

14 provides an equation for deriving an inverse non-linear video bandwidth component, corresponding to the video bandwidth DPD datapath 404 , where the equation is expressed as:

15 provides an equation for deriving the inverse second harmonic component, corresponding to the second harmonic DPD datapath 408 , wherein the equation is expressed as:

16 provides an equation for deriving the inverse third harmonic component, corresponding to the third harmonic DPD datapath 410 , wherein the equation is expressed as:

Referring now to FIGS. 17-23 , a plurality of data is shown herein illustrating at least some of the advantages and advantages of various embodiments of the present disclosure. Referring first to FIG. 17 , a power spectrum 1700 for a single carrier showing non-linear effects of a CATV amplifier is illustrated here. The power spectrum 1700 and the power spectra of FIGS. 18-22 are generated using a spectrum analyzer using a resolution bandwidth of 100 kHz and a video bandwidth of 1 MHz. In this example, the carrier frequency for a single carrier is equal to 254 MHz, and the CATV amplifier operates at V = 34V with bias current = 320 mA and CATV amplifier output = 76 dbmV. In some embodiments, the waveform illustrated for power spectrum 1700 is a 4K QAM DOCSIS 3.1 waveform. As shown in FIG. 17 , power spectrum 1700 includes non-linear baseband components 1704 , non-linear video bandwidth component 1706 , second harmonic component 1708 , and third harmonic component 1710 . ) is further included. As noted above, the power spectrum 1700 is for a single carrier. However, as previously discussed, it is contemplated having a plurality of different carriers arranged side-by-side in frequency. In such a case, non-linear components of power spectrum 1700 (eg, non-linear baseband components 1704 , non-linear video bandwidth component 1706 , second harmonic component 1708 , and third harmonic) component 1710) will clearly affect and degrade the power spectrum of neighboring carriers.

Referring now to FIG. 18 , a power spectrum 1700 (including the non-linear effects of the CATV amplifier) and a power spectrum 1800 superimposed on the power spectrum 1700, showing the result of applying baseband DPD correction, are excitation is exemplified in Stated another way, power spectrum 1800 illustrates the beneficial effect (eg, at the output of a CATV amplifier) of adding an inverse non-linear baseband component by baseband DPD datapath 406 . In particular, as shown in FIG. 18 and as a result of applying baseband DPD correction, non-linear baseband components 1704 of power spectrum 1700 are represented by components 1802 of power spectrum 1800 . was corrected (removed) as In the example of FIG. 18 , the baseband DPD correction results in an improvement of about 10 dB in the power spectrum 1800 , as indicated by arrow 1804 .

19 illustrates a power spectrum 1700 (including non-linear effects of a CATV amplifier) and a power spectrum 1900 superimposed over the power spectrum 1700 , showing the result of applying a second harmonic DPD correction. Stated another way, the power spectrum 1900 illustrates the beneficial effect (eg, on the output of the CATV amplifier) of adding a second harmonic component inverse by the second harmonic DPD datapath 408 . In particular, as shown in FIG. 19 and as a result of applying the second harmonic correction, the second harmonic component 1708 of the power spectrum 1700 is corrected as represented by the component 1902 of the power spectrum 1900 ( removed). As shown in the example of FIG. 19 , the second harmonic DPD correction results in an improvement of about 5 dB in the power spectrum 1900 .

Referring to FIG. 20 , a power spectrum 1700 (including the non-linear effects of the CATV amplifier) and a power spectrum 2000 superimposed on the power spectrum 1700, showing the result of applying the third harmonic DPD correction, are excitation is exemplified in Stated another way, the power spectrum 2000 illustrates the beneficial effect (eg, on the output of the CATV amplifier) of adding a third harmonic component inverse by the third harmonic DPD datapath 410 . In particular, as shown in FIG. 20 and as a result of applying the third harmonic correction, the third harmonic component 1710 of the power spectrum 1700 is corrected as represented by the component 2002 of the power spectrum 2000 ( removed). As shown in the example of FIG. 20 , the third harmonic DPD correction results in an improvement of about 5 dB in the power spectrum 2000 .

Referring to FIG. 21 , a power spectrum 2100 for two carriers 2103 , 2105 showing the non-linear effects of a CATV amplifier is illustrated here. Figure 21 also shows the power spectrum 2102 superimposed on the power spectrum 2100, showing the result of applying the baseband DPD correction, and the power spectra showing the result of applying both the baseband DPD correction and the video bandwidth DPD correction ( power spectrum 2104 superimposed over 2100 and 2102 . Stated another way, the power spectrum 2102 illustrates the beneficial effect (eg, at the output of the CATV amplifier) of adding an inverse non-linear baseband component by the baseband DPD datapath 406 . Similarly, the power spectrum 2104 is that of both an inverse non-linear baseband component by the baseband DPD datapath 406 and an inverse non-linear video bandwidth component by the video bandwidth DPD datapath 404 added. It illustrates the beneficial effect (eg, on the output of the CATV amplifier). As a result of applying only the baseband DPD correction (power spectrum 2102 ), power spectrum 2102 illustrates corrections (eg, as indicated by arrow 2112 ) compared to power spectrum 2100 . Also, as a result of applying baseband DPD correction and video bandwidth DPD correction (power spectrum 2104 ), power spectrum 2104 is compared to power spectrum 2100 (eg, indicated by arrows 2106 and 2110 ). as) exemplify corrections. In particular, the improvement shown in power spectrum 2104 within the region indicated by arrow 2110 compared to, eg, the regions indicated by arrow 2108 (eg, prior to applying baseband DPD correction and video bandwidth DPD correction). This is particularly noticeable. This is because the carrier 2105 has a higher power, resulting in a higher level of non-linearity. Therefore, the carrier 2105 will benefit much more from the corrections provided by the DPD system 304 .

22 illustrates a power spectrum 2200 comprising six different carriers arranged side-by-side in frequency over a full-bandwidth of about 66 MHz to about 1218 MHz. In some embodiments, the waveform illustrated for power spectrum 2200 is a 4K QAM DOCSIS 3.1 waveform. In some examples, power spectrum 2200 may be present at the output of analog tilt filter 208 ( FIG. 2 ). 22 also illustrates an adjacent channel power ratio (ACPR) correction 2202 that results from application of corrections provided by the DPD system 304 , as discussed above. For the purposes of this disclosure, ACPR can be described as the ratio of the power of an adjacent channel to the main channel power, and it is desirable that ACPR values are as low as possible. Accordingly, the ACPR correction 2202 shown in FIG. 22 is advantageous.

Referring to FIG. 23 , a table containing MER data for a CATV amplifier is illustrated here showing the effect of applying corrections provided by the DPD system 304 to the modulation error ratio (MER) data. As an example, MER is a measure used to quantify the performance of a digital radio (or digital TV) transmitter or receiver in a communication system using digital modulation (such as QAM). For the example of FIG. 23, the CATV amplifier module under test is operable at V=34V. Compare MER data with cable industry specifications: MER = 41dB, 4KQAM, 76.8 dbmV/75Ω. The CATV amplifier is tested using 6 carriers, wherein the first carrier is a 4K QAM signal with a carrier frequency of 204 MHz, the second carrier is a 4K QAM signal with a carrier frequency of 396 MHz, and the third carrier is 588 a 4K QAM signal with a carrier frequency of MHz, the fourth carrier is a 4K QAM signal with a carrier frequency of 786 MHz, the fifth carrier is a 4K QAM signal with a carrier frequency of 930 MHz, and the sixth carrier is a 4K QAM signal with a carrier frequency of 1122 MHz. It is a 4K QAM signal with a carrier frequency. In the first test 2302, for a CATV amplifier operating with a bias current of 530 mA and without DPD corrections, the sixth carrier does not meet the specification of MER = 41 dB. However, if DPD corrections are applied (eg, by the DPD system 304 ), all of the carriers meet the MER specification. In a second test 2304, for a CATV amplifier operating with a bias current of 440 mA (a reduction of about 3 watts per amplifier compared to operating with a bias current of 530 mA) and without DPD corrections, All tested carriers do not meet the specification of MER = 41 dB. However, if DPD corrections are applied (eg, by the DPD system 304 ), all of the carriers meet the MER specification.

Referring now to FIG. 24 , illustrated herein is a method 2400 for performing a digital predistortion process in a DPD system, in accordance with various embodiments. Method 2400 begins at block 2402 , where a DPD input signal is received at an input of a DPD system, such as DPD system 304 of FIG. 4 . As discussed above and in some embodiments, the DPD input signal is a DPD input signal x(n) ( FIG. 3 ), which may further include a composite signal c(n) generated by the DUC 302 ( FIG. 3 ). 4) may be included. In some examples, the method 2400 proceeds to block 2404 , where a non-linear datapath coupled to an input of the DPD system is provided. For example, the non-linear data path may include the non-linear data path 405 of FIG. 4A . Therefore, a non-linear datapath may include a plurality of parallel datapath elements. In some examples, the plurality of parallel datapath elements connect the video bandwidth DPD datapath 404 , the baseband DPD datapath 406 , the second harmonic DPD datapath 408 , and the third harmonic DPD datapath 410 . include In some embodiments, the method 2400 proceeds to block 2406 , where each of the different parallel datapath elements may be used to add a different aspect of the inverse non-linear behavior of the CATV amplifier to the incoming signal. In some examples, the method 2400 then proceeds to block 2408 , where the first combiner combines the output of each of the plurality of parallel datapath elements to generate a first predistortion signal. In some cases, the first predistortion signal can include a composite signal x′(n) ( FIG. 4A ) that models the baseband, video, and harmonic components of a CATV amplifier. In some embodiments, the method 2400 proceeds to block 2410, where a linear data path coupled to the input in parallel with the non-linear data path is provided, the linear data path to receive the second predistortion signal. create In some embodiments, the second predistortion signal may include a time-delayed DPD input signal x(n) 419 ( FIG. 4A ). The method then proceeds to block 2412, where the second combiner combines the first predistortion signal and the second predistortion signal to generate a DPD output signal. In some embodiments, the DPD output signal may include the DPD output signal y(n) ( FIG. 4A ). In various embodiments, the method proceeds to block 2414 , where the DPD output signal is provided to a CATV amplifier (eg, such as the CATV amplifiers 212 of FIG. 2 ). According to embodiments of the present disclosure, the DPD output signal is configured to compensate for a plurality of non-linear components of the CATV amplifier. Without departing from the scope of the present disclosure, additional method steps may be implemented before, during, and after method 2400 , some method steps described above in accordance with various embodiments of method 2400 . It will be appreciated that they may be replaced or eliminated.

The various configurations (eg, the components of the cable network 200 , the DFE system 300 , and the DPD system 304 , the number of parallel datapath elements in FIG. 4A , as well as other features and components illustrated in the figures. ) is illustrative only and is not intended to be limiting beyond what is specifically recited in the claims that follow. It will be understood by those skilled in the art that other configurations may be used. Also, while an exemplary cable network 200 is illustrated, the DPD system disclosed herein may be used, for example, in other communication systems where other communication systems deploy amplifiers exhibiting detrimental non-linear behavior.

The present invention may be represented by, but not limited to, one or more of the following examples.

Embodiment 1: A crest factor reduction (CFR) system, a digital tilt filter coupled to an input of the CFR system, the digital tilt filter configured to receive a system input signal and to generate a digital tilt filter output signal at the digital tilt filter output -; a CFR module coupled to the digital tilt filter output, the CFR module configured to receive the digital tilt filter output signal and perform a CFR process on the digital tilt filter output signal to generate a CFR module output signal at the CFR module output; and a digital tilt equalizer coupled to the CFR module output, wherein the digital tilt equalizer is configured to receive the CFR module output signal and generate a system output signal.

Embodiment 2: The CFR system of embodiment 1, further comprising a digital predistortion (DPD) module coupled to the CFR module output, wherein the DPD module receives the CFR module output signal, the DPD module output signal at the DPD module output and perform a DPD process on the CFR module output signal to generate The digital tilt equalizer is coupled to the DPD module output, and the digital tilt equalizer is configured to receive the DPD module output signal and generate a system output signal.

Embodiment 3: The CFR system of embodiment 1, wherein the system input signal has a first peak-to-average power ratio (PAPR), and the CFR module output signal has a second PAPR less than the first PAPR.

Embodiment 4: The CFR system of embodiment 2, further comprising: a first linear datapath coupled to the input of the CFR system and in parallel with the CFR module and the DPD module to generate a first time-delay signal; and a first combiner configured to combine the digital tilt equalizer output signal and the first time-delay signal to generate a system output signal.

Embodiment 5: The CFR system of embodiment 4, further comprising: a second linear datapath coupled in parallel with the CFR module and to the input of the CFR system to generate a second time-delay signal; a second combiner configured to combine the CFR module output signal and the second time-delay signal to generate a first output signal; and a third combiner configured to combine the first output signal and the DPD module output signal to generate a system output signal.

Embodiment 6: The CFR system of embodiment 2, wherein the DPD module further comprises a non-linear datapath coupled to the CFR module output, the non-linear datapath comprising a plurality of non-linear datapaths each coupled to the CFR module output parallel datapath elements, each of the plurality of parallel datapath elements configured to add a different inverse non-linear component corresponding to the non-linear component of the amplifier to the CFR module output signal, and the combiner is configured to add the DPD module output signal and combine the output of each of the plurality of parallel datapath elements to produce

Embodiment 7: The CFR system of embodiment 1, wherein a digital-to-analog converter (DAC) receives the system output signal and is configured to generate a DAC output signal, wherein the analog tilt filter receives the DAC output signal; The analog tilt filter is configured to generate an output signal, and the digital tilt filter is configured to model the analog tilt filter.

Embodiment 8 The CFR system of embodiment 7, wherein the digital tilt equalizer is configured to model the inverse of the analog tilt filter.

Embodiment 9: The CFR system of embodiment 2, further comprising a single side band Hilbert filter, wherein the single side band Hilbert filter input is configured to receive the DPD module output signal, and the single side band Hilbert filter output is digital tilt equalization. coupled to the input.

Embodiment 10 The CFR system of embodiment 1, further comprising a steering engine configured to receive feedback data from the amplifier output, based on the feedback data, the adjustment engine is configured to update a configuration of the CFR module.

Embodiment 11: A digital front-end (DFE) system configured to perform a crest factor reduction (CFR) process, the DFE system comprising: a digital upconverter (DUC) configured to receive and convert a baseband data input signal to generate a composite signal ); CFR system comprising a digital tilt filter, a CFR module, and a digital tilt equalizer, wherein the digital tilt filter is configured to receive the composite signal and generate a digital tilt filter output signal, the CFR module receives the digital tilt filter output signal, and perform a CFR process on the digital tilt filter output signal to generate a CFR module output signal, wherein the digital tilt equalizer receives the CFR module output signal, and is configured to generate a CFR system output signal, wherein the CFR system output signal is configured to: coupled to the amplifier -; and an adjustment engine configured to receive feedback data from an output of the amplifier, wherein based on the feedback data, the adjustment engine is configured to update a configuration of the CFR system.

Embodiment 12 The DFE system of embodiment 11, wherein the CFR process is configured to reduce a peak-to-average power ratio (PAPR) of the digital tilt filter output signal.

Embodiment 13 The DFE system of embodiment 11, wherein the CFR system further comprises a digital predistortion (DPD) module comprising a non-linear datapath coupled to the CFR module output, wherein the non-linear datapath is CFR a plurality of parallel datapath elements each coupled to the module output, wherein each of the plurality of parallel datapath elements is configured to model a different inverse non-linear component corresponding to a non-linear component of the amplifier, wherein the combiner is a DPD and combine the output of each of the plurality of parallel datapath elements to produce a module output signal, and the digital tilt equalizer is configured to receive the DPD module output signal and generate a CFR system output signal.

Embodiment 14: The DFE system of embodiment 11, wherein a digital-to-analog converter (DAC) receives the CFR system output signal, and is configured to generate a DAC output signal, wherein the analog tilt filter receives the DAC output signal; , the analog tilt filter is configured to generate an output signal, and the digital tilt filter is configured to model the analog tilt filter.

Embodiment 15 The DFE system of embodiment 14, wherein the digital tilt equalizer is configured to model the inverse of the analog tilt filter.

Embodiment 16: A method, comprising: receiving an input signal at a digital tilt filter of a crest factor reduction (CFR) system, and generating a digital tilt filter output signal at a digital tilt filter output; In the CFR module of the CFR system, performing a CFR process on the digital tilt filter output signal to generate a CFR module output signal - The CFR process reduces the peak-to-average power ratio (PAPR) of the digital tilt filter output signal Constructed to do -; receiving a CFR module output signal from a digital tilt equalizer of the CFR system, and generating a system output signal; and providing the system output signal to the amplifier.

Embodiment 17 The method of embodiment 16, further comprising, in response to feedback data received from an output of the amplifier, updating a configuration of the CFR system.

Embodiment 18: The method of embodiment 16, further comprising: in a digital predistortion (DPD) module of the CFR system, performing a DPD process on the CFR module output signal to generate a DPD module output signal; and receiving the DPD module output signal from the digital tilt equalizer of the CFR system, and generating a system output signal.

Embodiment 19 The method of embodiment 18, wherein the DPD module further comprises a non-linear datapath coupled to an output of the CFR module, the non-linear datapath comprising a plurality of parallel datapaths each coupled to the CFR module output datapath elements, wherein each of the plurality of parallel datapath elements is configured to model a different inverse non-linear component corresponding to a non-linear component of the amplifier, and wherein the combiner is configured to generate a DPD module output signal. configured to couple the output of each of the parallel datapath elements.

Embodiment 20 The method of embodiment 16, further comprising reducing power consumption of the amplifier in response to providing a system output signal to the amplifier and while operating the amplifier in a non-linear region.

Embodiment 21 A digital predistortion (DPD) system, comprising: an input configured to receive a DPD input signal; non-linear datapath coupled to input—the non-linear datapath includes a plurality of parallel datapath elements each coupled to the input, each of the plurality of parallel datapath elements being coupled to a non-linear component of the amplifier configured to add a corresponding different inverse non-linear component to the DPD input signal, wherein the first combiner is configured to combine the output of each of the plurality of parallel datapath elements to generate a first predistortion signal; a linear data path coupled to the input in parallel with the non-linear data path to generate a second predistortion signal; and a second combiner configured to combine the first predistortion signal and the second predistortion signal to generate a DPD output signal.

Embodiment 22 The DPD system of embodiment 21, wherein the plurality of parallel datapath elements comprises a baseband DPD datapath, a video bandwidth DPD datapath, a second harmonic DPD datapath, and a third harmonic DPD datapath.

Embodiment 23 The DPD system of embodiment 22, wherein the baseband DPD datapath is configured to add an inverse non-linear baseband component to the DPD input signal.

Embodiment 24 The DPD system of embodiment 22, wherein the video bandwidth DPD datapath is configured to add an inverse non-linear video bandwidth component to the DPD input signal.

Embodiment 25 The DPD system of embodiment 22, wherein the second harmonic DPD datapath is configured to add an inverse second harmonic component to the DPD input signal.

Embodiment 26 The DPD system of embodiment 22, wherein the third harmonic DPD datapath is configured to add an inverse third harmonic component to the DPD input signal.

Embodiment 27 The DPD system of embodiment 21, further comprising a digital tilt filter configured to model an analog tilt filter, wherein the digital tilt filter input is coupled to the input, and the digital tilt filter output is in a non-linear datapath. coupled

Embodiment 28: The DPD system of embodiment 21, further comprising a digital tilt equalizer configured to model the inverse of the analog tilt filter, wherein the digital tilt equalizer input is configured to receive the first predistortion signal, the second combiner is configured to couple the digital tilt equalizer output to the second predistortion signal to generate a DPD output signal.

Embodiment 29 The DPD system of embodiment 28, further comprising a single side band Hilbert filter, wherein the single side band Hilbert filter input is configured to receive the first predistortion signal, and the single side band Hilbert filter output is a digital tilt coupled to the equalizer input.

Embodiment 30 The DPD system of embodiment 21, wherein the DPD output signal is coupled to an amplifier input to generate an amplified output signal, the DPD output signal configured to compensate for the plurality of non-linear components of the amplifier.

Embodiment 31: A digital front-end (DFE) system configured to perform a digital predistortion (DPD) process, the DFE system comprising: a digital upconverter (DUC) configured to receive and convert a baseband data input signal to generate a composite signal ; and a DPD system configured to receive the composite signal at the DPD input and perform a DPD process on the composite signal, the DPD input coupled to the plurality of parallel datapath elements, wherein the DPD input is coupled to at least one of the plurality of parallel datapath elements. one configured to add an inverse harmonic component corresponding to the non-linear harmonic component of the amplifier to the composite signal, the combiner configured to combine the output of each of the plurality of parallel datapath elements to generate a DPD output signal; the DPD output signal is coupled to the amplifier; The DPD output signal is configured to compensate for non-linear harmonic components of the amplifier.

Embodiment 32 The DFE system of embodiment 30, wherein the plurality of parallel datapath elements comprises a baseband DPD datapath, a video bandwidth DPD datapath, a second harmonic DPD datapath, and a third harmonic DPD datapath.

Embodiment 33 The DFE system of embodiment 31, wherein the DUC is configured to perform an interpolation process on the baseband data input signal to generate an interpolated signal, and wherein the DUC is configured to perform an interpolation process on the interpolated signal to generate a composite signal. is configured to perform a mixing process on the

Embodiment 34 The DFE system of embodiment 31, wherein the DPD system further comprises a digital tilt filter configured to model an analog tilt filter, wherein the digital tilt filter input is configured to receive the composite signal, and the digital tilt filter output comprises: coupled to a plurality of parallel datapath elements.

Embodiment 35 The DFE system of embodiment 31, wherein the DPD system further comprises a digital tilt equalizer configured to model the inverse of the analog tilt filter, wherein the digital tilt equalizer input is a combined signal of each of the plurality of datapath elements. and the other combiner is configured to couple the digital tilt equalizer output to the linear DPD signal to generate a DPD output signal.

Embodiment 36 A method comprising: receiving a DPD input signal at an input of a digital predistortion (DPD) system; receiving a DPD input signal in a non-linear datapath coupled to an input of the DPD system, the non-linear datapath including a plurality of parallel datapath elements each coupled to the input; adding, by each of the plurality of parallel datapath elements, an inverse non-linear component corresponding to the non-linear component of the amplifier to the DPD input signal; combining the output of each of the plurality of parallel datapath elements to produce a first predistortion signal by a first combiner; receiving the DPD input signal in a linear data path coupled to the input in parallel with the non-linear data path to generate a second predistortion signal; and combining, by a second combiner, the first predistortion signal and the second predistortion signal to generate a DPD output signal.

Embodiment 37 The method of embodiment 36, wherein the plurality of parallel datapath elements comprises a baseband DPD datapath, a video bandwidth DPD datapath, a second harmonic DPD datapath, and a third harmonic DPD datapath.

Embodiment 38: The method of embodiment 37, further comprising: adding an inverse non-linear baseband component to the DPD input signal by the baseband DPD datapath; adding, by the video bandwidth DPD datapath, an inverse non-linear video bandwidth component to the DPD input signal; adding an inverse second harmonic component to the DPD input signal by the second harmonic DPD datapath; and adding, by the third harmonic DPD datapath, an inverse third harmonic component to the DPD input signal.

Embodiment 39 The method of embodiment 36, further comprising providing a DPD output signal to an amplifier input to generate an amplified output signal, wherein the DPD output signal is configured to compensate for the plurality of non-linear components of the amplifier is composed

Embodiment 40 The method of embodiment 36, further comprising reducing power consumption of the amplifier in response to providing the DPD output signal to the amplifier and while operating the amplifier in the non-linear region.

While specific embodiments have been shown and described, it is to be understood that it is not intended to limit the claimed inventions to the preferred embodiments, and that various changes and modifications may be made without departing from the spirit and scope of the claimed inventions. It will be apparent to those skilled in the art. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense. The claimed inventions are intended to cover alternatives, modifications, and equivalents.

Claims (15)

As a crest factor reduction (CFR) system,
a digital tilt filter coupled to an input of the CFR system, the digital tilt filter configured to receive a system input signal and generate a digital tilt filter output signal at a digital tilt filter output;
a CFR module coupled to the digital tilt filter output, the CFR module receiving the digital tilt filter output signal and performing a CFR process on the digital tilt filter output signal to generate a CFR module output signal at the CFR module output configured to －; and
a digital tilt equalizer coupled to the CFR module output;
and the digital tilt equalizer is configured to receive the CFR module output signal and generate a system output signal. The method of claim 1,
Further comprising a digital predistortion (DPD) module coupled to the CFR module output,
the DPD module is configured to receive the CFR module output signal, and perform a DPD process on the CFR module output signal to generate a DPD module output signal at the DPD module output;
wherein the digital tilt equalizer is coupled to the DPD module output, the digital tilt equalizer is configured to receive the DPD module output signal and generate the system output signal. The method of claim 1,
The system input signal has a first peak-to-average power ratio (PAPR) and the CFR module output signal has a second PAPR less than the first PAPR. The method of claim 2,
a first linear data path coupled to the input of the CFR system and in parallel with the CFR module and the DPD module to generate a first time-delay signal; and
and a first combiner configured to combine the first time-delay signal and a digital tilt equalizer output signal to generate the system output signal. The method of claim 4,
a second linear data path coupled to the input of the CFR system and in parallel with the CFR module to generate a second time-delay signal;
a second combiner configured to combine the CFR module output signal and the second time-delay signal to generate a first output signal; and
and a third combiner configured to combine the first output signal and the DPD module output signal to generate the system output signal. The method of claim 2,
wherein the DPD module further comprises a non-linear datapath coupled to the CFR module output;
The non-linear datapath includes a plurality of parallel datapath elements each coupled to the CFR module output, each of the plurality of parallel datapath elements comprising: a different inverse non-linearity corresponding to a non-linear component of an amplifier and add a linear component to the CFR module output signal, and a combiner configured to combine the output of each of the plurality of parallel datapath elements to generate the DPD module output signal. The method of claim 1,
A digital-to-analog converter (DAC) is configured to receive the system output signal and generate a DAC output signal,
the analog tilt filter is configured to receive the DAC output signal and generate an analog tilt filter output signal;
wherein the digital tilt filter is configured to model the analog tilt filter. The method of claim 7,
and the digital tilt equalizer is configured to model the inverse of the analog tilt filter. The method of claim 2,
Further comprising a single side band Hilbert filter (single side band Hilbert filter),
wherein a single side band Hilbert filter input is configured to receive the DPD module output signal, and wherein the single side band Hilbert filter output is coupled to a digital tilt equalizer input. The method of claim 1,
a regulating engine configured to receive feedback data from the amplifier output;
based on the feedback data, the reconciliation engine is configured to update a configuration of the CFR module. A digital front-end (DFE) system configured to perform a crest factor reduction (CFR) process, comprising:
a digital upconverter (DUC) configured to receive and convert a baseband data input signal to generate a composite signal;
A CFR system comprising a digital tilt filter, a CFR module, and a digital tilt equalizer, wherein the digital tilt filter is configured to receive the composite signal and generate a digital tilt filter output signal, the CFR module comprising the digital tilt filter output signal and perform the CFR process on the digital tilt filter output signal to generate a CFR module output signal, wherein the digital tilt equalizer receives the CFR module output signal and generates a CFR system output signal configured, the CFR system output signal coupled to an amplifier; and
a regulating engine configured to receive feedback data from an output of the amplifier;
based on the feedback data, the coordination engine is configured to update a configuration of the CFR system. The method of claim 11,
and the CFR process is configured to reduce a peak-to-average power ratio (PAPR) of the digital tilt filter output signal. The method of claim 11,
The CFR system further comprises a digital predistortion (DPD) module comprising a non-linear datapath coupled to the CFR module output;
The non-linear datapath includes a plurality of parallel datapath elements each coupled to the CFR module output, each of the plurality of parallel datapath elements having a different inverse non-linearity corresponding to a non-linear component of the amplifier configured to model a linear component, wherein the combiner is configured to combine the output of each of the plurality of parallel datapath elements to generate a DPD module output signal, the digital tilt equalizer receiving the DPD module output signal; and generate the CFR system output signal. The method of claim 11,
A digital-to-analog converter (DAC) is configured to receive the CFR system output signal and generate a DAC output signal,
the analog tilt filter is configured to receive the DAC output signal and generate an analog tilt filter output signal;
and the digital tilt filter is configured to model the analog tilt filter. The method of claim 14,
and the digital tilt equalizer is configured to model the inverse of the analog tilt filter.

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